Cross-cell local interconnection with BPR and CBoA

Abstract

Cross-cell local interconnect with BPR and CBoA A semiconductor device is presented that includes a source / drain epitaxial region disposed over a substrate, source / drain contacts (CA) disposed in direct contact with the source / drain epitaxial region, at least one of the CA contacts in direct contact with a buried power rail or a backside power rail through a Via-to-BPR (VBPR) contact, a dielectric cap disposed over one or more of the CA contacts, and a local interconnect constructed in direct contact with a region of the dielectric cap such that a portion of the local interconnect is vertically aligned with the backside power rail. A backside power distribution network (BSPDN) is disposed adjacent to the backside power rail.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more particularly, to buried power rails or backside power rails (BPRs), and cross-cell local interconnects with gate contacts (CBs) (CBoA) on an active region.

Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric layers, conductive layers, and semiconductive layers of materials on a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0003] The semiconductor industry has experienced rapid growth due to improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). Most of this improvement in integration density has resulted from shrinking semiconductor processing nodes.

[0004] With the increasing demand for miniaturization, higher speed, larger bandwidth, lower power consumption, and lower latency, chip layout has become increasingly complex and difficult to achieve in the production of semiconductor dies. For example, the wiring area has decreased.

Summary of the Invention

[0005] According to the embodiment, a semiconductor device is provided. The semiconductor device includes a source / drain epitaxial region disposed on a substrate, a source / drain contact (CA) disposed in direct contact with the source / drain epitaxial region, at least one of the CA contacts in direct contact with an embedded power rail through a via-to-BPR (VBPR) contact, a dielectric cap disposed on one or more of the CA contacts, and a local interconnect, a local interconnect constructed in direct contact with one region of the dielectric cap such that a portion of the local interconnect is aligned perpendicularly with the embedded power rail.

[0006] According to another embodiment, a semiconductor device is provided. The semiconductor device includes a source / drain epitaxial region disposed on a substrate; source / drain contacts (CAs) disposed in direct contact with the source / drain epitaxial region, at least one of the CA contacts in direct contact with a backside power rail through a via-to-BPR (VBPR) contact; a dielectric cap disposed on one or more of the CA contacts; a local interconnection constructed in direct contact with one region of the dielectric cap such that a portion of the local interconnection is aligned perpendicularly with the backside power rail; and a backside power distribution network (BSPDN) disposed adjacent to the backside power rail.

[0007] Another embodiment provides a method for forming a semiconductor device. This method includes forming a source / drain epitaxial region on a substrate, forming source / drain contacts (CAs) in direct contact with the source / drain epitaxial region, wherein at least one of the CA contacts is in direct contact with an embedded power rail or backside power rail through a via-to-BPR (VBPR) contact, recessing the CA contacts to form an opening, arranging a dielectric cap within the opening, constructing a local interconnection in direct contact with one area of ​​the dielectric cap, and forming a via in direct contact with the local interconnection.

[0008] It should be noted that exemplary embodiments are described with reference to different subject matter. In particular, some embodiments are described with reference to method-type claims, while others are described with reference to apparatus-type claims. However, those skilled in the art will infer from the above and below descriptions that, unless otherwise stated, any combination of features belonging to one type of subject matter, as well as any combination of features relating to different subject matter, in particular, any combination of features of method-type claims and features of apparatus-type claims, are also described herein.

[0009] These and other features and advantages will become apparent from the following detailed description of the illustrative embodiments, which should be read in conjunction with the accompanying drawings.

[0010] The present invention provides further details in the following description of preferred embodiments with reference to the following figures. [Brief explanation of the drawing]

[0011] [Figure 1] This is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention, in which source / drain epitaxial formation occurs adjacent to a nanosheet structure. [Figure 2]Figure 1 is a cross-sectional view of a semiconductor structure in which various types of middle-of-line (MOL) contacts are formed according to embodiments of the present invention. [Figure 3] Figure 2 is a cross-sectional view of a semiconductor structure in which a conductive material is recessed from metallization according to an embodiment of the present invention. [Figure 4] Figure 3 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention, in which exposed gate spacers are selectively removed and dielectric caps are deposited on a concave dielectric material. [Figure 5] Figure 4 is a cross-sectional view of a semiconductor structure in which interlayer insulation (ILD) and local interconnections are formed according to an embodiment of the present invention. [Figure 6] Figure 5 is a cross-sectional view of a semiconductor structure in which BEOL vias and a first BEOL metal layer are formed according to an embodiment of the present invention. [Figure 7] This is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention, in which patterning occurs after metallization and selective recessing of conductive material from metallization. [Figure 8] Figure 7 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention, in which dielectric caps are deposited on one or more conductive material regions. [Figure 9] Figure 8 is a cross-sectional view of a semiconductor structure in which interlayer insulation (ILD) and local interconnects are deposited according to an embodiment of the present invention. [Figure 10] This is a cross-sectional view of the semiconductor structure shown in Figure 9, in which BEOL vias and a metal wire layer are formed according to an embodiment of the present invention. [Figure 11] This is a cross-sectional view of a semiconductor structure, including a backside power rail and a backside power distribution network, according to another embodiment of the present invention. [Modes for carrying out the invention]

[0012] Throughout the drawing, the same or similar reference numbers represent the same or similar elements.

[0013] Embodiments of the present invention provide a method and device for wire-connecting source / drain (S / D) contacts from one cell to another via a local interconnect formed on a recessed S / D contact that is wire-connected to an embedded power rail or backside power rail (BPR) to achieve pin access at or across cell boundaries.

[0014] Fin-based active devices, primarily transistors, are widely applied to generate standard cell and other active device configurations processed in the front-end-of-line (FEOL) portion of integrated circuit manufacturing processes, including finFETs, as well as more recent devices based on nanowires or nanosheets. Exemplary techniques involve the use of embedded interconnect rails within the FEOL, or backside power rails on the back of the wafer. BPRs can directly connect transistors within the FEOL to a power delivery network located on the back of the integrated circuit chip. In particular, the source or drain regions of some transistors are directly connected to the BPR. Current conventions for achieving this configuration involve generating interconnect vias to the BPR and connecting the interconnect vias to the source or drain regions through local interconnects that are part of the middle-of-line (MOL) metallization level of the chip, which is a transition between active devices within the FEOL, and the interconnection levels (M1, M2, etc.) within the back-end-of-line (BEOL).

[0015] Some implementations of this method have several drawbacks. The signal distribution (S / D) of the FEOL device is wired to the signal relay (BPR), but the BEOL signal wires above the S / D are still not freed up for other wiring purposes.

[0016] Embodiments according to the present invention provide a method and structure for wire connecting S / D contacts from one cell to another cell through a local interconnect above a recessed S / D contact that is wire connected or connected to a BPR to achieve pin access at or across a cell boundary. In other words, the local interconnect is formed over a recessed contact that is wire connected to the BPR. An exemplary structure includes at least a first S / D contact having a higher surface, at least another S / D contact having a dielectric cap, and a local interconnect that lands on the higher surface and also partially lands on the dielectric cap. The method includes forming an S / D contact having at least one contact connected to the BPR, dimpling the contact, forming a contact dielectric cap, forming a local interconnect having one side that lands on the contact dielectric cap and another side that connects to another S / D contact, and wire connecting the local interconnect to BEOL.

[0017] Examples of semiconductor materials that can be used to form such structures include silicon (Si), germanium (Ge), silicon-germanium alloy (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), group III-V compound semiconductors, or group II-VI compound semiconductors or combinations thereof. Group III-V compound semiconductors are materials that include at least one element from group III of the periodic table and at least one element from group V of the periodic table. Group II-VI compound semiconductors are materials that include at least one element from group II of the periodic table and at least one element from group VI of the periodic table.

[0018] The present invention is described with respect to a given exemplary architecture, but it should be understood that other architectures, structures, substrate materials, as well as process features and steps / blocks can be varied within the scope of the present invention. Note that not all features are shown in all figures for purposes of clarity. This is not intended to be construed as a limitation on the scope of any particular embodiment, or illustration, or claim.

[0019] FIG. 1 is a cross-sectional view of a semiconductor structure in which source / drain epitaxial formation occurs adjacent to a nanosheet structure according to an embodiment of the present invention.

[0020] Integrated circuit (IC) structures have been developed that enable the formation of field effect transistors (FETs) having gate contacts (CB)(CBoA) on an active region to enable area scaling. More specifically, middle-of-line (MOL) contacts are contacts that connect the FET to the back-end-of-line (BEOL) metal levels. These MOL contacts include at least one gate contact and source / drain contacts (CA). The gate contact extends vertically through an interlayer dielectric (ILD) material from a metal wire or via within a first BEOL metal level (referred to as the M1 level) to the gate of the FET. Each source / drain contact extends vertically through the ILD material from a metal wire or via within the first BEOL metal level to a metal plug (TS) that is above and directly adjacent to the source / drain region of the FET. Conventional techniques for forming these MOL contacts essentially involve the risks of, in particular, short circuits that occur between the gate contact and the metal plug, and short circuits that occur between the source / drain contact and the gate, especially when the gate contact is above or near the active region. However, exemplary embodiments provide a method and structure for wire connecting the S / D contacts from one cell to another cell through a local interconnect above a recessed S / D contact that is wire connected or connected to a BPR to achieve pin access at or across a cell boundary, thereby alleviating such problems in buried power rails or backside power rails where pins in one cell are inaccessible by another cell due to the presence of tall S / D contacts. In other words, the local interconnect is formed above a recessed contact that is wire connected to a BPR.

[0021] Referring to Figure 1, the semiconductor structure 5 includes a semiconductor substrate 10. A dielectric layer 14 is formed on the semiconductor substrate 10. A nanosheet stack 20 may be formed on the dielectric layer 14. The nanosheet stack 20 may include, for example, alternating layers of a first semiconductor material and a second semiconductor material 24. The first semiconductor material may be, for example, silicon-germanium (SiGe), and the second semiconductor material 24 may be, for example, silicon (Si). A dummy gate (not shown) may be formed on the nanosheet stack 20. A hard mask (not shown) may be formed on the dummy gate.

[0022] The first semiconductor material, dummy gate, and hard mask of the nanosheet stack 20 are replaced with high-k metal gates (HKMG) 36 in a substitution metal gate (RMG) process. The HKMG 36 is positioned adjacent to the second semiconductor material 24 of the nanosheet stack 20. Additionally, an inner spacer 26 is formed adjacent to the etched first semiconductor material.

[0023] The source / drain epitaxial region 30 may be formed adjacent to the opposite end of the nanosheet stack 20. The source / drain epitaxial region 30 is in direct contact with the upper surface of the dielectric layer 14. The source / drain epitaxial region 30 is also in direct contact with the inner spacer 26, as well as the second semiconductor material 24 of the nanosheet stack 20. The source / drain epitaxial region 30 extends over the nanosheet stack 20.

[0024] An interlayer dielectric (ILD) 32 is formed on and in direct contact with the source / drain epitaxial region 30. A gate spacer 34 is formed on the nanosheet stack 20 so that a gate dielectric cap 38 is positioned between the gate spacers 34. The gate dielectric cap 38 is in direct contact with a portion of the HKMG 36. The gate spacer 34 is aligned perpendicularly to the inner spacer 26. The source / drain epitaxial region 30 is aligned perpendicularly to the ILD 32. A dielectric layer 14 is formed beneath the S / D epitaxial and gate. A buried power rail (BPR) 40 may be formed between the active regions. In some embodiments, the buried power rail is not formed at this stage of the process, and later, a backside power rail may be formed after the wafer has been inverted and substrate thinning has been performed (Figure 11).

[0025] The semiconductor structure 5 is a cross-sectional view along axis X in the top view 9.

[0026] The semiconductor structure 7 is shown in a cross-sectional view along axis Y in the top view 9.

[0027] The semiconductor structure 7 also illustrates a shallow trench isolation (STI) region 12 formed within the semiconductor substrate 10 that defines the fin 16. Additionally, a BPR 40 is formed within the semiconductor substrate 10. The BPR 40 is offset perpendicularly from the source / drain epitaxial region 30.

[0028] Top view 9 illustrates the CA and CB contacts, as well as the BPR40. Top view 9 also illustrates the local interconnect 64, which is described below.

[0029] The semiconductor substrate 10 may be crystalline, semicrystalline, microcrystalline, or amorphous. The semiconductor substrate 10 may be essentially (e.g., excluding contaminants) a single element (e.g., silicon), or primarily a single element (e.g., with doping), such as silicon (Si) or germanium (Ge), or the semiconductor substrate 10 may contain compounds, such as GaAs, SiC, or SiGe. The semiconductor substrate 10 may also have multiple material layers. In some embodiments, the semiconductor substrate 10 includes, but is not limited to, semiconductor materials such as silicon (Si), silicon-germanium (SiGe), silicon carbide (SiC), Si:C (carbon-doped silicon), silicon-germanium carbide (SiGeC), carbon-doped silicon-germanium (SiGe:C), Group III-V semiconductors (e.g., GaAs, AlGaAs, InAs, InP, etc.), Group II-V compound semiconductors (e.g., ZnSe, ZnTe, ZnCdSe, etc.), or other similar semiconductors. In addition, multiple layers of semiconductor material may be used as the semiconductor material of the semiconductor substrate 10. In some embodiments, the semiconductor substrate 10 includes both semiconductor material and dielectric material. The semiconductor substrate 10 may also include organic semiconductors or layered semiconductors, such as Si / SiGe, silicon-on-insulator, or SiGe-on-insulator. Part or all of the semiconductor substrate 10 may be amorphous, polycrystalline, or single-crystal. In addition to the semiconductor substrates of the types described above, the semiconductor substrate 10 used in the present invention may also include a hybrid-oriented (HOT) semiconductor substrate, which has surface regions with different crystal orientations.

[0030] The dielectric layer 14 may include, but is not limited to, porous silica, carbon-doped oxides, silicon dioxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide (SiCOH), and porous variants thereof, SiN, SiOCN, SiOC, SiBCN, SO2, or ultra-low-k (ULK) materials, silsesquioxanes, siloxanes, or other dielectric materials having a relative permittivity in the range of about 2 to about 10.

[0031] In some embodiments, the dielectric layer 14 may be conformally deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). Variations of the CVD process suitable for forming the dielectric layer 14 include, but are not limited to, atmospheric CVD (APCVD), low-pressure CVD (LPCVD), and plasma-accelerated CVD (PECVD), and organometallic CVD (MOCVD) and combinations thereof may also be employed.

[0032] Examples of semiconductor materials that can be used to form the nanosheet stack 20 include at least silicon (Si), germanium (Ge), silicon-germanium alloy (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), III-V compound semiconductors, or II-VI compound semiconductors, or combinations thereof. Those skilled in the art may conceive of several different semiconductor materials for forming the nanosheet stack 20.

[0033] The terms “epitaxial growth” and “epitaxial deposition” refer to the growth of a semiconductor material on a deposition surface, where the growing semiconductor material has substantially the same crystalline properties as the semiconductor material on the deposition surface. The term “epitaxial material” refers to a material formed using epitaxial growth. In some embodiments, when the chemical reactants are controlled and the system parameters are correctly set, the deposited atoms move around on the surface and reach the deposition surface with sufficient energy to determine their own position in the crystalline arrangement of atoms on the deposition surface. Therefore, in some examples, an epitaxial film deposited on a {100} crystalline surface will exhibit a {100} orientation.

[0034] The source / drain epitaxial region 30 may be of the same or different material for p-type field-effect transistor (pFET) and n-type field-effect transistor (nFET) devices and may be in-situ doped with the appropriate polarity dopant (B for pFET devices and P for nFET devices) or doped by ion implantation.

[0035] ILD32 can be any suitable dielectric, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride, silicon-boron carbon nitride (SiBCN), silicon oxygen carbon nitride (SiOCN), silicon oxygen carbon (SiOC), silicon carbon nitride (SiCN), silicon carbon hydride oxide (SiCOH), or any suitable combination thereof. In one example, ILD32 may be a low-k oxide.

[0036] The inner spacer 26 and gate spacer 34 may include one or more of the following: a SiN film, a SiBN film, a SiCN film, or a SiBCN film, or a combination thereof.

[0037] As described above, HKMG36 is formed within regions or openings of the device structure previously occupied by a dummy gate, hard mask, and a first semiconductor material (e.g., SiGe). In one example, a high-k material and a work function metal may be deposited. Among the many materials, the high-k material is the material HfO X , HfSiO x Al2O3, ZrO2, ZrSiO x It could be any of the following. Among the many materials, the work function materials are the following metal compounds: TiN, TaN, TiC, TaC, La2O3, Al, AlO x It may include any of the following. Both high-k and work function metals can be deposited by PVD, CVD, or ALD processes.

[0038] Etching may include dry etching processes, such as reactive ion etching, plasma etching, ion etching, or laser ablation. Etching may further include wet chemical etching processes in which one or more chemical etching solutions are used to remove portions of the blanket layer that are not protected by the patterned photoresist.

[0039] Dry and wet etching processes may have adjustable etching parameters, such as the etching solution used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etching solution flow rate, and other suitable parameters. Dry etching processes may include deflected plasma etching processes that utilize the chemical properties of chlorine-based systems. Other dry etching gases may include tetrafluoromethane (CF4), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), helium (He), and chlorine trifluoride (ClF3). Dry etching may also be carried out anisotropically using mechanisms such as DRIE (Deep Reactive Ion Etching). Chemical vapor etching may be used as a selective etching method, and the etching gas may include a gas mixture with hydrogen chloride (HCl), tetrafluoromethane (CF4), and hydrogen (H2). Chemical vapor etching may be carried out by CVD at suitable pressure and temperature.

[0040] Figure 2 is a cross-sectional view of the semiconductor structure of Figure 1, in which various types of middle-of-line (MOL) contacts are formed according to embodiments of the present invention.

[0041] In various exemplary embodiments, various MOL contacts include a CA contact 50 (also referred to as a source / drain (S / D) contact) and a via-to-BPR (VBPR) contact 52 (also referred to as an extension region) that wires the CA contact 50 to the BPR 40. The CA contact 50 is formed on and in direct contact with the source / drain epitaxial region 30.

[0042] In structure 7', in the Y direction, one of the CA contacts 50 extends to the upper surface of BPR40.

[0043] CA contacts 50 and VBPR contacts 52 include metals such as Ti, Ni, and NiPt, silicide liners, thin metal deposition layers such as TiN or TaN, and highly conductive metals such as Co, W, and Ru.

[0044] In various exemplary embodiments, excessive metal loads for the CA contact 50 and VBPR contact 52 can be removed by a chemical mechanical polishing (CMP) process.

[0045] Figure 3 is a cross-sectional view of the semiconductor structure shown in Figure 2, in which the conductive material from metallization is recessed according to an embodiment of the present invention.

[0046] In various exemplary embodiments, a mask layer 56 (e.g., an organic planarization layer (OPL)) is formed by a conventional lithography and etching process, and the exposed CA contacts 50 and VBPR contacts 52 are recessed.

[0047] In the X direction, the CA contact 50 is recessed by a distance D1, and as a result, the remaining CA contact (or recessed CA contact) is shown as 50'. The opening 54 is formed above the recessed CA contact 50'.

[0048] In the Y direction, the CA contact 50 is also recessed by a distance D1, and as a result, the remaining CA contact (or concave CA contact) is shown as 50'. The opening 54 is formed on the concave CA contact 50'. The presence of the mask layer 56 results in one of the concave CA contacts 50' (the left side) having an irregular shape. In this case, the irregular shape resembles an inverted L-shape. Thus, the VBPR contact 52 has a substantially inverted L-shape.

[0049] The mask layer 56 may contain an organic planarizing material, which is a self-planarizing organic material containing carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon. In one embodiment, the self-planarizing organic material may be a polymer with sufficiently low viscosity so that the upper surface of the mask layer 56 forms a flat horizontal surface. Exemplary organic planarizing materials include, but are not limited to, near-frictionless carbon (NFC) materials, diamond-like carbon, polyarylene ethers, and polyimides. The mask layer 56 may be deposited, for example, by spin coating. The thickness of the mask layer 56 may be about 100 nm to about 500 nm, but smaller or larger thicknesses may also be employed.

[0050] Figure 4 is a cross-sectional view of the semiconductor structure of Figure 3, according to an embodiment of the present invention, in which the exposed gate spacer 34 is selectively removed and the dielectric cap 60 is deposited on the concave dielectric material.

[0051] In various exemplary embodiments, the dielectric cap 60 is deposited on the concave CA contact 50'. The dielectric cap 60 may also be referred to as the CA cap.

[0052] Figure 5 is a cross-sectional view of the semiconductor structure of Figure 4, in which interlayer insulation (ILD) and local interconnections are formed according to an embodiment of the present invention.

[0053] In various exemplary embodiments, the ILD 62 and local interconnect 64 are formed. The ILD 62 may be deposited by, for example, a PVD or CVD process. The local interconnect 64 is formed by a conventional lithography / etch patterning and metallization process and is later wired to the BEOL. The local interconnect 64 wires the non-recessed portion of the CA contact 50 onto the fully recessed CA / VBPR contact so that the non-recessed CA may have the opportunity to connect to the BEOL wire in different cells. Thus, the local interconnect 64 is wired to the BEOL.

[0054] Figure 6 is a cross-sectional view of the semiconductor structure of Figure 5, in which BEOL vias and a first BEOL metal layer are formed according to an embodiment of the present invention.

[0055] In various exemplary embodiments, via and metal wire (M1) layers are formed.

[0056] In the X direction, the gate CB contact 70 is formed between the dielectric caps 60. The gate CB contact 70 is positioned in direct contact with the sidewall of the dielectric cap 60. The ILD 72 is deposited on top of the ILD 62, the gate CB contact 70, and the local interconnect 64. The via 74 "VB" is formed on top of the gate CB contact 70 and in direct contact with it. The metal wire (M1) layer 76 is formed on top of the via 74 and in direct contact with it.

[0057] In the Y direction, via 74'"VA" is formed on and in direct contact with the local interconnect 64. Layer M1 76 is formed on and in direct contact with via 74'.

[0058] The first end of the local interconnect 64 rests on the non-recessed portion (L-shaped CA contact) of the CA contact 50 associated with the first source / drain epitaxial region, and the second end of the local interconnect 64 rests on the recessed portion of the CA contact 50' associated with the second source / drain epitaxial region. In this way, the exemplary method effectively wires the first S / D region to the M1 line on the second S / D region, which favorably improves wiring flexibility and availability.

[0059] ILD72 can be any suitable dielectric, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride, silicon-boron carbon nitride (SiBCN), silicon oxygen carbon nitride (SiOCN), silicon oxygen carbon (SiOC), silicon carbon nitride (SiCN), silicon hydride carbon oxide (SiCOH), low-k dielectrics (k value < 3.9), or any suitable combination of these materials. In one example, dielectric 72 is a low-k dielectric.

[0060] A non-limiting example of a suitable conductive material for the M1 layer 76 and vias 74, 74' (VB and VA) is conventional Cu metallized by the damascene process. Suitable conductive materials can also be metals such as Co or Ru. A thin metal deposition layer is deposited in front of the Cu, Co, or Ru fill.

[0061] Figure 7 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention, in which patterning occurs after metallization and selective recessing of conductive material from metallization.

[0062] In another exemplary embodiment, CA contacts 50 and VBPR contacts 52 are formed, and some CA contacts that connect to the BPR 40 through the VBPR contacts 52 are recessed, while other CA contacts are protected by a mask layer 56 using a conventional lithographic patterning process.

[0063] In the Y direction, the recessed CA contact 50' is recessed within the structure 82 by a distance D1. The opening 54 is formed on top of the recessed CA contact 50'.

[0064] In the X direction, within the structure 80, the CA contacts 50 retain their original shape; that is, they are not recessed. The CA contacts 50 are coplanar or at the same height as the upper surface of the gate spacer 34 and the upper surface of the gate dielectric cap 38.

[0065] Top view 84 illustrates the CA contact, CB contact, "VA" via, and BPR40. Top view 84 also illustrates the local interconnect 64.

[0066] Figure 8 is a cross-sectional view of the semiconductor structure of Figure 7, according to an embodiment of the present invention, in which dielectric caps are deposited on one or more conductive material regions.

[0067] In various exemplary embodiments, the dielectric cap 60 is deposited on the recessed CA / VBPR contacts 50' / 52. The dielectric cap 60 is aligned perpendicularly to the VBPR contacts 52 and the source / drain epitaxial region 30. The VBPR contacts 52 are in direct contact with the upper surface of the BPR 40.

[0068] In the X direction, the dielectric cap 60 does not exist.

[0069] Figure 9 is a cross-sectional view of the semiconductor structure of Figure 8, in which interlayer insulation (ILD) and local interconnects are deposited according to an embodiment of the present invention.

[0070] In various exemplary embodiments, an ILD 62 and a local interconnect 64 are formed. The ILD 62 may be deposited, for example, by CVD or PVD. The local interconnect 64 is wired to the BEOL.

[0071] Figure 10 is a cross-sectional view of the semiconductor structure shown in Figure 9, in which BEOL vias and a metal wire layer are formed according to an embodiment of the present invention.

[0072] In various exemplary embodiments, via and metal wire (M1) layers are formed.

[0073] In the X direction, ILD 72 is deposited, and vias 74 are formed on and in direct contact with the CA contact 50. M1 layer 76 is formed on and in direct contact with the vias 74.

[0074] In the Y direction, via 74 is formed on and in direct contact with the local interconnect 64. M1 layer 76 is formed on and in direct contact with via 74. Via 74 is aligned perpendicularly to the dielectric cap 60. The first end of the local interconnect 64 is on the non-recessed CA contact 50 associated with the first source / drain epitaxial region, and the second end of the local interconnect 64 is on the dielectric cap on the recessed CA / VBPR region associated with the second source / drain epitaxial region.

[0075] Figure 11 is a cross-sectional view of a semiconductor structure, including a backside power rail and a backside power distribution network, according to another embodiment of the present invention.

[0076] It should be noted that the exemplary embodiment functions not only for buried power rails but also for backside power rails using backside power distribution networks.

[0077] Therefore, in some embodiments, buried power rails are not used, and instead, backside power rails 110 are employed together with backside power distribution networks (BSPDN) 102.

[0078] After MOL processing using concave CA / VBPR, dielectric CA cap formation, and local interconnection formation, BEOL interconnections (VA / VB, M1, and further BEOL layers 120) are formed, followed by carrier-wafer bonding 130.

[0079] Subsequently, the wafer may be inverted, and then the substrate is removed to expose the VBPR contacts and FEOL devices. Following the backside ILD deposition 104, the backside power rail 110 and BSPDN 102 are formed using conventional patterning and metallization techniques. The BSPDN 102 is positioned adjacent to the backside power rail 110.

[0080] Similar to Figure 10, using a concave CA / VBPR, dielectric cap, and local interconnect, the exemplary method allows for successful wire connection of S / D regions (not extending to the backside power rail and BSPDN) to the M1 line in different cells on a concave S / D region connected to the backside power rail 110 and BSPDN 102 via VBPR contacts 52. Thus, one of the source / drain epitaxial regions 30 is wired to the M1 layer 76 in different cells on a concave source / drain epitaxial region connected to the buried power rail or backside power rail 110 via VBPR contacts 52.

[0081] In summary, exemplary embodiments of the present invention disclose a method and device for advantageously wire-connecting S / D contacts from one cell to another via a local interconnect on recessed S / D contacts that wire-connect or connect to a buried power rail or backside power rail to achieve pin access at or across cell boundaries. In other words, the local interconnect is formed on a recessed contact that wires to a buried power rail or backside power rail. An exemplary device includes at least a first S / D contact having a higher surface area, at least another S / D contact having a dielectric cap, and a local interconnect mounted on the higher surface, also partially landing on the dielectric cap. The method includes forming an S / D contact having at least one contact that connects to a buried power rail or backside power rail, recessing the contact, forming a contact dielectric cap, forming a local interconnect having one side landing on the contact dielectric cap and the other side connecting to another S / D contact, and wire-connecting the local interconnect to the BEOL.

[0082] Regarding Figures 1 to 11, deposition is any process of growing, coating, or separately transferring a material onto a wafer. Available technologies are not limited to, but include thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). As used herein, “depositing” may include, but is not limited to, any currently known or subsequently developed techniques suitable for the material to be deposited, including, for example, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-accelerated CVD (PECVD), semi-atmospheric CVD (SACVD), and high-density plasma CVD (HDPCVD), fast thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), restricted-reaction CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser deposition, thermal oxidation, thermal nitriding, spin-on method, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, and evaporation.

[0083] It should be understood that this invention is described in relation to a given illustrative architecture.

[0084] When an element such as a layer, region, or substrate is said to be "on" or "over" another element, it should be understood that it can be directly on top of the other element, or there may be an intervening element. In contrast, when an element is said to be "directly on" or "directly over" another element, there is no intervening element. When an element is said to be "connected" or "joined" to another element, it should be understood that it can be directly connected or joined to the other element, or there may be an intervening element. In contrast, when an element is said to be "directly connected" or "directly joined" to another element, there is no intervening element.

[0085] This embodiment may include a design for an integrated circuit chip, which may be created in a graphics computer programming language and stored on a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive, such as within a storage access network). If the designer does not manufacture the chip or the photolithography mask used to manufacture the chip, the designer may transmit the resulting design directly or indirectly to such an entity, either by a physical mechanism (e.g., by providing a copy of the storage medium that stores the design) or electronically (e.g., via the Internet). The stored design is then converted into a suitable format (e.g., GDSII) for manufacturing a photolithography mask containing multiple copies of the chip design to be formed on a wafer. The photolithography mask is used to define areas of the wafer (and / or layers on top of it) to be etched or otherwise processed.

[0086] The methods described herein may be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer as bare dies in raw material wafer form (i.e., a single wafer with multiple unpackaged chips) or in packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other high-level carrier) or a microchip package (such as a ceramic carrier with either surface-mounted or embedded wiring or both). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices or combinations thereof as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product may be any product containing an integrated circuit chip, ranging from toys and other low-end applications to displays, keyboards or other input devices, and advanced computer products with a central processor.

[0087] It should also be understood that the material compounds are described with respect to the listed elements, for example, SiGe. These compounds contain different proportions of elements within the compound; for example, SiGe contains Si where x is less than or equal to 1. x Ge 1-x This includes, for example, other elements. In addition, other elements may be included in the compound and it will still function according to this embodiment. Compounds having additional elements are referred to herein as alloys. Any reference herein to “one embodiment” or “embodiment” of the present invention, as well as to other variations thereof, means that certain features, structures, properties, etc., described in relation to that embodiment are included in at least one embodiment of the present invention. Therefore, the expressions “in one embodiment” or “in an embodiment” and any other variations appearing in various places throughout this specification do not necessarily all refer to the same embodiment.

[0088] Please understand that the use of any of the following " / ", "or... or a combination thereof", and "at least one of the following" is intended to include, for example, "A / B", "A or B or a combination thereof", and "at least one of A and B", the selection of only the first enumerated option (A), only the second enumerated option (B), or the selection of both options (A and B). As a further example, in the case of "A, B, or C or a combination thereof", and "at least one of A, B, and C", such expressions are intended to include the selection of only the first enumerated option (A), only the second enumerated option (B), only the third enumerated option (C), only the first and second enumerated options (A and B), only the first and third enumerated options (A and C), only the second and third enumerated options (B and C), or the selection of all three options (A, B, and C). This can be expanded to the same number of items as listed, as will be readily apparent to those skilled in the art.

[0089] The terms used herein are for the sole purpose of describing specific embodiments and are not intended to be an limitation of the embodiments. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless the context explicitly indicates otherwise. The terms “equip,” “equip,” “include,” or “include,” or any combination thereof, where used herein, describe the presence of the described feature, integer, step, action, element, or component or combination thereof, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components or groups or combinations thereof.

[0090] Spatial terms such as “beneath,” “below,” “downward,” “up,” “above,” and similar terms may be used herein for the purpose of facilitating explanation to describe the relationship of one element or feature to another, as illustrated in the figures. It should be understood that spatial terms are intended to encompass different orientations of a device in use or operation, in addition to the orientation depicted in the figures. For example, if a device is upside down in the figures, an element described as “below” or “beneath” another element or feature will be oriented “above” the other element or feature. Thus, the term “below” may encompass both up and down orientations. A device may be oriented separately (rotated by 90 degrees or other orientations), and spatial descriptions used herein may be interpreted accordingly. In addition, it should be understood that when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.

[0091] Terms such as "First," "Second," etc., may be used herein to describe various elements, but it should be understood that these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. Therefore, the first element discussed below may be named the second element without deviating from the scope of this concept.

[0092] Preferred embodiments of cross-cell local interconnections of buried power rails or backside power rails (BPRs) and gate contacts (CBs) (CBoA) on active regions have been described (intended to be illustrative and not limiting), but it should be noted that modifications and variations may be made by those skilled in the art in consideration of the above teachings. Therefore, it should be understood that changes within the scope of the invention, as outlined by the appended claims, may be made in the particular embodiments described. While aspects of the invention have thus been described with details and those particularly required by patent law, those claimed and for which patent protection is desired are specified in the appended claims.

Claims

1. It is a semiconductor device, Source / drain epitaxial regions arranged on the substrate, Source / drain contacts (CA contacts) disposed in direct contact with the source / drain epitaxial region, wherein at least one of the CA contacts is in direct contact with the buried power rail through a via-to-BPR (VBPR) contact, A dielectric cap is disposed on one or more of the CA contacts, A local interconnection comprising a local interconnection constructed in direct contact with one region of the dielectric cap such that a portion of the local interconnection is aligned perpendicularly to the buried power rail, A semiconductor device in which the local interconnect lies on two CA contacts, and the first end of the local interconnect is in direct contact with one of the two CA contacts.

2. The semiconductor device according to claim 1, further comprising a backside power distribution network (BSPDN) arranged adjacent to a backside power rail used in place of the buried power rail.

3. The semiconductor device according to claim 1 or 2, wherein the via is arranged in direct contact with the local interconnection.

4. The semiconductor device according to claim 3, wherein a metal wire (M1) layer is disposed on and in direct contact with the via.

5. The semiconductor device according to claim 1 or 2, wherein the local interconnection is wired to the back end of line (BEOL).

6. The semiconductor device according to claim 1 or 2, wherein the first end of the local interconnection rests on a non-recessed portion of a CA contact associated with a first source / drain epitaxial region, and the second end of the local interconnection rests on a recessed portion of a CA contact associated with a second source / drain epitaxial region.

7. The semiconductor device according to claim 1 or 2, wherein the VBPR contact has a substantially inverted L-shaped configuration.

8. The semiconductor device according to claim 1, wherein the gate contact (CB) is disposed in direct contact with the side wall of the dielectric cap.

9. The semiconductor device according to claim 1 or 2, wherein one of the source / drain epitaxial regions is wire-connected to a metal wire (M1) layer in a different cell on a concave source / drain epitaxial region connected to the buried power rail via the VBPR contact.

10. A semiconductor device, Source / drain epitaxial regions arranged on the substrate, Source / drain contacts (CA contacts) disposed in direct contact with the source / drain epitaxial region, wherein at least one of the CA contacts is in direct contact with the buried power rail through a via-to-BPR (VBPR) contact, A dielectric cap is disposed on one or more of the CA contacts, A local interconnection comprising a local interconnection constructed in direct contact with one region of the dielectric cap such that a portion of the local interconnection is aligned perpendicularly to the buried power rail, A semiconductor device in which the first end of the local interconnection rests on a non-recessed portion of a CA contact associated with a first source / drain epitaxial region, and the second end of the local interconnection rests on a recessed portion of a CA contact associated with a second source / drain epitaxial region.

11. The semiconductor device according to claim 10, further comprising a backside power distribution network (BSPDN) arranged adjacent to a backside power rail used in place of the buried power rail.

12. It is a method, Forming source / drain epitaxial regions on the substrate, The source / drain contacts (CA contacts) are formed in direct contact with the source / drain epitaxial region, wherein at least one of the CA contacts is formed in direct contact with the buried power rail or backside power rail through a via-to-BPR (VBPR) contact. The CA contact is recessed in order to form an opening, A dielectric cap is placed inside the aforementioned opening, The method involves constructing a local interconnection by directly contacting one area of ​​the dielectric cap, wherein the local interconnection lies on two of the CA contacts, and the first end of the local interconnection directly contacts one of the two CA contacts. A method comprising forming a via in direct contact with the aforementioned local interconnection.

13. The method according to claim 12, wherein the metal wire (M1) layer is disposed on and in direct contact with the via.

14. The method according to claim 12, wherein the first end of the local interconnection rests on a non-recessed portion of a CA contact associated with a first source / drain epitaxial region, and the second end of the local interconnection rests on a recessed portion of a CA contact associated with a second source / drain epitaxial region.

15. The method according to claim 12, wherein the VBPR contact has a substantially inverted L-shaped configuration.

16. The method according to claim 12, wherein one of the source / drain epitaxial regions is wired to a metal wire (M1) layer in a different cell on a concave source / drain epitaxial region connected to the buried power rail or the backside power rail via the VBPR contact.

17. A method, Forming source / drain epitaxial regions on the substrate, The source / drain contacts (CA contacts) are formed in direct contact with the source / drain epitaxial region, wherein at least one of the CA contacts is formed in direct contact with the buried power rail or backside power rail through a via-to-BPR (VBPR) contact. The CA contact is recessed in order to form an opening, A dielectric cap is placed inside the aforementioned opening, The method involves constructing a local interconnection by direct contact with one area of ​​the dielectric cap, wherein the first end of the local interconnection rests on the non-recessed portion of the CA contact associated with the first source / drain epitaxial region, and the second end of the local interconnection rests on the recessed portion of the CA contact associated with the second source / drain epitaxial region. A method comprising forming a via in direct contact with the aforementioned local interconnection.

Images