Common data strobes between multiple memory devices

Abstract

A plurality (e.g., four) of memory devices on the module are connected to a common pair of differential data strobe signal conductors. The common pair of differential data strobe conductors is also coupled to a memory controller for timing the transmission of data to the plurality of memory devices and for timing the reception of data from the memory devices. The controller calibrates two or more different data transmission delays relative to its transmission of a write data strobe signal on the common pair of differential data strobe conductors. The controller also calibrates to account for two or more different data reception delays (skews) relative to its reception of a read data strobe signal on the common pair of differential data strobe conductors.

Description

Brief Description of the Drawings

[0001] [Figure 1] It is a block diagram showing a memory system. [Figure 2] It is a schematic diagram showing the electrical environment of a common data strobe connected to a plurality of devices. [Figure 3] It is a block diagram showing a write data strobe calibration circuit. [Figure 4] It is a block diagram showing a read data strobe calibration circuit. [Figure 5] It is a flowchart showing a method of sharing data strobe signals. [Figure 6] It is a flowchart showing a method of providing a read data strobe. [Figure 7] It is a flowchart showing a method of transmitting data to a plurality of memory devices using a common write data strobe. [Figure 8] It is a block diagram of a processing system.

Modes for Carrying Out the Invention

[0002] In one embodiment, a plurality (e.g., four) of memory devices on a module are connected to a common pair of differential data strobe signal conductors. The common pair of differential data strobe conductors is also coupled to a memory controller to time the transmission of data to the plurality of memory devices and to time the reception of data from the memory devices. The controller calibrates two or more different data transmission delays for the transmission of the write data strobe signal on the common pair of differential data strobe conductors. The controller also calibrates to account for two or more different data reception delays (skew) for the reception of the read data strobe signal on the common pair of differential data strobe conductors.

[0003] Figure 1 is a block diagram of a memory system. In Figure 1, the memory system 100 comprises a controller 110 and a module 120. Module 120 includes a substrate 121 and memory devices 130a to 130d. Module 120 may include additional memory devices, data buffer devices, and / or registered clock driver (RCD) devices not shown in Figure 1. Memory devices 130a and 130c are located on the first side (e.g., the bottom in Figure 1) of the substrate 121. Memory devices 130b and 130d are located on the second side (e.g., the top in Figure 1) of the substrate 121. In one embodiment, memory devices 130a to 130d are dynamic random access memory (DRAM) devices.

[0004] Controller 110 is operably coupled to module 120 via data (DQ) signals and at least one data strobe signal DQS. In one embodiment, the data strobe signal DQS is carried using differential signaling and two signal conductors. The DQ signal is carried using single-ended signaling and each is carried using a single signal conductor. In Figure 1, the data strobe signals DQS are operably coupled to each memory device 130a-130d. Data signals DQ[1:0] to / from controller 110 are operably coupled to memory device 130a. Data signals DQ[3:2] to / from controller 110 are operably coupled to memory device 130c. Data signals DQ[5:4] to / from controller 110 are operably coupled to memory device 130d. Data signals DQ[7:6] to / from controller 110 are operably coupled to memory device 130b. Additional data signals to and from controller 110 (e.g., DQ[9:8] or DQ[19:8]) can be operably coupled to additional memory devices not shown in Figure 1.

[0005] As shown in the diagram, module 120 can be considered an unbuffered module. However, this is merely one example of a module type that may contain memory devices 130a to 130d. Other examples of modules include dual inline memory modules (DIMMs) such as DDR4, DDR5, etc., DIMMs, load-reducing DIMMs (LRDIMMs), register-type DIMMs (RDIMMs), fully buffered DIMMs (FB-DIMMs), unbuffered DIMMs (UDIMMs), or SO-DIMMs.

[0006] In one embodiment, the controller 110 and memory devices 130a-130d are integrated circuit type devices, commonly referred to as “chips.” The controller function of the memory controller (such as the controller function of controller 110) manages the flow of data into and out of the memory devices and / or memory modules. The memory devices 130a-130d may be standalone devices or may comprise multiple memory integrated circuit dies, such as components of a multi-chip module. The memory controller may be a separate standalone chip or may be integrated into another chip. For example, the memory controller may be contained on a single die with a microprocessor or may be contained as part of a more complex integrated circuit system, such as a system-on-a-chip (SOC) block.

[0007] To coordinate the timing of the reception of data DQ[7:0] by memory devices 130a to 130d, controller 110 transmits a common write data strobe signal DQS to memory devices 130a to 130d in conjunction with data DQ[7:0]. To coordinate the timing of the reception of data DQ[7:0] by controller 110, one of the memory devices 130a to 130d transmits a data strobe signal DQS in conjunction with data DQ[7:0], which is used by controller 110 as a common read data strobe for memory devices 130a to 130d.

[0008] Since memory devices 130a to 130d may have different delays from the controller 110 to each of the memory devices 130a to 130d, the controller 110 may transmit different groups of data DQ[7:0] at different times (i.e., different delays) to the transmitted write data strobe signal DQS that accompanies the data DQ[7:0]. For example, the controller 110 may be configured (or calibrated) to transmit data signals DQ[1:0] and DQ[7:6] to memory devices 130a and 130b, respectively, with a first delay to the DQS signal, and to transmit data signals DQ[3:2] and DQ[5:4] to memory devices 130c and 130d, respectively, with a second delay to the DQS signal that is not equal to the first delay. In one embodiment, with respect to the DQS signal, the delay from the controller 110 to the memory devices 130a to 130b in response to the DQS signal is smaller than the delay from the controller 110 to the memory devices 130c to 130d in response to the DQS signal, and the first delay is smaller than the second delay.

[0009] Since memory devices 130a to 130d may have different delays from each of the memory devices 130a to 130d to the controller 110, the controller 110 may receive different groups of data DQ[7:0] at different times (i.e., different delays) with respect to the received read data strobe signal DQS associated with the data DQ[7:0]. Therefore, for example, the controller 110 may be configured (or calibrated) to time the sampling of data signals DQ[1:0] and data signals DQ[7:6] from memory devices 130a and 130b, respectively, using a first delay with respect to the received read data strobe on DQS, or it may be configured (or calibrated) to time the sampling of data signals DQ[3:2] and data signals DQ[5:4] from memory devices 130c and 130d, respectively, using a second delay that is not equal to the first delay.

[0010] In one embodiment, memory devices 130a-130d may be configured to operate in a locked step, thereby transmitting each bit of the data DQ[7:0] substantially simultaneously, using a delayed locked loop timed to a clock signal (not shown in Figure 1). Furthermore, one of the memory devices 130a-130d (e.g., memory device 130d) may be configured to transmit the DQS on behalf of all memory devices 130a-130d. Thus, in this embodiment, there may be, for example, a first delay from memory devices 130a and 130b to the controller 110 for DQ[7:6] and DQ[1:0], and a second delay from memory devices 130c and 130d to DQ[3:2] and DQ[5:4], respectively, where the first and second delays are not equal. In this example, the controller 110 samples DQ[7:6], DQ[1:0], DQ[3:2], and DQ[5:4] with different delays from the DQS signal received from one of the memory devices 130a to 130d (for example, memory device 130d) that transmits the DQS signal on behalf of all of the memory devices 130a to 130d.

[0011] Figure 2 is a schematic diagram showing the electrical environment of a common data strobe connected to multiple devices. Figure 2 shows an electrical signal environment 200 similar to the DQS signal connection between the controller 110 and memory devices 130a-130d shown in Figure 1.

[0012] Figure 2 shows a controller 210 having a DQS receiver 211, a DQS transmitter 212, and DQS termination impedances 213-214. Module 220 is shown with four memory devices 230a-230d. Each memory device 230a-230d contains, respectively, DQS receivers 231a-231d, DQS transmitters 232a-232d, DQS termination impedances 233a-233d, DQS termination impedances 234a-234d, and configurations 239a-239d (e.g., configuration information in storage such as registers). Interconnections 241a-241l connect the controller DQS receiver 211 and controller DQS transmitter 212 to the DQS receivers 231a-231d and DQS transmitters 232a-232d of memory devices 230a-230d. In one embodiment, interconnections 241a to 241l may be configured in an H-tree routing topology. In one embodiment, interconnections 241a to 241l may be configured in a star-signaled routing topology (not shown in Figure 2).

[0013] In particular, interconnects 241a to 241b extend from the controller DQS receiver 211 and the controller DQS transmitter 212 to the junctions with interconnects 241f and 241d, and interconnects 241c and 241e, respectively. From these junctions, interconnects 241g to 241h extend to the junctions with interconnects 241j and 241l, and interconnects 241i and 241k, respectively. Interconnections 241a to 241b as a whole may represent the signal conductors on the controller package, printed circuit board traces (e.g., motherboard signal conductors), module connector connections, and a first section of module circuit board traces. Interconnections 241c to 241f may represent module circuit board vias connecting interconnects 241a to 241b to memory devices 230a to 230b. Interconnections 241g to 241h may represent a second section of module circuit board traces. Interconnections 241i to 241l may represent module circuit board vias connecting interconnections 241g to 241h to memory devices 230c to 230d.

[0014] In one embodiment, the controller DQS termination impedances 213-214 and the memory device DQS termination impedances 233a-233d, 234a-234d are configured with different impedance values ​​depending on whether the controller 210 is performing a write operation (i.e., DQS drive) or a read operation (i.e., DQS reception) on the memory devices 230a-230d. When the controller 210 is performing a write operation, the controller DQS termination impedances 213-214 are disconnected from the interconnects 241a-241l (i.e., very high impedance). Furthermore, when the controller 210 is performing a write operation, the DQS termination impedances 233a-233d, 234a-234d of the memory devices 230a-230d are configured to present (i.e., have) a selected termination impedance (e.g., 34Ω, 40Ω, 48Ω, 60Ω, 80Ω, 120Ω, or 240Ω, as determined by configurations 239a-239d).

[0015] When controller 210 is performing a read operation, controller DQS termination impedances 213-214 are configured to present (i.e., have) a selected termination impedance (e.g., 50Ω) connected to interconnects 241a-241l. Also, when controller 210 is performing a read operation, the DQS termination impedances 233a-233d, 234a-234d of memory devices 230a-230d are configured to be disconnected or present (i.e., have) a selected termination impedance (e.g., one of 34Ω, 40Ω, 48Ω, 60Ω, 80Ω, 120Ω, or 240Ω, as determined by configurations 239a-239d) connected to interconnects 241a-241l. In particular, in one embodiment, one of the memory devices 230a-230d that transmits the DQS signal to the controller 210 (e.g., memory device 230d) may be configured to disconnect its DQS termination impedance (e.g., DQS termination impedances 233d-234d) from the interconnects 241a-241l, while the other memory devices (e.g., memory devices 230a-230c) are configured to present (i.e., have) a selected termination impedance (e.g., one selected from 34Ω, 40Ω, 48Ω, 60Ω, 80Ω, 120Ω, or 240Ω, determined by configurations 239a-239c) connected to the interconnects 241a-241l. Tables 1 and 2 show exemplary termination configurations that may be used when memory device 230d is configured to transmit the DQS signal to the controller on behalf of memory devices 230a-230d. In Tables 1 and 2, OFF refers to a configuration in which the associated memory device DQS termination impedances 233a-233d and 234a-234d are disconnected from the interconnects 241a-241l, and RTERM refers to the configured termination impedance. [Table 1] [Table 2]

[0016] Figure 3 is a block diagram showing a write data strobe calibration circuit. In Figure 3, the memory system 300 comprises a controller 310, memory devices 330a and 330c, a nearby device data interconnect 342, far-far device data interconnects 343a to 343b, and data strobe interconnects 344a to 344d. The controller 310 may be an example of some of the circuitry and write data functions of the controller 110 and memory system 100 shown in Figure 1, and / or the controller 210 and environment 200 shown in Figure 2. For brevity and clarity, other memory devices not shown in Figure 3 may be included in the memory system 300.

[0017] The controller 310 includes a data strobe transmitter 312, a nearby device data transmitter 315a, a far-field device data transmitter 315b, a nearby delay 316a, a far-field delay 316b, and a control circuit 318. The control circuit 318 includes configuration information 319 (e.g., configuration information in a storage device such as a register). The differential output of the data strobe transmitter 312 is operably coupled to the first terminals of the data strobe interconnects 344a to 344b. The second terminals of the data strobe interconnects 344a to 344b are operably coupled to the first terminals of the data strobe interconnects 344c to 344d and the inputs of the data strobe (DQS) tree 336a. The second terminals of the data strobe interconnects 344c to 344d are operably coupled to the inputs of the DQS tree 336c. In one embodiment, interconnections 344c to 344d represent the difference in propagation time between interconnections 344a to 344b to memory devices 330a that are close to the data strobe transmitter 312, and interconnections 344a to 344d to memory devices 330c that are farther from the data strobe transmitter 312.

[0018] The output of the nearby device data transmitter 315a is operably coupled to the first terminal of the nearby device data interconnect 342, and the input of the nearby device data transmitter 315a is operably coupled to the nearby delay 316a. The output of the far device data transmitter 315b is operably coupled to the first terminal of the far device data interconnects 343a to 343b, and the input of the far device data transmitter 315b is operably coupled to the far delay 316b. The nearby delay 316a is operably coupled to the control circuit 318, enabling the control circuit 318 to adjust the timing of the data transmitted by the nearby device data transmitter 315a in relation to the data strobe signal transmitted by the data strobe transmitter 312. The far delay 316b is operably coupled to the control circuit 318, enabling the control circuit 318 to adjust the timing of the data transmitted by the far device data transmitter 315b in relation to the data strobe signal transmitted by the data strobe transmitter 312.

[0019] Memory devices 330a and 330c each include receivers (also known as samplers) 335a and 335c, respectively. Memory devices 330a and 330c each include data strobe (DQS) trees 336a and 336c, respectively. The output of DQS tree 336a is operably coupled to the timing reference input of receiver 335a to control (e.g., set) the timing at which receiver 335a samples its data input. The output of DQS tree 336c is operably coupled to the timing reference input of receiver 335c to control (e.g., set) the timing at which receiver 335c samples its data input.

[0020] Data input to the receiver 335a is operably coupled to the second terminal of the interconnection 342 to receive data transmitted by the nearby device data transmitter 315a via the interconnection 342. Data input to the receiver 335c is operably coupled to the second terminal of the interconnection 343b to receive data transmitted by the remote device data transmitter 315b via the interconnections 343a - 343b. In one embodiment, the interconnection 343b represents the difference in propagation time between the interconnection 342 from the nearby device data transmitter 315a to the nearby memory device 330a and the interconnections 343a - 343b from the remote device data transmitter 315b to the remote memory device 330c.

[0021] In one embodiment, the control circuit 318 may determine, for example, during an initial calibration period, the propagation delay (e.g., due to the interconnection 342) between the output of the nearby device data transmitter 315a and the data input of the receiver 335a via a calibration process. The control circuit 318 may also determine, for example, during an initial calibration period, the propagation delay (e.g., due to the interconnections 343a - 343b) between the output of the remote device data transmitter 315b and the data input of the receiver 335c via a calibration process. These propagation delays can be determined (e.g., measured) with respect to the data strobe signals transmitted by the data strobe transmitter 312 via the interconnections 344a - 344d. Thus, the propagation delay from the nearby device data transmitter 315a to the input of the data receiver 335a can be based on the propagation delays of the interconnections 344a - 344b. Similarly, the propagation delay from the remote device data transmitter 315b to the input of the data receiver 335c can be based on the propagation delays of the interconnections 344a - 344b and the interconnections 344c - 344d. These measured propagation delays (or delay differences) may be stored in the control circuit 318 as the configuration information 319.

[0022] In one embodiment, the configuration information 319 is used by the control circuit 318 to control the amount of delay provided by the near delay 316a and the far delay 316b. The delays provided by the near delay 316a and the far delay 316b allow the controller 310 to transmit different groups of data (e.g., data transmitted by the near device data transmitter 315a and far data transmitted by the far device data transmitter 315b) at different times with respect to the data strobe signals transmitted by the data strobe transmitter 312 that are associated with the data transmitted by the near device data transmitter 315a and the data transmitted by the far device data transmitter 315b. Thus, for example, the controller 310 can use the configuration information 319 to transmit data signals to the near memory device 330a and the far memory device 330c with different first and second delays, respectively, using the near delay 316a and the far delay 316b.

[0023] In one embodiment, the configuration information 319 is stored by a serial presence detect (SPD) device (not shown in FIG. 3) and received by the controller 310 from the serial presence detect (SPD) device. In another embodiment, the configuration information 319 is stored by a host device or a host system (not shown in FIG. 3) and received by the controller 310 from the host device or the host system.

[0024] Figure 4 is a block diagram showing a read data strobe calibration circuit. In Figure 4, the memory system 400 comprises a controller 410, memory devices 430a and 430c, a nearby device data interconnect 442, far-far device data interconnects 443a to 443b, data strobe interconnects 444a to 444d, and clock signal interconnects 445a to 445b. The controller 410 may be an example of some of the circuitry and read data functions of the controller 110 and memory system 100 shown in Figure 1, and / or the controller 210 and environment 200 shown in Figure 2, and / or the controller 310 and memory system 300 shown in Figure 3. For brevity and clarity, other memory devices not shown in Figure 4 may be included in the memory system 400.

[0025] The controller 410 includes a data strobe receiver 411, a nearby device data receiver 415a, a far-field device data receiver 415b, nearby skew compensation 417a, far-field skew compensation 417b, a clock signal transmitter 413, and a control circuit 418. The control circuit 418 includes configuration information 419. The differential input of the data strobe receiver 411 is operably coupled to the first terminals of the data strobe interconnects 444a to 444b. The second terminals of the data strobe interconnects 444a to 444b are operably coupled to the first terminals of the data strobe interconnects 444c to 444d and the output of the data strobe (DQS) transmitter 437a. The second terminals of the data strobe interconnects 444c to 444d are operably coupled to the DQS transmitter 437c. In one embodiment, interconnections 444c to 444d represent the difference in propagation time between interconnections 444a to 444b from the data strobe receiver 411 to the nearby memory device 430a and interconnections 444a to 444d from the data strobe receiver 411 to the far memory device 430c.

[0026] The input of the nearby device data receiver 415a is operably coupled to the first terminal of the nearby device data interconnect 442. The timing reference input of the nearby device data receiver 415a is operably coupled to the nearby skew compensation 417a. The input of the far device data receiver 415b is operably coupled to the first terminal of the far device data interconnects 443a to 443b. The timing reference input of the far device data receiver 415b is operably coupled to the far skew compensation 417b. The nearby skew compensation 417a is operably coupled to the control circuit 418, which enables the control circuit 418 to adjust the timing of the data received by the nearby device data receiver 415a with respect to the data strobe signal received by the data strobe receiver 411. The far-field skew compensation 417b is operably coupled to the control circuit 418, enabling the control circuit 418 to adjust the timing of the data received by the far-field device data receiver 415b with respect to the data strobe signal received by the data strobe receiver 411.

[0027] Memory devices 430a and 430c each include transmitters (also known as drivers) 435a and 435c, respectively. Memory device 430a includes a delayed-locked loop 436a, a data strobe transmitter 437a, and configuration information 439a (e.g., configuration information in storage such as registers). Memory device 430c includes a delayed-locked loop 436c, a data strobe transmitter 437c, and configuration information 439c. DLLs 436a and 436c are operably coupled to the timing reference inputs of transmitters 435a and 435c, respectively. DLLs 436a and 436c are operably coupled to the timing reference inputs of DQS transmitters 437a and 437c, respectively. Configuration information 439a is operably coupled to DQS transmitters 437a and DLLs 436a. Configuration information 439c is operably coupled to the DQS transmitter 437c and DLL436c.

[0028] The output of DQS transmitter 437a is operably coupled to the second terminals of interconnects 444a to 444b, providing a timing reference signal to the input of DQS receiver 411 via interconnects 444a to 444b when memory device 430a is configured accordingly by configuration information 439a. This timing reference signal provides a timing reference for receivers 415a to 415b to sample their respective data inputs after skew compensation by skew compensation 417a to 417b. The output of DQS transmitter 437c is operably coupled to the second terminals of interconnects 444c to 444d, providing a timing reference signal to the input of DQS receiver 411 via interconnects 444a to 444d when memory device 430c is configured accordingly by configuration information 439c. This timing reference signal provides a timing reference for receivers 415a to 415b to sample their respective data inputs after skew compensation by skew compensation 417a to 417b.

[0029] The data output of the nearby device data transmitter 435a is operably coupled to a second terminal of interconnect 442 to transmit data to be received by the nearby data receiver 415a via interconnect 442. The data output of the far-away device data transmitter 435c is operably coupled to a second terminal of interconnect 443b to transmit data to be received by the far-away data receiver 415b via interconnects 443a to 443b. In one embodiment, interconnect 443b represents the difference in propagation time between the interconnect 442 from the nearby data receiver 415a to the nearby memory device 430a and the interconnects 443a to 443b from the far-away data receiver 415b to the far-away memory device 430c.

[0030] The output of the clock signal transmitter 413 is operably coupled to the first terminal of the clock signal interconnect 445a. The second terminal of the clock signal interconnect 445a is operably coupled to the delay-locked loop (DLL) 436a of the memory device 430a and the first terminal of the clock signal interconnect 445b. The second terminal of the clock signal interconnect 445b is operably coupled to the DLL 436c of the memory device 430c. In one embodiment, interconnect 445b represents the difference in propagation time between the propagation time from the clock signal transmitter 413 to the nearby memory device 430a via interconnect 445a and the propagation time from the clock signal transmitter 413 to the distant memory device 430c via interconnects 445a-445b.

[0031] In one embodiment, DLL436a is configured to generate a timing reference signal for data transmitter 435a and DQS transmitter 437a based on a clock signal transmitted by clock signal transmitter 413. DLL436c is configured to generate a timing reference signal for data transmitter 435c and DQS transmitter 437c based on a clock signal transmitted by clock signal transmitter 413. In one embodiment, DLL436a and DLL436c are configured to provide matching timing reference signals. In other words, DLL436a and DLL436c are configured to provide timing reference signals to data transmitter 435a and data transmitter 435c, respectively, so that both data transmitter 435a and data transmitter 435c initiate transitions substantially simultaneously. Similarly, DLL436a and DLL436c are configured to provide timing reference signals to DQS transmitters 437a and 437c, respectively, so that both DQS transmitters 437a and 437c initiate the transition substantially simultaneously, if both are configured to transmit. However, in one embodiment, only one of DQS transmitters 437a and 437c is configured with configuration information 439a and 439c, respectively, to transmit a data strobe signal to the data strobe receiver 411.

[0032] The data strobe signal transmitted by one of the DQS transmitters 437a or 437c is received by the data strobe receiver 411. The data strobe receiver 411 is operably coupled to near-neighbor skew compensation 417a and far-far skew compensation 417b. Near-neighbor skew compensation 417a is operably coupled to the timing reference input of the near-neighbor data receiver 415a to control the timing at which the near-neighbor data receiver 415a samples the signal presented to the input of the near-neighbor data receiver 415a by the interconnect 442. Far-far skew compensation 417b is operably coupled to the timing reference input of the far-far data receiver 415b to control the timing at which the far-far data receiver 415b samples the signal presented to the input of the far-far data receiver 415b by the interconnect 443a.

[0033] In one embodiment, the control circuit 418 may, for example, determine the difference in arrival times of transitions received via the nearby data receiver 415a and the data strobe receiver 411 through a calibration process during the initial calibration period. Similarly, the control circuit 418 may, for example, determine the difference in arrival times of transitions received via the far receiver 415b and the data strobe receiver 411 through a calibration process during the initial calibration period. These measured differences in arrival times may be stored in the control circuit 418 as configuration information 419.

[0034] In one embodiment, configuration information 419 is used by a control circuit 418 to control the amount of delay provided by the near-neighbor skew compensation 417a and the far-field skew compensation 417b. The delay (or skew compensation) provided by the near-neighbor skew compensation 417a and the far-field skew compensation 417b allows the controller 410 to receive different groups of data (e.g., data received by data receiver 415a and data received by data receiver 415b) at different times with respect to the data strobe signal received by the data strobe receiver 411, with respect to the data received by the data receiver 415a and the data received by the data receiver 415b. Thus, for example, the controller 410 can use the configuration information 419 to receive data signals from the near-neighbor memory device 430a and data signals from the far-field memory device 430c with unequal first skew compensation (delay) and second skew compensation, respectively, using the near-neighbor skew compensation 417a and the far-field skew compensation 417b.

[0035] In one embodiment, the configuration information 419 is stored by a serial presence detection (SPD) device (not shown in Figure 4) and received from the serial presence detection (SPD) device by the controller 410. In another embodiment, the configuration information 419 is stored by a host device or host system (not shown in Figure 4) and received from the host device or host system by the controller 410.

[0036] Figure 5 is a flowchart illustrating how data strobe signals are shared. One or more steps shown in Figure 5 may be performed, for example, by memory system 100, environment 200, memory system 300, memory system 400, and / or their components. The memory controller transmits a first data strobe signal to multiple memory devices via a single pair of signal conductors (502). For example, controller 310 (and in particular DQS transmitter 312) may transmit a write data strobe signal to memory device 330a and memory device 330c (and possibly other memory devices) via a pair of signal conductors of interconnect 344a-344d. The memory controller transmits first data, timed according to the first data strobe signal, to multiple memory devices (504). For example, the controller 310 can transmit data to the memory device 330a via the nearby device data transmitter 315a, and transmit data to the memory device 330c via the far device data transmitter 315b, along with the data strobe signals transmitted by the data strobe transmitter 312, which are appropriately aligned with the data strobe signals transmitted by the data strobe transmitter 312, due to the nearby delay 316a and the far delay 316b.

[0037] The memory controller receives a second data strobe signal from a first memory device among the multiple memory devices via a single pair of signal conductors (506). For example, controller 410 (and in particular, DQS receiver 411) may receive a read data strobe signal from one of memory devices 430a and 430c (e.g., memory device 430c) via a pair of signal conductors of interconnects 444a to 444d. The memory controller receives second data from the multiple memory devices, timed according to the second data strobe signal (508). For example, the controller 410 can receive data from memory device 430a via the nearby data receiver 415a along with the data strobe signal transmitted by the DQS transmitter 437c of memory device 430c, and can receive data from memory device 430c via the far data receiver 415b. The data sampling by the nearby data receiver 415a is appropriately aligned with the received data strobe signal by nearby skew compensation 417a, and the data sampling by the far data receiver 415b is appropriately aligned with the received data strobe signal by far skew compensation 417b.

[0038] Figure 6 is a flowchart illustrating how to provide a read data strobe. One or more steps shown in Figure 6 may be performed, for example, by memory system 100, environment 200, memory system 300, memory system 400, and / or their components. A first memory device among a plurality of memory devices is configured to provide a data strobe signal to a memory controller on a pair of signal conductors connected to other memory devices among the plurality of memory devices in response to a read command (602). For example, memory device 430c may be configured by configuration information 439c to provide a read data strobe signal on interconnects 444a-444d to a controller 410 in response to a read command, if both memory devices 430a and 430c are connected to interconnects 444a-444d.

[0039] In response to a read command, one of the memory devices is configured not to provide a data strobe signal on a single pair of signal conductors (604). For example, any other memory device connected to memory device 430a and interconnects 444a-444d may be configured (e.g., by configuration information 439a) not to provide a read data strobe signal on interconnects 444a-444d to the controller 410 in response to a read command, if both memory devices 430a and 430c are connected to interconnects 444a-444d. The memory controller sends a read command to the multiple memory devices (606). For example, the memory controller 410 can send a read command via the command / address bus to all memory devices connected to interconnects 444a-444d (e.g., memory devices 430a and 430c).

[0040] The memory controller receives data associated with a first read command from each of a plurality of memory devices, whose timing is coordinated according to a first data strobe signal transmitted by a first memory device among the plurality of memory devices (608). For example, controller 410 can receive data from memory device 430a via nearby data receiver 415a, along with a data strobe signal transmitted by the DQS transmitter 437c of memory device 430c, and receive data from memory device 430c via far device data receiver 415b, wherein the sampling of data by nearby data receiver 415a is appropriately aligned with the received data strobe signal by nearby skew compensation 417a, and the sampling of data by far data receiver 415b is appropriately aligned with the received data strobe signal by far skew compensation 417b.

[0041] Figure 7 is a flowchart illustrating a method for transmitting data to multiple memory devices using a common write data strobe. One or more steps shown in Figure 7 may be performed, for example, by memory system 100, environment 200, memory system 300, memory system 400, and / or their components. A first data transmitter of a memory controller connected to a first memory device is configured with a first delay relative to the data strobe transmitter of a memory controller connected to a single pair of signal conductors connected to the first and second memory devices (702). For example, a neighbor device data transmitter 315a of controller 310 may be configured with a neighbor delay 316a under the control of a control circuit 318 and configuration information 319, having a first delay relative to the data strobe signal transmitted to memory devices 330a and 330c by data strobe transmitter 312 via interconnects 344a-344d.

[0042] The second data transmitter of the memory controller connected to the second memory device is configured with a second delay relative to the data strobe transmitter of the memory controller (704). For example, the remote device data transmitter 315b of controller 310 may be configured with a remote delay 316b under the control of the control circuit 318 and configuration information 319, which has a second delay relative to the data strobe signals transmitted by the data strobe transmitter 312 to memory devices 330a and 330c via interconnects 344a to 344d. A first write command is transmitted to the first and second memory devices (706). For example, controller 310 may transmit the write command to memory devices 330a and 330c via the command / address bus.

[0043] The first data is transmitted to the first memory device using a first delay relative to the first data strobe signal (708). For example, the controller 310 and the nearby device data transmitter 315a may transmit data to the memory device 330a using a delay relative to the data strobe provided by the data strobe transmitter 312, in particular based on the delay determined by the nearby delay 316a. The second data is transmitted to the second memory device using a second delay relative to the first data strobe signal (710). For example, the controller 310 and the far-field device data transmitter 315b may transmit data to the memory device 330c using a delay relative to the data strobe provided by the data strobe transmitter 312, in particular based on the delay determined by the far-field delay 316b.

[0044] Data strobe (DQS) signals are described and shown herein as using differential signaling and interconnects. However, it should be understood that this is merely an illustrative configuration. The data strobes described herein (e.g., data strobe (DQS) transmitters 212, 232a-232d, 312, 437a, and 437c, data strobe receivers 211, 231a-231c, and 411, and DQS trees 336a, 336c) and associated interconnects may use single-ended signaling configurations.

[0045] The methods, systems, and devices described above may be implemented in a computer system or stored by a computer system. The methods described above may also be stored in a non-temporary computer-readable medium. The devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art and may be embodied by computer-readable files containing software descriptions of such circuits. These include, but are not limited to, one or more elements of memory system 100, environment 200, memory system 300, and memory system 400, as well as their components. These software descriptions may be descriptions at the behavior, register transfer, logic component, transistor, and layout geometry levels. Furthermore, the software descriptions may be stored in a storage medium or communicated by carrier waves.

[0046] Data formats in which such descriptions can be implemented include, but are not limited to, formats supporting behavioral languages ​​such as C, formats supporting register transfer level (RTL) languages ​​such as Verilog and VHDL, formats supporting geometry description languages ​​(such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Furthermore, data transfer of such files on machine-readable media can be carried out electronically via various media on the Internet or, for example, via email. It should be noted that physical files can be implemented on machine-readable media such as 4mm magnetic tape, 8mm magnetic tape, 3-1 / 2 inch floppy disks, CDs, and DVDs.

[0047] Figure 8 is a block diagram showing one embodiment of a processing system 800 for processing or generating, including a representation of a circuit component 820. The processing system 800 includes one or more processors 802, a memory 804, and one or more communication devices 806. The processors 802, the memory 804, and the communication devices 806 communicate using any preferred type, number, and / or configuration of wired and / or wireless connections 808.

[0048] The processor 802 executes instructions of one or more processes 812 stored in memory 804 to process and / or generate circuit components 820 in response to user input 814 and parameters 816. Process 812 may be any suitable electronic design automation (EDA) tool or part thereof used to design, simulate, analyze, and / or verify electronic circuits, and / or generate photomasks for electronic circuits. Representation 820 includes data describing all or part of memory system 100, environment 200, memory system 300, and memory system 400, as well as their components, as shown in the figure.

[0049] Representation 820 may include one or more descriptions at the behavior, register transfer, logic component, transistor, and layout geometry levels. Furthermore, representation 820 may be stored in a storage medium or communicated by carrier wave.

[0050] Data formats in which Representation 820 can be implemented include, but are not limited to, formats supporting behavioral languages ​​such as C, formats supporting register transfer level (RTL) languages ​​such as Verilog and VHDL, formats supporting geometry description languages ​​(such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Furthermore, data transfer of such files on machine-readable media can be carried out electronically via various media on the Internet or, for example, via email.

[0051] User input 814 may include input parameters from a keyboard, mouse, voice recognition interface, microphone and speaker, graphic display, touchscreen, or other type of user interface device. This user interface may be distributed across multiple interface devices. Parameters 816 may include specifications and / or characteristics that are input to help define the representation 820. For example, parameters 816 may include information that defines the device type (e.g., NFET, PFET, etc.), topology (e.g., block diagram, circuit description, schematic diagram, etc.), and / or device description (e.g., device characteristics, device dimensions, power supply voltage, simulated temperature, simulated model, etc.).

[0052] The memory 804 includes any preferred type, number, and / or configuration of non-temporary computer-readable storage media for storing the process 812, user input 814, parameters 816, and circuit components 820.

[0053] The communication device 806 includes any preferred type, number, and / or configuration of wired and / or wireless devices for transmitting information from the processing system 800 to another processing or storage system (not shown) and / or receiving information from another processing or storage system (not shown). For example, the communication device 806 may transmit a circuit component 820 to another system. The communication device 806 can receive the process 812, user input 814, parameter 816, and / or circuit component 820, and cause the process 812, user input 814, parameter 816, and / or circuit component 820 to be stored in the memory 804.

[0054] The implementations discussed herein include, but are not limited to, the following examples:

[0055] Example 1: A memory controller comprising: a data interface for communicating data with at least two distinct memory devices, each including at least two distinct data signals; and a data strobe interface for transmitting a first data strobe signal to the at least two distinct memory devices during a write operation, providing a first timing for the at least two distinct data signals; and receiving a second data strobe signal from a first memory device among the at least two distinct memory devices, providing the memory controller with a second timing for the at least two distinct data signals.

[0056] Example 2: The memory controller according to Example 1, further comprising a circuit that configures the first memory device to provide the second data strobe signal to the memory controller.

[0057] Example 3: The first data strobe signal is transmitted during a write operation by the memory controller described in Example 1.

[0058] Example 4: The second data strobe signal is transmitted during a read operation by the memory controller described in Example 2.

[0059] Example 5: The memory controller according to Example 2, wherein the second memory device of the at least two separate memory devices provides an on-die termination impedance to the second data strobe signal while the first memory device is transmitting the second data strobe signal.

[0060] Example 6: The memory controller according to Example 1, further comprising a circuit that configures the at least two separate memory devices to calibrate the skew between the first data strobe signal and the at least two separate data signals.

[0061] Example 7: The memory controller according to Example 1, wherein the data strobe interface communicates the first data strobe signal and the second data strobe signal with the at least two separate memory devices via an H-tree signal routing topology.

[0062] Example 8: The memory controller according to Example 1, wherein the data strobe interface communicates the first data strobe signal and the second data strobe signal with the at least two separate memory devices via a star signal routing topology.

[0063] Example 9: The memory controller described in Example 1, further comprising a circuit that constitutes the on-die termination impedance of at least two separate memory devices.

[0064] Example 10: A memory controller comprising a data strobe interface for transmitting a first data strobe signal to a plurality of memory devices via a single pair of signal conductors, and a data interface for transmitting first data whose timing has been adjusted by the first data strobe signal to the plurality of memory devices.

[0065] Example 11: The memory controller according to Example 10, wherein the data strobe interface receives a second data strobe signal from a first memory device among the plurality of memory devices via the single pair of signal conductors, and the data interface receives second data from the plurality of memory devices that is timed according to the second data strobe signal.

[0066] Example 12: The memory controller according to Example 11, further comprising a first circuit constituting the first memory device among the plurality of memory devices to provide the second data strobe signal to the memory controller via the single pair of signal conductors.

[0067] Example 13: The memory controller according to Example 12, further comprising a second circuit that constitutes the on-die termination impedance of the plurality of memory devices.

[0068] Example 14: The memory controller according to Example 13, wherein while the first memory device among the plurality of memory devices transmits the second data strobe signal, the second memory device among the plurality of memory devices presents the on-die termination impedance to the pair of signal conductors.

[0069] Example 15: The memory controller according to Example 14, further comprising a third circuit that configures the plurality of memory devices to calibrate the skew between the first data strobe signal and the first data.

[0070] Example 16: A method comprising the steps of: transmitting a first data strobe signal to a plurality of memory devices via a single pair of signal conductors by a memory controller; and transmitting first data to the plurality of memory devices that is timed according to the first data strobe signal by the memory controller.

[0071] Example 17: The method of Example 16, further comprising the steps of: the memory controller receiving a second data strobe signal from a first memory device among the plurality of memory devices via the pair of signal conductors; and the memory controller receiving second data from the plurality of memory devices that is timed according to the second data strobe signal.

[0072] Example 18: The method of Example 17, further comprising the step of configuring the first memory device among the plurality of memory devices to provide the second data strobe signal to the memory controller via the pair of signal conductors.

[0073] Example 19: The method according to claim 18, further comprising the step of configuring the on-die termination impedance that the plurality of memory devices present to the pair of signal conductors.

[0074] Example 20: The method according to Example 19, wherein while the first memory device among the plurality of memory devices transmits the second data strobe signal, the second memory device among the plurality of memory devices presents the on-die termination impedance to the pair of signal conductors.

[0075] The above description of the present invention is presented for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit the invention to the exact form disclosed, and other modifications and variations may be possible in light of the above teachings. The implementations have been selected and described to best illustrate the principles of the invention and its practical applications, so that those skilled in the art can make the most of the invention in various embodiments and modifications suitable for the specific use to be intended. The appended claims are intended to be construed to include other alternative embodiments of the invention, unless limited by the prior art.

Claims

1. It is a memory controller, A data interface that includes at least two distinct data signals and communicates data with at least two distinct memory devices, A data strobe interface for transmitting a first data strobe signal to at least two separate memory devices during a write operation, providing a first timing for the at least two separate data signals, and receiving a second data strobe signal from the first of the at least two separate memory devices to the memory controller, providing a second timing for the at least two separate data signals. A memory controller wherein the data interface is configured to receive data from the first memory device in a first timing adjustment based on the second data strobe signal, and to receive data from the second memory device among the at least two separate memory devices in a second timing adjustment different from the first timing adjustment based on the second data strobe signal.

2. The memory controller according to claim 1, wherein the first data strobe signal is transmitted during a write operation.

3. The memory controller according to claim 1, wherein the second data strobe signal is transmitted during a read operation.

4. The memory controller according to claim 1, further comprising a DQS termination impedance circuit configured to present a DQS termination impedance to the data strobe interface while the first memory device is transmitting the second data strobe signal to the data strobe interface.

5. A first skew compensation circuit that adjusts the timing of data received from the first memory device by the data interface as a first timing adjustment based on the second data strobe signal, The memory controller according to claim 1, further comprising: a second skew compensation circuit that adjusts the timing of data received by the data interface from a second memory device among the at least two separate memory devices as a second timing adjustment based on the second data strobe signal.

6. The memory controller according to claim 1, wherein the data strobe interface communicates the first data strobe signal and the second data strobe signal with the at least two separate memory devices via an H-tree signal routing topology.

7. The memory controller according to claim 1, wherein the data strobe interface communicates the first data strobe signal and the second data strobe signal with the at least two separate memory devices via a star signal routing topology.

8. The memory controller according to claim 1, further comprising a circuit that constitutes a DQS termination impedance configured to disconnect the DQS termination impedance of the data strobe interface while the data strobe interface is transmitting the first data strobe signal to the at least two separate memory devices.

9. It is a memory controller, A data strobe interface that transmits a first data strobe signal to multiple memory devices via a single pair of signal conductors, The system includes a data interface that transmits first data, whose timing has been adjusted by the first data strobe signal, to the plurality of memory devices, The data strobe interface receives a second data strobe signal from a first memory device among the plurality of memory devices via the pair of signal conductors. A memory controller configured such that the data interface receives second data from the first memory device with a first timing adjustment based on the second data strobe signal, and receives second data from a second memory device among the plurality of memory devices with a second timing adjustment different from the first timing adjustment based on the second data strobe signal.

10. The memory controller according to claim 9, further comprising a DQS termination impedance circuit configured to present a DQS termination impedance to the data strobe interface while the first memory device is transmitting the second data strobe signal to the data strobe interface.

11. The memory controller according to claim 9, further comprising a DQS termination impedance circuit configured to disconnect the DQS termination impedance of the data strobe interface while the data strobe interface is transmitting the first data strobe signal to the plurality of memory devices.

12. A first skew compensation circuit that adjusts the timing of the second data received from the first memory device by the data interface as the first timing adjustment based on the second data strobe signal, The memory controller according to claim 9, further comprising: a second skew compensation circuit that adjusts the timing of second data received by the data interface from a second memory device among the plurality of memory devices as a second timing adjustment based on the second data strobe signal.

13. It is a method, The memory controller transmits a first data strobe signal to multiple memory devices via a pair of signal conductors. The memory controller transmits first data, time-adjusted according to the first data strobe signal, to the plurality of memory devices. The memory controller receives a second data strobe signal from a first memory device among the plurality of memory devices via the pair of signal conductors. The memory controller receives second data from the plurality of memory devices, which has been timed according to the second data strobe signal. A method comprising the step of configuring the first memory device among the plurality of memory devices to provide the second data strobe signal to the memory controller via the pair of signal conductors.

14. The method according to claim 13, further comprising the step of configuring the on-die termination impedance that the plurality of memory devices present to the pair of signal conductors.

15. The method according to claim 14, wherein while the first memory device among the plurality of memory devices is transmitting the second data strobe signal, the second memory device among the plurality of memory devices presents the on-die termination impedance to the pair of signal conductors.

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