A heterogeneous control circuit based on spiking neural networks
By introducing a highly versatile peripheral interface, a sub-instruction receiving module, an instruction buffer, and an instruction lock module into the heterogeneous control circuit of the pulse neural network, the problems of low flexibility and parallelism are solved, and efficient instruction sending and system flexibility are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2024-02-29
- Publication Date
- 2026-06-26
Smart Images
Figure CN118194941B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of spiking neural network hardware technology, specifically relating to a heterogeneous control circuit based on spiking neural networks. Background Technology
[0002] Neuromorphic computing is a type of machine intelligence computing that mimics neurophysiological mechanisms through computational modeling and is achieved through hardware and software collaboration. Heterogeneous computing refers to systems that use more than one type of processor or core. These systems improve performance or energy efficiency not only by adding processors of the same type but also by adding different coprocessors, which typically combine specialized processing power to handle specific tasks. In neuromorphic computing, neuromorphic computing tasks are usually accomplished by combining heterogeneous computing systems with spiking neural network accelerators.
[0003] Existing heterogeneous control circuits for spiking neural networks have certain problems and defects:
[0004] The existing heterogeneous control circuits for spiking neural networks are limited in flexibility, as they are customized for a single model or algorithm and have a single control path. However, neuromorphic computing requires heterogeneous accelerators for spiking neural networks that can effectively adapt to various boundary conditions.
[0005] Low parallelism: Many existing heterogeneous control circuits for spiking neural networks use serial instructions, resulting in low instruction parallelism and low instruction control efficiency.
[0006] Data conflict issues are prone to occur: Even if existing heterogeneous controllers of spiking neural networks adopt parallel design to improve parallelism, they still face a large number of data conflict issues while increasing parallelism, making it difficult to improve instruction control efficiency. Summary of the Invention
[0007] To address the above problems and shortcomings, this invention provides a heterogeneous control circuit based on a spiking neural network. It expands the coprocessor instructions through a highly versatile peripheral interface and a sub-instruction receiving module, thereby improving the overall design flexibility of the heterogeneous control circuit. At the same time, this invention improves the parallelism of the overall instruction sending through a sub-instruction cache module and effectively solves the data conflict problem caused by the increase in parallelism by proposing an instruction lock module.
[0008] The technical solution of this invention is:
[0009] A heterogeneous control circuit based on a spiking neural network, such as Figure 1 As shown, it includes an instruction fetch module, an instruction cache module, a peripheral interface module, and an instruction lock module;
[0010] The instruction fetch module consists of a coprocessor main controller and a sub-instruction receiving module. The coprocessor main controller is responsible for receiving the corresponding custom instructions, pre-decoding them, and transmitting them to the corresponding sub-instruction receiving module. The number of sub-instruction receiving modules in the coprocessor is equal to the number of types configured in the high-general-purpose peripheral interface module. Pre-decoding simplifies the instruction flow and speeds up instruction reception. Combined with the instruction receiving module, it can effectively improve the parallelism of the overall instruction sending.
[0011] The instruction cache module consists of multiple asynchronous FIFO (First-In-First-Out) memories. Each instruction is configured with a sub-instruction cache module of corresponding depth according to system needs. The number of sub-instruction cache modules is equal to the number of types of peripheral modules configured. By caching the same type of instruction, the transmission efficiency of the overall heterogeneous control system can be effectively improved, and the overall instruction parallelism can be improved.
[0012] The instruction lock module consists of an instruction ID comparison submodule, an instruction sending submodule, and a flag generation module. The instruction ID comparison submodule retrieves custom instructions from the instruction cache module in parallel and compares the ID segments contained within each custom instruction with the access ID permission, generating a result. The number of custom instructions retrieved in parallel is equal to the number of peripheral module types. The instruction sending submodule sends instructions that meet the ID comparison conditions in parallel, with the number of sent instructions equal to the number of peripheral module types minus the blocking count of the flag generation module. The flag generation module generates corresponding flag bit signals and access ID permissions based on the output of the ID comparison submodule, thereby enabling the issuance and blocking of different types of instructions and effectively avoiding the risk of instruction data conflicts.
[0013] The peripheral interface module is used to transmit instructions to the connected peripheral expansion module and configure the information parameters and data storage address information of the specific peripheral. The peripheral interface module adopts a unified handshake interface, and the number and types of interfaces are configured according to the operator requirements of the actual spiking neural network. The high versatility of the peripheral interface module can improve the flexibility of the overall system.
[0014] like Figure 2 As shown, the workflow of the heterogeneous control circuit based on a spiking neural network in this invention is as follows:
[0015] 1) Clock input, providing a master clock for the system;
[0016] 2) Perform initialization configuration, instantiate and enable the corresponding sub-instruction receive buffer and peripheral modules;
[0017] 3) The instruction fetch module receives custom instructions through the coprocessor main controller and sends them to the instruction cache module;
[0018] Step 3 includes the following sub-steps:
[0019] 31) The coprocessor main controller pre-decodes the instructions and sends them to the sub-instruction receiving module;
[0020] 32) The sub-instruction receiving module stores the instruction into the corresponding sub-instruction buffer module;
[0021] 33) The sub-instruction receiving module returns the instruction return value to the outside through the main control module;
[0022] 34) If the sub-instruction buffer module is full, the corresponding sub-instruction receiving module will be blocked until the corresponding sub-storage module exits the full state, and then the sub-instruction module will continue to receive the corresponding type of instruction.
[0023] 4) The instruction lock module sends instructions in parallel based on the current state;
[0024] Step 4 includes the following sub-steps:
[0025] 41) The instruction ID comparison module preloads instructions;
[0026] 42) The flag generation module generates a pass ID permission based on the ID corresponding to the preloaded instruction in this round and generates the corresponding instruction lock flag based on the preload result;
[0027] 43) If the instruction ID is equal to the access ID, the sub-instruction sending instruction will send the corresponding instruction to the corresponding peripheral interface;
[0028] 5) The peripheral interface hands with the corresponding peripheral to complete the specific calculation operation;
[0029] 6) Repeat steps 3 and 4 until all instruction handshake operations are completed and the work is finished.
[0030] The beneficial effects of this invention are as follows: 1) This invention effectively improves the overall parallelism of instruction execution through the design of a configurable instruction fetch module and an instruction cache module; 2) This invention effectively solves the pipeline conflict problem caused by the improvement of parallelism through the design of an instruction lock module; 3) This invention can effectively realize the instruction sending combination of various spiking neural networks in the edge computing scenario of neuromorphic computing through a highly versatile peripheral interface, which can effectively improve the flexibility of the overall system. Attached Figure Description
[0031] Figure 1 This is a schematic diagram of a heterogeneous control circuit based on a spiking neural network.
[0032] Figure 2 This is the overall execution flowchart of the heterogeneous control circuit.
[0033] Figure 3 This is a flowchart of the instruction receiving process.
[0034] Figure 4This is a flowchart of the execution process for a single instruction. Detailed Implementation
[0035] The present invention will now be described in detail with reference to specific embodiments.
[0036] Example
[0037] This neuromorphic computing scenario involves 5 peripherals, each corresponding to a different instruction set. The computation requires 20 instruction rounds, each round consisting of 16 parallel instructions with IDs ranging from 0 to f in hexadecimal. The five instruction sets can be executed any number of times (non-zero) within the parallel instruction set. Different IDs indicate conflicts in the memory range accessed by the corresponding peripheral interfaces. The five instruction cache modules each have a depth of 5. The overall system will then operate as follows:
[0038] First, the instruction fetch module will poll and read instructions in the order of the five instructions, send them to the corresponding sub-receive module, and store them in the corresponding word storage module. The flowchart is as follows. Figure 3 As shown, during the receiving process, assuming that after the sub-receiving module 1 receives the full signal from the sub-storage module 1, the sub-receiving module 1 will pause receiving instruction 1, and the instruction receiving order will become the polling of instructions 2-5. If the other sub-instruction buffer modules have full signals, the same applies. If all sub-buffer modules have full signals, the receiving instruction will be blocked until the final instruction group is sent.
[0039] With all five sub-instruction cache modules being non-empty, the instruction begins its first round of preloading and sending. The execution flowchart for a single round of instructions is as follows: Figure 4 In the first round, the instruction receiving and instruction lock module control the transmission in parallel. The initial value of the instruction ID comparison module is f, which is overwritten with the ID to be executed next after preloading instructions 1-5. Simultaneously, the instruction locks for instructions 1-5 are raised. Assuming the ID of instructions 1-5 is 01101 at this time, the pass-through ID for this round of parallel instruction execution is 0. Only instructions 1 and 4 will be sent through the corresponding sub-instruction sending module, raising the send locks for instructions 1 and 4. Peripheral interface 1 and peripheral interface 4 will handshake with their respective peripherals. After the handshake, the corresponding instruction locks and send locks are lowered, and the next round of instruction loading begins. This continues until the f-th instruction in this round. At this point, instructions 1-5 are all empty instructions and will not be sent by the sub-instruction sending module. The purpose of the f-th instruction is to refresh the instruction ID of this round to the initial value f, preventing out-of-order execution between adjacent rounds. This process is repeated 20 times, after which all instructions in this heterogeneous instruction control module have been executed.
Claims
1. A heterogeneous control circuit based on a spiking neural network, characterized in that, It includes an instruction fetch module, an instruction cache module, a peripheral interface module, and an instruction lock module; The instruction fetch module consists of a coprocessor main controller and multiple sub-instruction receiving modules. The coprocessor main controller is responsible for receiving the corresponding custom instructions, pre-decoding them, and transmitting them to the corresponding sub-instruction receiving modules. The instruction cache module receives data transmitted by the instruction fetch module; the instruction cache module consists of multiple asynchronous FIFO memories, the number of which is equal to the number of sub-instruction receiving modules; each instruction is configured with a corresponding depth of sub-instruction cache module according to system needs, the number of sub-instruction cache modules is equal to the number of types of configured peripheral modules, each sub-instruction cache module is used to cache the custom instructions of a sub-instruction receiving module, and the maximum number of sub-instruction cache modules is equal to the number of sub-instruction receiving modules; The instruction lock module consists of an instruction ID comparison submodule, an instruction sending submodule, and a flag generation module. The instruction ID comparison submodule retrieves custom instructions from the instruction cache module in parallel and compares the ID segment contained within the custom instructions with the access ID permission to generate a result. The number of custom instructions retrieved in parallel is equal to the number of peripheral module types. The instruction sending submodule sends instructions that meet the ID comparison conditions in parallel. The number of instructions sent is the number of peripheral module types minus the number of blocking operations by the flag generation module. The flag generation module is used to generate corresponding flag bit signals and access ID permissions based on the output result of the ID comparison submodule, thereby realizing the issuance and blocking of different types of instructions. The peripheral interface module receives instructions sent by the instruction sending submodule, transmits instructions to the connected peripheral expansion module, and configures the information parameters and data storage address information of the specific peripheral. The peripheral interface module adopts a unified handshake interface, and the number and types of interfaces are configured according to the operator requirements of the actual spiking neural network.