Heterogeneous co-simulation method, system, device, computer equipment, readable storage medium and program product

Abstract

The application relates to a heterogeneous co-simulation method, system and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: writing an instruction message to a target monitoring area of a shared memory, wherein the shared memory can be accessed by at least one coprocessor simulation model; the coprocessor simulation model is used for responding to the instruction message and writing an instruction response message to the target monitoring area of the shared memory according to an instruction response result; the target monitoring area is a monitoring area for communication between a host processor simulation model and the coprocessor simulation model; when a second state change of the target monitoring area is detected, a first interrupt signal is triggered and a corresponding first interrupt callback function is called according to the instruction response message; wherein the second state change is caused by the instruction response message written by the coprocessor simulation model after the instruction message is processed. The method can be used in hardware design, and the efficiency of debugging and verification can be improved.

Description

Technical Field

[0001] This application relates to the field of complex system-on-a-chip technology, and in particular to a heterogeneous co-simulation method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Technology

[0002] In complex system-on-a-chip (SoC) design, the development and verification of audio coprocessor software must rely on the hardware environment of the main control processor and the coprocessor. The development cycle from design to productization for complex SoCs is generally long; if the development and verification of audio coprocessor software cannot proceed in a timely manner, it will inevitably affect the entire development cycle of the complex SoC.

[0003] In traditional technologies, software solution verification can generally only be considered after silicon, which severely restricts the timeliness of software development and solution verification, resulting in low efficiency in research and development and debugging. Summary of the Invention

[0004] Therefore, it is necessary to provide a heterogeneous co-simulation method, system, device, computer equipment, computer-readable storage medium, and computer program product that can improve efficiency in response to the above-mentioned technical problems.

[0005] Firstly, this application provides a heterogeneous co-simulation method applied to a main control processor simulation model, the method comprising:

[0006] An instruction message is written to a target monitoring region of shared memory, wherein the shared memory can be accessed by at least one coprocessor simulation model; the coprocessor simulation model is used to obtain an instruction message of the target monitoring region when a first state change of the target monitoring region of the shared memory is detected, respond to the instruction message, and write an instruction response message to the target monitoring region of the shared memory according to the instruction response result; the first state change is generated by the instruction message written by the main control processor simulation model to the target monitoring region of the shared memory; the target monitoring region is the monitoring region for communication between the main control processor simulation model and the coprocessor simulation model;

[0007] When a second state change in the target monitoring area is detected, a first interrupt signal is triggered according to the instruction response message and the corresponding first interrupt callback function is called; wherein, the second state change is generated by the instruction response message written by the coprocessor simulation model after processing the instruction message.

[0008] In one embodiment, the target monitoring area includes a first sub-region; wherein the first sub-region is an area for monitoring instruction messages and instruction response messages sent between the main control processor and the coprocessor; the step of writing instruction messages to the target monitoring area of ​​shared memory includes:

[0009] The instruction message is sent through the user layer;

[0010] The kernel driver writes the instruction message to the first sub-region; wherein, the coprocessor simulation model is used to obtain the instruction message of the first sub-region when a first state change of the first sub-region is detected, respond to the instruction message, obtain the instruction response result, and write the instruction response message to the first sub-region according to the instruction response result.

[0011] If the instruction response message corresponding to the instruction message exists in the first sub-region, it is determined that a second state change in the first sub-region has been detected;

[0012] When a second state change in the target monitoring area is detected, a first interrupt signal is triggered according to the instruction response message, and the corresponding first interrupt callback function is called, including:

[0013] When a second state change in the first sub-region is detected, the first interrupt signal is triggered according to the instruction response message and the corresponding first interrupt callback function is called.

[0014] In one embodiment, the target monitoring area further includes a second sub-region; wherein the second sub-region is the area where request messages and request-response messages are sent between the main control processor and the coprocessor; the method further includes:

[0015] When a third state change in the second sub-region is detected, a second interrupt signal is triggered according to the request message and the corresponding second interrupt callback function is called to obtain a response request message; wherein, the third state change is generated by the request message written by the coprocessor simulation model;

[0016] The response request message is written to the second sub-region; wherein, when the fourth state change of the second sub-region is detected, the coprocessor simulation model is used to trigger a third interrupt signal and call the corresponding third interrupt callback function according to the response request message in the second sub-region, and the fourth state change is generated by the request response message written by the main control processor simulation model after processing the request message.

[0017] In one embodiment, prior to writing the instruction message to the target monitoring region of the shared memory, the method further includes:

[0018] The shared memory is divided into a target monitoring area and a shared data area; wherein, the target monitoring area is used to monitor the communication between the main control processor simulation model and the coprocessor simulation model; the shared data area is used to exchange data during the communication between the main control processor simulation model and the coprocessor simulation model.

[0019] Secondly, this application provides a heterogeneous co-simulation method applied to a coprocessor simulation model, the method comprising:

[0020] When a first state change is detected in the target monitoring area of ​​the shared memory, the instruction message of the target monitoring area is acquired and responded to, and an instruction response result is obtained; wherein, the shared memory can be accessed by the main control processor simulation model; the first state change is generated by the instruction message written by the main control processor simulation model to the target monitoring area of ​​the shared memory; the target monitoring area is used as a monitoring area for communication between the main control processor simulation model and the coprocessor simulation model;

[0021] According to the instruction response result, an instruction response message is written to the target monitoring area of ​​the shared memory; wherein, when the main control processor simulation model detects a second state change in the target monitoring area, it triggers a first interrupt signal and calls the corresponding first interrupt callback function according to the instruction response message; the second state change is generated by the instruction response message written by the coprocessor simulation model after processing the instruction message.

[0022] In one embodiment, the target monitoring area includes a first sub-region; wherein the first sub-region is an area for monitoring instruction messages and instruction response messages sent between the main control processor and the coprocessor; the step of acquiring and responding to instruction messages and obtaining instruction response results when a first state change of the target monitoring area of ​​shared memory is detected includes:

[0023] When a first state change in the first sub-region is detected, the monitoring component writes a fourth interrupt signal to the target bit of the memory-mapped input / output component according to the instruction message.

[0024] The fourth interrupt signal triggers the fourth interrupt callback function corresponding to the target bit, thereby obtaining the instruction response result.

[0025] In one embodiment, the method further includes:

[0026] A request message is written to the target monitoring area of ​​the shared memory. The main control processor simulation model is used to trigger a second interrupt signal and call the corresponding second interrupt callback function according to the request message of the target monitoring area when a third state change of the target monitoring area is detected, so as to obtain a response request message; and write the response request message to the target monitoring area.

[0027] When a fourth state change is detected in the target monitoring area, a third interrupt signal is triggered based on the response request message in the target monitoring area, and the corresponding third interrupt callback function is called.

[0028] In one embodiment, the target monitoring area further includes a second sub-region; wherein the second sub-region is the area for request messages and request-response messages sent between the main control processor and the coprocessor; the step of writing a request message to the target monitoring area of ​​the shared memory includes:

[0029] A request message is written to the second sub-region, wherein the main control processor simulation model is used to trigger a second interrupt signal and call the corresponding second interrupt callback function according to the request message of the second sub-region when a third state change of the second sub-region is detected, so as to obtain a response request message; and write the response request message to the second sub-region.

[0030] When a fourth state change is detected in the target monitoring area, a third interrupt signal is triggered based on the response request message in the target monitoring area, and the corresponding third interrupt callback function is called, including:

[0031] When a fourth state change in the second sub-region is detected, a third interrupt signal is triggered based on the response request message in the second sub-region, and the corresponding third interrupt callback function is called.

[0032] In one embodiment, when a fourth state change in the second sub-region is detected, triggering a third interrupt signal and calling the corresponding third interrupt callback function based on the response request message in the second sub-region includes:

[0033] When a fourth state change in the second sub-region is detected, the monitoring component writes a third interrupt signal to the target bit of the memory-mapped input / output component according to the response request message.

[0034] The third interrupt signal triggers the third interrupt callback function corresponding to the target bit.

[0035] Thirdly, this application provides a heterogeneous collaborative simulation system, which includes a main control processor simulation model, a coprocessor simulation model, and shared memory; wherein, the interaction between the main control processor simulation model and the coprocessor simulation model is realized through the shared memory;

[0036] The main control processor simulation model is used to write instruction messages to the target monitoring area of ​​the shared memory, wherein the shared memory can be accessed by at least one coprocessor simulation model; the target monitoring area is used for communication between the main control processor simulation model and the coprocessor simulation model.

[0037] The coprocessor simulation model is used to acquire the instruction message of the target monitoring area when a first state change of the target monitoring area of ​​the shared memory is detected, respond to the instruction message, and write an instruction response message to the target monitoring area of ​​the shared memory according to the instruction response result; the first state change is generated by the instruction message written by the main control processor simulation model to the target monitoring area of ​​the shared memory.

[0038] The main control processor simulation model is also used to trigger a first interrupt signal and call the corresponding first interrupt callback function according to the instruction response message when a second state change of the target monitoring area is detected; wherein, the second state change is generated by the instruction response message written by the coprocessor simulation model after processing the instruction message.

[0039] Fourthly, this application provides a heterogeneous co-simulation device applied to a main control processor simulation model, the device comprising:

[0040] A first writing module is used to write instruction messages to a target monitoring region of shared memory, wherein the shared memory can be accessed by at least one coprocessor simulation model; the coprocessor simulation model is used to, when detecting a first state change in the target monitoring region of the shared memory, acquire the instruction message of the target monitoring region, respond to the instruction message, and write an instruction response message to the target monitoring region of the shared memory according to the instruction response result; the first state change is generated by the instruction message written by the main control processor simulation model to the target monitoring region of the shared memory; the target monitoring region is the monitoring region for communication between the main control processor simulation model and the coprocessor simulation model;

[0041] The first calling module is used to trigger a first interrupt signal and call the corresponding first interrupt callback function according to the instruction response message when a second state change of the target monitoring area is detected; wherein, the second state change is generated by the instruction response message written by the coprocessor simulation model after processing the instruction message.

[0042] Fifthly, this application provides a heterogeneous co-simulation device for use in coprocessor simulation models, the device comprising:

[0043] A response module is used to acquire and respond to the instruction message of the target monitoring area when a first state change of the target monitoring area of ​​the shared memory is detected, and to obtain an instruction response result; wherein, the shared memory can be accessed by the main control processor simulation model; the first state change is generated by the instruction message written by the main control processor simulation model to the target monitoring area of ​​the shared memory; the target monitoring area is used as a monitoring area for communication between the main control processor simulation model and the coprocessor simulation model;

[0044] The second writing module is used to write an instruction response message to the target monitoring area of ​​the shared memory according to the instruction response result; wherein, when the main control processor simulation model detects a second state change in the target monitoring area, it triggers a first interrupt signal and calls the corresponding first interrupt callback function according to the instruction response message; the second state change is generated by the instruction response message written by the coprocessor simulation model after processing the instruction message.

[0045] Sixthly, this application provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described above.

[0046] In a seventh aspect, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0047] Eighthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described method.

[0048] The aforementioned heterogeneous co-simulation methods, systems, devices, computer equipment, computer-readable storage media, and computer program products are applied to the main control processor simulation model and the coprocessor simulation model, respectively. Through software virtualization technology, a main control processor simulation model and a heterogeneous audio coprocessor simulation model are constructed. Hardware interaction is simulated using shared memory and IPC communication mechanisms, decoupling the software architecture from the hardware topology. This enables the main control processor simulation model to send instruction messages to the heterogeneous audio coprocessor simulation model, and simultaneously enables the heterogeneous audio coprocessor simulation model to send response instruction messages to the main control processor simulation model. Furthermore, it enables the heterogeneous audio coprocessor simulation model to send request messages to the main control processor simulation model, and simultaneously enables the main control processor simulation model to send response request messages to the heterogeneous audio coprocessor simulation model. On the one hand, this allows for pre-verification, enabling debugging and verification at any stage, significantly improving the development efficiency of complex on-chip systems. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is an architecture diagram of a heterogeneous co-simulation method in one embodiment;

[0051] Figure 2 This is a schematic diagram illustrating communication between the main control processor and the coprocessor IPC in one embodiment;

[0052] Figure 3 This is a flowchart illustrating the process of writing instruction messages to a target monitoring region of shared memory in one embodiment.

[0053] Figure 4 This is an architecture diagram of the main control processor simulation model in one embodiment;

[0054] Figure 5 This is an architecture diagram of a coprocessor simulation model in one embodiment;

[0055] Figure 6 This is an architecture diagram of a single-core coprocessor simulation model in one embodiment;

[0056] Figure 7 This is an architecture diagram of a multi-core coprocessor simulation model in one embodiment;

[0057] Figure 8 This is a structural block diagram of a heterogeneous co-simulation device applied to a main control processor in one embodiment;

[0058] Figure 9 This is a structural block diagram of a heterogeneous co-simulation device applied to a coprocessor in one embodiment;

[0059] Figure 10 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0061] The heterogeneous collaborative simulation method provided in this application embodiment, such as Figure 1 The diagram shows the architecture of the heterogeneous collaborative simulation method. Figure 1 The main control processor simulation model, shared memory simulation model, and coprocessor simulation model involved are all simulated in the form of computer software. That is, the structure and behavior of a hardware system are simulated and verified through software methods. Among them, the main control processor simulation model, shared memory simulation model, and coprocessor simulation model can be deployed on the same terminal device or server device, or they can be deployed on different devices.

[0062] Shared memory is used to simulate the IPC (Inter-Process Communication) mechanism between the main processor simulation model and the coprocessor simulation model, as well as the data interaction during IPC communication. Shared memory is accessible in both the main processor simulation model and the coprocessor simulation model. Furthermore, shared memory can be partitioned according to different uses, which facilitates software development and debugging.

[0063] In the main control processor simulation model, user space deploys applications, such as audio software processing programs, responsible for audio data transmission and processing in user space (also known as the user layer). Kernel space (also known as the kernel driver) is an abstraction of the underlying hardware interface, responsible for interacting with the underlying hardware, processing various instructions issued by user space (such as playing / recording), and coordinating and controlling related hardware resources to meet the requirements of the corresponding instructions. The interrupt monitoring thread simulates the high or low pull of underlying interrupt signals through the interrupt IRQ module. Its reserved memory provides fixed and predictable access entry points for shared memory. The reserved memory establishes a unified address mapping between the main control processor simulation model and shared memory.

[0064] In the coprocessor simulation model, the user space, kernel space, and underlying hardware architecture are consistent with the main controller processor simulation model. Its reserved memory establishes a unified address mapping between the coprocessor simulation model and shared memory.

[0065] In one exemplary embodiment, a heterogeneous co-simulation method is provided, which is applied to... Figure 1 Taking the main control processor simulation model as an example, the process includes: writing instruction messages to the target monitoring area of ​​shared memory; when a second state change of the target monitoring area is detected, triggering the first interrupt signal according to the instruction response message and calling the corresponding first interrupt callback function.

[0066] In this system, the shared memory can be accessed by at least one coprocessor simulation model. The coprocessor simulation model is used to acquire the instruction message of the target monitoring area when a first state change of the target monitoring area of ​​the shared memory is detected, respond to the instruction message, and write an instruction response message to the target monitoring area of ​​the shared memory according to the instruction response result. The first state change is generated by the instruction message written by the main processor simulation model to the target monitoring area of ​​the shared memory. The target monitoring area is the monitoring area for communication between the main processor simulation model and the coprocessor simulation model. The second state change is generated by the instruction response message written by the coprocessor simulation model after processing the instruction message.

[0067] Interrupt callback functions are the "entry point of the event handler" or "software simulation of the interrupt service routine" in this simulation system. Their core function is to automatically execute a predefined processing logic when the simulated interrupt signal is triggered.

[0068] Optionally, the core of the heterogeneous co-simulation method is to simulate the IPC communication mechanism between the main control processor simulation model and the coprocessor simulation model. For example, the main control processor simulation model is deployed on the host side, and the coprocessor simulation model is deployed on the device side. Figure 2 As shown, the IPC communication process between the host-side main control processor simulation model and the device-side coprocessor simulation model is described.

[0069] The main processor simulation model simulates writing instruction messages to the target monitoring area of ​​shared memory, such as playing audio or video, recording, or pausing audio or video playback; the instruction messages instruct the coprocessor simulation model to execute. Audio data is also written to the target monitoring area simultaneously. After the main processor simulation model simulates writing instruction messages to the target monitoring area of ​​shared memory, the target monitoring area changes. The coprocessor simulation model obtains the instruction messages and audio data from the target monitoring area, processes the audio data to respond to the instruction messages, obtains the response results, and writes instruction response messages to the target monitoring area of ​​shared memory based on the instruction response results; for example, writing "playback ready" to the target monitoring area.

[0070] The monitoring interrupt status thread of the main control processor simulation model continuously checks for changes in the content of the address in the target monitoring area. If the content changes, that is, when the main control processor simulation model detects an instruction response message written to the target monitoring area, in a real hardware system, the first interrupt signal is an electrical pulse (voltage high) generated on the hardware interrupt line IRQ. In the simulation system, the monitoring interrupt status thread simulates the high or low pull of the underlying interrupt signal through the interrupt IRQ module. A high interrupt signal means that the interrupt callback function of the kernel driver bound to the interrupt signal will be called by the main control processor simulation model to handle this IPC communication event; a low interrupt signal means that the main control processor simulation model will stop calling the interrupt callback function of the kernel driver. The main control processor simulation model triggers the first interrupt signal according to the instruction response message, that is, the interrupt signal goes high, notifying the corresponding interrupt module to generate the corresponding first interrupt callback function, such as confirming the start of playback.

[0071] The aforementioned heterogeneous co-simulation method is applied to the main control processor simulation model. Through software virtualization technology, a main control processor simulation model and a heterogeneous audio coprocessor simulation model are constructed. Shared memory and IPC communication mechanisms are used to simulate hardware interaction, decoupling the software architecture from the hardware topology. This enables the main control processor simulation model to send instruction messages to the heterogeneous audio coprocessor simulation model, and simultaneously enables the heterogeneous audio coprocessor simulation model to send response instruction messages to the main control processor simulation model. On the one hand, this allows for pre-verification, enabling debugging and verification at any stage, significantly improving the development efficiency of complex on-chip systems.

[0072] In one exemplary embodiment, such as Figure 3 As shown, the target monitoring area includes a first sub-area; wherein, the first sub-area is the area that monitors the instruction messages and instruction response messages sent between the main control processor simulation model and the coprocessor simulation model; writing instruction messages to the target monitoring area of ​​shared memory includes steps S302 to S306. Wherein:

[0073] Step S302: Send instruction messages through the user layer.

[0074] Step S304: Write instruction messages to the first sub-region via the kernel driver.

[0075] The coprocessor simulation model is used to obtain the instruction message of the first sub-region when a first state change of the first sub-region is detected, respond to the instruction message, obtain the instruction response result, and write the instruction response message to the first sub-region according to the instruction response result.

[0076] The main control processor simulation model is responsible for simulating the behavior of the main control processor and uses a shared memory mechanism to simulate IPC communication, thereby implementing a series of request and response behaviors of the coprocessor simulation model. The internal structure of the main control processor simulation model is as follows: Figure 4 As shown, the main control processor simulation model includes the main control processor CPU, a monitoring interrupt status thread, and an interrupt module. The main control processor CPU includes user space and kernel space. Taking the audio software processing program of the main control processor as an example of a user space application, it is responsible for user-level audio data transmission and processing. The kernel driver is an abstraction of the underlying hardware interface, responsible for interacting with the underlying hardware, processing various instructions issued by the user layer (such as playing recordings), and coordinating and controlling relevant hardware resources to meet the requirements of the corresponding instructions.

[0077] To simulate IPC communication, the main processor simulation model selects an unused region within shared memory as the target monitoring area, also known as the IPC communication monitoring area. The main processor simulation model continuously checks the contents of addresses within this target monitoring area using an interrupt status monitoring thread. If a change is detected, the simulation model uses an interrupt module to simulate the raising or lowering of underlying interrupt signals. A high interrupt signal means the kernel driver's interrupt callback function bound to the interrupt signal will be called by the main processor to handle the IPC communication event; a low interrupt signal means the main processor will stop calling the kernel driver's interrupt callback function. Therefore, the main processor simulation model must simulate two interrupt signals: a first interrupt signal and a second interrupt signal, where the second interrupt signal refers to the low interrupt signal. The target monitoring area of ​​the main processor simulation model, such as the IPC communication monitoring area, is primarily used to monitor messages between the coprocessor simulation model and the main processor simulation model.

[0078] Optionally, taking an audio software processing program as an example of a user-space application, the main control processor simulation model issues instruction messages (such as playing recordings) through the user-level application running code in the user space. It coordinates and controls relevant hardware resources through the kernel driver to meet the requirements of the corresponding instruction messages and writes the instruction messages into the first sub-region of the target monitoring area, such as region A in IPC0.

[0079] Furthermore, when a first state change is detected in the target monitoring region of the shared memory, the coprocessor simulation model acquires the instruction message from the target monitoring region, responds to the instruction message, and writes an instruction response message to the target monitoring region of the shared memory based on the instruction response result; the first state change is caused by the instruction message written by the main processor simulation model to the target monitoring region of the shared memory. After processing the instruction message, the coprocessor simulation model writes the instruction response message to the first sub-region.

[0080] Step S306: If there is an instruction response message corresponding to the instruction message in the first sub-region, it is determined that a second state change in the first sub-region has been detected.

[0081] The second state change is generated by the instruction response message written by the coprocessor simulation model after processing the instruction message.

[0082] Optionally, if the main control processor simulation model detects an instruction response message corresponding to an instruction message in the first sub-region through the monitoring interrupt status thread, it is determined that a second state change in the first sub-region has been detected.

[0083] When a second state change in the target monitoring area is detected, a first interrupt signal is triggered according to the instruction response message and the corresponding first interrupt callback function is called, including step S308: When a second state change in the first sub-region is detected, a first interrupt signal is triggered according to the instruction response message and the corresponding first interrupt callback function is called.

[0084] Optionally, when a second state change in the first sub-region is detected, the main control processor simulation model triggers a first interrupt signal and calls the corresponding first interrupt callback function according to the instruction response message.

[0085] like Figure 2 As shown, the coprocessor simulation model writes an instruction response message to region B in the first sub-region.

[0086] It should be noted that the first sub-region IPC0 can be divided into two independent regions, such as A and B. Region A is the region where the main processor simulation model sends instruction information to the coprocessor simulation model; region B is the region where the coprocessor simulation model sends response instruction information to the main processor simulation model. Regions A and B are independent and do not affect each other.

[0087] In this embodiment, communication between the two is achieved by simulating the IPC communication process between the main control processor simulation model and the coprocessor simulation model.

[0088] In an exemplary embodiment, the target monitoring area further includes a second sub-region; the method further includes: when a third state change of the second sub-region is detected, triggering a second interrupt signal according to a request message and calling the corresponding second interrupt callback function to obtain a response request message; writing the response request message into the second sub-region; wherein, the coprocessor simulation model is used to trigger a third interrupt signal according to the response request message in the second sub-region and call the corresponding third interrupt callback function when a fourth state change of the second sub-region is detected.

[0089] The second sub-region is the area where request messages and request-response messages are sent between the main processor and the coprocessor; the third state change is generated by the request message written by the coprocessor simulation model; and the fourth state change is generated by the request-response message written by the main processor simulation model after processing the request message.

[0090] Optionally, such as Figure 2 As shown, the coprocessor simulation model writes a request message to area C of the target monitoring area, such as the IPC1 monitoring area.

[0091] The main control processor simulation model detects a change in the state of area C in the IPC1 monitoring area through the monitoring interrupt status thread. It immediately triggers a second interrupt signal based on the request message, i.e., pulls the level high, and calls the second interrupt callback function corresponding to the second interrupt signal to obtain the response request message. After the second interrupt callback function of the main control processor simulation model completes its processing, the main control processor simulation model writes a request response message to area D of the IPC1 monitoring area to notify the coprocessor simulation model that it has completed the response message processing for this IPC communication.

[0092] The coprocessor simulation model detects a change in the state of region D in the IPC1 monitoring area through the monitoring component. This change corresponds to the request response message written by the main processor simulation model after processing the request message. When the coprocessor simulation model detects a fourth state change in region D of the second sub-region through the monitoring component, it triggers a third interrupt signal based on the response request message of region D in the second sub-region and calls the pre-registered third interrupt callback function corresponding to the high-level signal.

[0093] It should be noted that two independent regions, such as C and D, can be divided in the second sub-region IPC1. Region C is the region where the coprocessor simulation model sends request messages to the main processor simulation model; region D is the region where the main processor simulation model sends response request messages to the coprocessor simulation model. Regions C and D are independent and do not affect each other.

[0094] In this embodiment, communication between the two is achieved by simulating the IPC communication process between the coprocessor simulation model and the main control processor simulation model.

[0095] In an exemplary embodiment, before writing instruction messages to the target monitoring region of the shared memory, the method further includes: dividing the shared memory into a target monitoring region and a shared data region; wherein, the target monitoring region is used to monitor the communication between the main control processor simulation model and the coprocessor simulation model; and the shared data region is used to exchange data during the communication between the main control processor simulation model and the coprocessor simulation model.

[0096] Optionally, such as Figure 2 As shown. Before the interaction between the main processor simulation model and the coprocessor simulation model, the size of the shared memory is determined. The entire shared memory is divided according to different actual uses, into a hardware resource area, a target monitoring area (the first and second sub-monitoring areas, i.e., IPC0 and IPC1 monitoring areas), and a shared data area. The hardware resource area is used to store the hardware resources participating in the test; the specific behavior of the hardware does not need to be simulated here. The target monitoring area is the area for IPC communication between the main processor simulation model and the coprocessor simulation model, monitoring IPC command messages, response command messages, request messages, and response request messages. The shared data area is mainly used for exchanging data between the main processor simulation model and the coprocessor simulation model during IPC communication.

[0097] Considering that the main control processor simulation model needs to access and operate on shared memory, the memory distribution on the main control processor simulation model must reserve a dedicated unused area for shared memory, that is... Figure 1 The reserved memory in the main control processor simulation model must be at least equal to the size of the shared memory. To implement the IPC communication mechanism of the main control processor simulation model, two simulated interrupt signals (IRQ0 / IRQ1) need to be added to the main control processor simulation model. The function of the IRQ0 interrupt is to monitor the coprocessor simulation model's response to the instruction response message sent by the main control processor simulation model, and the function of the IRQ1 interrupt is to monitor the coprocessor simulation model sending request messages to the main control processor simulation model.

[0098] Considering that the coprocessor simulation model also needs to access and operate on shared memory, the memory distribution on the coprocessor simulation model must also reserve a dedicated unused area for shared memory, that is... Figure 1The reserved memory for the coprocessor simulation model must be at least equal to the size of the shared memory. To implement the IPC communication mechanism of the coprocessor simulation model, two interrupt signals (IRQ0 / IRQ1) need to be added to the device side and bound to two bits on MMIO. The IRQ0 interrupt monitors the main processor simulation model sending instruction messages to the coprocessor simulation model, and the IRQ1 interrupt monitors the main processor simulation model responding to the response request messages sent by the coprocessor simulation model.

[0099] In this embodiment, by simulating the various regions in the shared memory, the interaction between the main control processor simulation model and the coprocessor simulation model can be realized.

[0100] In one exemplary embodiment, a heterogeneous co-simulation method is provided, which is applied to... Figure 1 Taking the coprocessor simulation model in the example, the process includes: when a first state change of the target monitoring area of ​​the shared memory is detected, the instruction message of the target monitoring area is acquired and responded to, and the instruction response result is obtained; the instruction response message is written to the target monitoring area of ​​the shared memory according to the instruction response result.

[0101] In this system, the shared memory can be accessed by the main control processor simulation model; the first state change is generated by the instruction message written by the main control processor simulation model to the target monitoring area of ​​the shared memory; the target monitoring area is used for communication between the main control processor simulation model and the coprocessor simulation model; when the main control processor simulation model detects the second state change of the target monitoring area, it triggers the first interrupt signal and calls the corresponding first interrupt callback function according to the instruction response message; the second state change is generated by the instruction response message written by the coprocessor simulation model after processing the instruction message.

[0102] The coprocessor simulation model is used to simulate the behavior of the coprocessor and to simulate IPC communication through a shared memory mechanism, so as to realize the behavioral operations corresponding to a series of instruction messages of the request message and response to the main processor simulation model. Figure 5 The document describes a heterogeneous coprocessor software simulation model, including multiple coprocessors, an interrupt module, and a monitoring module. The multiple coprocessors, such as coprocessor 0, coprocessor 1, coprocessor 2, etc., indicate that the coprocessor subsystem can run multiple coprocessor CPUs simultaneously. Each coprocessor internally includes coprocessor program execution code, related runtime dependency libraries, and basic hardware (supporting dependency libraries), coordinating and controlling related hardware resources to meet the requirements of the corresponding instructions.

[0103] Furthermore, the coprocessor simulation model employs the TLM (Transaction Level Modeling) approach. TLM is an advanced solution for modeling digital systems, its core feature being the separation of data transmission from specific implementation details. It is primarily used in software to simulate hardware behavior, while improving simulation development efficiency by abstracting the implementation details between various modules. The coprocessor simulation model requires the following components: an arbitration component, a routing component, a coprocessor, a coprocessor MMIO (Memory Mapped Input / Output Component), and a monitoring component. The arbitration component is responsible for allocating the right to use shared resources, preventing access conflicts when multiple devices simultaneously request shared resources; the routing component manages access to shared resources by multiple devices, controlling path selection and data forwarding; the coprocessor reads and executes program instructions, manages memory, controls data flow, and coordinates hardware and software resource calls; the coprocessor MMIO is a 32-bit memory segment bound to the coprocessor's interrupt signals, simulating the IPC communication mechanism between the coprocessor and the main processor; the monitoring component reads commands from script files to access the TLM model interface.

[0104] If a coprocessor simulation model contains only one coprocessor, it is called a single-core coprocessor simulation model; if it contains multiple coprocessors, it is called a multi-core coprocessor simulation model. A single-core coprocessor simulation model is as follows: Figure 6 As shown, the model includes the following components: one system bus arbitration component, one system bus routing component, one system monitoring component, one coprocessor bus component, one coprocessor input routing component, one coprocessor MMIO, one coprocessor, one instruction arbitration component, and one data arbitration component.

[0105] Using TLM modeling, the coprocessor simulation model is connected to various modules such as bus, memory, and peripherals to form a basic coprocessor subsystem. To simulate the IPC communication mechanism between the main processor and the coprocessor, arbitrary bits of the MMIO (Memory Mapped Input / Output) module need to be bound to arbitrary interrupt signals on the coprocessor's memory-mapped input / output (IMO) components. MMIO is a 32-bit memory space; each bit of MMIO can be connected to one interrupt signal of the coprocessor, so a maximum of 32 interrupt IRQ signals can be bound to one MMIO. When a bit on the MMIO is written to 1, the bound coprocessor interrupt level signal is pulled high; when a bit on the MMIO is written to 0, the bound coprocessor interrupt level signal is pulled low.

[0106] The principle of the coprocessor's true model simulating the IPC communication mechanism is as follows: First, an unused region on shared memory needs to be selected as the IPC communication monitoring area. The system monitoring component continuously checks whether the content of the address in this region has changed. If the content changes, the system monitoring component will write 1 to a certain bit on the coprocessor's MMIO to notify the interrupt callback function registered on the coprocessor to handle this IPC communication event.

[0107] The multi-core coprocessor simulation model is based on the single-core coprocessor model, with the addition of multiple coprocessor subsystem components. Each coprocessor subsystem component includes a coprocessor bus component, a coprocessor input routing component, a coprocessor MMIO component, a coprocessor, an instruction arbitration component, and a data arbitration component. The connection relationships of the components required for the multi-core coprocessor are as follows: Figure 7 As shown.

[0108] Optionally, such as Figure 2 As shown, the main control processor simulation model simulates writing instruction messages to the target monitoring area of ​​shared memory, such as playing audio or video, recording, or pausing audio or video playback; the instruction messages instruct the coprocessor simulation model to execute. Audio data is also written to the target monitoring area simultaneously. After the main control processor simulation model simulates writing instruction messages to the target monitoring area of ​​shared memory, the target monitoring area changes. The coprocessor simulation model obtains the instruction messages and audio data from the target monitoring area, processes the audio data to respond to the instruction messages, obtains the response results, and writes instruction response messages to the target monitoring area of ​​shared memory based on the instruction response results; for example, writing "playback ready" to the target monitoring area. The monitoring interrupt status thread of the main control processor simulation model continuously checks whether the content of the address in the target monitoring area has changed. If the content changes, that is, when the main control processor simulation model detects an instruction response message written to the target monitoring area, in a real hardware system, the first interrupt signal is an electrical pulse (voltage pull-up) generated on the hardware interrupt line IRQ. In the simulation system, the monitoring interrupt status thread simulates the high or low pull-up of the underlying interrupt signal through the interrupt IRQ module. A high interrupt signal means that the kernel driver's interrupt callback function bound to the interrupt signal will be called by the main control processor simulation model to handle this IPC communication event; a low interrupt signal means that the main control processor simulation model will stop calling the kernel driver's interrupt callback function. The main control processor simulation model triggers the first interrupt signal according to the instruction response message, that is, the interrupt signal goes high, notifying the corresponding interrupt module to generate the corresponding first interrupt callback function, such as confirming the start of playback.

[0109] The aforementioned heterogeneous co-simulation method is applied to the coprocessor simulation model. Through software virtualization technology, a main control processor simulation model and a heterogeneous audio coprocessor simulation model are constructed. Shared memory and IPC communication mechanisms are used to simulate hardware interaction, decoupling the software architecture from the hardware topology. This enables the heterogeneous audio coprocessor simulation model to send request messages to the main control processor simulation model, and simultaneously enables the main control processor simulation model to send response request messages to the heterogeneous audio coprocessor simulation model. On the one hand, this allows for pre-verification, enabling debugging and verification at any stage, significantly improving the development efficiency of complex on-chip systems.

[0110] In an exemplary embodiment, the target monitoring area includes a first sub-region; wherein, the first sub-region is the area that monitors the instruction messages and instruction response messages sent between the main control processor simulation model and the coprocessor simulation model; when a first state change in the target monitoring area of ​​the shared memory is detected, the instruction message is acquired and responded to to obtain the instruction response result, including: when a first state change in the first sub-region is detected, the monitoring component writes a fourth interrupt signal to the target bit of the memory-mapped input / output component according to the instruction message; the fourth interrupt callback function corresponding to the target bit is triggered by the fourth interrupt signal to obtain the instruction response result.

[0111] When the coprocessor simulation model detects a first state change in the target monitoring region of shared memory through the monitoring component, that is, when the main control processor simulation model writes an instruction message to region A of the first sub-region IPC0 of the target monitoring region of shared memory, such as the instruction message "Start recording playback," the monitoring component writes a fourth interrupt signal (1) to the target bit of the memory-mapped input / output component (MMIO) according to the instruction message. Specifically, if bit 2 of the MMIO is bound to an interrupt callback function, such as the fourth interrupt callback function, a 1 is written to bit 2. Figure 2 As shown, changes in the MMIO bit are mapped to the corresponding interrupt signal (IRQ0). When the interrupt signal goes high, it triggers the fourth interrupt callback function pre-registered for that bit. When the coprocessor simulation model executes the fourth interrupt function, it first reads the instruction message from the first sub-region IPC0 and the audio exchange data from the shared data region, and performs the corresponding hardware configuration or data processing, such as configuring the sampling rate, number of channels, and initializing the audio pipeline. After executing the fourth interrupt function, it obtains the instruction response result corresponding to the fourth interrupt function, and writes the instruction response message to region B of the IPC0 monitoring area according to the instruction response result to notify the main processor simulation model to perform the next operation.

[0112] In this embodiment, a fourth interrupt signal is written to the target bit of the memory-mapped input / output component according to the instruction message written by the main control processor simulation model, simulating the actual high or low level signal on the hardware, so as to realize that the main control processor simulation model sends instruction messages to the coprocessor simulation model, and the coprocessor simulation model calls the execution of the fourth interrupt function according to the fourth interrupt signal to obtain the instruction response message.

[0113] In an exemplary embodiment, the method further includes: writing a request message to a target monitoring region of shared memory, wherein the main control processor simulation model is used to trigger a second interrupt signal and call a corresponding second interrupt callback function according to the request message of the target monitoring region when a third state change of the target monitoring region is detected, thereby obtaining a response request message; writing the response request message to the target monitoring region; and triggering a third interrupt signal and calling a corresponding third interrupt callback function according to the response request message in the target monitoring region when a fourth state change of the target monitoring region is detected.

[0114] The target monitoring area also includes a second sub-area; the second sub-area is the area where request messages and request-response messages are sent between the main control processor and the coprocessor.

[0115] Optionally, writing a request message to the target monitoring region of shared memory includes: writing a request message to a second sub-region, wherein the main control processor simulation model is used to trigger a second interrupt signal and call the corresponding second interrupt callback function according to the request message of the second sub-region when a third state change of the second sub-region is detected, to obtain a response request message; and writing the response request message to the second sub-region. When a fourth state change of the target monitoring region is detected, triggering a third interrupt signal and calling the corresponding third interrupt callback function according to the response request message in the target monitoring region includes: triggering a third interrupt signal and calling the corresponding third interrupt callback function according to the response request message of the second sub-region when a fourth state change of the second sub-region is detected.

[0116] For example, when the main processor simulation model issues a playback command, the coprocessor simulation model responds with a command message, such as: playback ready, write to the target monitoring area in shared memory. The main processor simulation model's monitoring thread detects a change in IPC0_B, triggers an interrupt callback function (handling the playback response), and notifies the host application that playback has started.

[0117] Continue as Figure 2As shown, assume the coprocessor simulation model detects that the buffer is about to run out during playback. It writes a request message to region C (IPC1_C) of the IPC1 monitoring area. The main processor simulation model detects the change in IPC1_C through its monitoring thread, triggers a second interrupt signal, and calls the corresponding second interrupt callback function (processing the request message) to write the next segment of audio data to the shared data area. Simultaneously, it writes a data-ready request response message to region D (IPC1_D) of the IPC1 monitoring area. The coprocessor simulation model's monitoring component detects the change in IPC1_D, triggers a third interrupt signal based on the response request message in the target monitoring area, and calls the corresponding third interrupt callback function (e.g., processing data readiness).

[0118] In this embodiment, communication between the two is achieved by simulating the IPC communication process between the coprocessor simulation model and the main control processor simulation model.

[0119] In an exemplary embodiment, when a fourth state change in the second sub-region is detected, a third interrupt signal is triggered and the corresponding third interrupt callback function is invoked according to the response request message in the second sub-region. This includes: when a fourth state change in the second sub-region is detected, the monitoring component writes a third interrupt signal to the target bit of the memory-mapped input / output component according to the response request message; and the third interrupt callback function corresponding to the target bit is triggered by the third interrupt signal.

[0120] When the coprocessor simulation model detects a fourth state change in the second sub-region of the target monitoring area of ​​shared memory through the monitoring component, that is, when the main control processor simulation model writes a request-response message to the D region of IPC1, the second sub-region of the target monitoring area of ​​shared memory, the coprocessor simulation model writes a third interrupt signal (1) to the target bit of the memory-mapped input / output component (MMIO) according to the instruction message through the monitoring component, i.e., pulls the terminal signal high; specifically, if Bit2 of the MMIO is bound to an interrupt callback function, such as being bound to the third interrupt callback function, a 1 is written to Bit3. Figure 2 As shown, changes in the MMIO bit are mapped to the corresponding interrupt signal (IRQ1). When the interrupt signal goes high, it triggers the third interrupt callback function pre-registered for that bit. The coprocessor simulation model executes the third interrupt callback function. The interrupt callback function internally aggregates all instruction messages. The instructions are written by the requesting party. Figure 2 The shared data area will be read by the responder (coprocessor simulation model), and the responder will perform different processing according to different instructions in the execution of the third interrupt callback function.

[0121] In this embodiment, a third interrupt signal is written to the target bit of the memory-mapped input / output component by the request message actively written by the coprocessor simulation model to the main control processor simulation model, simulating the actual high or low level signal on the hardware, so as to realize the coprocessor simulation model actively sending request information to the main control processor simulation model.

[0122] In an exemplary embodiment, a heterogeneous co-simulation system includes a main control processor simulation model, a coprocessor simulation model, and shared memory. The shared memory enables interaction between the main control processor simulation model and the coprocessor simulation model. The main control processor simulation model is used to write instruction messages to a target monitoring area of ​​the shared memory, wherein the shared memory can be accessed by at least one coprocessor simulation model. The target monitoring area is used for communication between the main control processor simulation model and the coprocessor simulation model. The coprocessor simulation model is used to acquire instruction messages from the target monitoring area when a first state change is detected in the target monitoring area of ​​the shared memory, respond to the instruction messages, and write instruction response messages to the target monitoring area of ​​the shared memory based on the instruction response results. The first state change is generated by the instruction messages written by the main control processor simulation model to the target monitoring area of ​​the shared memory. The main control processor simulation model is also used to trigger a first interrupt signal and call a corresponding first interrupt callback function based on the instruction response messages when a second state change is detected in the target monitoring area. The second state change is generated by the instruction response messages written by the coprocessor simulation model after processing the instruction messages.

[0123] System architecture such as Figure 1 As shown. Before the interaction between the main processor simulation model and the coprocessor simulation model, the size of the shared memory is determined. The entire shared memory is divided according to actual usage, into a hardware resource area, a target monitoring area (the first and second sub-monitoring areas, i.e., IPC0 and IPC1 monitoring areas), and a shared data area. The hardware resource area stores the hardware resources participating in the test; the specific behavior of the hardware does not need to be simulated here. The target monitoring area is the area for IPC communication between the main processor simulation model and the coprocessor simulation model, monitoring IPC command messages, response command messages, request messages, and response request messages. The shared data area is mainly used for exchanging data between the main processor simulation model and the coprocessor simulation model during IPC communication.

[0124] The IPC communication process between the main processor simulation model and the coprocessor simulation model is as follows: Figure 2 As shown.

[0125] Phase 1: The main control processor simulation model issues the command message "play command". The specific process is as follows:

[0126] Step 1: Taking an audio software processing program as an example of a user-space application, the main control processor simulation model issues playback commands through the user-level application code in user space. The kernel driver coordinates and controls relevant hardware resources to meet the requirements of the corresponding playback commands, and writes the playback commands into the first sub-region of the target monitoring area, such as region A in IPC0. The exchange data corresponding to the playback commands is then written to the shared data area.

[0127] Step 2: When the coprocessor simulation model detects the first state change in area A of IPC0 through the monitoring component, that is, when the main control processor simulation model writes the "playback instruction" to area A of IPC0.

[0128] Step 3: The coprocessor simulation model, through the monitoring component, writes the fourth interrupt signal (1) to the target bit of the memory-mapped input / output (MMIO) component according to the instruction message; specifically, it binds Bit 2 of the MMIO component to the fourth interrupt signal and writes 1 to Bit 2. Figure 2 As shown, changes in the MMIO bit are mapped to the corresponding interrupt signal (IRQ0). When the interrupt signal goes high, it triggers the fourth interrupt callback function, such as "process playback command," which is pre-registered for that bit. When the coprocessor simulation model executes the fourth interrupt function, it first reads the instruction message from the first sub-region IPC0 and the audio exchange data from the shared data region, and performs the corresponding hardware configuration or data processing, such as configuring the sampling rate, number of channels, and initializing the audio pipeline. After executing the fourth interrupt function "process playback command," the audio coprocessor configures the audio parameters and starts playback, obtaining the instruction response result corresponding to the fourth interrupt function, such as the playback ready response.

[0129] Step 4: The coprocessor simulation model writes an instruction response message to area B of the IPC0 monitoring area based on the playback ready response, so that the main control processor simulation model can perform the next operation.

[0130] Step 5: The monitoring interrupt status thread of the main control processor simulation model continuously checks whether the contents of the address in area B of the IPC0 monitoring area have changed.

[0131] Step 6: If the content changes, that is, when the main control processor simulation model detects an instruction response message written to the target monitoring area, in the real hardware system, the first interrupt signal is an electrical pulse (voltage high) generated on the hardware interrupt line IRQ. In the simulation system, the thread monitoring the interrupt status will simulate the high or low pull of the underlying interrupt signal through the interrupt IRQ module. A high interrupt signal means that the interrupt callback function of the kernel driver bound to the interrupt signal will be called by the main control processor simulation model to handle this IPC communication event; a low interrupt signal means that the main control processor simulation model will stop calling the interrupt callback function of the kernel driver. The main control processor simulation model triggers the first interrupt signal according to the instruction response message, that is, the interrupt signal goes high, notifying the corresponding interrupt module to generate the corresponding first interrupt callback function, such as handling the playback response.

[0132] Phase Two: The coprocessor simulation model sends a request message "Request More Data". The specific process is as follows:

[0133] Step 7: During playback, the coprocessor simulation model detects that the exchanged data in the shared data area is about to run out. The coprocessor simulation model writes "Request more data" to area C (IPC1_C) of the IPC1 monitoring area.

[0134] Step 8: The main control processor simulation model detects changes in IPC1_C through the monitoring thread.

[0135] Step 9: The main control processor simulation model triggers the second interrupt signal based on "request more data", that is, pulls the high level signal, and calls the second interrupt callback function corresponding to the second interrupt signal, that is, processes the data request and obtains the response request message.

[0136] Step 10: After the second interrupt callback function (processing data request) of the main control processor simulation model is completed, the main control processor writes the next segment of audio data into the shared data area (SHM_Data) and writes the request response message "data ready response" into area D (IPC1_D) of the IPC1 monitoring area to notify the coprocessor simulation model that the IPC communication processing response message has been completed.

[0137] Step 11: The coprocessor simulation model detects a change in the state of area D in the IPC1 monitoring area through the monitoring component, which is the request response message written by the main processor simulation model after processing the request message.

[0138] Step 12: When the coprocessor simulation model detects the fourth state change of region D in the second sub-region through the monitoring component, it triggers the third interrupt signal according to the response request message of region D in the second sub-region, that is, pulls up the high-level signal and calls the pre-registered third interrupt callback function corresponding to the high-level signal, such as when the data processing is ready.

[0139] Step 13: The audio coprocessor updates the buffer pointer and continues playing new data, i.e., the next segment of audio data.

[0140] In this embodiment, the communication interaction between the main control processor simulation model and the coprocessor simulation model can be used for software design and development in advance before the hardware design is completed, so as to realize the pre-verification of software solutions and improve the efficiency of software development; it can also be used simultaneously for problem location and debugging during the hardware simulation verification process, so that debugging can be migrated from hardware to software model, assisting hardware verification and improving the efficiency of debugging and verification.

[0141] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0142] Based on the same inventive concept, this application also provides a heterogeneous collaborative simulation device for implementing the heterogeneous collaborative simulation method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more embodiments of the heterogeneous collaborative simulation device provided below can be found in the limitations of the heterogeneous collaborative simulation method described above, and will not be repeated here.

[0143] In one exemplary embodiment, such as Figure 8 As shown, a heterogeneous co-simulation device is provided for use in a main control processor simulation model, including: a first writing module 801 and a first calling module 802, wherein:

[0144] The first writing module 801 is used to write instruction messages to the target monitoring area of ​​the shared memory, wherein the shared memory can be accessed by at least one coprocessor simulation model; the coprocessor simulation model is used to obtain the instruction message of the target monitoring area when a first state change of the target monitoring area of ​​the shared memory is detected, respond to the instruction message, and write an instruction response message to the target monitoring area of ​​the shared memory according to the instruction response result; the first state change is generated by the instruction message written by the main control processor simulation model to the target monitoring area of ​​the shared memory; the target monitoring area is the monitoring area for communication between the main control processor simulation model and the coprocessor simulation model.

[0145] The first calling module 802 is used to trigger a first interrupt signal and call the corresponding first interrupt callback function according to the instruction response message when a second state change of the target monitoring area is detected; wherein, the second state change is generated by the instruction response message written by the coprocessor simulation model after processing the instruction message.

[0146] In an exemplary embodiment, the target monitoring area includes a first sub-region; wherein, the first sub-region is the area that monitors the instruction messages and instruction response messages sent between the main control processor and the coprocessor; the first writing module 801 is further configured to issue instruction messages through the user layer; and write instruction messages to the first sub-region through the kernel driver; wherein, the coprocessor simulation model is configured to, when a first state change of the first sub-region is detected, obtain the instruction messages of the first sub-region, respond to the instruction messages, obtain the instruction response results, and write instruction response messages to the first sub-region according to the instruction response results.

[0147] The detection module is used to determine that a second state change in the first sub-region has been detected if an instruction response message corresponding to an instruction message exists in the first sub-region.

[0148] The first calling module 802 is also used to trigger a first interrupt signal and call the corresponding first interrupt callback function according to the instruction response message when a second state change of the first sub-region is detected.

[0149] In an exemplary embodiment, the target monitoring area further includes a second sub-region; wherein, the second sub-region is the area where request messages and request-response messages are sent between the main control processor and the coprocessor; the device further includes a second invocation module, which is used to trigger a second interrupt signal and invoke the corresponding second interrupt callback function according to the request message when a third state change of the second sub-region is detected, thereby obtaining a response request message; wherein, the third state change is generated by the request message written by the coprocessor simulation model; and the response request message is written to the second sub-region; wherein, when a fourth state change of the second sub-region is detected, the coprocessor simulation model is used to trigger a third interrupt signal and invoke the corresponding third interrupt callback function according to the response request message in the second sub-region, wherein the fourth state change is generated by the request-response message written by the main control processor simulation model after processing the request message.

[0150] In one exemplary embodiment, the heterogeneous co-simulation device further includes a partitioning module for dividing the shared memory into a target monitoring region and a shared data region; wherein, the target monitoring region is used to monitor the communication between the main control processor simulation model and the coprocessor simulation model; and the shared data region is used to exchange data during the communication between the main control processor simulation model and the coprocessor simulation model.

[0151] In one exemplary embodiment, such as Figure 9 As shown, a heterogeneous co-simulation device is provided for use in a coprocessor simulation model, including: a response module 901 and a second writing module 902, wherein:

[0152] The response module 901 is used to acquire and respond to the instruction message of the target monitoring area when a first state change of the target monitoring area of ​​the shared memory is detected, and to obtain the instruction response result; wherein, the shared memory can be accessed by the main control processor simulation model; the first state change is generated by the instruction message written by the main control processor simulation model to the target monitoring area of ​​the shared memory; the target monitoring area is the monitoring area used for communication between the main control processor simulation model and the coprocessor simulation model.

[0153] The second writing module 902 is used to write instruction response messages to the target monitoring area of ​​shared memory according to the instruction response results; wherein, when the main control processor simulation model detects the second state change of the target monitoring area, it triggers the first interrupt signal and calls the corresponding first interrupt callback function according to the instruction response message; the second state change is generated by the instruction response message written by the coprocessor simulation model after processing the instruction message.

[0154] In an exemplary embodiment, the target monitoring area includes a first sub-area; wherein, the first sub-area is the area that monitors the instruction messages and instruction response messages sent between the main control processor and the coprocessor; the response module 901 is used to, when a first state change of the first sub-area is detected, write a fourth interrupt signal to the target bit of the memory-mapped input / output component according to the instruction message through the monitoring component; and trigger the fourth interrupt callback function corresponding to the target bit through the fourth interrupt signal to obtain the instruction response result.

[0155] In an exemplary embodiment, a heterogeneous collaborative simulation device further includes: a third invocation module, configured to write a request message to a target monitoring region of shared memory, wherein the main control processor simulation model is configured to, when a third state change of the target monitoring region is detected, trigger a second interrupt signal according to the request message of the target monitoring region and invoke the corresponding second interrupt callback function to obtain a response request message; write the response request message to the target monitoring region; and when a fourth state change of the target monitoring region is detected, trigger a third interrupt signal according to the response request message in the target monitoring region and invoke the corresponding third interrupt callback function.

[0156] In an exemplary embodiment, the target monitoring area further includes a second sub-region; wherein the second sub-region is the area where request messages and request-response messages are sent between the main control processor and the coprocessor; the third calling module is further configured to write request messages to the second sub-region, wherein the main control processor simulation model is configured to, when a third state change of the second sub-region is detected, trigger a second interrupt signal according to the request message of the second sub-region and call the corresponding second interrupt callback function to obtain a response request message; write the response request message to the second sub-region; when a fourth state change of the target monitoring area is detected, trigger a third interrupt signal according to the response request message in the target monitoring area and call the corresponding third interrupt callback function, including: when a fourth state change of the second sub-region is detected, trigger a third interrupt signal according to the response request message in the second sub-region and call the corresponding third interrupt callback function.

[0157] In an exemplary embodiment, the third calling module is further configured to, when a fourth state change of the second sub-region is detected, write a third interrupt signal to the target bit of the memory-mapped input / output component according to the response request message through the monitoring component; and trigger the third interrupt callback function corresponding to the target bit through the third interrupt signal.

[0158] Each module in the aforementioned heterogeneous collaborative simulation device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the computer device's memory as software, so that the processor can call and execute the operations corresponding to each module.

[0159] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 10 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores message data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a heterogeneous co-simulation method.

[0160] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0161] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0162] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0163] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0164] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0165] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0166] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A heterogeneous collaborative simulation method, characterized in that, The method, applied to a main control processor simulation model, includes: An instruction message is written to a target monitoring region of shared memory, wherein the shared memory can be accessed by at least one coprocessor simulation model; the coprocessor simulation model is used to obtain an instruction message of the target monitoring region when a first state change of the target monitoring region of the shared memory is detected, respond to the instruction message, and write an instruction response message to the target monitoring region of the shared memory according to the instruction response result; the first state change is generated by the instruction message written by the main control processor simulation model to the target monitoring region of the shared memory; the target monitoring region is the monitoring region for communication between the main control processor simulation model and the coprocessor simulation model; When a second state change in the target monitoring area is detected, a first interrupt signal is triggered according to the instruction response message and the corresponding first interrupt callback function is called; wherein, the second state change is generated by the instruction response message written by the coprocessor simulation model after processing the instruction message.

2. The method according to claim 1, characterized in that, The target monitoring area includes a first sub-area; wherein, the first sub-area is the area that monitors the instruction messages and instruction response messages sent between the main control processor simulation model and the coprocessor simulation model; the step of writing instruction messages to the target monitoring area of ​​shared memory includes: The instruction message is sent through the user layer; The kernel driver writes the instruction message to the first sub-region; wherein, the coprocessor simulation model is used to obtain the instruction message of the first sub-region when a first state change of the first sub-region is detected, respond to the instruction message, obtain the instruction response result, and write the instruction response message to the first sub-region according to the instruction response result. If the instruction response message corresponding to the instruction message exists in the first sub-region, it is determined that a second state change in the first sub-region has been detected; When a second state change in the target monitoring area is detected, a first interrupt signal is triggered according to the instruction response message, and the corresponding first interrupt callback function is called, including: When a second state change in the first sub-region is detected, the first interrupt signal is triggered according to the instruction response message and the corresponding first interrupt callback function is called.

3. The method according to claim 1, characterized in that, The target monitoring area further includes a second sub-area; wherein, the second sub-area is the area where request messages and request-response messages are sent between the main control processor simulation model and the coprocessor simulation model; the method further includes: When a third state change in the second sub-region is detected, a second interrupt signal is triggered according to the request message and the corresponding second interrupt callback function is called to obtain a response request message; wherein, the third state change is generated by the request message written by the coprocessor simulation model; The response request message is written to the second sub-region; wherein, when the fourth state change of the second sub-region is detected, the coprocessor simulation model is used to trigger a third interrupt signal and call the corresponding third interrupt callback function according to the response request message in the second sub-region, and the fourth state change is generated by the request response message written by the main control processor simulation model after processing the request message.

4. The method according to claim 1, characterized in that, Before writing the instruction message to the target monitoring region of the shared memory, the method further includes: The shared memory is divided into a target monitoring area and a shared data area; wherein, the target monitoring area is used to monitor the communication between the main control processor simulation model and the coprocessor simulation model; the shared data area is used to exchange data during the communication between the main control processor simulation model and the coprocessor simulation model.

5. A heterogeneous collaborative simulation method, characterized in that, The method, applied to a coprocessor simulation model, includes: When a first state change is detected in the target monitoring area of ​​the shared memory, the instruction message of the target monitoring area is acquired and responded to, and an instruction response result is obtained; wherein, the shared memory can be accessed by the main control processor simulation model; the first state change is generated by the instruction message written by the main control processor simulation model to the target monitoring area of ​​the shared memory; the target monitoring area is used as a monitoring area for communication between the main control processor simulation model and the coprocessor simulation model; According to the instruction response result, an instruction response message is written to the target monitoring area of ​​the shared memory; wherein, when the main control processor simulation model detects a second state change in the target monitoring area, it triggers a first interrupt signal and calls the corresponding first interrupt callback function according to the instruction response message; the second state change is generated by the instruction response message written by the coprocessor simulation model after processing the instruction message.

6. The method according to claim 5, characterized in that, The target monitoring area includes a first sub-area; wherein, the first sub-area is the area that monitors instruction messages and instruction response messages sent between the main control processor and the coprocessor; when a first state change in the target monitoring area of ​​the shared memory is detected, the instruction message is acquired and responded to, and the instruction response result is obtained, including: When a first state change in the first sub-region is detected, the monitoring component writes a fourth interrupt signal to the target bit of the memory-mapped input / output component according to the instruction message. The fourth interrupt signal triggers the fourth interrupt callback function corresponding to the target bit, thereby obtaining the instruction response result.

7. The method according to claim 5, characterized in that, The method further includes: A request message is written to the target monitoring area of ​​the shared memory. The main control processor simulation model is used to trigger a second interrupt signal and call the corresponding second interrupt callback function according to the request message of the target monitoring area when a third state change of the target monitoring area is detected, so as to obtain a response request message; and write the response request message to the target monitoring area. When a fourth state change is detected in the target monitoring area, a third interrupt signal is triggered based on the response request message in the target monitoring area, and the corresponding third interrupt callback function is called.

8. The method according to claim 7, characterized in that, The target monitoring area further includes a second sub-area; wherein, the second sub-area is the area for request messages and request-response messages sent between the main control processor and the coprocessor; the step of writing a request message to the target monitoring area of ​​the shared memory includes: A request message is written to the second sub-region, wherein the main control processor simulation model is used to trigger a second interrupt signal and call the corresponding second interrupt callback function according to the request message of the second sub-region when a third state change of the second sub-region is detected, so as to obtain a response request message; and write the response request message to the second sub-region. When a fourth state change is detected in the target monitoring area, a third interrupt signal is triggered based on the response request message in the target monitoring area, and the corresponding third interrupt callback function is called, including: When a fourth state change in the second sub-region is detected, a third interrupt signal is triggered based on the response request message in the second sub-region, and the corresponding third interrupt callback function is called.

9. The method according to claim 8, characterized in that, When a fourth state change in the second sub-region is detected, triggering a third interrupt signal and calling the corresponding third interrupt callback function based on the response request message in the second sub-region includes: When a fourth state change in the second sub-region is detected, the monitoring component writes a third interrupt signal to the target bit of the memory-mapped input / output component according to the response request message. The third interrupt signal triggers the third interrupt callback function corresponding to the target bit.

10. A heterogeneous collaborative simulation system, characterized in that, The system includes a main control processor simulation model, a coprocessor simulation model, and shared memory; wherein, the interaction between the main control processor simulation model and the coprocessor simulation model is realized through the shared memory. The main control processor simulation model is used to write instruction messages to the target monitoring area of ​​the shared memory, wherein the shared memory can be accessed by at least one coprocessor simulation model; the target monitoring area is used for communication between the main control processor simulation model and the coprocessor simulation model. The coprocessor simulation model is used to acquire the instruction message of the target monitoring area when a first state change of the target monitoring area of ​​the shared memory is detected, respond to the instruction message, and write an instruction response message to the target monitoring area of ​​the shared memory according to the instruction response result; the first state change is generated by the instruction message written by the main control processor simulation model to the target monitoring area of ​​the shared memory. The main control processor simulation model is also used to trigger a first interrupt signal and call the corresponding first interrupt callback function according to the instruction response message when a second state change of the target monitoring area is detected; wherein, the second state change is generated by the instruction response message written by the coprocessor simulation model after processing the instruction message.

11. A heterogeneous collaborative simulation device, characterized in that, The device, applied to a main control processor simulation model, includes: A first writing module is used to write instruction messages to a target monitoring region of shared memory, wherein the shared memory can be accessed by at least one coprocessor simulation model; the coprocessor simulation model is used to, when detecting a first state change in the target monitoring region of the shared memory, acquire the instruction message of the target monitoring region, respond to the instruction message, and write an instruction response message to the target monitoring region of the shared memory according to the instruction response result; the first state change is generated by the instruction message written by the main control processor simulation model to the target monitoring region of the shared memory; the target monitoring region is the monitoring region for communication between the main control processor simulation model and the coprocessor simulation model; The first calling module is used to trigger a first interrupt signal and call the corresponding first interrupt callback function according to the instruction response message when a second state change of the target monitoring area is detected; wherein, the second state change is generated by the instruction response message written by the coprocessor simulation model after processing the instruction message.

12. A heterogeneous collaborative simulation device, characterized in that, The device, applied to a coprocessor simulation model, includes: A response module is used to acquire and respond to the instruction message of the target monitoring area when a first state change of the target monitoring area of ​​the shared memory is detected, and to obtain an instruction response result; wherein, the shared memory can be accessed by the main control processor simulation model; the first state change is generated by the instruction message written by the main control processor simulation model to the target monitoring area of ​​the shared memory; the target monitoring area is used as a monitoring area for communication between the main control processor simulation model and the coprocessor simulation model; The second writing module is used to write an instruction response message to the target monitoring area of ​​the shared memory according to the instruction response result; wherein, when the main control processor simulation model detects a second state change in the target monitoring area, it triggers a first interrupt signal and calls the corresponding first interrupt callback function according to the instruction response message; the second state change is generated by the instruction response message written by the coprocessor simulation model after processing the instruction message.

13. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 9.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 9.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 9.

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