Non-volatile memory cell array formed in P wells within deep N wells on a P substrate.

Abstract

To reduce a peak positive voltage that needs to be applied to a cell to erase a memory cell.SOLUTION: A non-volatile memory system 500 includes an array 501, a row decoder 502, and a high voltage decoder 503. The array 501 is formed in a p-well 504 formed in a deep n-well 505, and the deep n-well 505 is formed in a p-substrate 580. Therefore, the p-well 504 is separated from the p-substrate 580 by the deep n-well 505 and thus can receive a negative voltage. In an erase operation, the p-substrate 580 can be biased at 0 V, the deep n-well 505 can be biased at 0 to 2 V, and the p-well 504 can be biased at 0.1 V to 10 V. These bias voltages are generated by a bias generator 409 or another voltage source.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] (Claim of Priority) This application claims the priority of U.S. Provisional Patent Application No. 63 / 190,200, entitled "Non-Volatile Memory Cell Array with Substrate Capable of Receiving Negative Voltage During Erase Operations", filed on May 18, 2021, and U.S. Patent Application No. 17 / 461,981, entitled "Non-Volatile Memory Cell Array Formed in a P-Well in a Deep N-Well in a P-Substrate", filed on August 30, 2021, which are hereby incorporated by reference herein.

[0002] (Field of the Invention) A number of embodiments of a non-volatile memory cell array formed in a p-well within a deep n-well within a p-substrate are disclosed. During an erase operation, a negative voltage is applied to the p-well to reduce the peak positive voltage required to erase the cells within the array.

Background Art

[0003] Different types of non-volatile memory are well known. For example, U.S. Patent No. 5,029,130 ​​("'130"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, a type of flash memory cell. Such a memory cell 110 is shown in Figure 1. Each memory cell 110 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed insulated above a first portion of the channel region 18 (and controlling the conductivity of the first portion of the channel region 18) and extends above a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed insulated above a second portion of the channel region 18 (and controlling the conductivity of the second portion of the channel region 18) and a second portion extending upward above the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by the gate oxide. The bit line 24 is coupled to the drain region 16.

[0004] By applying a high positive voltage to the word line terminal 22 (relative to the substrate 12), erasure is performed on the memory cell 110 (electrons are removed from the floating gate), causing the electrons in the floating gate 20 to pass through the insulator between them to the word line terminal 22 via a Fowler-Nordheim (FN) tunnel.

[0005] The memory cell 110 is programmed by source-side injection (SSI) using hot electrons by applying a positive voltage to the word line terminal 22 (relative to the substrate 12) and a positive voltage to the source region 14 (electrons are added to the floating gate). The electron flow flows from the drain region 16 towards the source region 14. The electrons are accelerated and generate heat when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 via the gate oxide due to the electrostatic attraction from the floating gate 20.

[0006] The memory cell 110 is read by applying a positive read voltage (to the substrate 12) to the drain area 16 and the word line terminal 22 (turning on the portion of the channel area 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., electrons are erased), the portion of the channel area 18 below the floating gate 20 is also turned on, and current flows through the channel area 18, which is detected as the erased state, i.e., the "1" state. When the floating gate 20 is negatively charged (i.e., electrons are programmed), the portion of the channel area 18 below the floating gate 20 is almost or completely off, and no (or very little) current flows through the channel area 18, which is detected as the programmed state, i.e., the "0" state.

[0007] Table 1 shows typical voltage / current ranges that can be applied to the terminals of the memory cell 110 to perform read, erase, and program operations. [Table 1]

[0008] The voltages in Table 1 are based on the circuit board 12 to which 0V is applied during read, erase, or program operations.

[0009] Other types of flash memory cells, such as other split-gate memory cell configurations, are also known.

[0010] For example, Figure 2 shows a four-gate memory cell 210 comprising a source region 14, a drain region 16, a floating gate 20 above a first portion of the channel region 18, a selection gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates are non-floating gates, except for the floating gate 20; that is, they are electrically connected to or can be connected to a voltage source. Programming is performed by heated electrons from the channel region 18 injected into the floating gate 20 via the gate oxide due to an electrostatic attraction from the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0011] Table 2 shows typical voltage / current ranges that can be applied to the terminals of the memory cell 210 to perform read, erase, and program operations. [Table 2]

[0012] A voltage of 0V is applied to the circuit board 12 during read operation, erase operation, or program operation.

[0013] Figure 3 shows a different type of flash memory cell, a 3-gate memory cell 310. Memory cell 310 is identical to memory cell 210 in Figure 2, except that memory cell 310 does not have a separate control gate. The erase operation (erasure occurs through the use of an erase gate) and read operation are the same as those of memory cell 210 in Figure 2, except that no control gate bias is applied. The programming operation is also performed without a control gate bias; therefore, during the programming operation, a higher voltage must be applied to the source line to compensate for the lack of control gate bias.

[0014] Table 3 shows typical voltage / current ranges that can be applied to the terminals of the memory cell 310 to perform read, erase, and program operations. [Table 3]

[0015] A voltage of 0V is applied to the circuit board 12 during read operation, erase operation, or program operation.

[0016] Space within the semiconductor die is precious. In the prior art systems described above, considerable space is required for the external circuitry necessary for read, program, and / or erase operations. For example, the high voltage required for the erase operation necessitates special high-voltage generation and regulation circuits, which in turn necessitates high-voltage transistors that require a larger area on the semiconductor die due to thicker gate oxide, longer channel length, and wider physical spacing.

[0017] What is needed is a new architecture for non-volatile memory cell arrays that reduces the voltage required for erasure operations, and subsequently reduces the space required for high-voltage generation and regulation circuits. [Overview of the Initiative]

[0018] A number of embodiments of a non-volatile memory cell array formed within a p-well formed within a deep n-well formed within a p-substrate are disclosed. During an erase operation, a negative voltage is applied to the p-well, reducing the peak positive voltage that needs to be applied to the cell to erase the cell.

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Brief Description of the Drawings

[0027] [Figure 1] Shows a prior art split gate flash memory cell. [Figure 2] Shows another prior art split gate flash memory cell. [Figure 3] Shows another prior art split gate flash memory cell. [Figure 4] Shows a non-volatile memory system. [Figure 5] Shows a non-volatile memory system including a p-well surrounding an array. [Figure 6] Shows a non-volatile memory system including a plurality of p-wells surrounding an array, a low voltage decoder circuit, and a high voltage decoder circuit. [Figure 7] Shows a non-volatile memory system including a plurality of p-wells surrounding a first array, a second array, a low voltage decoder circuit, and a high voltage decoder circuit. [Figure 8]The diagram shows a non-volatile memory system comprising a first array, a second array, a first low-voltage decoder circuit, a second low-voltage decoder circuit, a first high-voltage decoder circuit, and a plurality of p-wells surrounding the second high-voltage decoder circuit. [Figure 9] This shows a cross-section of a non-volatile memory system with p-wells surrounding an array. [Modes for carrying out the invention]

[0028] Embodiments described herein allow a negative voltage to be applied to a p-well surrounding a particular component in order to enable the use of a lower voltage during the erase operation of a non-volatile memory cell.

[0029] Figure 4 shows a block diagram of the non-volatile memory system 400. The non-volatile memory system 400 comprises an array 401, a row decoder 402, a high-voltage decoder 403, a column decoder 404, a bit line driver (also known as a column driver) 405 (for controlling the program (current) on the bit line terminals), an output circuit 407, control logic 408, and a bias generator 409. The non-volatile memory system 400 further comprises a high-voltage generation block 410, which includes a charge pump 411, a charge pump regulator 412, and a high-voltage level generator 413. The non-volatile memory system 400 further comprises an algorithm controller 414 (for program / erase or weight adjustment), analog circuitry 415, a control engine 416 (which may include, but is not limited to, special functions such as arithmetic functions, startup functions, or embedded microcontroller logic), and test control logic 417.

[0030] The output circuit 407 may include circuits such as a digital sensing circuit for converting the cell current to a logical "1" or "0", or an analog sensing circuit such as an ADC (analog-to-digital converter), an AAC (analog-to-analog converter) such as a current-to-voltage converter, a logarithmic converter, an APC (analog-to-pulse converter), an analog-to-time modulated pulse converter, or any other type of converter for converting the neuron analog output to a digital bit. The output circuit 407 may perform an activation function such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 407 may perform statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) on the neuron output. The output circuit 407 may perform a temperature compensation function for the bit line output.

[0031] In the embodiments described below with reference to Figures 5 to 9, the array, and optionally other components, are surrounded by deep n-wells and located in p-wells above the deep n-wells. Then, during certain operations, such as the erase operation of non-volatile memory cells, a negative voltage is applied to the p-wells on the p-substrate by a bias generator 409 or another voltage source. This reduces the maximum voltage required for the erase operation, thereby reducing the overall size and power of the high-voltage generation block 410.

[0032] Figure 5 shows a plan view of the non-volatile memory system 500. The non-volatile memory system 500 comprises an array 501, a row decoder 502 (an example of the row decoder 402 in Figure 4), and a high-voltage decoder 503 (an example of the high-voltage decoder 403 in Figure 4). The array 501 is formed within a p-well 504 formed within a deep n-well 505, and the deep n-well 505 is formed within a p-substrate 580. Therefore, the p-well 504 can receive different voltages (including, but not limited to, negative voltages) because it is isolated from the p-substrate 580 by the deep n-well 505. For example, the p-substrate 580 may be biased at 0V, the deep n-well 505 may be biased at 0-2V, and the p-well 504 may be biased at -0.1V--10V. These bias voltages can be generated by a bias generator 409 or another voltage source.

[0033] Figure 6 shows the non-volatile memory system 600. The non-volatile memory system 600 comprises an array 601, a row decoder 602 (an example of the row decoder 402 in Figure 4), and a high-voltage decoder 603 (an example of the high-voltage decoder 403 in Figure 4).

[0034] Array 601 is formed within p-well 604, and p-well 604 is formed within deep n-well 605.

[0035] The row decoder 602 is formed in the p-well 608, and the p-well 608 is formed in the deep n-well 609.

[0036] The high-voltage decoder 603 is formed in the p-well 606, and the p-well 606 is formed in the deep n-well 607.

[0037] Deep n-wells 605, 607, and 609 are formed within (and above) the p-substrate 680, respectively. Optionally, deep n-wells 605, 607, and 609 may be separate deep n-wells or part of a common deep n-well.

[0038] Therefore, since the p-well 604 containing array 601 is isolated from the p-substrate 680 by the deep n-well 605, it can be driven with a negative voltage relative to the p-substrate 680 by the bias generator 409 or another voltage source.

[0039] Therefore, since the p-well 606 containing the high-voltage decoder 603 is isolated from the p-board 680 by the deep n-well 607, it can be driven with a negative voltage relative to the p-board 680 by the bias generator 409 or another voltage source.

[0040] For example, the p-board 680 can be biased at 0V, and the deep n-well 605, 6 Wells 07 and 609 can be biased to 0-3V, and p-wells 604, 606, and 608 can be biased to -0.1V--10V. These bias voltages can be generated by bias generator 409 or another voltage source.

[0041] Figure 7 shows a non-volatile memory system 700. The non-volatile memory system 700 comprises array 701, array 702, a low-voltage decoder 703, and a high-voltage decoder 704. Array 701 is formed in a p-well 705, and p-well 705 is formed in a deep n-well 706. Array 702 is formed in a p-well 707, and p-well 707 is formed in a deep n-well 708. The low-voltage decoder 703 is formed in a p-well 709, and p-well 709 is formed in a deep n-well 710. The high-voltage decoder 704 is formed in a p-well 711, and p-well 711 is formed in a deep n-well 712. Optionally, deep n-wells 706, 708, 710, and 712 may be separate deep n-wells or part of a common deep n-well. The p-substrate PSUB780 is a substrate on which all circuits, namely array 701, array 702, low-voltage decoder 703, and high-voltage decoder 704, are formed.

[0042] Figure 8 shows a non-volatile memory system 800. The non-volatile memory system 800 comprises array 801, array 802, low-voltage decoder 803, low-voltage decoder 804, high-voltage decoder 805, and high-voltage decoder 806. Array 801 is formed in a p-well 807, and p-well 807 is formed in a deep n-well 808. Array 802 is formed in a p-well 809, and p-well 809 is also formed in a deep n-well 808. Low-voltage decoder 803 is formed in a p-well 810, and p-well 810 is formed in a deep n-well 811. Low-voltage decoder 804 is formed in a p-well 812, and p-well 812 is formed in a deep n-well 813. High-voltage decoder 805 is formed in a p-well 814, and p-well 814 is formed in a deep n-well 815. The high-voltage decoder 806 is formed in a p-well 816, and the p-well 816 is formed in a deep n-well 817. Optionally, the deep n-wells 808, 811, 815, 813, and 817 may be separate deep n-wells or part of a common deep n-well. The p-substrate 880 is the substrate on which all the circuits, namely arrays 801, 802, low-voltage decoder 803, low-voltage decoder 804, high-voltage decoder 805, and high-voltage decoder 806, are formed.

[0043] Therefore, since p-wells 807 or 809 are isolated from p-board 880 by the deep n-well 808, they can be driven to a negative voltage independently of p-board 880 by the bias generator 409 or another voltage source. Similarly, since p-wells 810, 812, 814, and 816 are isolated from p-board 880 by their respective deep n-wells 811, 813, 815, and 817, they can be driven to a negative voltage independently of p-board 880 by the bias generator 409 or another voltage source.

[0044] Figure 9 shows a cross-section of 900. The array 901 or low-voltage decoder, row decoder 902, or high-voltage decoder 903 (representing the array, row decoder, and high-voltage decoder shown in Figures 5 to 8, respectively) is formed within the p-well 904, the p-well 904 is formed within the deep n-well 905, and the deep n-well 905 is formed within the p-board 980. The p-well terminal 906 provides access to the p-well 904 and can be used, for example, to apply a negative voltage to the p-well 904 (relative to the p-board 980) by a bias generator 409 or another voltage source during an erase operation. The n-well terminal 907 is used to apply a bias voltage to the deep n-well 905, and the p-board terminal 908 is used to apply a bias voltage (which may include 0V) to the p-board 980. The p-board 980 is the board on which all the circuits, namely the array 901 or low-voltage decoder, row decoder 902, or high-voltage decoder 903, are formed.

[0045] Optionally, the p board 980 in Figures 5 to 9 may be biased by the bias generator 409 or another voltage source with a negative voltage such as -0.1V to -3V instead of 0V.

[0046] Using the architectures in Figures 5-9, the following operating voltages may be used to perform read, program, and erase operations on the non-volatile memory cells 110, 210, and 310 in Figures 1-3. However, it should be understood that the substrate 12 (which is the p-substrate) in Figures 1-3 is modified to include a p-well within a deep n-well, as shown in the cross-section 900 of Figure 9, so that the substrate 12 becomes the p-substrate 980, with a deep n-well 905 formed within the substrate 12, a p-well 904 formed within the deep n-well 905, and the array of memory cells 110, 210, and 310 formed within the p-well 904. Furthermore, as shown in Figure 9, the p-well 904 is accessed using the p-well terminal 906, the deep n-well 905 is accessed using the n-well terminal 907, and the p-substrate 980 is accessed using the p-substrate 980. In this configuration, the p-well 904 acts as a (virtual) p-substrate for the memory cells and other components of the array.

[0047] Tables 4-10 below contain exemplary operating voltages applied to memory cells 110, 210, and 310 when configured as shown in Figure 9. In these examples, a voltage of 0V is applied to the p-board 980 (board 12) via the p-board terminal 908 by the bias generator 409 or another voltage source, a voltage of 0-2V is applied to the deep n-well 905 via the n-well terminal 907, and a voltage of -0.1V--12V is applied to the p-well 904 via the p-well terminal 906.

[0048] Table 4 shows the first set of operating voltages (defined with respect to the substrate 12) for the memory cell 110 in Figure 1 when the substrate 12 is modified to include a p well 904 within the deep n well 905 in the substrate 12. [Table 4]

[0049] Table 5 shows the second set of operating voltages for the memory cell 110 in Figure 1 when the substrate contains p wells within a deep n well. [Table 5]

[0050] The p-well 904 is particularly advantageous in situations where a negative voltage is applied to one or more terminals of the cell during the erase operation, because in such situations, applying a negative voltage to the p-well 904 using the bias generator 409 or another voltage source reduces stress on the gate oxide region when a negative voltage is applied to the terminals, as the p-well 904 acts as a virtual substrate for the cell that is biased to a negative voltage.

[0051] Table 4 is appropriate when stress on the gate oxide region is not a concern, and Table 5 is appropriate when stress on the gate oxide region is a concern. In Table 4, a word line voltage of 0V is applied to the unselected cell during the erase operation, whereas in Table 5, a word line voltage of -2.5V is applied to the unselected cell during the erase operation due to the fact that it is desirable to reduce stress on the gate oxide region of the memory cell 110 and on the peripheral (decoding) transistor for the 2.5V gate oxide. In the operation of Table 4, the required absolute voltage does not cause the voltage across the gate oxide region to exceed the gate oxide breakdown voltage of both the decoding circuit and the cell, and as a result, the isolated p subwell 04 is not required for the decoding circuit, so stress on the gate oxide region of the decoding circuit is not a concern. In contrast, in the embodiment of Table 5, a bias generator 409 or another voltage source applies a negative voltage to specific terminals to reduce stress on the gate oxide region, and as a result, the isolated p subwell 904 is advantageous for the decoding circuit.

[0052] Table 6 shows the first set of operating voltages for the memory cell 210 in Figure 2 when the substrate contains p wells within a deep n well. [Table 6]

[0053] Table 7 shows the second set of operating voltages for the memory cell 210 in Figure 2 when the substrate contains p wells within a deep n well. [Table 7]

[0054] Table 8 shows the first set of operating voltages for the memory cell 310 in Figure 3 when the substrate contains p wells within a deep n well. [Table 8]

[0055] For the same reasons as described above with respect to Tables 5 and 6, the use of p-well 904 is particularly advantageous for Table 8 and significantly more advantageous for Table 7.

[0056] Table 9 shows the second set of operating voltages for the memory cell 310 in Figure 3 when the substrate contains p wells within a deep n well. [Table 9] [Table 10]

[0057] For the same reasons as described above with respect to Tables 5 and 6, the use of p-well 904 is particularly advantageous for Table 10 and significantly more advantageous for Table 9.

[0058] It should be noted that, as used herein, the terms “over” and “on” both encompass “directly” (without intermediate material, element, or gap between them) and “indirectly to” (with intermediate material, element, or gap between them). Similarly, the term “adjacent” includes “directly adjacent” (without intermediate material, element, or gap between them) and “indirectly adjacent” (with intermediate material, element, or gap between them); “attached” includes “directly attached” (without intermediate material, element, or gap between them) and “indirectly attached to” (with intermediate material, element, or gap between them); and “electrically coupled” includes “directly electrically coupled” (without intermediate material or element between them electrically connecting the elements together) and “indirectly electrically coupled to” (with intermediate material or element between them electrically connecting the elements together). For example, forming an element "on top of a substrate" may include forming the element directly on the substrate without any intermediate materials / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. A non-volatile memory system, Deep n-wells formed on the p-substrate of a semiconductor die, A first p-well formed within the deep n-well, A second p-well formed within the deep n-well, A third p-well formed within the deep n-well, A fourth p-well formed within the deep n-well, A first array of multiple nonvolatile memory cells formed in the first p-well, wherein each nonvolatile memory cell in the first array includes a floating gate and a plurality of terminals, A second array of multiple nonvolatile memory cells formed in the second p-well, wherein each nonvolatile memory cell in the second array includes a floating gate and a plurality of terminals, A bias generator for applying a negative voltage to the first p-well during the erase operation of one or more of the plurality of non-volatile memory cells in the first array, and for independently applying a negative voltage to the second p-well during the erase operation of one or more of the plurality of non-volatile memory cells in the second array, A low-voltage decoder formed in the third p-well, A non-volatile memory system comprising a high-voltage decoder formed in the fourth p-well.

2. The non-volatile memory system according to claim 1, wherein the plurality of terminals of each non-volatile memory cell in the first array and the second array include bit line terminals, source line terminals, and word line terminals.

3. The non-volatile memory system according to claim 2, wherein the plurality of terminals of each non-volatile memory cell in the first array and the second array further include erase gate terminals.

4. The non-volatile memory system according to claim 1, wherein the bias generator applies a voltage of 0V to the word lines of unselected non-volatile memory cells in the first array and the second array during read, erase, and programming operations.

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