Analog-to-digital converter with automatic zeroing residual amplification circuit

Abstract

To disclose several examples of analog-to-digital converters (ADCs) capable of performing automatic zeroing accompanied by amplifying a signal to improve the signal-to-noise ratio.SOLUTION: An ADC may generate a first digital code for representing an analog input signal and a second digital code based on the residuals from the first digital code, and in combination with the first digital code and the second digital code, a digital output code for representing an analog input signal can be generated. The ADC can use the first and second observations of the analog residual value to represent the residual to generate a second digital code.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] This disclosure generally relates to the field of electronic circuits, and more specifically, but not limited to, systems and methods for data conversion.

Background Art

[0002] Analog signals and / or values can be generated by various types of circuit elements such as signal generators, sensors, and antennas. However, there can be many instances where having a digital signal or value can be beneficial for purposes such as processing or storing the signal or value. To utilize the advantages of having a digital signal or value when an analog signal or value is generated, analog-to-digital converters (ADCs) have been developed to convert analog signals or values to digital signals or values.

[0003] A signal can be a time-based sequence of values. Digital values can be represented by codes. The name of a code (e.g., CODE1) can refer to the digital value represented by the code. Some (but not all) digital values can be represented by codes using binary weighted encoding. The resolution of a digital value or code represented by the number of bits can be related to binary weighted encoding regardless of how it can be encoded.

[0004] In many electronics applications, an analog input value is converted to a digital output value (e.g., for further digital processing or storage). For example, in a precision measurement system, an electronic device includes one or more sensors for making measurements, and these sensors can generate analog values. The analog values can be provided as inputs to an ADC to generate a digital output value for further processing or storage.

[0005] ADCs can be found in many applications, including broadband communication systems, automated test equipment, audio systems, vehicles, and factory automation systems. ADCs can convert analog electrical values ​​representing real-world phenomena such as light, sound, temperature, flow, or pressure. Designing an ADC is a critical task, as each application may have different needs in terms of speed, performance, power, cost, and size. As the number of applications requiring ADCs increases, so does the need for accurate and reliable conversion performance.

[0006] Some applications may require precise and accurate conversion of analog values, giving rise to the need for precision ADCs (precision meaning precise and / or accurate). Specifications required for precision ADCs may include low noise and small, stable offset. Constant-zero offset may be ideal. While ADCs and other circuits may be designed to aim for constant-zero offset, imperfections in the manufacturing process, inconsistencies in nominally identical semiconductor devices, atomic-level charge mobility, etc., can result in a circuit offset that is potentially non-zero, and the offset may drift with respect to parameters such as time, temperature, and / or supply voltage. Auto-zeroing (AZ) circuits may be used within precision ADCs to stabilize potentially non-zero offsets (i.e., reduce and / or substantially prevent their drift). The offset of an auto-zeroing circuit can be substantially zero (e.g., less than 100 microvolts, including drift). However, conventional AZ circuits can increase broadband noise levels, which is detrimental when low noise and low power are desired. The power consumption of precision ADCs may need to be increased to reduce noise to an acceptable level when AZ circuitry is used. There is a need for low-power ADCs, including a need for low-power, low-offset, and low-noise precision ADCs.

[0007] Several types of AZ circuits have been developed. Figure 1 shows a conventional AZ amplifier circuit 120. The AZ amplifier circuit 120 can operate in two phases: phase 1 (labeled Φ1 in Figure 1) and phase 2 (labeled Φ2 in Figure 1). Phases 1 and 2 are non-overlapping in time, and the operation can repeat periodically or aperiodically. Switches 113 and 107 are closed (conductive) during phase 1, and otherwise these switches are open (non-conductive). Similarly, switches 115p and 115m are closed during phase 2, and otherwise these switches are open. The voltage-in-voltage-out amplifier circuit 121 has two input terminals 103p and 103m and two output terminals 105p and 105m. In one embodiment, terminals 103m and 105m are connected and share a common potential such as ground or 0V. In phase 1, input terminals 103p and 103m are short-circuited by switch 107, thereby establishing a nominal zero voltage across input terminals 103p and 103m. Amplifier circuit 121 has a potentially non-zero offset, such as OS = 1mV. The amplified offset may be observed at terminals 105p and 105m when switch 107 is closed during phase 1. For example, if amplifier circuit 121 has a voltage gain coefficient of GAIN = 200, the amplified offset GAIN·OS = 200·1mV = 200mV will be observed as the voltage between output terminals 105p and 105m. Note that the offset OS can be an undesirable artifact of amplifier circuit 121, and that the AZ amplifier circuit 120 does not need to include circuitry to intentionally provide a non-zero offset OS. Therefore, Figure 1 does not (and should not) show a source or any other circuit to provide or represent an offset OS that may (but does not need to) be nominally zero. The amplified non-zero offset may be observed as a non-zero voltage between terminals 105p and 105m, even if the voltage between terminals 103p and 103m is exactly zero.

[0008] Capacitor 109 is located between terminals 105p and 111p. Switch 113 short-circuits terminals 111p and 105m during phase 1, thereby allowing the amplified offset to be observed as a voltage across capacitor 109. Switch 113 is opened shortly before switch 107 is opened during the transition from phase 1 to phase 2, thereby sampling the observed amplified offset over capacitor 109. The voltage VRES (i.e., analog value) applied to input terminals 101p and 101m of the AZ amplifier circuit 120 is supplied to terminals 103p and 103m of the amplifier circuit 121 via switches 115p and 115m, which are closed during phase 2. On the other hand, if (VRES > 0), a voltage greater than the amplified offset GAIN·OS is observed between terminals 105p and 105m, and a voltage greater than zero is observed between terminals 111p and 105m. On the other hand, when (VRES < 0), a voltage less than the amplified offset GAIN·OS is observed between terminals 105p and 105m, and a voltage less than zero is observed between terminals 111p and 105m. Therefore, the polarity of the voltage VRES applied to the input (terminals 101p, 101m) of the AZ amplifier circuit 120 corresponds to the polarity of the amplified voltage GAIN·VRES observed at the output (terminals 111p, 105m) of the AZ amplifier circuit 120. When the polarities correspond, the effective offset of the AZ amplifier circuit 120 can be zero. The effective offset of the AZ amplifier circuit 120 can be zero even if the offset OS of the amplifier circuit 121 is non-zero. The described two-phase operation of the AZ amplifier circuit 120 can substantially cancel (i.e., reduce to a small value nominally zero) the potentially non-zero offset of the amplifier circuit 121. Circuits, processes, or operations that operate in multiple phases and are configured to effectively cancel out potentially non-zero offsets are sometimes referred to as “auto-zeroing” circuits, processes, or operations. Note that auto-zeroing operations may require little or no knowledge of the circuit’s potentially non-zero offsets.An AZ circuit (e.g., an AZ amplifier circuit 120) provides nominal operation (e.g., amplification) for only one of several phases of its operation (e.g., phase 1 and phase 2) (e.g., phase 2).

[0009] The AZ amplifier circuit 120 illustrates that the offset OS can be amplified and observed in one phase. The combination of the input VRES and the offset OS can be amplified and observed in another phase. The AZ amplifier circuit 120 outputs a combined combination of the two observations, so that the combined contribution from the offset OS can be substantially zero. Specifically, the first observation GAIN·OS and the second observation GAIN·(VRES+OS) are combined such that the contribution from the offset in one observation can be substantially canceled out by an equal and opposite (equal magnitude and opposite polarity) contribution from the offset in the other observation. For example, the combination of the two observations is GAIN·(VRES+OS)-GAIN·OS=GAIN·VRES. The contribution from the input VRES to the combined output is GAIN·VRES. The contribution from the offset OS to the combined output can be substantially zero, GAIN·(OS-OS)=0. The auto-zeroed offset can be nominally zero. The AZ circuit can suppress low-frequency noise, which is modeled as an offset that drifts over time.

[0010] The normal operation of the AZ amplifier circuit 120 in Figure 1 depends on the observation sampled on capacitor 109 in phase 1 being substantially maintained during the subsequent phase 2. To achieve this, the AZ amplifier circuit 120 is coupled to an amplifier (or buffer) circuit 117 configured to draw little, if any, charge from terminal 111p via capacitor 109 during phase 2. The offset of the amplifier circuit 117 is suppressed by the gain coefficient (e.g., GAIN=200) provided by the AZ amplifier circuit 120, when the gain coefficient is directed toward the input VRES. In some applications, the amplifier circuit 117 is an auto-zeroing amplifier circuit, such as the AZ amplifier circuit 120. In some implementation examples, capacitor 109 is split into two (not shown), with the first capacitor configured in series with terminal 105p and the second capacitor configured in series with terminal 105m.

[0011] Figure 2 shows another prior art type of AZ amplifier circuit 220. The voltage-in voltage-out amplifier circuit 221 subject to auto-zeroing has a pair of input terminals 203p and 203m and a pair of output terminals 205p and 205m. Amplifier circuit 211 further has an auxiliary input 211 for applying an auxiliary (control) voltage. The effective (auto-zeroed) offset of the AZ amplifier circuit 220 is the combination of the potentially non-zero offset of amplifier circuit 221 and the auxiliary voltage applied to input 211 to cancel the contribution from the offset. Amplifier circuit 221 is a two-stage amplifier circuit known to those skilled in the art. Amplifier circuit 221 comprises an input gm stage (i.e., a transconductance circuit, not shown) coupled to input terminals 203p and 203m and an output stage (e.g., a mutual resistance stage, not shown) coupled to output terminals 205p and 205m. An auxiliary gm stage (not shown) is coupled to input 211 and to the input gm stage. The currents provided by the input gm stage and the auxiliary gm stage are combined such that the current provided by the auxiliary gm stage can cancel out the offset of the input gm stage. The auxiliary voltage is sampled and stored on capacitor 209 coupled to input 211. Capacitor 209 is not directly coupled to output terminals 205p, 205m. The first terminal of capacitor 209 connected to input 211 is substantially floating when switch 213 is open. The output terminals 205p, 205m of amplifier circuit 221 are also the output terminals of AZ amplifier circuit 220. The input impedance of the optional loading circuit 217 may not be particularly important, and AZ amplifier circuit 220 may be more versatile in use than AZ amplifier circuit 120 in Figure 1.

[0012] The AZ amplifier circuit 220 operates in two phases: phase 1 (labeled Φ1 in Figure 2) and phase 2 (labeled Φ2 in Figure 2). During phase 1, switch 207 is closed, applying a zero voltage across terminals 203p and 203m. The amplified combination of the potentially non-zero offset and the auxiliary voltage is observed as a voltage at terminals 205p and 205m connected to the gm stage (transconductance stage circuit) 223. Switch 213 couples the gm stage 223 to capacitor 209 and input 211 during phase 1. The polarity of the amplified combination nominally determines the polarity of the current supplied by the gm stage 223, and thus can increase or decrease the auxiliary voltage at input 211 during phase 1 when switch 213 is closed. The operation in negative feedback mode ensures that the auxiliary voltage at input 211 settles substantially at the end of phase 1, and that the amplified combination at terminals 205p and 205m can be substantially zero.

[0013] Switch 213 is open for a certain period of time before switch 207 is opened during the transition from phase 1 to phase 2. This effectively samples the substantially set auxiliary voltage on capacitor 209, and the auxiliary voltage is held at input 211 during phase 2. Switch 219 is closed during phase 2 to bypass the current that could be supplied by gm stage 223. Alternatively, gm stage 223 is temporarily turned off during phase 2 to conserve power, and / or gm stage 223 is disconnected from terminals 205p, 205m by a switch (not shown). The analog input value VRES is applied to input terminals 201p, 201m of AZ amplifier circuit 220. The analog input value is supplied to terminals 203p, 203m of amplifier circuit 221 via switch 215p, 215m, which is closed during phase 2.

[0014] The operation of the AZ amplifier circuit 220 is as follows: In phase 1, when the auxiliary voltage is sampled on capacitor 209, a negative feedback operation modulates the auxiliary voltage so that the amplified combination of the offset and the auxiliary voltage is substantially zero at or near the end of phase 1. The amplified contribution from the sampled auxiliary voltage may be substantially equal to and opposite to the amplified contribution from the offset. The sampled auxiliary voltage is the first observation of the amplified offset.

[0015] In phase 2, amplifier circuit 221 amplifies the combination of input VRES, offset, and sampled auxiliary voltage. The amplified combination is observed and output at terminals 205p and 205m. The contribution of the offset to the amplified combination can be substantially equal to and inversely equal to the contribution of the sampled auxiliary voltage to the amplified combination, and these two contributions can substantially cancel each other at terminals 205p and 205m. This is the auto-zeroing operation. Therefore, the amplified combination observed and output at terminals 205p and 205m responds to VRES and substantially does not respond to the offset of amplifier circuit 221. The sampled auxiliary voltage is the first observation of the amplified offset, and this first observation is combined with a second observation of the amplified offset that takes place during phase 2.

[0016] Various types of auto-zeroing amplifiers are conventionally known. Common characteristics include their operation in multiple phases, and the application of a nominally zero voltage to the input during one of these phases of operation. Another common characteristic is that observations made between the multiple phases combine to substantially cancel out potentially non-zero offsets.

[0017] An auto-zeroing amplifier can be configured to amplify the residual value in an analog-to-digital converter (ADC) circuit. Figure 3 shows a block diagram of an ADC 300 with a residual amplifier 320. In some embodiments, the residual amplifier 320 is the AZ amplifier circuit 220 shown in Figure 2. The ADC 300 receives an analog voltage VIN(t). A sample-and-hold (S / H) circuit 301 samples VIN(t) at the sampling instant (t=T0) and outputs the held analog value VIN. A first quantizer (ADC1) 303 is configured to receive the analog value VIN and derive a first digital value (CODE1) representing VIN. The digital value CODE1 is a relatively low-resolution digital representation of VIN. For example, CODE1 may be a 5-bit digital representation of VIN. The ADC 300 derives and processes the residual of VIN with respect to CODE1 as a step in a method for deriving a higher-resolution and more precise digital representation of VIN. Specifically, the digital-to-analog converter (DAC) 305 derives the analog representation of CODE1, and the difference between VIN and the analog representation of CODE1 is the residual value VRES. The residual value VRES is amplified by the residual amplifier 320, and the second quantizer (ADC2) 330 is configured to derive the digital representation of the residual value VRES, CODE2, taking into account the gain coefficient A provided by the residual amplifier 320. The combination of CODE1 and CODE2 is the high-resolution, high-precision representation of VIN.

[0018] The accuracy achievable by ADC300 may substantially depend on the accuracy achieved by DAC305 and residual amplifier 320. For comparison, if CODE2 is an accurate representation of the residual value VRES, the accuracy of ADC1303 may be relatively insignificant. The accuracy required from ADC2330 is lower than the overall accuracy provided by ADC300 if the absolute value of the gain coefficient A of residual amplifier 320 is greater than 1. The upper limit of the gain coefficient A depends on the resolution and accuracy of CODE1 representing VIN. For example, if CODE1 has a 5-bit resolution and an accuracy that does not cause overload / saturation of residual amplifier 320 and / or ADC2330, a gain coefficient A = 16 is used.

[0019] For clarity, ADC1 and / or ADC2 are sometimes referred to as “quantizers” instead of ADCs. PHOSITA recognizes that, in the overall recurrent structure, ADC2330 in Figure 3 can be implemented as ADC300 in Figure 3. A known example of a so-called pipelined ADC is ADC300, where ADC2330 is a cascade of several similar stages.

[0020] The block diagram of ADC300 in Figure 3 represents one of several types of analog-to-digital converters equipped with a residual amplifier 320. For example, ADC300 could be a so-called hybrid SAR ADC in which CODE1 is at least partially derived by using a successive approximation algorithm (PHOSITA recognizes that SAR ADC means “successive approximation register analog-to-digital converter” and PHOSITA is familiar with the design and operation of SAR ADCs). In another example, CODE1 is derived by a flash ADC1303 configured to receive VIN. In yet another example, CODE1 is provided by a flash or other type of ADC configured to receive VIN(t), and its operation (e.g., the operation of sampling VIN(t)) is synchronized with the operation of the S / H circuit 301. In yet another example, ADC1303 in Figure 3 is a SAR quantizer, a hybrid SAR quantizer, a VCO-based quantizer, a two-stage quantizer, a multi-stage quantizer, or a pipelined quantizer that provides a digital value CODE1 (where CODE1 may have a resolution of 10 bits or more) which is a relatively high-resolution representation of VIN. Thus, ADC1303 in Figure 3 is a representation of some type of circuit or some type of method for providing a digital representation of VIN, CODE1. ADC300 derives an analog residual value VRES as the difference between the analog representation of the digital value CODE1 and the analog value VIN. In one embodiment, a capacitive digital-to-analog converter (CDAC) circuit receives an analog value VIN and a digital value CODE1 and generates an analog residual value VRES based on the analog value VIN and the digital value CODE1. The terminology may be that VRES is the residual of VIN with respect to CODE1, or equivalently (with the polarity reversed) VRES is the residual of CODE1 with respect to VIN. The magnitude and other characteristics of the residual VRES depend on how CODE1 can be derived to represent VIN, in particular including (but not limited to) the resolution and precision of CODE1.

[0021] The accuracy achievable by the ADC300 substantially depends on the accuracy achievable by the DAC305 and residual amplifier 320. Several approaches involve deriving VIN by sampling a combination of the analog input value VIN(t) and the analog dither value. This approach can generalize the operation of the S / H circuit 301 and DAC305, which are combined via a capacitive digital-to-analog converter (CDAC) circuit. Another approach derives a high-resolution digital value CODE1 that enables a high gain coefficient A of the residual amplifier 320 (if desired). Thus, many variations of the ADC circuit can be configured to incorporate the low-offset residual amplifier circuit described herein.

[0022] Figure 4 shows an exemplary ADC400 corresponding to the block diagram in Figure 3. This is a differential ADC400 that receives the analog input voltage difference VIN(t)=Vp(t)-Vm(t) at input terminals 401p and 401m. During the acquisition phase (labeled Φ0 in Figure 4), switches 403p, 403m, 405p, and 405m are closed, and the analog input voltage is applied to the capacitor array 407p and 407m. At the end of the acquisition phase or a sampling instant (t=T0) near thereto, sampling switches 405p and 405m are opened, isolating the differential charge amount at nodes 409p and 409m. Input switches 403p and 403m are opened after the sampling instant with a short delay (e.g., 200 picoseconds). The capacitor array 407p and 407m is part of the CDAC structure. PHOSITA is familiar with the CDAC structure. The capacitor array 407p has a shared terminal connected to terminal 409p and a plurality of N1 terminals connected to input switch 403p (see Figure 2 of U.S. Patent No. 8,810,443). Therefore, input switch 403p may be an array of switches having a shared terminal connected to input terminal 401p and a plurality of N1 terminals connected to capacitor array 407p. The same applies to 407m, 409m, 403m, and 401m.

[0023] Figure 4 partially shows the first quantizer ADC1, implemented as a pair of quantizers ADC1p (411p) and ADC1m (411m) configured to process the voltages Vp(t) and Vm(t) applied to input terminals 401p and 401m individually (each voltage is observed relative to a predetermined potential such as ground or 0V). When sampling switches 405p and 405m are open, quantizers 411p and 411m sample Vp(t) and Vm(t) at the sampling instant (t=T0). Thus, the positively input digital value CODE1p represents the value of Vp(t) Vp(T0) at the sampling instant, and the negatively input digital value CODE1m represents the value of Vm(t) Vm(T0) at the sampling instant. The positive-to-negative digital value CODE1 = CODE1p - CODE1m represents the analog input value VIN = Vp(T0) - Vm(T0) at the sampling instant. In another embodiment, a single differential quantizer ADC1 is configured to provide a digital value CODE1 representing VIN=Vp(T0)-Vm(T0) without necessarily processing each input Vp(t) and Vm(t) individually.

[0024] The derived digital value CODE1p is applied via switches 413p and 415p such that the analog value (e.g., voltage) at terminal 409p is the residual VRESp of Vp(T0) with respect to CODE1p. Similarly, CODE1m is applied via switches 413m and 415m such that the analog value (e.g., voltage) at terminal 409m is the residual VRESm of Vm(T0) with respect to CODE1m. Switches 413p and 413m connect individual capacitors in capacitor arrays 407p and 407m to a first / higher reference potential VH in response to individual bits of CODE1p and CODE1m. Similarly, switches 415p and 415m connect individual capacitors in capacitor arrays 407p and 407m to a second / lower reference potential VL in response to individual bits of CODE1p and CODE1m. The capacitors in capacitor array 407p or capacitor array 407m are connected to either VH or VL in response to the bits of CODE1p or CODE1m. The term capacitive digital-to-analog converter (CDAC) may be used to describe capacitor arrays 407p, 407m and associated switches and reference potentials.

[0025] Therefore, an analog value is sampled on the CDAC (for example, Vp(T0) is sampled on one or more capacitors in capacitor array 407p via switches 403p and 405p), a digital value is applied to the CDAC (for example, switches 413p and 415p selectively connect individual capacitors in capacitor array 407p to a reference potential VH or VL in response to CODE1p), and the CDAC provides an analog value which is the residual of the sampled analog value with respect to the digital code (for example, the potential / voltage at node 409p is the residual VRESp of Vp(T0) with respect to CODE1p).

[0026] The residual amplifier 420 is configured to receive a residual value VRES = VRESp - VRESm (for example, the voltage between nodes 409p and 409m) representing the residual of the analog value VIN = Vp(T0) - Vm(T0) with respect to the digital value CODE1 = CODE1p - CODE1m. The residual amplifier 420 provides an amplified residual value A·VRES which is processed by the quantization circuit ADC2430. The ADC2430 is configured to provide a digital value CODE2 representing the residual VRES of VIN = Vp(T0) - Vm(T0) with respect to CODE1 = CODE1p - CODE1m, taking into account the gain coefficient A provided by the residual amplifier 420. The digital circuit 440 combines CODE1p, CODE1m, and CODE2 to provide a digital output code DOUT which can be a high-resolution representation of VIN = Vp(T0) - Vm(T0). For example, the ADC400 provides an output code DOUT with a resolution of 20 bits or 24 bits. To achieve high accuracy, the digital circuit 440 optionally receives and processes calibration information. The calibration information includes multiple codes representing the capacitance ratios of the capacitors in the capacitor arrays 407p, 407m. The calibration information is acquired / measured as part of the manufacturing process and stored in a memory device (not shown). The accuracy that can be achieved by the ADC 400 is substantially limited by the noise levels of the offset and residual amplifier 420. Conventional AZ residual amplifiers (e.g., AZ amplifier circuit 220 in Figure 2) may offer good offset stability but are at relatively high / poor noise levels. For comparison, non-automatic zeroing residual amplifiers may offer relatively lower / better noise and power operation but their offset stability may be relatively poor. [Overview of the Initiative] [Means for solving the problem]

[0027] In this specification, several embodiments of an analog-to-digital converter (ADC) that can perform auto-zeroing with signal amplification for improving the signal-to-noise ratio are disclosed. The ADC can generate a first digital code for representing an analog input signal and a second digital code based on a residual from the first digital code, and can combine the first digital code and the second digital code to generate a digital output code for representing the analog input signal. The ADC can utilize a first observation and a second observation of an analog residual value representing the residual to generate the second digital code.

[0028] Some embodiments disclosed herein may include an analog-to-digital converter (ADC) circuit comprising a sampling-quantization-residual generation (SQRG) circuit, an auto-zeroing residual amplification circuit, a quantization circuit, and a digital circuit. The sampling-quantization-residual generation (SQRG) circuit can generate a first digital code based at least in part on an analog input value received by the ADC circuit, and can generate an analog residual value based at least in part on the first digital code and the analog input value. The auto-zeroing residual amplification circuit can amplify the analog residual value and generate a first observation and a second observation of the amplified analog residual value. The quantization circuit can generate a second digital code, and the second digital code represents at least a combination of the first observation and the second observation. A digital circuit for generating a digital output code, a digital output code for representing the analog input value, the first digital code, and the second digital code are combined to generate the digital output code.

[0029] Some embodiments disclosed herein may include an auto-zeroing residual amplifier circuit for offset cancellation, the auto-zeroing residual amplifier circuit comprising an amplifier circuit and one or more switches. An amplifier circuit that amplifies a first observation of an analog residual value received by the auto-zeroing residual amplifier circuit and a second observation of the analog residual value, wherein the analog residual value is a residual of a digital code generated from an analog-to-digital conversion of an analog input value, and the amplified first observation and the amplified second observation are utilized with the digital code to generate a digital output code representing the analog input value. One or more switches coupled between the amplifier circuit and the input of the auto-zeroing residual amplifier circuit, wherein the analog residual value is received via the input of the auto-zeroing residual amplifier circuit, and the one or more switches selectively apply the first observation and the second observation to the amplifier circuit.

[0030] The auto-zeroing residual amplifier may be configured to operate in two phases, and the input residual value may be amplified and observed in both phases. Similar to conventional auto-zeroing amplifiers, the two observations may be combined to substantially cancel the potentially non-zero offset of the active circuit configured to provide amplification. Having two observations closely spaced in time may be advantageous. However, unlike conventional auto-zeroing amplifiers, both observations include the amplified residual value. Thus, the combined observations of the amplified residual values include a relatively higher level of signal (residual value) compared to the noise level. The noise level may be normalized by the signal level, and the relative noise level may be substantially lower than that of conventional auto-zeroing residual amplifier circuits. The relatively lower noise level facilitates the implementation of an ADC having substantially reduced noise and power operation, which is a significant improvement.

Brief Description of the Drawings

[0031] This disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, various features are not necessarily depicted to scale and are used for illustrative purposes only. Where a scale is explicitly or implicitly indicated, the scale provides only an illustrative example. In other embodiments, the dimensions of various features may be arbitrarily increased or decreased for clarity of description.

[0032] [Figure 1] This shows a conventional AZ amplifier circuit. [Figure 2] Another conventional type of AZ amplifier circuit is shown. [Figure 3] A block diagram of an ADC equipped with a residual amplifier is shown. [Figure 4] Figure 3 shows an exemplary ADC corresponding to the block diagram. [Figure 5] An exemplary first embodiment of an ADC circuit including an automatic zeroing residual amplification circuit is shown, according to various embodiments. [Figure 6] Exemplary quantizer ADC2s that can be used as alternatives to the ADC2 in Figure 5, according to various embodiments, are shown. [Figure 7A] Another exemplary embodiment of the ADC circuit is shown, according to various embodiments. [Figure 7B] Illustrative timing diagrams of the ADC circuit in Figure 7A are shown according to various embodiments. [Figure 7C] Exemplary ADC circuits featuring modified AZ residual amplifier circuits in various embodiments are shown. [Figure 7D] Further exemplary embodiments of ADC circuits, including modified AZ residual amplification circuits, are shown according to various embodiments. [Modes for carrying out the invention]

[0033] The following disclosure provides many different embodiments or examples for implementing various features of this disclosure. For the sake of simplicity, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. Furthermore, this disclosure may repeat reference numbers and / or reference letters in various embodiments or, in some cases, across different drawings. This repetition is for the purpose of simplification and clarification and does not in itself determine any particular relationship between the various embodiments and / or configurations considered. Different embodiments may have different advantages, and certain advantages are not necessarily required of any embodiment.

[0034] Figure 5 shows an exemplary first embodiment of the ADC circuit 500, including an automatic zeroing residual amplification circuit 520, according to this teaching. A sampling-quantization-residual generation circuit (SQRG circuit) 510 may be implemented, and the SQRG circuit 510 may include one or more features of the SQRG circuit 410 in Figure 4. The function of the SQRG circuit may be similar to the function of the part of the ADC 300 shown by 310 in Figure 3. Terminals 501p and 501m in Figure 5 may correspond to terminals 401p and 401m in Figure 4, respectively. Furthermore, terminals 509p and 509m may correspond to terminals 409p and 409m, respectively. Thus, the SQRG circuit 510 may provide an analog residual value VRES representing the residual of the analog input value VIN = Vp(T0) - Vm(T0) with respect to a first digital value CODE1 = CODE1p - CODE1m, where T0 is a specific time when the sample is generated. For example, the SQRG circuit 510 may receive an analog input value VIN via terminals 501p and 501m, where, in the exemplary embodiment, the analog input value VIN includes a differential voltage, the voltage provided via terminal 501p may include the positive component of the differential voltage, and the voltage provided via terminal 501m may include the negative component of the differential voltage. The SQRG circuit 510 may include an ADC1 (such as ADC1303 (Figure 3)) that generates a first digital value CODE1 based on the analog input value VIN. In the exemplary embodiment, the first digital value CODE1 may be represented by a positive digital component value CODE1p representing the positive component of the differential voltage of the input value VIN, and a negative digital component value CODE1m representing the negative component of the differential voltage of the analog input value VIN. The SQRG circuit 510 may output the first digital value CODE1. In the exemplary embodiment, the first digital value CODE1 output by the SQRG circuit 510 may include a positive digital component value CODE1p and a negative digital component value CODE1m.

[0035] The SQRG circuit 510 may further include a DAC (such as DAC305 (Figure 3)) that generates an analog representation of the first digital value CODE1. For example, the DAC may receive the first digital value CODE1 from ADC1 and generate an analog representation of the first digital value CODE1. In an exemplary embodiment in which the first digital value CODE1 is represented by a positive digital component value CODE1p and a negative digital component value CODE1m, the DAC may receive the positive digital component value CODE1p and the negative digital component value CODE1m, and generate an analog representation of the positive digital component value CODE1p and an analog representation of the negative digital component value CODE1m to form an analog representation of the first digital value CODE1.

[0036] The SQRG circuit 510 may further include a subtraction circuit (such as subtraction circuit 308 (Figure 3)) for generating a residual value VRES between an analog input value VIN and the analog representation of a first digital value CODE1. In particular, subtraction circuit 308 may receive the analog input value VIN and the analog representation of the first digital value CODE1, and generate the residual value VRES from the analog input value VIN and the analog representation of the first digital value CODE1. The residual value VRES may be output by the SQRG circuit 510. In the exemplary embodiment, the residual value VRES may be output as a positive analog component value at terminal 509p and a negative analog component value at terminal 509m, where the positive analog component value and the negative analog component value form the difference representation of the residual value VRES. The residual value VRES may be provided by the SQRG circuit 510 to the automatic zeroing residual amplification circuit 520 of the ADC circuit 500. In another embodiment, the digital value CODE1 may be provided as a single code rather than as a pair of codes (CODE1p, CODE1m). In another embodiment, VRES may be the residual of CODE1 with respect to the combination of the analog input value Vp(T0)-Vm(T0) and the dither value. The resolution of CODE1 may be relatively low (e.g., 5 bits or less), medium, or relatively high (e.g., 10 bits or more), depending on the set of design goals.

[0037] The automatic zeroing residual amplifier circuit 520 can operate in two phases (phase 2 and phase 3). The illustrated automatic zeroing residual amplifier circuit 520 includes instructions on which switches are closed during which phases, such that a switch with label Φ2 on it is closed during phase 2 and open during phase 3, and a switch with label Φ3 on it is closed during phase 3 and open during phase 2. For example, switches 503p and 503m may be closed during phase 2 and open during phase 3. Switches 505p and 505m may be open during phase 2 and closed during phase 3. Phase 2 may occur during a first period, and phase 3 may occur during a second period, and the first and second periods may not overlap in time. Phases 2 and 3 may repeat periodically or aperiodicly.

[0038] An active circuit configured to provide an amplifier circuit 521 may receive a first polarity (e.g., +VRES) of the analog residual value as input during phase 2. For example, during phase 2, switches 503p and 503m may be closed, while switches 505p and 505m may be open. Switches 503p and 503m may couple an SQRG circuit 510 to the amplifier circuit 521. The SQRG circuit 510 may provide the analog residual value VRES to the amplifier circuit 521 via switches 503p and 503m, with the positive analog component value of the analog residual value VRES being provided to the first input of the amplifier circuit 521 via switch 503p, and the negative analog component value of the analog residual value VRES being provided to the second input of the amplifier circuit 521 via switch 503m. Furthermore, during phase 3, the active circuit may receive a second polarity (e.g., -VRES) of the analog residual value opposite to the first polarity as input. For example, during phase 3, switches 505p and 505m may be closed, while switches 503p and 503m may be open. Switches 505p and 505m may couple the SQRG circuit 510 to the amplifier circuit 521. The SQRG circuit 510 may provide the amplifier circuit 521 with an analog residual value VRES via switches 505p and 505m, the positive analog component value of the analog residual value VRES is provided to the second input of the amplifier circuit 521 via switch 505m, and the negative analog component value of the analog residual value VRES is provided to the first input of the amplifier circuit 521 via switch 505p.

[0039] The amplifier circuit 521 may generate a first amplified combination A·(OS+VRES) of the residual value VRES and a potentially non-zero offset OS during phase 2, and may generate a second amplified combination A·(OS-VRES) of them during phase 3. For example, the amplifier circuit 521 may provide the first amplified combination A·(OS+VRES) to the ADC2530 at or near the end of phase 2, and the amplifier circuit 521 may provide the second amplified combination A·(OS-VRES) to the ADC2530 at or near the end of phase 3. In this embodiment, the AZ amplifier circuit 520 itself does not combine the two amplified combinations A·(OS+VRES) and A·(OS-VRES).

[0040] The two amplified combinations are available / observable at two different phases of operation (phase 2 and phase 3), but not simultaneously. For example, the first amplified combination A·(OS+VRES) may be available / observable at the output of amplifier circuit 521 at or near the end of phase 2, and the second amplified combination A·(OS-VRES) may be available / observable at the output of amplifier circuit 521 at or near the end of phase 3. ADC2530 may observe the first combination A·(OS+VRES) at or near the end of phase 2, and ADC2530 may generate a digital value CODE2p to represent A·(OS+VRES). ADC2530 may further observe the second combination A·(OS-VRES) at or near the end of phase 3, and ADC2530 may generate a digital value CODE2m to represent A·(OS-VRES). The ADC2530 may provide a positive digital component value CODE2p and a negative digital component value CODE2m at different times in the sequence corresponding to when each digital value is observed by the ADC2530.

[0041] The ADC circuit 500 can combine two observations of the amplified residual. In the exemplary embodiment, the digital circuit 540 may be coupled to the ADC 2530 at its output, and may receive a positive digital component value CODE2p and a negative digital component value CODE2m from the ADC 2530. Two observations that can be individually quantized by the ADC 2530 (represented by the positive digital component value CODE2p and the negative digital component value CODE2m generated by the ADC 2530) can be numerically combined by the digital circuit 540, which is configured to calculate the digital value CODE2 = CODE2p - CODE2m. The potentially non-zero offset OS of the amplification circuit 521 can be substantially canceled in CODE2 when CODE2p and CODE2m are combined by subtraction. This may be an auto-zeroing operation. CODE2 may represent the amplified analog residual value 2·A·VRES, or CODE2 may be scaled by the nominal amplification factor 2·A to represent VRES. By canceling potentially non-zero offset OS and amplifying the analog residual value VRES, the auto-zeroing residual amplification circuit 520 can produce an improved signal-to-noise representation of the analog residual value VRES, while maintaining or reducing the power consumption of the ADC 500 compared to conventional ADCs with auto-zeroing. This can result in improved ADC operation and / or reduced ADC power consumption compared to conventional ADCs.

[0042] The digital circuit 540 may be configured to derive a high-resolution representation DOUT of the analog input value VIN = Vp(T0) - Vm(T0) by calculating DOUT = CODE1p - CODE1m + (CODE2p - CODE2m) / (2·A). In another embodiment, the digital circuit 540 may be configured to calculate DOUT = CODE1p - CODE1m + CODE2p - CODE2m. For example, the digital circuit 540 may be coupled to an SQRG circuit 510 and receive a first digital code CODE1 representing the analog signal VIN from the SQRG circuit 510. The digital circuit 540 may be further coupled to an ADC 2530 and receive a digital value CODE2 from the ADC 2530. In an exemplary embodiment where the first digital code CODE1 and the digital value CODE2 are represented differentially, the digital circuit 540 may receive a positive digital component value CODE1p and a negative digital component value CODE1m to represent the first digital code CODE1, and may receive a positive digital component value CODE2p and a negative digital component value CODE2m to represent the digital value CODE2. The digital circuit may generate an output code DOUT for the analog input value VIN by any equation for calculating the output code DOUT. The output code DOUT may also respond to calibration information. The calibration information may include codes representing potential mismatches in the amplification coefficient A and / or potential mismatches in the parameters of the SQRG circuit 510 and / or ADC2530. The calibration information may be derived during the production process (e.g., production testing), or the calibration information may be derived by foreground and / or background calibration processes during operation, while the ADC circuit 500 may be deployed for use in an application (e.g., factory automation).

[0043] In another embodiment, the ADC2530 may be implemented as two separate quantizers. A first quantizer ADC2p (not shown) may observe A·(OS+VRES) at or near the end of phase 2 and provide a digital value CODE2p to represent A·(OS+VRES). Another quantizer ADC2m (not shown) may observe A·(OS-VRES) at or near the end of phase 3 and provide a digital value CODE2m to represent A·(OS-VRES). CODE1p, CODE1m, CODE2p, and CODE2m may be combined as described above. A potential advantage of implementing the ADC2 using two separate quantizers is that the two observations can be made with less temporal separation. This may improve the suppression of low-frequency noise from the amplifier circuit 521.

[0044] The advantages of the AZ residual amplifier circuit 520 can easily be overlooked. Both of the two observations that can be made to derive CODE2 represent the amplified residual value (A·VRES) in combination with the amplified offset (A·OS). Compare this to the operation of a conventional AZ amplifier (e.g., as shown in Figures 1 and 2) where only one of the two observations includes the amplified residual value (A·VRES), and both observations include the amplified offset (A·OS). The payload signal content (VRES) can be substantially higher (better) for the AZ amplifier circuit 520 compared to that of a conventional AZ amplifier. Each observation may be partially affected by broadband noise from the active circuits configured for amplification (amplifier circuit 521 in Figure 5, amplifier circuit 121 in Figure 1, and amplifier circuit 221 in Figure 2). The signal-to-noise ratio (residual-to-noise ratio) may be better when the residual value VRES is amplified, as shown in Figure 5 for the ADC circuit 500. The improved signal-to-noise ratio can enable a very significant (e.g., nearly four-fold) reduction in power consumption of the AZ residual amplifier circuit 520 compared to that of conventional AZ residual amplifier circuits (120 in Figure 1, 220 in Figure 2) for a given noise specification. Thus, in one embodiment, this teaching facilitates a significant reduction in the power consumption of the precision ADC. In another embodiment, this teaching facilitates a significant improvement in the signal-to-noise ratio of the precision ADC for a given power budget (e.g., 20 mW).

[0045] Figure 6 shows an exemplary quantizer ADC2630 that can be used in place of ADC2530 in Figure 5. The ADC2630 can combine two observations in the analog domain and perform a single analog-to-digital (A / D) conversion operation to derive a digital value CODE2 to represent the combination of the two observations. Thus, when implemented in place of ADC2530 in ADC circuit 500, the ADC2630 can receive amplified combinations (such as a first amplified combination A·(OS+VRES) and a second amplified combination A·(OS-VRES)) and output a digital value CODE2 to represent the combination of amplified combinations.

[0046] The ADC2630 may be a fully differential structure comprising a positive-side CDAC601p and a negative-side CDAC601m. The first observation may consist of an amplified analog residual value such as A·(OS+VRES), submitted to the ADC2630 by the AZ residual amplifier circuit 520 in Figure 5. The first observation may be sampled on capacitors 623p and 623m at or near the end of phase 2, when sampling switches 625p and 625m are open at or near the end of phase 2 (the switches that are closed during phase 2 are labeled Φ2 in Figure 6 and may coincide with Φ2 in Figure 5). Connecting switches 627p and 627m may be opened with a small delay (e.g., 200ps) after sampling switches 625p and 625m have been opened.

[0047] The second observation may consist of an amplified analog residual value, such as A·(OS-VRES), provided to the ADC2630 by the AZ residual amplifier 520 in Figure 5. The second observation may be sampled on capacitors 633p and 633m at or near the end of phase 3 when sampling switches 635p and 635m are open at or near the end of phase 3 (switches that are closed during phase 3 are labeled Φ3 in Figure 6 and may coincide with Φ3 in Figure 5). The sampling of the second observation may have the opposite polarity to the positive side CDAC601p and the negative side CDAC601m compared to the first observation. In particular, the amplified analog residual value of the first observation and the amplified analog residual value of the second observation may each be represented by a differential voltage. By closing switches 627p and 627m during phase 2, the positive component of the differential voltage of the first observation can be sampled on capacitor 623p of the positive side CDAC 601p, and the negative component of the differential voltage of the first observation can be sampled on capacitor 623m of the negative side CDAC 601m. By closing switches 637p and 637m during phase 3, the negative component of the differential voltage of the second observation can be sampled on capacitor 633p of the positive side CDAC 601p, and the positive component of the differential voltage of the second observation can be sampled on capacitor 633m of the negative side CDAC 601m. Therefore, the polarity of the first and second observations may be opposite with respect to the positive-side CDAC601p and the negative-side CDAC601m due to the swapping of the positive and negative components of the differential voltage of the observations between phases 2 and 3, between the positive-side CDAC601p and the negative-side CDAC601m. After the sampling switches 635p and 635m are opened, the connection switches 637p and 637m may be opened with a small delay (e.g., 200 ps). The ADC2630 may perform SAR-type ADC conversion operation during phase 4 after phases 2 and 3 (the switches closed during phase 4 are labeled Φ4 in Figure 6).

[0048] Phases 2, 3, and 4 may be temporally non-overlapping and may repeat periodically or aperiodically. For example, Phase 2 may occur during a first period, Phase 3 during a second period following the first period, and Phase 4 during a third period following the second period. In some embodiments, the order of the phases 2 and 3 may be swapped so that the first period in which Phase 2 occurs follows the second period in which Phase 3 occurs. Aperiodic operation may involve a substantially random selection of the sequence of Phases 2 and 3 preceding Phase 4 (i.e., in one transformation cycle, the sequence of phases may be 0, 1, 2, 3, 4, and in another transformation cycle, the sequence of phases may be 0, 1, 3, 2, 4). An exemplary embodiment may operate with a periodic sequence of phases (0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0, 1, ...).

[0049] Switches 641p and 643p may be closed during phase 4, thereby allowing the first and second observations sampled on capacitors 623p and 633p during phases 2 and 3 to be combined by charge sharing, and the combined value may be represented by the charge value at node 603p. Because the polarities of the first and second observations applied to the positive side CDAC 601p are opposite, the combination by charge sharing may result in a combination where the positive component of the differential voltage of the first observation sampled on capacitor 623p is combined with the negative component of the differential voltage of the second observation sampled on capacitor 633p. The charge value at node 603p may further include the charge value sampled on segment 605p of CDAC 601p at or near the end of phase 3. The charge value sampled on CDAC segment 605p may be a fixed value. In another embodiment, this charge value may be a dither value.

[0050] The negative side CDAC601m may operate in the same way as the positive side CDAC601p, as described. Specifically, switches 641m and 643m may be closed during phase 4, thereby combining observations sampled on capacitors 623m and 633m during phases 2 and 3 by charge sharing operation, which may be represented by the charge value at node 603m. Because the polarities of the first and second observations applied to the negative side CDAC601m are opposite, the combination by charge sharing operation may result in a combination where the negative component of the differential voltage of the first observation sampled on capacitor 623m is combined with the positive component of the differential voltage of the second observation sampled on capacitor 633m. The charge at node 603m may further include the charge value sampled on segment 605m of CDAC601m at or near the end of phase 3. The charge value sampled on CDAC segment 605m may be a fixed value. In another embodiment, this charge value may be a dither value.

[0051] PHOSITA recognizes that a digital state machine 607, sometimes called a Successive Approximation Register (SAR), can be configured to provide a successive approximation sequence of codes to successively reduce the range of uncertainty of the difference values ​​observed by the comparator circuit 609. The comparator circuit 609 may induce the SAR 607 to select individual codes within the successive approximation sequence of codes. The resulting codes provided by the SAR 607 may be a digital value CODE2 representing a combination of two observations. Specifically, CODE2 may represent a residual value VRES. Contributions from a potentially non-zero offset OS of a circuit configured to provide amplification can be substantially canceled in CODE2, since the contribution from the first observation may be substantially equal to and opposite to the contribution from the second observation. For example, swapping the polarities of the first and second observations with respect to the positive side CDAC 601p and the negative side CDAC 601m may result in the differential voltage of one of the observations being treated negatively with respect to the other observation. For understanding, this can be seen as applying the positive component of the differential voltage of the first observation to the positive side CDAC601p and the negative component of the differential voltage of the first observation to the negative side CDAC601m, resulting in the first observation being positive, for example, A·(OS+VRES). Applying the positive component of the differential voltage of the second observation to the negative side CDAC601m and the negative component of the differential voltage of the second observation to the positive side CDAC601p, results in the second observation being negative, for example, -(A·(OS-VRES)). The combination of the first and second observations results in the addition of a positive first observation and a negative second observation, which can result in the offset OS being effectively canceled out and the amplified residual value A·VRES being effectively doubled. For example, the combination of a positive first observation and a negative second observation may result in a value of 2·A·VRES.Switches 611p (i.e., the switch located within the dashed rectangle 611p) and 611m (i.e., the switch located within the dashed rectangle 611m) can connect individual capacitors within CDAC601p and CDAC601m to a higher reference potential VH or a lower reference potential VL, in response to the state of individual bits of each code in the successive approximation sequence of codes. PHOSITA recognizes that the operation of switch 611p in the fully differential ADC2630 may be complementary to the operation of switch 611m. The description herein of how CDAC601p operates is equivalent to the description of how CDAC601m operates.

[0052] The capacitor 623p and the switch 611p that drives capacitor 633p can be controlled by a single bit of each code in the successive approximation sequence of codes. Thus, with respect to the successive approximation sequence, capacitors 623p and 633p can be switched as a single capacitor (C / 4+C / 4) nominally twice the size (capacitance) compared to the largest capacitor (C / 4) in the CDA segment 605p. In one embodiment, the nominal weight coefficients of individual bits in CDA 601p that can be switched during the SAR ADC operating mode can be binary scaled (e.g., having weight coefficients of 1 / 2, 1 / 4, 1 / 8, 1 / 16, ...). In another embodiment, the nominal weight coefficients of individual bits in a modified CDA (not shown) may include redundancy (e.g., having weight coefficients of 1 / 2, 1 / 4, 1 / 8, 1 / 8, 1 / 16, 1 / 32, 1 / 64, 1 / 64, 1 / 128, ...). The resolution of the ADC2630 can be relatively low (e.g., 5 bits or less), medium, or relatively high (e.g., 10 bits or more).

[0053] PHOSITA recognizes that the ADC2630 can be modified to incorporate any type of A / D conversion principle (including, but not limited to, SAR ADCs, pipeline ADCs, VCO-based ADCs, flash ADCs, cyclic ADCs, interpolation ADCs, and hybrid ADCs). The ADC2630 can be configured to sample and convert combinations of multiple analog values. In some embodiments, an ADC can be implemented that can be configured to sample and convert combinations of an analog input value and a dither value (i.e., multiple pairs of analog values). The two analog values ​​can be sampled on separate segments of a CDAC. The ADC2630 in Figure 6 can be configured to sample and convert combinations of a first analog value (e.g., A·(OS+VRES)), a second analog value (e.g., A·(OS-VRES)), and a third analog value (e.g., a fixed value or dither value applied via switches 611p and 611m). Thus, the ADC2630 can be configured to sample and convert combinations of multiple pairs of analog values. Multiple analog values ​​can be sampled on multiple segments of the CDAC601p (e.g., capacitor 623p, capacitor 633p, and CDAC segment 605p). Each segment may have one or more capacitors that can be switched individually or jointly during the A / D conversion operation mode. Multiple analog values ​​can be sampled individually on separate segments of the CDAC at multiple nominally different sampling instants (e.g., at or near the end of phase 2, and at or near the end of phase 3). Individual segments of the CDAC configured to sample multiple analog values ​​can be combined before or as part of the analog-to-digital conversion operation (e.g., switches 641p and 643p can be closed at phase 4). Switches 643p, 643m, 635p, and 635m in Figure 6 may be nominally redundant or excessive, but they may be included to mitigate secondary artifacts such as switch charge injection, which is well known in PHOSITA.PHOSITA is also familiar with many types of circuits and methods for A / D conversion of analog values, which are represented as isolated charge quantities on the nodes of the CDAC (e.g., node 603p), after the analog values ​​have been sampled as described herein. Therefore, it is not necessary to provide further explanation herein of how to construct and operate the comparator circuit 609, the SAR circuit 607, and / or switches 611p and 611m.

[0054] In another embodiment, the ADC2630 in Figure 6 may be configured to provide A / D conversion operation, and during phase 4, regardless of any bit of any code in the successive approximation sequence of codes provided by SAR607, switches 611p and 611m may connect capacitors 623p, 633p, 623m, and 633m to a predetermined set of potentials (all of which may be connected to VH). Thus, the CDAC segment 605p may be configured to sample multiple input values ​​(such as A·(OS+VRES) and A·(OS-VRES)) on multiple segments of the CDAC (such as segment 605p) which are different from the segment of the CDAC (such as segment 605p) which is configured to apply the successive approximation sequence of codes via switches (such as switch 611p) during A / D conversion operation.

[0055] In another embodiment, switches 611p and 611m cannot drive capacitors 623p, 633p, 623m, and 633m during phase 4 or at any time. Instead, during phase 4, the left terminals of capacitors 623p, 633p, 623m, and 633m in Figure 6 may be short-circuited to each other by four switches not shown in Figure 6 (and these capacitors may not be connected to any fixed potential). The purpose of nominally short-circuiting and floating the four terminals during phase 4 may be to suppress common mode components of the first and second observations (such as A·(OS+VRES) and A·(OS-VRES)). CDAC segments 605p and 605m may be switched according to a successive approximation sequence of codes provided by SAR607. The CDAC segments 605p and 605m can be scaled with respect to capacitors 623p, 623m, 633p, and 633m to provide scaling of CODE2 with respect to the reference voltage difference (VH-VL) and the full-scale input range of the ADC2630. For example, each capacitor within the CDAC segments 605p and 605m can be reduced in size by a factor of 3 to compensate for the potential drop across the full-scale input range at a factor of 3.

[0056] In yet another embodiment, the quantizer ADC2 may be configured to sample and combine more than two (three, four, five, ..., etc.) observations to derive a digital value CODE2 to represent a weighted combination of more than two observations. For example, capacitors 623p and 623m may each be divided into two half-size (C / 8) capacitors and configured with switches to sample analog values ​​at two different points in time (e.g., at or near the end of phase 2a, and at or near the end of phase 2b). The quantizer ADC2 may be incorporated into a modified ADC circuit, similar to the ADC circuit 500 in Figure 5. The control circuit may provide switch control signals to provide a modified sequence of phases of operation, (phase 0, phase 1, phase 2a, phase 3, phase 2b, phase 4). Phase 2 may be an OR combination of phase 2a and phase 2b. Specifically, the switches 503p and 503m of the AZ amplifier circuit 520 in Figure 5 can be closed in phase 2a and in phase 2b. Thus, the AZ amplifier circuit 520 can be configured to provide a sequence of amplified analog residual values, i.e., A·(OS+VRES) during phase 2a, A·(OS-VRES) during phase 3, and A·(OS+VRES) during phase 2b. The first value A·(OS+VRES) can be observed and sampled on the front half (C / 8) of capacitors 623p and 623m during phase 2a. The second value A·(OS-VRES) can be observed and sampled on the (C / 4) capacitors 633p and 633m during phase 3. The third value A·(OS+VRES) can be observed and sampled on the rear half (C / 8) of capacitors 623p and 623m during phase 2b. The potentially non-zero offset of the amplification circuit 521 can be substantially canceled in CODE2, which may represent a weighted combination of three sampled observations. Thus, a modified ADC circuit 500, equipped with a quantizer ADC2 and operating in a phase-corrected sequence, can be configured to provide an automatic zeroing operation for the potentially non-zero offset of the circuit 521 configured to provide amplification.The modified ADC circuit 500 may provide improved robustness against secondary artifacts such as charge injection, and / or the modified ADC circuit 500 may provide improved suppression of low-frequency noise compared to the ADC circuit of prior art. The ADC 2 may be configured to observe and combine any number (two or more) of amplified analog residual values. The ADC 2 may be configured to combine the multiple observations with nominally uniform or non-uniform weighting. The exemplary embodiments described herein may be configured to apply nominally non-uniform weighting, i.e., [+0.25, -0.50, +0.25]. The weighting coefficient (-0.50) may be given substantially more weight (more than 20 percent more weight) than the other two weighting coefficients (+0.25, +0.25). The three weighting coefficients may represent the nominal weighting of the first observed amplified analog residual value, the second observed amplified analog residual value, and the third observed amplified analog residual value. In another embodiment, the first weighting coefficient may be substantially equal to the second weighting coefficient (the absolute values ​​of the two weighting coefficients may be within ±5%, for example, [-0.48, +0.52]).

[0057] Figure 7A shows another exemplary embodiment of the ADC circuit 700 according to this teaching. The ADC circuit 700 may have a similar structure to the ADC circuit 300 in Figure 3. The ADC circuit 700 may comprise a sampling-quantization-residual generation (SQRG) circuit 710 (compared to SQRG circuits 310, 410, and 510 in Figures 3, 4, and 5, respectively), an auto-zeroing residual amplifier circuit 720 (compared to residual amplifier circuit 320 and amplifier circuit 420 in Figures 3 and 4, respectively), and a quantization circuit ADC2730 (compared to ADC2330 and ADC2430 in Figures 3 and 4, respectively).

[0058] The amplified analog residual value may be the differential charge amount provided via terminals 707p and 707m. The amplified analog residual value may be partially derived by combining observations of two (or more) amplified analog residual values ​​to provide an automatic zeroing operation. The ADC2730 can receive an analog value (e.g., differential charge amount) from the AZ residual amplifier circuit 720 and perform an A / D conversion operation to provide a digital value CODE2 that may represent the analog residual value VRES, which may be the voltage difference output by the SQRG circuit 710 at terminals 709p and 709m. Thus, the AZ residual amplifier circuit 720 may be configured to combine two (or more) observations as part of an automatic zeroing operation to output the differential charge amount (i.e., analog value) to the ADC circuit 730.

[0059] Figure 7B shows an exemplary timing diagram of the ADC circuit 700 of Figure 7A. The AZ residual amplifier circuit 720 may provide amplification by integrating an analog value, which can be derived from the residual value VRES received from the SQRG circuit 710, over a predetermined period TINT. The first observation may occur during phase 2 (labeled Φ2 in Figure 7B), and the transconductance circuit (GM circuit) 721 may receive the residual value VRES via switches 703p and 703m and provide a differential output current GM·(VRES+OS). As shown, OS may be a potentially non-zero offset of the circuit 721 configured to provide amplification, and GM may be the coefficient of transconductance (i.e., the voltage-current gain coefficient). The differential output current may be integrated over capacitors 743p and 743m over a predetermined period TINT to accumulate a differential charge Q2 = TINT·GM·(VRES+OS) on capacitors 743p and 743m. The differential charge Q2 may be the first observation of the amplified analog residual value.

[0060] A second observation may be made during phase 3 (labeled Φ3 in Figure 7B), during which the GM circuit 721 receives the residual value VRES via switches 705p and 705m and provides differential output current via switches 715p and 715m. The residual value VRES of the second observation received by the GM circuit 721 may have the opposite polarity to the residual value VRES of the first observation. In particular, the residual value VRES output by the SQRC circuit 710 may be a differential voltage. In phase 2, when switches 703p and 703m are closed, the positive component of the residual voltage of the first observation is provided to the first input of the GM circuit 721, and the negative component of the residual voltage of the first observation is provided to the second input of the GM circuit 721. In phase 2, when switches 705p and 705m are closed, the positive component of the residual voltage of the second observation is supplied to the second input of GM circuit 721, and the negative component of the residual voltage of the second observation is supplied to the first input of GM circuit 721, thereby having the opposite polarity to the residual voltage of the first observation supplied to GM circuit 721. Furthermore, the polarity of the output of GM circuit 721 may be opposite to that of the first and second observations. In particular, by closing switches 713p and 713m during phase 2, the first output of GM circuit 721 may be coupled to capacitor 743p, and the second output of GM circuit 721 may be coupled to capacitor 743m for the first observation. By closing switches 715p and 715m during phase 3, the first output of GM circuit 721 may be coupled to capacitor 745m, and the second output of GM circuit 721 may be coupled to capacitor 745p for the second observation. Since capacitors 743p and 745p are used to generate a positive component when the observations are combined (as will be further explained below), and capacitors 743m and 745m are used to generate a negative component when the observations are combined, the polarity of the GM circuit 721 can be opposite to the polarity of the first observation and the second observation combination.The differential output current can be integrated over capacitors 745p and 745m for a predetermined period TINT, accumulating a differential charge Q3 = TINT·GM·(VRES-OS) on capacitors 745p and 745m. This differential charge Q3 can be a second observation of the amplified analog residual value.

[0061] When switches 723p, 723m, 725p, 725m, 753p, 753m, 755p, and 755m are closed, two (or more) observations may be combined at the beginning of phase 4 (labeled Φ4 in Figures 7A and 7B). Charge sharing operation may occur between capacitors 743p and 745p, and between capacitors 743m and 745m, combining two (or more) observations (e.g., Q2 and Q3). The combined observations may be amplified analog residual values ​​represented by the charge quantity Q = Q2 + Q3 = 2·TINT·GM·VRES available through terminals 707p and 707m. Specifically, a zero voltage across terminals 707p and 707m may indicate that the differential charge Q = Q2 + Q3 may have been transported through terminals 707p and 707m during phase 4. ADC2730 may be a SAR-type ADC with a comparator circuit 761. The SAR state machine 763 may be configured to derive a digital value CODE2 where the voltage between terminals 707p and 707m is approximately zero (the degree of approximation may depend on the resolution of CODE2 in ADC2730).

[0062] The term "amplification" may not be limited to characterizing signal processing where the input and output values ​​are of the same nature (such as voltage-in-voltage-out or current-in-current-out). For example, the AZ residual amplifier circuit 720 could be a voltage-in-charge-out amplifier circuit where the amplification factor A may be expressed in units such as coulombs per volt. A relatively large amplification factor A may indicate that noise sources within the ADC 2730 may contribute relatively little to the overall noise level of the ADC circuit 700 when the noise sources are directed to the inputs (e.g., terminals 701p and 701m).

[0063] Switches 765p and 765m can apply a first predetermined bias voltage to terminals 707p and 707m, while the SAR state machine 763 can be configured with a predetermined reset code during phase 3 (i.e., the SAR state machine 763 can be in a predetermined reset state). A second predetermined bias voltage, which may optionally be the same as the first predetermined bias voltage, can be applied via switches 733p, 733m, 735p, and 735m. A third predetermined potential, which may optionally be the same as the first and / or second predetermined bias voltages, can be applied via switches 723p, 723m, 725p, and 725m. The first, second, and third predetermined bias voltages may not be labeled in Figure 7A.

[0064] The exemplary timing diagram in Figure 7B shows that switches 723p, 723m, 725p, 725m, 733p, 733m, 735p, and 735m may be closed before phase 2, thereby allowing capacitors 743p, 743m, 745p, and 745m to be reset to a predetermined voltage and charge (e.g., nominal zero differential voltage and zero differential charge). Furthermore, before phase 2, switches 703p, 703m, 713p, and 713m may be closed, allowing the differential current GM·(OS+VRES) to flow through switches 713p, 723p, 713m, and 723m. Phase 2 may begin when switches 723p and 723m are opened, and differential current flows through capacitors 743p and 743m, as well as switches 713p, 733p, 713m, and 733m. Phase 2 may end after a predetermined period TINT when switches 733p and 733m are opened, effectively sampling the differential charge Q2 = TINT·GM·(OS+VRES) on capacitors 743p and 743m. Switches 723p and 723m may be closed with a short delay (e.g., 200ps) after switches 733p and 733m are opened, for example, to provide a path for current to flow through the GM circuit 721. Switches 703p, 703m, 705p, 705m, 713p, 713m, 715p, and 715m can be switched substantially simultaneously in preparation for a second observation during phase 3. The control signals (Φ2x and Φ3x) that control switches 703p, 703m, 705p, 705m, 713p, 713m, 715p, and 715m may be temporally non-overlapping to avoid establishing a transient conductive path between terminals 709p and 709m, for example (compare with terminals 409p and 409m in Figure 4). The non-overlapping period may be short, such as 200ps.PHOSITA is proficient in the use of non-overlapping control signals and in implementing circuits for generating switch control signals, including non-overlapping switch control signals.

[0065] The illustrative timing diagram in Figure 7B shows that switches 725p, 725m, 735p, and 735m may be closed before phase 3, thereby allowing capacitors 745p and 745m to be reset to a predetermined voltage and charge (e.g., nominal zero differential voltage and zero differential charge). Furthermore, before phase 3, switches 705p, 705m, 715p, and 715m may be closed, allowing the differential current GM·(VRES-OS) to flow through switches 715p, 725p, 715m, and 725m. Phase 3 may begin when switches 725p and 725m are opened, allowing the differential current to flow through capacitors 745p and 745m, as well as through switches 715p, 735p, 715m, and 735m. Phase 3 may end after a predetermined period TINT, when switches 735p and 735m are open and the differential charge Q3 = TINT·GM·(VRES-OS) on capacitors 745p and 745m is effectively sampled. Switches 725p and 725m may be closed with a short delay (e.g., 200ps) after switches 735p and 735m are opened, for example, to provide a path for current to flow from the GM circuit 721. The residual voltage VRES may not be needed after phase 3 is completed, and the SQRG circuit 710 may be reset at the start of phase 4.

[0066] The SAR ADC730 may be configured to receive an amplified residual value Q=Q2+Q3 and, through successive approximate charge equilibrium operation provided during phase 4, provide a digital value CODE2 to represent the analog residual value VRES. A digital circuit (not shown) may be configured to receive and combine CODE1p, CODE1m, and CODE2 (and optionally calibration information as well) to derive and output a code DOUT to represent the analog input value VIN=Vp(T0)-Vm(T0). Methods for combining CODE1p, CODE1m, and CODE2 may include correction of capacitance ratio mismatches of the CDAC (e.g., digital correction) and / or any other known and / or useful techniques.

[0067] Figure 7C shows an exemplary ADC circuit 702 with a modified AZ residual amplifier circuit 722 compared to the AZ residual amplifier circuit 720 in Figure 7A. The SQRG circuit 710 and ADC2 circuit 730 may be identical in the ADC circuit 700 in Figure 7A and the ADC circuit 702 in Figure 7C. More generally, the same reference numbers may correspond to identical parts in Figures 7A and 7C. The timing diagram in Figure 7B may apply to either or both of the ADC circuits 700 and 702. The AZ residual amplifier circuit 722 may be an extension of the AZ residual amplifier circuit 720. Specifically, the AZ residual amplifier circuit 722 may have four additional capacitors (capacitors 741p, 741m, 747p, and 747m) added to the AZ residual amplifier circuit 720. Capacitors 741p and 741m may be configured to provide negative feedback to the GM circuit 721 when switches 703p, 703m, 713p, and 713m are closed (Φ2x=1). Capacitors 747p and 747m may be configured to provide negative feedback to the GM circuit 721 when switches 705p, 705m, 715p, and 715m are closed (Φ3x=1). The durations TINT of phases 2 and 3 (see Figure 7B) may be long enough to allow the GM circuit 721 to settle substantially to the asymptotic output voltage and the nominal zero input voltage (which PHOSITA would recognize as a "virtual short"). Various imperfections in the GM circuit 721 may result in a non-zero virtual short input voltage. Such imperfections may include a potentially non-zero offset OS.

[0068] The AZ residual amplifier circuit 722 may be configured to operate as a charge-in-charge-out AZ residual amplifier circuit. As the GM circuit 721 settles toward an asymptotic state in phase 2 and / or phase 3, charge may be transported through terminals 709p and 709m, as well as negative feedback capacitors 741p, 741m, 747p, and 747m. The output impedance of the SQRG circuit 710 may be capacitive (see Figure 4; the SQRG circuit 710 may be implemented as the SQRG circuit 410). The SQRG circuit 710 may provide an analog residual value that can be expressed as charge quantity QRES = VRES·C, where C may be the capacitance (e.g., output impedance) that characterizes the SQRG circuit 710. A zero voltage across terminals 709p and 709m may indicate that the charge quantity QRES, representing the analog residual value, has been transported through terminals 709p and 709m since the sampling instant (t=T0). The AZ residual amplifier circuit 722 amplifies QRES during phase 2, and the first observation of the amplified residual value can be stored as the charge Q2=A·(VRES+OS)·C=A·(QRES+OS·C) on capacitors 743p and 743m. The AZ amplifier circuit 722 further amplifies QRES during phase 3, and the second observation of the amplified residual value can be stored as the charge Q3=A·(VRES-OS)·C=A·(QRES-OS·C) on capacitors 745p and 745m. The two observations can be combined at the start of phase 4 by a charge-sharing operation Q=Q2+Q3=2A·QRES (as described for the AZ amplifier circuit 720).

[0069] In phase 2, switches 725p and 725m may be closed, and switches 723p and 723m may be opened. The GM circuit 721 then settles toward an asymptotic state by transporting charge (nominal QRES) through terminals 709p and 709m, and capacitors 741p and 741m, and can establish a virtual short voltage at its input (e.g., OS is nominally zero). The transported charge can be returned (transported and returned) through terminals 709p and 709m, and capacitors 741p and 741m, if switches 725p and 725m are closed immediately after phase 2 (see timing diagram in Figure 7B). Then, in phase 3, switches 725p and 725m may be opened, and switches 723p and 723m may be closed. Subsequently, the GM circuit 721 settles toward an asymptotic state by transporting charge (nominal QRES) through terminals 709p and 709m, and capacitors 747p and 747m, thereby establishing a virtual short voltage at its input.

[0070] The first amplification coefficient of the AZ amplifier circuit 722 during phase 2 may be substantially a function of the capacitance ratios of capacitor 743p and capacitor 743m, and capacitor 741p and capacitor 741m. The second amplification coefficient of the AZ amplifier circuit 722 during phase 3 may be substantially a function of the capacitance ratios of capacitor 745p and capacitor 745m, and capacitor 747p and capacitor 747m. The first and second amplification coefficients may be nominally identical. Capacitors 743p, 743m, 745p, and 745m may be nominally identical. Capacitors 741p, 741m, 747p, and 747m may be nominally identical.

[0071] For comparison, the amplification coefficient of the AZ amplifier circuit 720 (Figure 7A) may be a combination of period (TINT), transconductance (GM), and capacitance. In one comparison, the amplification coefficient of the AZ residual amplifier circuit 722 may be relatively less sensitive to manufacturing process variations than that of the AZ residual amplifier circuit 720. In another comparison, the AZ residual amplifier circuit 720 may be relatively less sensitive to noise from the GM circuit 721 than that of the AZ amplifier circuit 722. The preference of the AZ residual amplifier circuit 722 over the AZ residual amplifier circuit 720 (or vice versa) may depend on one or more design objectives. In another embodiment, the ADC circuit 702 in Figure 7C may be configured not to fully settle between phases 2 and 3. For example, a given period TINT shown in the timing diagram of Figure 7B may be relatively short compared to the period required for the AZ amplifier circuit 722 to substantially fully settle. For example, the AZ residual amplifier circuit 722 may be configured to settle to a predetermined percentage of the asymptotic value (e.g., 63 percent, 86 percent, 95 percent, 98 percent, or...).

[0072] The operation of the AZ amplifier 722 may not significantly depend on the linearity of capacitors 741p, 741m, 743p, 743m, 745p, 745m, 747p, and 747m (linear capacitors can provide a linear relationship between voltage and charge). In some embodiments, capacitors 741p, 741m, 743p, 743m, 745p, 745m, 747p, and 747m may be implemented using MOS (metal oxide semiconductor) semiconductor devices that are somewhat nonlinear, i.e., biased to provide capacitance that is relatively constant (e.g., within ±10%) over the voltage range used in operation. MOS capacitors may be relatively smaller and less expensive than MOM (metal oxide metal) capacitors, which may be relatively more linear. Any insulating barrier structure, such as many semiconductor devices, configured to store charge, may be used to implement capacitors 741p, 741m, 743p, 743m, 745p, 745m, 747p, and / or 747m. PHOSITA will recognize that MOS semiconductors do not need to be constructed with metal gate terminals, and that the general term / acronym "MOS" (metal oxide semiconductor) should not be interpreted as being limited to the materials used to manufacture semiconductor devices. The term "MOS semiconductor device" shall include a wide range of semiconductor devices having a nominally nonconductive barrier (which may, but does not need to be, made from oxides). Any capacitor or other circuit components described in this teaching may be at least slightly nonlinear. If the common-mode voltages at node 709p, terminal 709m, node 707p, and terminal 707m are made substantially equal (e.g., within ±50mV), then considerable capacitor nonlinearity can be almost canceled for the charge-in / charge-out operation of the AZ amplifier circuit 722.In other words, even if capacitors 741p, 741m, 743p, 743m, 745p, 745m, 747p, and 747m have relatively low linearity, the charge-in and charge-out operation of the AZ amplifier circuit 722 can be substantially linear. The common-mode voltage can be a function of the bias voltages applied through switches 733p, 733m, 735p, and 735m (Figure 7C) and the bias voltages applied through switches 405p and 405m (Figure 4) in the SQRG circuit 710, which can be implemented as the SQRG circuit 410 in Figure 4.

[0073] Figure 7D shows yet another exemplary embodiment of the ADC circuit 704, including a modified AZ residual amplifier circuit 724. Compared to the AZ residual amplifier circuit 722 in Figure 7C, the four capacitors in Figure 7C (capacitors 741p, 741m, 747p, and 747m) can be replaced by two capacitors (capacitors 771p and 771) and four switches (switches 773p, 773m, 775p, and 775m). An advantage of the AZ residual amplifier circuit 724 compared to the AZ residual amplifier circuit 722 may be reduced sensitivity to noise from the GM circuit 721.

[0074] The AZ circuit 724 in Figure 7D can be further modified (in part) by replacing the GM circuit 721 with a voltage-in / voltage-out circuit configured to provide amplification. An exemplary voltage-in / voltage-out amplifier circuit may be a two-stage amplifier circuit incorporating a known Miller-type frequency compensation. Other embodiments may incorporate other types of circuits configured to provide amplification.

[0075] Example implementation The following examples are provided as illustrative examples.

[0076] Embodiment 1 may include an analog-to-digital converter (ADC) circuit for receiving an analog input value and providing a digital output code for representing the analog input value, the ADC circuit comprising: a sampling-quantization-residual generation (SQRG) circuit configured to receive an analog input value and provide a first digital code at least partially derived from the analog input value, further configured to provide an analog residual value at least partially derived from the analog input value and the first code; an auto-zeroing residual amplification circuit configured to receive and amplify the analog residual value and provide first and second observations of the amplified analog residual value; a quantization circuit configured to derive a second code for representing a combination of at least first and second observations of the amplified analog residual value; and a digital circuit configured to combine at least the first and second codes to derive a digital output code.

[0077] Example 2 may include the ADC circuit of Example 1, wherein the first code is at least partially derived from a combination of an analog input value and a dither value.

[0078] Embodiment 3 may include the ADC circuit of Embodiment 1, wherein the automatic zeroing residual amplification circuit comprises an active circuit configured to provide amplification, the active circuit configured to receive an analog residual value in a first polarity and provide a first observation of an amplified analog residual value, and the active circuit further configured to receive an analog residual value in a second polarity opposite to the first polarity and provide a second observation of an amplified analog residual value.

[0079] Embodiment 4 may include the ADC circuit of Embodiment 1, wherein the automatic zeroing residual amplification circuit comprises an active circuit having a potentially non-zero offset that contributes to first and second observations of the amplified analog residual value, and the combination of first and second observations of the amplified analog residual value substantially cancels out the contribution of the offset to the second code.

[0080] Embodiment 5 may include the ADC circuit of Embodiment 1, wherein the auto-zeroing residual amplification circuit is further configured to provide a third observation of the amplified analog existence value, and the second code provided by the quantization circuit represents a weighted combination of the first, second, and third observations of the amplified residual value.

[0081] Example 6 may include the ADC circuit of Example 5, wherein the weighted combination places substantially more weight on at least one of the three observations of the amplified residual value.

[0082] Example 7 may include the ADC circuit of Example 1, wherein the second code provided by the quantization circuit is a weighted combination of first and second observations of the amplified residual value, and the absolute value of the first weighting coefficient for the first observation of the amplified residual value is substantially the same as the second weighting coefficient for the second observation of the amplified residual value.

[0083] Example 8 may include the ADC circuit of Example 1, wherein the quantization circuit derives a third code for representing a first observation of the amplified analog residual value, and further derives a fourth code for representing a second observation of the amplified analog residual value, the second code being at least partially derived by combining the third code and the fourth code.

[0084] Example 9 may include the ADC circuit of Example 1, wherein first and second observations of amplified analog residual values ​​are individually represented by first and second analog values ​​that are combined to provide a combined analog value.

[0085] Example 10 may include the ADC circuit of Example 9, in which the first and second analog values ​​are combined by charge sharing operation.

[0086] Example 11 may include the ADC circuit of Example 1, wherein the quantization circuit is a CDAC circuit configured to sample a first observation of amplified residual values ​​on a first segment of the CDAC circuit, and further configured to sample a second observation of amplified residual values ​​on a second segment of the CDAC circuit.

[0087] Example 12 may include the ADC circuit of Example 11, wherein the first and second segments of the CDAC circuit are used to perform digital-to-analog conversion of multiple codes in a successive approximation sequence of codes.

[0088] Example 13 may include the ADC circuit of Example 1, wherein the quantization circuit comprises a successive approximation register (SAR) state machine.

[0089] Example 14 may include the ADC circuit of Example 1, wherein the analog residual value is the amount of charge provided as an input to an auto-zeroing residual amplifier circuit.

[0090] Example 15 may include the ADC circuit of Example 14, wherein the quantization circuit is configured to receive charge quantities representing a combination of first and second observations of the amplified analog residual value.

[0091] Example 16 may include the ADC circuit of Example 15, wherein the semiconductor device is configured to store a charge quantity representing one of two observations of the amplified residual value.

[0092] Example 17 may include the ADC circuit of Example 1, wherein the resolution of the first code is at least 10 bits.

[0093] Example 18 may include the ADC circuit of Example 1, wherein the automatic zeroing residual amplification circuit is configured to provide amplification by substantially integrating an analog quantity derived from an analog residual value over a predetermined period.

[0094] Example 19 may include the ADC circuit of Example 1, wherein the automatic zeroing residual amplifier circuit is configured to provide amplification by settling to a predetermined percentage of the asymptotic value, where the predetermined percentage is at most 98 percent.

[0095] Example 20 may include the ADC circuit of Example 1, wherein the SQRG circuit is configured to partially derive the first code by deriving a residual with respect to a code having a resolution at least 3 bits lower than the resolution of the first code.

[0096] Embodiment 21 may include an analog-to-digital converter (ADC) circuit comprising: a sampling-quantization-residual generation (SQRG) circuit for generating a first digital code based at least partially on an analog input value received by the ADC circuit and generating an analog residual value based at least partially on the first digital code and the analog input value; an auto-zeroing residual amplification circuit for amplifying the analog residual value, generating a first observation of the amplified analog residual value and generating a second observation of the amplified analog residual value; a quantization circuit for generating a second digital code, wherein the second digital code represents a combination of at least the first observation and the second observation; and a digital circuit for generating a digital output code, wherein the digital output code represents an analog input value, and the first digital output code and the second digital code are combined to generate a digital output code.

[0097] Example 22 may include the ADC circuit of Example 21, wherein the automatic zeroing residual amplification circuit comprises an amplification circuit for providing amplification, the amplification circuit receiving the analog residual value in a first polarity to generate a first observation of the amplified analog residual value, and the amplification circuit receiving the analog residual value in a second polarity to generate a second observation of the amplified analog residual value, the second polarity being opposite to the first polarity.

[0098] Example 23 may include the ADC circuit of Example 22, wherein the automatic zeroing residual amplifier circuit includes a first switch that is closed during phase to swap the polarity of the analog residual value, and a second switch.

[0099] Example 24 may include the ADC circuit of Example 22, in which the polarity of the analog residual value is swapped before amplification to produce a second observation.

[0100] Example 25 may include the ADC circuit of Example 21, wherein the second digital code includes a weighted combination of the first observation and the second observation, and the absolute value of the first weighting coefficient for the first observation is substantially equal to the absolute value of the second weighting coefficient for the second observation.

[0101] Example 26 may include the ADC circuit of Example 21, wherein the quantization circuit combines a first observation and a second observation to generate at least a combination of the first and second observations, and the combination of the first and second observations substantially cancels out the offset.

[0102] Example 27 may include the ADC circuit of Example 26, wherein the automatic zeroing residual amplification circuit includes an active circuit, and the offset is caused by the active circuit and contributes to the first and second observations.

[0103] Example 28 may include the ADC circuit of Example 21, in which the first digital code is generated at least in part based on analog input values ​​and dither values.

[0104] Example 29 may include the ADC circuit of Example 21, wherein an automatic zeroing residual amplification circuit further generates a third observation of the amplified analog residual value, and the combination of at least the first observation and the second observation includes a weighted combination of the first observation, the second observation and the third observation.

[0105] Example 30 may include the ADC circuit of Example 21, in which a first observation is represented by a first analog value, a second observation is represented by a second analog value, the first analog value and the second analog value are combined to generate a combined analog value, and the combined analog value is used to generate a second digital code.

[0106] Example 31 may include the ADC circuit of Example 30 in which charge sharing operation is used to comb a first analog value and a second analog value.

[0107] Example 32 may include the ADC circuit of Example 21, in which the analog residual value is transmitted as a charge quantity as an input to an auto-zeroing residual amplifier circuit.

[0108] Example 33 may include the ADC circuit of Example 32, wherein the above charge quantity is the first charge quantity, and the quantization circuit receives a second charge quantity that represents a combination of at least the first observation and the second observation.

[0109] Example 34 may include the ADC circuit of Example 33, wherein a semiconductor device is used for storing a second amount of charge.

[0110] Example 35 may include the ADC circuit of Example 24, in which the polarity of the amplified analog residual value is swapped after amplification to produce a second observation.

[0111] Embodiment 36 may include an automatic zeroing residual amplification circuit for canceling an offset, comprising: an amplification circuit for amplifying a first observation of an analog residual value and a second observation of an analog residual value received by the automatic zeroing residual amplification circuit, wherein the analog residual value is the residual of a digital code generated from the analog-to-digital conversion of an analog input value, and the amplified first observation and the amplified second observation are used together with the digital code to generate a digital output code representing an analog input value; and one or more switches coupled between the amplification circuit and the input of the automatic zeroing residual amplification circuit, which selectively apply the first observation and the second observation to the amplification circuit.

[0112] Example 37 may include the auto-zeroing residual amplifier circuit of Example 36, wherein a second group of one or more switches applies a first observation to the second and third capacitors during a first phase, and a second group of one or more switches applies a second observation to the first and fourth capacitors during a second phase.

[0113] Embodiment 38 may include the automatic zeroing residual amplifier circuit of Embodiment 37, wherein one or more switches comprise a first group of one or more switches, the automatic zeroing residual amplifier circuit further comprises a first capacitor and a second capacitor for storing and combining a first charge, a third capacitor and a fourth capacitor for storing and combining a second charge, an amplifier circuit, and a second group of one or more switches coupled between the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor, the second group of one or more switches selectively apply a first observation and a second observation to the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor, the first observation and the second observation forming a first charge on the first capacitor and the second capacitor, and a second charge on the third capacitor and the fourth capacitor.

[0114] Example 39 may include the auto-zeroing residual amplifier circuit of Example 38, wherein a second group of one or more switches applies a first observation to the second and third capacitors with a first output polarity during a first phase, and a second group of one or more switches applies a second observation to the first and fourth capacitors with a second output polarity during a second phase, the second output polarity being opposite to the first output polarity.

[0115] Embodiment 40 may include the auto-zeroing residual amplifier circuit of Embodiment 38, further comprising a third group of one or more switches coupled between the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor and the output of the auto-zeroing residual amplifier circuit, wherein the third group of one or more switches combines the first charge of the first capacitor and the second capacitor during the third phase, and the third group of one or more switches combines the second charge of the third capacitor and the fourth capacitor during the third phase, and the third phase is separated from the first and second phases.

[0116] Example 41 may include the auto-zeroing residual amplifier circuit of Example 36, further comprising one or more capacitors coupled between the input and output of the amplifier circuit, wherein one or more capacitors provide feedback to the auto-zeroing residual amplifier circuit.

[0117] The above outlines the features of one or more embodiments of the subject matter disclosed herein. These embodiments are provided to enable a person skilled in the art (PHOSITA) to better understand various aspects of this disclosure. Certain well-understood terms, as well as underlying technologies and / or standards, may be referenced without further explanation. It is expected that a PHOSITA possesses, or has access to, sufficient background knowledge or information of these technologies and standards to put the teachings of this disclosure into practice.

[0118] PHOSITA will understand that the present disclosure may readily be used as a basis for designing or modifying other processes, structures, or variations to perform the same purposes as the embodiments described herein and / or to achieve the same advantages. PHOSITA will also recognize that such equivalent structures will not deviate from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without deviating from the spirit and scope of the present disclosure.

[0119] Referencing the figures, the activities described above can be applied to any integrated circuit, particularly specialized software programs or algorithms, that are involved in signal processing (e.g., gesture signal processing, video signal processing, audio signal processing, analog-to-digital conversion, digital-to-analog conversion), some of which may be associated with the processing of digitized real-time data. Specific embodiments may relate to multi-DSP, multi-ASIC, or multi-SoC signal processing, floating-point processing, signal / control processing, fixed-function processing, microcontroller applications, etc. In a particular context, the features considered herein may be applicable to medical systems, scientific instruments, wireless and wired communications, radar, industrial process control, audio and video equipment, current sensing, (potentially high-precision) measurement, and other digital processing-based systems. Furthermore, the specific embodiments described above may be provided for digital signal processing technologies for medical imaging, patient monitoring, medical devices, and home healthcare. This may include, for example, lung monitors, accelerometers, heart rate monitors, or pacemakers, and their peripheral devices. Other applications may include automotive technologies for safety systems (e.g., stability control systems, driver assistance systems, braking systems, infotainment, and all kinds of interior applications). Furthermore, powertrain systems (e.g., hybrid and electric vehicles) may utilize high-precision data conversion, rendering, and display products in areas such as battery monitoring, control systems, reporting control, and maintenance work. In yet another exemplary scenario, the teachings of this disclosure may be applicable in industrial markets, including process control systems that help drive productivity, energy efficiency, and reliability. In consumer applications, the teachings of the signal processing circuits described above may be used in image processing, autofocus, and image stabilization (e.g., digital still cameras, camcorders, etc.). Other consumer applications may include audio and video processors for home theater systems, DVD recorders, and high-definition televisions.Other consumer applications could include advanced touchscreen controllers (for example, for any type of portable media device). Thus, such technology could easily be incorporated into smartphones, tablets, security systems, PCs, gaming technologies, virtual reality, and simulation training.

[0120] The above outlines some features of embodiments so that those skilled in the art may better understand aspects of the disclosure. Those skilled in the art should understand that the disclosure may readily be used as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures will not deviate from the spirit and scope of the disclosure, and that various changes, substitutions, and modifications may be made herein without deviating from the spirit and scope of the disclosure.

[0121] Certain embodiments of this disclosure may readily include a system-on-a-chip (SoC) central processing unit (CPU) package. An SoC represents an integrated circuit (IC) that integrates components of a computer or other electronic system onto a single chip. An SoC may include digital functions, analog functions, mixed-signal functions, and radio frequency functions, all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM) having multiple chips located within a single electronic package and configured to interact closely with each other through the electronic package. Any module, function, or block element of an ASIC or SoC may, if necessary, be provided within a reusable “black box” intellectual property (IP) block, which may be distributed without disclosing the logic details of the IP block. In various other embodiments, digital signal processing functions may be implemented within one or more silicon cores in an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), and other semiconductor chips.

[0122] In some cases, the teachings of this disclosure may be encoded in one or more tangible, non-transient, computer-readable media containing executable instructions that, when executed, instruct a programmable device (such as a processor or DSP) to perform the methods or functions disclosed herein. If the teachings of this disclosure are embodied, at least in part, within a hardware device (such as an ASIC, IP block, or SoC), the non-transient media may include a hardware device hardware-programmed with logic for performing the methods or functions disclosed herein. The teachings may also be practiced in the form of register transfer level (RTL) or other hardware description languages ​​such as VHDL or Verilog, which may be used to program manufacturing processes for producing the disclosed hardware elements.

[0123] In exemplary implementations, at least some of the processing activities outlined herein may also be implemented in software. In some embodiments, one or more of these features may be implemented in hardware provided outside of the elements of the disclosed figures, or may be integrated in any suitable way to achieve the intended functionality. Various components may include software (or reciprocating software) that can work together to achieve the behavior outlined herein. In yet other embodiments, these elements may include any preferred algorithms, hardware, software, components, modules, interfaces, or objects that facilitate their operation.

[0124] In addition, some of the components associated with the described microprocessors may be excluded or integrated in a different way. Generally, while the arrangements shown in the diagrams may be more logical in their representation, the physical architecture may include various permutations, combinations, and / or hybrids of these elements. It should be noted that the operational objectives outlined herein can be achieved using countless possible design configurations. Thus, the associated infrastructure has countless alternative arrangements, design choices, device possibilities, hardware configurations, software implementations, equipment options, and so on.

[0125] Any suitably configured processor component may execute any type of instruction associated with data to achieve the operations detailed herein. Any processor disclosed herein may transform elements or articles (e.g., data) from one state or thing to another. In other embodiments, some activities outlined herein may be performed by fixed logic or programmable logic (e.g., software and / or computer instructions executed by the processor), and elements identified herein may be a certain type of programmable processor, programmable digital logic (e.g., FPGA, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), digital logic, software, code, ASIC including electronic instructions, flash memory, optical disc, CD-ROM, DVD-ROM, magnetic card or optical card, other types of machine-readable media suitable for storing electronic instructions, or any suitable combination thereof. During operation, the processor may use any suitable type of non-temporary storage medium (e.g., random access memory (RAM), read / write Information may be stored in dedicated memory (ROM), FPGA, EPROM, electrically erasable programmable ROM (EEPROM), software, hardware, or, as needed and based on specific needs, in any other suitable component, device, element, or object. Furthermore, information tracked, transmitted, received, or stored in a processor may be provided in any database, register, table, cache, queue, control list, or storage structure based on specific needs and implementation, all of which may be referenced in any suitable time frame. Any memory article considered herein should be interpreted as encompassing the broad term “memory.” Similarly, any potential processing elements, modules, and machines described herein should be interpreted as encompassing the broad term “microprocessor” or “processor.”Furthermore, in various embodiments, the processors, memory, network cards, buses, storage devices, associated peripherals, and other hardware elements described herein may be realized by processors, memory, and other associated devices configured with software or firmware for emulating or virtualizing the functions of these hardware elements.

[0126] Computer program logic that implements all or part of the functions described herein may be embodied in various forms, including, but not limited to, source code, computer executable, hardware description, and various intermediate forms (e.g., mask work, or forms generated by an assembler, compiler, linker, or locator). In one embodiment, source code includes a set of computer program instructions implemented in various programming languages, such as object code, assembly language, or high-level languages ​​such as OpenCL, RTL, Verilog, VHDL, Fortran, C, C++, JAVA®, or HTML, for use in various operating systems or operating environments. Source code may define and use various data structures and communication messages. Source code may be computer executable (e.g., via an interpreter), or source code may be converted to computer executable (e.g., via a translator, assembler, or compiler).

[0127] In the consideration of the embodiments described above, capacitors, buffers, graphic elements, interconnect boards, clocks, DDRs, camera sensors, converters, inductors, resistors, amplifiers, switches, digital cores, transistors, and / or other components can be readily replaced, substituted, or otherwise modified to meet specific circuit needs. Furthermore, it should be noted that the use of complementary electronic devices, hardware, non-transient software, etc., also provides equally feasible options for carrying out the teachings of this disclosure.

[0128] In one exemplary embodiment, any number of electrical circuits in the figure may be mounted on a substrate of the associated electronic device. The substrate may be a general circuit board that can hold various components of the internal electronic system of the electronic device and further provide connectors for other peripherals. More specifically, the substrate may provide electrical connections that allow other components of the system to communicate electrically. Any suitable processor (including digital signal processors, microprocessors, supporting chipsets, etc.), memory elements, etc., may be appropriately coupled to the substrate based on specific configuration needs, processing requirements, computer design, etc. Other components such as external storage devices, additional sensors, audio / video display controllers, and peripherals may be attached to the substrate via cables as plug-in cards, or may be integrated into the substrate itself. In another exemplary embodiment, the electrical circuits in the figure may be implemented as standalone modules (e.g., devices having associated components and circuits configured to perform a specific application or function) or as plug-in modules within the application-specific hardware of the electronic device.

[0129] It should be noted that in the numerous embodiments provided herein, interactions may be described with respect to two, three, four, or more electrical components. However, this is done for clarification and illustrative purposes only. It should be understood that the system may be integrated in any suitable way. In line with similar design alternatives, any of the components, modules, and elements illustrated in the figures may be combined in a variety of possible configurations, all of which are obviously within the broad scope of this disclosure. In some cases, one or more functions of a given set of flows can be more easily described by referring to only a limited number of electrical elements. It should be understood that the electrical circuits and their teachings in the figures are readily extensible and can be adapted to a large number of components, as well as more complex / sophisticated arrangements and configurations. Thus, the embodiments provided do not limit or hinder the broad teachings of electrical circuits applicable to potentially countless other architectures.

[0130] A number of other changes, substitutions, variations, alterations, and modifications will be apparent to those skilled in the art, and this disclosure is intended to encompass all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the attached claims. In interpreting the claims attached herein, the Applicant states that (a) none of the attached claims are intended to apply 35 U.S. SC § 112(f) as of the filing date of this application unless the terms “means for” or “steps for” are specifically used in a particular claim, and (b) nothing in this disclosure is intended to limit this disclosure in a manner not otherwise reflected in the attached claims.

Claims

1. An analog-to-digital converter (ADC) circuit, A sampling-quantization-residual generation (SQRG) circuit, A first digital code is generated based at least partially on the analog input value received by the ADC circuit. A sampling-quantization-residual generation (SQRG) circuit for generating an analog residual value based at least partially on the first digital code and the analog input value, The analog residual value is amplified, To generate a first observation of the amplified analog residual value, An automatic zeroing residual amplification circuit for generating a second observation of the amplified analog residual value, wherein the automatic zeroing residual amplification circuit comprises an amplification circuit for providing amplification, wherein the amplification circuit receives the analog residual value in a first polarity to generate the first observation of the amplified analog residual value, and the amplification circuit receives the analog residual value in a second polarity to generate the second observation of the amplified analog residual value, wherein the second polarity is opposite to the first polarity, and the automatic zeroing residual amplification circuit includes a first switch and a second switch that are closed in phase to swap the polarity of the analog residual value, A quantization circuit for generating a second digital code, wherein the quantization circuit combines the first observation and the second observation to generate at least a combination of the first observation and the second observation, the second digital code represents at least the combination of the first observation and the second observation, and the combination of the first observation and the second observation substantially cancels the offset, An analog-to-digital converter (ADC) circuit comprising: a digital circuit for generating a digital output code, wherein the digital output code represents an analog input value, and the first digital code and the second digital code are combined to generate the digital output code.

2. The ADC circuit according to claim 1, wherein the polarity of the analog residual value is swapped before amplification to generate the second observation.

3. The ADC circuit according to claim 1, wherein the second digital code includes a weighted combination of the first observation and the second observation, and the absolute value of the first weighting coefficient for the first observation is substantially equal to the absolute value of the second weighting coefficient for the second observation.

4. The ADC circuit according to claim 1, wherein the automatic zeroing residual amplification circuit includes an active circuit, the offset is caused by the active circuit, and the offset contributes to the first and second observations.

5. The ADC circuit according to claim 1, wherein the first digital code is generated at least in part based on the analog input value and the dither value.

6. The ADC circuit according to claim 1, wherein the automatic zeroing residual amplification circuit further generates a third observation of the amplified analog residual value, and the combination of at least the first observation and the second observation includes a weighted combination of the first observation, the second observation and the third observation.

7. The ADC circuit according to claim 1, wherein the first observation is represented by a first analog value, the second observation is represented by a second analog value, the first analog value and the second analog value are combined to generate a combined analog value, and the combined analog value is used to generate a second digital code.

8. The ADC circuit according to claim 7, wherein a charge sharing operation is used to comb the first analog value and the second analog value.

9. The ADC circuit according to claim 1, wherein the analog residual value includes an amount of charge as an input to the automatic zeroing residual amplification circuit.

10. The ADC circuit according to claim 9, wherein the charge quantity is a first charge quantity, and the quantization circuit receives a second charge quantity that represents the combination of at least the first observation and the second observation.

11. The ADC circuit according to claim 10, wherein a semiconductor device is used for storing the second amount of charge.

12. The ADC circuit according to claim 6, wherein the weighted combination places substantially more weight on at least one of the first observation, second observation, and third observation of the amplified analog residual value.

13. The ADC circuit according to claim 1, wherein the quantization circuit derives a third digital code for representing the first observation of the amplified analog residual value, and further derives a fourth digital code for representing the second observation of the amplified analog residual value, the second digital code being at least partially derived by combining the third digital code and the fourth digital code.

14. The quantization circuit comprises a capacitive digital-to-analog converter having a first segment and a second segment, The first segment samples the first observation, The second segment samples the second observation. The ADC circuit according to claim 1.

15. The ADC circuit according to claim 14, wherein the first segment and the second segment are switched to apply a successive approximation sequence of codes from a digital state machine.

16. The ADC circuit according to claim 1, wherein the quantization circuit comprises a successive approximation register state machine.

17. The ADC circuit according to claim 1, wherein the resolution of the first digital code is at least 10 bits.

18. The ADC circuit according to claim 1, wherein the automatic zeroing residual amplification circuit amplifies the analog residual value by integrating an analog quantity derived from the analog residual value over a predetermined period of time.

19. The ADC circuit according to claim 1, wherein the automatic zeroing residual amplification circuit amplifies the analog residual value by setting it to a predetermined ratio of the asymptotic value.

20. The ADC circuit according to claim 19, wherein the predetermined percentage is at most 98 percent.

21. The ADC circuit according to claim 2, wherein the polarity of the analog residual value is swapped after amplification to generate the second observation.

22. A method for canceling an offset, wherein the method is A step of amplifying an analog residual value, wherein the analog residual value is based on an analog input value and a first digital code generated from the analog input value. The steps include generating a first observation of the amplified analog residual value, The steps include generating a second observation of the amplified analog residual value, A step of generating a second digital code, wherein the second digital code represents at least a combination of the first observation and the second observation. Includes, The step of generating the first observation includes the step of receiving the analog residual value with a first polarity, The step of generating the second observation includes receiving the analog residual value with a second polarity, wherein the second polarity is opposite to the first polarity. The step of closing the first switch and the second switch during the phase to swap the polarity of the analog residual value. It further includes, A method wherein the step of generating the combination of at least the first and second observations includes the step of combining the first and second observations to substantially cancel out the offset.

23. The steps include generating the first digital code based on the analog input value, The steps include generating an analog representation of the first digital code, A step of generating the amplified analog residual value based on the analog input value and the analog representation of the first digital code. The method according to claim 22, further comprising:

24. A step of generating a digital output code, wherein the digital output code represents an analog input value, and the first digital code and the second digital code are combined to generate the digital output code. The method according to claim 22, further comprising:

25. The step of swapping the polarity of the analog residual value before the amplification. The method according to claim 22, further comprising:

26. The step of swapping the polarity of the analog residual value after the amplification. The method according to claim 22, further comprising:

27. The method according to claim 23, wherein the step of generating the first digital code further includes the step of generating the first digital code based on a dither value.

28. The process further includes the step of generating a third observation of the amplified analog residual value, The step of generating the combination includes the step of generating a weighted combination of the first observation, the second observation, and the third observation. The method according to claim 22.

29. The step of generating the second digital code is A step of generating a combined analog value by combining a first analog value representing the first observation and a second analog value representing the second observation, wherein the combined analog value is used to generate the second digital code. The method according to claim 22, including the method described in claim 22.

30. The method according to claim 29, wherein the step of combining the first analog value and the second analog value includes a charge sharing operation.

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