Semiconductor package and method for manufacturing the same
The semiconductor package addresses the complexity and cost issues of flash memory packaging by using a substrate with integrated dies and conductive pillars, resulting in reduced manufacturing costs and improved yield.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- ORIENT SEMICONDUCTOR ELECTRONICS LTD
- Filing Date
- 2025-02-07
- Publication Date
- 2026-07-07
AI Technical Summary
Current flash memory packaging methods are difficult to operate and require the use of three-dimensional steel plates, leading to high manufacturing costs and low yield.
A semiconductor package design that includes a substrate with memory and control dies, conductive pillars, a redistribution layer, and a processing die, connected via conductive blocks and solder balls, allowing for efficient electrical connections and reduced manufacturing complexity.
The design achieves lower manufacturing costs and higher yield by simplifying the packaging process and improving electrical connectivity.
Smart Images
Figure 0007886445000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor package and a method for manufacturing the same, and particularly to a flash memory package and a method for manufacturing the same.
Background Art
[0002] Currently, the memory and control dies of a flash memory card are packaged in one package body and then mounted on a package of a system single chip.
[0003] However, such a design uses surface adhesion technology, which is not only difficult to operate, but also requires the use of a three-dimensional steel plate.
Summary of the Invention
Problems to be Solved by the Invention
[0004] In view of this, the present invention provides a semiconductor package and a method for manufacturing the same that solve the above problems.
Means for Solving the Problems
[0005] To achieve the above object, the semiconductor package of the present invention includes a substrate having opposite first and second surfaces, a memory die installed on the first surface of the substrate and electrically connected to the substrate, a control die installed on the first surface of the substrate, a sealing body formed on the first surface of the substrate to cover the control die and the memory die, a plurality of conductive pillars installed on the first surface of the substrate and electrically connected to the substrate, a redistribution layer formed on the sealing body and electrically connected to the control die and the plurality of conductive pillars, and a processing die installed on the second surface of the substrate and electrically connected to the substrate.
[0006] The present invention provides a method for manufacturing a semiconductor package, comprising the steps of: preparing a substrate having opposing first and second surfaces; placing a memory die on the first surface of the substrate and electrically connecting the memory die to the substrate; forming a plurality of first conductive blocks on the control die; placing the control die on the first surface of the substrate; placing a plurality of conductive pillars on the first surface of the substrate and electrically connecting the plurality of conductive pillars to the substrate; forming a encapsulant on the first surface of the substrate and covering the control die, the memory die, and the plurality of first conductive blocks; polishing the encapsulant to expose the plurality of first conductive blocks and the plurality of conductive pillars; forming a redistribution layer on the encapsulant and electrically connecting the redistribution layer to the plurality of first conductive blocks and the plurality of conductive pillars; and placing a processing die on the second surface of the substrate and electrically connecting the processing die to the substrate. [Effects of the Invention]
[0007] According to the semiconductor package of the present invention, the manufacturing cost is relatively low and the yield is also relatively high. [Brief explanation of the drawing]
[0008] [Figure 1] This is an explanatory diagram of the semiconductor package of the present invention. [Figure 2] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 3] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 4] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 5] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 6] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 7] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 8] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 9] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Figure 10] Figure 1 is an explanatory diagram of the semiconductor package manufacturing method. [Modes for carrying out the invention]
[0009] To further clarify the above and other objectives, features, and advantages of the present invention, embodiments of the present invention will be described in detail below, accompanied by the drawings.
[0010] The aspects of this disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various components are not drawn to a constant scale. In fact, for the sake of clarity in the description, the dimensions of various components may be arbitrarily enlarged or reduced.
[0011] The following disclosure provides many different embodiments or examples for carrying out different features of this disclosure. For the sake of brevity of this disclosure, specific examples of members and configurations are described below. Naturally, these members and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming a first member above or on top of a second member may include embodiments in which the first member and the second member are formed in direct contact, and may also include embodiments in which an additional member is formed between the first member and the first member so that the first member and the second member are not in direct contact. Also, in various examples of this disclosure, reference numbers and / or letters may be repeated. This repetition is for simplification and clarity and does not in itself indicate relationships between the various embodiments and / or configurations being discussed.
[0012] Furthermore, for the sake of clarity, the text may use spatially relative terms such as "below," "downward," "bottom," "above," and "top" to describe the relationship between one member or component shown in the diagram and one or more other members or components. Beyond the orientations shown in the diagrams, spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (90-degree rotation or other orientations), and the spatially relative descriptions used in the text shall be interpreted accordingly.
[0013] Referring to Figure 1, the semiconductor package of the present invention includes a substrate 110 having opposing first surfaces 111 and second surfaces 112, the first surface 111 and the second surface 112 being located in different planes. Conductive wires 113 and 114 are formed on the first surface 111 and the second surface 112 of the substrate 110, respectively, and the conductive wires 113 and 114 are electrically connected by a plurality of conductive plated through-holes 115 that penetrate the first surface 111 and the second surface 112 of the substrate 110.
[0014] In one embodiment, the substrate 110 may be a single-layer or multi-layer circuit board, a redistribution layer (RDL) substrate, or a glass substrate.
[0015] One or more memory dies 130 are provided on the first surface 111 of the substrate 110. For example, multiple memory dies 130 are provided, and each of the multiple memory dies 130 has an active surface and a back surface opposite to the active surface. The multiple memory dies 130 can be stacked vertically or in a stepped manner on the substrate 110 and are bonded to the substrate 110 with an adhesive or epoxy resin. When the multiple memory dies 130 are stacked in a stepped manner on the substrate 110, they can be electrically connected to the multiple conductive wires 113 on the first surface 111 of the substrate 110 via a plurality of solder wires 132.
[0016] On the first surface 111 of the substrate 110, a control die 120 having an active surface and a back surface opposite to the active surface is further installed. The back surface of the control die 120 is adhered to the first surface 111 of the substrate 110 by an adhesive or an epoxy resin.
[0017] On the active surface of the control die 20, a plurality of first conductive blocks 121 electrically connected to the control die 120 are provided. The plurality of first conductive blocks 121 may be metal bumps formed on the control die 120 using a bumping process. The plurality of first conductive blocks 121 can be composed of a eutectic alloy, a lead - free material, a high - lead material or copper pillars.
[0018] On the first surface 111 of the substrate 110, a passive member 160 can be installed as needed.
[0019] On the first surface 111 of the substrate 110, a sealing body 150 covering the control die 120, the plurality of memory dies 130, the plurality of passive members 160 and the plurality of solder wires 132 is formed. The sealing body 150 does not completely cover the plurality of first conductive blocks 121, and each of the plurality of first conductive blocks 121 is partially exposed from the sealing body 150.
[0020] The sealing body 150 has a first surface 151, a second surface 152 and a plurality of third surfaces 153. The first surface 151 and the second surface 152 are located in different planes, and the plurality of third surfaces 153 are connected to the first surface 151 and the second surface 152. The second surface 152 of the sealing body 150 contacts the first surface 151 of the substrate 110.
[0021] A plurality of conductive pillars 140 are further provided on the first surface 111 of the substrate 110, and the plurality of conductive pillars 140 are installed so as to surround the sealant 150 and in contact with the plurality of third surfaces 153 of the sealant 150. Each of the plurality of conductive pillars 140 has an opposing first surface 141 and a second surface 142, and the first surface 141 and the second surface 142 are located in different planes. The plurality of conductive pillars 140 are fixed upright on the substrate 110 and are electrically connected to the plurality of conductive wires 113 on the first surface 111. The plurality of second surfaces 142 of the plurality of conductive pillars 140 are in contact with the first surface 111 of the substrate 110. The plurality of first surfaces 141 of the plurality of conductive pillars 140 are not covered by the sealant 150.
[0022] A redistribution layer 170 is formed on the first surface 151 of the encapsulant 150, and conductive wires are laid inside it. The redistribution layer 170 contacts and electrically connects with the plurality of first conductive blocks 121 and the plurality of first surfaces 141 of the plurality of conductive pillars 140. The control die 120 and the plurality of first conductive blocks 121 are electrically connected to the redistribution layer 170.
[0023] A processor die 180 having an active surface and a back surface opposite the active surface is installed on the second surface 112 of the substrate 110. A plurality of second conductive blocks 182 are provided on the active surface of the processor die 180, which are electrically connected to the processor die 180. The plurality of second conductive blocks 182 are sandwiched between the processor die 180 and the substrate 110. The processor die 180 is electrically connected to the plurality of conductive pillars 140 via the plurality of second conductive blocks 182 and the plurality of conductive wires 113, 114 on the first surface 111 and the second surface 112 of the substrate 110.
[0024] Multiple solder balls 190 are provided on the redistribution layer 170. The multiple memory dies 130 can be electrically connected to the multiple solder balls 190 via the multiple solder wires 132, the substrate 110, the multiple conductive pillars 140, and the redistribution layer 170. The processing die 180 can be electrically connected to the multiple solder balls 190 via the second conductive block 182, the substrate 110, the multiple conductive pillars 140, and the redistribution layer 170. The control die 120 can be electrically connected to the solder balls 190 via the multiple first conductive blocks 121 and the redistribution layer 170. In this manner, the multiple memory dies 130, the control die 120, and the processing die 180 can be electrically connected to an external circuit by the solder balls 190.
[0025] Figures 2 to 10 show a method for manufacturing the semiconductor package shown in Figure 1. As shown in Figure 2, a substrate 110 having a first surface 111 and a second surface 112 is prepared, and the first surface 111 and the second surface 112 are located on different planes. Conductive wires 113 and 114 are formed on the first surface and the second surface 112 of the substrate 110, respectively, and the plurality of conductive wires 113 and 114 are electrically connected by a plurality of conductive plated through-holes 115 that penetrate the first surface 111 and the second surface 112 of the substrate 110.
[0026] In one embodiment, the substrate 110 may be a single-layer or multi-layer circuit board, a redistribution layer (RDL) substrate, or a glass substrate.
[0027] A plurality of conductive pillars 140 are installed on the first surface 111 of the substrate 110. Each of the plurality of conductive pillars 140 has an opposing first surface 141 and a second surface 142, and the first surface 141 and the second surface 142 are located in different planes. The plurality of conductive pillars 140 are fixed upright on the substrate 110 and are electrically connected to the plurality of conductive wires 113 on the first surface 111. The plurality of second surfaces 142 of the plurality of conductive pillars 140 are in contact with the first surface 111 of the substrate 110.
[0028] A passive member 160 can be installed on the first surface 111 of the substrate 110 as needed.
[0029] As shown in Figure 3, a control die 120 is then prepared, which has an active surface and a back surface opposite to the active surface. A plurality of first conductive blocks 121 are formed on the active surface of the control die 120, which are electrically connected to the control die 120. The plurality of first conductive blocks 121 are metal bumps formed on the control die 120 using a bumping process. The first conductive blocks 121 can be made of a eutectic alloy, lead-free material, high-lead material, or copper pillars.
[0030] As shown in Figure 4, the back surface of the control die 120 is then bonded to the first surface 111 of the substrate 110 using an adhesive or epoxy resin.
[0031] As shown in Figure 5, one or more memory dies 130, for example, multiple memory dies 130, are then stacked in a stepped manner on the first surface 111 of the substrate 110 and bonded to the substrate with an adhesive or epoxy resin. Each of the multiple memory dies 130 has an active surface and a back surface opposite to the active surface. The multiple memory dies 130 are electrically connected to the multiple conductive wires 113 on the first surface 111 of the substrate 110 via a plurality of solder wires 132.
[0032] As shown in Figure 6, a sealant 150 is formed on the first surface 111 of the substrate 110, covering the control die 120, the plurality of memory dies 130, the plurality of passive members 160, the plurality of first conductive blocks 121, and the plurality of solder wires 132.
[0033] As shown in Figure 7, a portion of the sealing body 150 is then removed by polishing, thereby exposing the first surfaces 141 of the plurality of first conductive blocks 121 and the plurality of conductive pillars 140.
[0034] After the sealing body 150 is partially removed, it has a first surface 151, a second surface 152, and a plurality of third surfaces 153. The first surface 151 and the second surface 152 are located in different planes, and the plurality of third surfaces 153 are connected to the first surface 151 and the second surface 152.
[0035] The second surface 152 of the sealant 150 is in contact with the first surface 111 of the substrate 110, and the plurality of conductive pillars 140 surround the sealant 150 and are in contact with the plurality of third surfaces 153 of the sealant 150.
[0036] Subsequently, as shown in Figure 8, a rewiring layer 170 is formed on the first surface 151 of the encapsulant 150, and conductive wires are laid inside. The rewiring layer 170 is electrically connected to the plurality of first conductive blocks 121 and the plurality of first surfaces 141 of the plurality of conductive pillars 140 by contact. The control die 120 is electrically connected to the rewiring layer 170 via the plurality of first conductive blocks 121.
[0037] Subsequently, as shown in Figure 9, a plurality of solder balls 190 that are electrically connected to the redistribution layer 170 are formed on the redistribution layer 170.
[0038] Subsequently, as shown in Figure 10, a processing die 180 having an active surface and a back surface opposite the active surface is prepared. A plurality of second conductive blocks 182 electrically connected to the processing die 180 are formed on the active surface of the processing die 180.
[0039] Next, the package shown in Figure 9 is turned inside out, and the processing die 180 is attached to the second surface 112 of the substrate 110 using flip-chip technology, and the plurality of second conductive blocks 182 are sandwiched between the processing die 180 and the substrate 110. The processing die 180 is electrically connected to the conductive pillar 140 via the plurality of second conductive blocks 182 and the plurality of conductive wires 113 and 114 on the first surface 111 and the second surface 112 of the substrate 110.
[0040] In the semiconductor package of the present invention, the plurality of memory dies 130 are electrically connected to the plurality of solder balls 190 via the plurality of solder wires 132, the substrate 110, the plurality of conductive pillars 140, and the redistribution layer 170. The processing die 180 is electrically connected to the solder balls 190 via the second conductive block 182, the substrate 110, the plurality of conductive pillars 140, and the redistribution layer 170. The control die 120 is electrically connected to the solder balls 190 via the first conductive block 121 and the redistribution layer 170. In this manner, the plurality of memory dies 130, the control die 120, and the processing die 180 are electrically connected to an external circuit by the plurality of solder balls 190.
[0041] According to the semiconductor package of the present invention, the manufacturing cost is relatively low and the yield is also high.
[0042] Although the present invention is disclosed in the embodiments described above, this does not limit the invention, and those skilled in the art can make various changes and modifications without departing from the spirit of the invention. Accordingly, the scope of protection of the present invention shall be as defined in the claims described below. [Explanation of Symbols]
[0043] 110 circuit boards 111 Page 1 112 Side 2 113 Conductive wire 114 Conductive wire 115 Conductive plated through-holes 120 control dies 121 First conductive block 130 memory dives 132 Solder wire 140 Conductive Pillars 141 Page 1 150 Sealing body 151 Page 1 152 2nd page 153 3rd page 160 Passive member 170 Redistribution layer 180 processing dies 182 Second conductive block 190 solder balls
Claims
1. A substrate having opposing first and second surfaces, A memory die is installed on the first surface of the substrate and electrically connected to the substrate, A control die installed on the first surface of the substrate, A plurality of first conductive blocks formed on the control die, A encapsulant formed on the first surface of the substrate and covering the control die and the memory die, having a first surface, a second surface and a plurality of third surfaces, wherein the first surface and the second surface are located in different planes, the plurality of third surfaces are connected to the first surface and the second surface, and the second surface is in contact with the first surface of the substrate. A plurality of conductive pillars are installed on the first surface of the substrate and electrically connected to the substrate, A rewiring layer is formed on the first surface of the sealing body and on the plurality of conductive pillars, and is electrically connected to the plurality of first conductive blocks and the plurality of conductive pillars, A processing die is installed on the second surface of the substrate and electrically connected to the substrate, Includes, The plurality of first conductive blocks are sandwiched between the control die and the redistribution layer and are electrically connected to the control die and the redistribution layer. A semiconductor package in which the plurality of conductive pillars are arranged to surround the encapsulant and to contact the plurality of third surfaces of the encapsulant.
2. The semiconductor package according to claim 1, further comprising a plurality of second conductive blocks sandwiched between the processing die and the substrate and electrically connected to the processing die and the substrate.
3. The semiconductor package according to claim 1, further comprising a plurality of solder wires arranged on the first surface of the substrate and electrically connected to the memory die and the substrate.
4. The semiconductor package according to claim 1, further comprising a plurality of solder balls formed on the redistribution layer.
5. A step of preparing a substrate having opposing first and second surfaces, A step of placing the memory die on the first surface of the substrate and electrically connecting the memory die to the substrate, A step of forming multiple first conductive blocks on a control die, The steps include: installing the control die on the first surface of the substrate; A step of installing a plurality of conductive pillars on the first surface of the substrate and electrically connecting the plurality of conductive pillars to the substrate, A step of forming a encapsulant on the first surface of the substrate and covering the control die, the memory die and the plurality of first conductive blocks, A step of polishing the encapsulant to expose the plurality of first conductive blocks and the plurality of conductive pillars, wherein the polished encapsulant has a first surface, a second surface and a plurality of third surfaces, the first surface and the second surface are located on different planes, the plurality of third surfaces are connected to the first surface and the second surface, the second surface is in contact with the first surface of the substrate, and the plurality of conductive pillars surround the encapsulant and are in contact with the plurality of third surfaces of the encapsulant. The process involves forming a rewiring layer on the first surface of the encapsulant and on the plurality of conductive pillars, and electrically connecting the rewiring layer to the plurality of first conductive blocks and the plurality of conductive pillars, A step of installing the processing die on the second surface of the substrate and electrically connecting the processing die to the substrate, A method for manufacturing semiconductor packages, including the method described above.
6. The method for manufacturing a semiconductor package according to claim 5, further comprising the step of installing a plurality of second conductive blocks between the processing die and the substrate.
7. A method for manufacturing a semiconductor package according to claim 5, further comprising the steps of placing a plurality of solder wires on the first surface of the substrate and electrically connecting the plurality of solder wires to the memory die and the substrate.
8. A method for manufacturing a semiconductor package according to claim 5, further comprising the step of forming a plurality of solder balls on the redistribution layer.