Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present invention provides a semiconductor device comprising an active part provided to a semiconductor substrate, and a temperature-sensitive part provided above the semiconductor substrate. The temperature-sensitive part has: a temperature-sensitive diode provided above the semiconductor substrate; a first interlayer insulation film provided above the temperature-sensitive diode; a temperature-sensitive contact portion provided extending from the upper surface to the lower surface of the first interlayer insulation film; and a housing portion provided below the temperature-sensitive contact portion. A bottom-surface corner section of the temperature-sensitive contact portion is in contact with the temperature-sensitive diode, and the bottom surface of the temperature-sensitive contact portion is in contact with the housing portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] Patent Document 1 describes "a semiconductor device including an integrated PN diode temperature sensor and a method for manufacturing the same". [Prior Art Document] [Patent Document] [Patent Document 1] U.S. Patent Application Publication No. 2019 / 0172770, general disclosure

[0003] In a first aspect of the present invention, there is provided a semiconductor device including an active portion provided on a semiconductor substrate and a temperature sensing portion provided above the semiconductor substrate. The temperature sensing portion includes a temperature sensing diode provided above the semiconductor substrate, a first interlayer insulating film provided above the temperature sensing diode, a temperature sensing contact portion provided to extend from the upper surface to the lower surface of the first interlayer insulating film, and a housing portion provided below the temperature sensing contact portion. A bottom corner portion of the temperature sensing contact portion contacts the temperature sensing diode, and a bottom surface of the temperature sensing contact portion contacts the housing portion.

[0004] In the semiconductor device, a side surface of the temperature sensing diode may contact a side surface of the housing portion.

[0005] Any of the above semiconductor devices may include a second interlayer insulating film provided between the temperature sensing diode and the semiconductor substrate in a depth direction of the semiconductor substrate.

[0006] In any of the above semiconductor devices, an upper surface of the second interlayer insulating film may contact a lower surface of the temperature sensing diode and a lower surface of the housing portion.

[0007] In any of the above semiconductor devices, the housing portion may be a region provided below the temperature sensing contact portion in the first interlayer insulating film.

[0008] In any of the above semiconductor devices, the housing portion may be the second interlayer insulating film provided above the semiconductor substrate.

[0009] In any of the semiconductor devices described above, the second interlayer insulating film may have a recess on its upper surface. The temperature-sensitive diode may be provided in the recess of the second interlayer insulating film.

[0010] In any of the semiconductor devices described above, the housing portion may have polysilicon of a different conductivity type than the contact region of the temperature-sensitive diode.

[0011] In any of the above semiconductor devices, the housing portion may have the same conductivity type as the contact region of the temperature-sensitive diode and a polysilicon with a lower doping concentration than the contact region.

[0012] In any of the semiconductor devices described above, the temperature-sensitive diode may have a temperature-sensitive anode region provided above the semiconductor substrate and a temperature-sensitive cathode region provided above the semiconductor substrate and in contact with the temperature-sensitive anode region.

[0013] In any of the semiconductor devices described above, the temperature-sensitive contact portion may include a barrier metal film provided at the bottom corner of the temperature-sensitive contact portion and a plug portion provided in contact with the inside of the barrier metal film.

[0014] In any of the semiconductor devices described above, the active portion may have a plurality of active contact portions provided on the front surface of the semiconductor substrate.

[0015] In any of the semiconductor devices described above, the bottom surface of the temperature-sensitive contact portion may be in contact with the temperature-sensitive diode and the housing portion.

[0016] In any of the semiconductor devices described above, the temperature-sensitive diode may be in contact with the bottom surface of the temperature-sensitive contact portion from the bottom surface corner to an area of ​​10% to 40% of the bottom surface of the temperature-sensitive contact portion.

[0017] In any of the semiconductor devices described above, the side wall of the temperature-sensing contact portion may have a trench contact structure that contacts the side surface of the temperature-sensing diode.

[0018] In any of the semiconductor devices described above, the side wall of the temperature-sensing contact portion may be in contact with the temperature-sensing diode and the first interlayer insulating film. The temperature-sensing diode may be in contact with the side wall of the temperature-sensing contact portion from the bottom corner to an area of ​​10% to 90% of the side wall of the temperature-sensing contact portion.

[0019] A second embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the steps of forming an active portion on a semiconductor substrate and forming a temperature-sensing portion above the semiconductor substrate, wherein the step of forming the temperature-sensing portion includes the steps of forming a temperature-sensing diode above the semiconductor substrate, forming a first interlayer insulating film above the temperature-sensing diode, forming a temperature-sensing contact portion extending from the upper surface to the lower surface of the first interlayer insulating film, and forming a housing portion below the temperature-sensing contact portion, wherein the bottom corner of the temperature-sensing contact portion is in contact with the temperature-sensing diode and the bottom surface of the temperature-sensing contact portion is in contact with the housing portion.

[0020] In a third embodiment of the present invention, a semiconductor device is provided comprising an active portion and an inactive portion, wherein the inactive portion comprises a polycrystalline portion provided above a semiconductor substrate, an interlayer insulating film provided above the polycrystalline portion, a first inactive contact portion extending from the upper surface to the lower surface of the interlayer insulating film, and a housing portion provided below the first inactive contact portion, wherein the bottom corner of the first inactive contact portion is in contact with the polycrystalline portion, and the bottom surface of the first inactive contact portion is in contact with the housing portion.

[0021] In the semiconductor device described above, the side surface of the polycrystalline portion may be in contact with the side surface of the housing portion.

[0022] In any of the semiconductor devices described above, the housing portion may be a region provided below the first non-active contact portion in the interlayer insulating film.

[0023] In any of the semiconductor devices described above, the first non-active contact portion may include a barrier metal film provided at the bottom corner of the first non-active contact portion and a plug portion provided in contact with the inside of the barrier metal film.

[0024] In any of the semiconductor devices described above, the active portion may include a plurality of active contact portions provided on the front surface of the semiconductor substrate.

[0025] In any of the semiconductor devices described above, the bottom surface of the first non-active contact portion may be in contact with the polycrystalline portion and the housing portion.

[0026] In any of the semiconductor devices described above, the polycrystalline portion may be in contact with the bottom surface of the first non-active contact portion in a region from the bottom corner to 10% or more and 40% or less of the bottom surface of the first non-active contact portion.

[0027] In any of the semiconductor devices described above, the side wall of the first non-active contact portion may have a trench contact structure in contact with the side surface of the polycrystalline portion.

[0028] In any of the semiconductor devices described above, the side wall of the first non-active contact portion may be in contact with the polycrystalline portion and the interlayer insulating film. The polycrystalline portion may be in contact with the side wall of the first non-active contact portion in a region from the bottom corner to 10% or more and 90% or less of the side wall of the first non-active contact portion.

[0029] Any of the above semiconductor devices may include a gate trench portion provided on the front surface of the semiconductor substrate and having a gate conductive portion, and a gate metal layer provided above the semiconductor substrate and electrically connected to the gate conductive portion. The polycrystalline portion may be connected to the gate metal layer via the first inactive contact portion and connected to the gate conductive portion.

[0030] Any of the above semiconductor devices may include a dummy trench portion provided on the front surface of the semiconductor substrate and having a dummy conductive portion, and an emitter electrode provided above the semiconductor substrate and electrically connected to the semiconductor substrate. The polycrystalline portion may be connected to the emitter electrode via the first inactive contact portion and to the dummy conductive portion.

[0031] Any of the above semiconductor devices may include a second conductivity type guard ring provided on the front surface of the semiconductor substrate between the active portion and the edge of the semiconductor substrate, and an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring. The polycrystalline portion may be connected to the edge metal layer via the first inactive contact portion.

[0032] Any of the above semiconductor devices may include a field insulating film provided below the interlayer insulating film. The first inactive contact portion may be provided above the polycrystalline portion above the field insulating film.

[0033] Any of the above semiconductor devices may include, on the front surface of the semiconductor substrate, a second conductivity type guard ring provided between the active portion and the edge of the semiconductor substrate, an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring, and a field insulating film provided below the interlayer insulating film. The polycrystalline portion may be connected to the edge metal layer via the first inactive contact portion. The housing portion may be a region of the field insulating film provided below the first inactive contact portion.

[0034] Any of the above semiconductor devices may include a second conductivity type guard ring provided on the front surface of the semiconductor substrate between the active portion and the edge of the semiconductor substrate, and an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring. The polycrystalline portion may be connected to the edge metal layer via the first inactive contact portion. The polycrystalline portion may have a contact region in contact with the housing portion. The housing portion may have polysilicon with a lower impurity concentration than the contact region of the polycrystalline portion.

[0035] Any of the above semiconductor devices includes a pad electrode provided above the semiconductor substrate, and the polycrystalline portion may be connected to the pad electrode via the first inactive contact portion.

[0036] A fourth embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the steps of forming an active portion and forming an inactive portion, wherein the step of forming the inactive portion includes forming a polycrystalline portion above a semiconductor substrate, forming an interlayer insulating film above the polycrystalline portion, forming a first inactive contact portion extending from the upper surface to the lower surface of the interlayer insulating film, and forming a housing portion below the first inactive contact portion, wherein the bottom corner of the first inactive contact portion is in contact with the polycrystalline portion and the bottom surface of the first inactive contact portion is in contact with the housing portion.

[0037] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0038] [Figure 1A] An example of an enlarged view of the top surface of the semiconductor device 100 is shown. [Figure 1B] An example of a cross-section from a-a' in Figure 1A is shown. [Figure 2A] An enlarged view of the top surface of a modified example of the semiconductor device 100 is shown. [Figure 2B]An example of a cross-section between b and b' in Figure 2A is shown. [Figure 3] An example of a top view of the semiconductor device 100 is shown. [Figure 4] An example of a cross-section of a semiconductor device 100 equipped with a temperature-sensing element 180 is shown. [Figure 5A] An example of an enlarged cross-sectional view of semiconductor device 100 is shown. [Figure 5B] This shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. [Figure 5C] This shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. [Figure 5D] An example of an enlarged cross-sectional view of the semiconductor device 100 when a void 302 occurs in the temperature-sensitive contact portion 188 is shown. [Figure 5E] Another example of an enlarged cross-sectional view of the semiconductor device 100 when a void 302 occurs in the temperature-sensitive contact portion 188 is shown. [Figure 6] A cross-section of a modified semiconductor device 100 equipped with a temperature-sensing element 180 is shown. [Figure 7A] This shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. [Figure 7B] This shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. [Figure 7C] This shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. [Figure 7D] An example of an enlarged cross-sectional view of the semiconductor device 100 when a void 302 occurs in the temperature-sensitive contact portion 188 is shown. [Figure 7E] Another example of an enlarged cross-sectional view of the semiconductor device 100 when a void 302 occurs in the temperature-sensitive contact portion 188 is shown. [Figure 8] This is a flowchart showing an example of the manufacturing process for semiconductor device 100. [Figure 9] Figure 3 shows an example of the electrical connections of various parts of the semiconductor device 100. [Figure 10A] An example of an enlarged view of the top surface of the semiconductor device 100 is shown. [Figure 10B] An example of a c-c' section in Figure 9 is shown. [Figure 11]An example of a d-d' section is shown in Figure 9. [Figure 12A] An example of an enlarged view of the d-d' section in Figure 9 is shown. [Figure 12B] An example of an enlarged view of the d-d' cross-section in Figure 9 when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 12C] Another example of an enlarged view of the d-d' cross-section in Figure 9 when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 13] An example of a d-d' section is shown in Figure 9. [Figure 14A] An example of an enlarged view of the d-d' section in Figure 9 is shown. [Figure 14B] An example of an enlarged view of the d-d' cross-section in Figure 9 when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 14C] Another example of an enlarged view of the d-d' cross-section in Figure 9 when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 15] An example of the e-e' section in Figure 9 is shown. [Figure 16A] An example of an enlarged view of the e-e' cross section in Figure 9 is shown. [Figure 16B] An example of an enlarged view of the e-e' cross-section in Figure 9 when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 16C] Another example of an enlarged view of the e-e' cross-section in Figure 9 when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 17] An example of the e-e' section in Figure 9 is shown. [Figure 18A] An example of an enlarged view of the e-e' cross section in Figure 9 is shown. [Figure 18B] An example of an enlarged view of the e-e' cross-section in Figure 9 when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 18C] Another example of an enlarged view of the e-e' cross-section in Figure 9 when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 19A]An example of a top view of the semiconductor device 100 is shown. [Figure 19B] An example of region R in Figure 19A is shown. [Figure 20] An example of the f-f' section in Figure 19B is shown. [Figure 21A] An example of an enlarged view of the f-f' section in Figure 19B is shown. [Figure 21B] An example of an enlarged view of the f-f' section in Figure 19B is shown. [Figure 21C] An example of an enlarged view of the f-f' section in Figure 19B is shown. [Figure 21D] An example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 21E] Another example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 22] An example of the f-f' section in Figure 19B is shown. [Figure 23A] An example of an enlarged view of the f-f' section in Figure 19B is shown. [Figure 23B] An example of an enlarged view of the f-f' section in Figure 19B is shown. [Figure 23C] An example of an enlarged view of the f-f' section in Figure 19B is shown. [Figure 23D] An example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 23E] Another example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 24] An example of the f-f' section in Figure 19B is shown. [Figure 25A] An example of an enlarged view of the f-f' section in Figure 19B is shown. [Figure 25B] An example of an enlarged view of the f-f' section in Figure 19B is shown. [Figure 25C]An example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 25D] Another example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 26] An example of the f-f' section in Figure 19B is shown. [Figure 27A] An example of an enlarged view of the f-f' section in Figure 19B is shown. [Figure 27B] An example of an enlarged view of the f-f' section in Figure 19B is shown. [Figure 27C] An example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 27D] Another example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134 is shown. [Figure 28] An example of a g-g' cross-section is shown in Figure 19A. [Figure 29A] An example of region P in Figure 19A is shown. [Figure 29B] Another example of region P in Figure 19A is shown. [Figure 29C] Another example of region P in Figure 19A is shown. [Figure 30] Another example of the g-g' section in Figure 19A is shown. [Figure 31] This is a flowchart showing an example of the manufacturing process for semiconductor device 100. [Modes for carrying out the invention]

[0039] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0040] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0041] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0042] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0043] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0044] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0045] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding the charge polarity of the donor concentration (where the donor concentration is the concentration of positive ions) and the acceptor concentration (where the acceptor concentration is the concentration of negative ions). For example, if the donor concentration is ND and the acceptor concentration is NA, the net doping concentration at any given position will be ND-NA. In this specification, net doping concentration may sometimes be simply referred to as doping concentration.

[0046] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are formed by the bonding of vacancies (V), oxygen (O), and hydrogen (H) in a semiconductor; Si-iH defects, which are formed by the bonding of interstitial silicon (Si-i) and hydrogen; and CiOi-H defects, which are formed by the bonding of interstitial carbon (Ci), interstitial oxygen (Oi), and hydrogen, all function as electron donors. In this specification, these defects may be referred to as hydrogen donors.

[0047] In this specification, when P+ or N+ is mentioned, it means a higher doping concentration than P or N, and when P- or N- is mentioned, it means a lower doping concentration than P or N. Furthermore, when P++ or N++ is mentioned in this specification, it means a higher doping concentration than P+ or N+.

[0048] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by spheroidal resistance (SR) spectroscopy may be used as the net doping concentration. A carrier refers to an electron or hole charge carrier. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0049] Furthermore, if the concentration distribution of donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of donor, acceptor, or net doping in that region. In cases where the concentrations of donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of donor, acceptor, or net doping in that region may be used as the concentration of donor, acceptor, or net doping.

[0050] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state within the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc. The reason for the decrease in carrier concentration is as follows: In the SR method, spreading resistance is measured, and the carrier concentration is converted from the measured value of spreading resistance. At this time, the carrier mobility of the crystalline state is used. On the other hand, at locations where lattice defects are introduced, the carrier concentration is calculated using the carrier mobility of the crystalline state, even though the carrier mobility is reduced. Therefore, the value will be lower than the actual carrier concentration, i.e., the donor or acceptor concentration.

[0051] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV method or SR method may be lower than the chemical concentrations of the elements that represent the donor or acceptor. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentrations of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which is a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration. This specification adopts the SI unit system. In this specification, units of distance and length may be expressed in cm (centimeters). In this case, calculations may be performed by converting to m (meters). Regarding the numerical representation of powers of 10, for example, the representation of 1E+16 is 1 × 10⁻⁶ 16 This indicates that the 1E-16 designation is 1 × 10 -16 This indicates.

[0052] Figure 1A shows an example of an enlarged view of the top surface of the semiconductor device 100. The semiconductor device 100 in this example is a semiconductor chip equipped with a transistor section 70. The semiconductor device 100 is not limited to a transistor, as long as it is a semiconductor element having a MOS gate structure on the semiconductor substrate 10. The configuration shown in this figure may be repeatedly provided in the positive and negative directions of the X axis.

[0053] The transistor section 70 is the region obtained by projecting the collector region 22, which is provided on the back side of the semiconductor substrate 10, onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor section 70 includes a transistor such as an IGBT. In this example, the transistor section 70 is an IGBT. However, the transistor section 70 may also be other transistors such as a MOSFET.

[0054] In this figure, the region around the active area 120 of the semiconductor device 100 is shown, and other regions are omitted. The active area 120 is the part where the main current flows between the front surface 21 and the back surface 23 of the semiconductor substrate 10. The active area 120 will be described later. For example, an edge termination structure may be provided in the negative region in the Y-axis direction of the semiconductor device 100 in this example. The edge termination structure mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure has, for example, a guard ring, a field plate, a resurf, or a structure combining these. In this example, for convenience, the negative edge in the Y-axis direction is described, but the same applies to other edges of the semiconductor device 100.

[0055] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, another compound semiconductor substrate, or a diamond semiconductor substrate. In this example, the semiconductor substrate 10 is a silicon substrate. In this specification, when simply referred to as a "top view," it means viewing from the top side of the semiconductor substrate 10. The semiconductor substrate 10 has a front surface 21 and a back surface 23, as described later.

[0056] The semiconductor device 100 in this example comprises a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 also includes an emitter electrode 52 and a gate metal layer 50 located above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and gate metal layer 50 are examples of front-side metal layers. The gate trench 40 is an example of a MOS gate structure provided by the semiconductor device 100. While the semiconductor device 100 in this example is a transistor with a MOS gate structure, it may also be a diode with a MOS gate structure.

[0057] The emitter electrode 52 is located above the gate trench 40, dummy trench 30, emitter region 12, base region 14, contact region 15, and well region 17. The gate metal layer 50 is located above the connection portion 25 and the well region 17.

[0058] The emitter electrode 52 and the gate metal layer 50 are formed from a metal-containing material. At least a portion of the emitter electrode 52 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal film formed of titanium or a titanium compound in the layer below the region formed of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separated from each other.

[0059] The emitter electrode 52 and gate metal layer 50 are provided above the semiconductor substrate 10, with an interlayer insulating film 38 in between. The interlayer insulating film 38 is omitted in Figure 1A. Contact holes 54, 55, and 56 are provided through the interlayer insulating film 38.

[0060] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive part within the transistor section 70 via the connection section 25. A barrier metal film made of titanium or a titanium compound and / or a plug made of tungsten may be formed inside the contact hole 55.

[0061] The contact hole 56 connects the emitter electrode 52 to the dummy conductive part in the dummy trench 30. A barrier metal film made of titanium or a titanium compound and / or a plug made of tungsten may be formed inside the contact hole 56.

[0062] The connection portion 25 is connected to the front-side metal layer, such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. In this example, the connection portion 25 may be provided extending in the X-axis direction and electrically connected to the gate conductive portion. The connection portion 25 may also be provided between the emitter electrode 52 and the dummy conductive portion. In this example, the connection portion 25 is not provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0063] The gate trench portion 40 is an example of an active trench portion 122 provided on the front surface 21 of the semiconductor substrate 10. That is, the active trench portion 122 may be a trench portion provided in the active portion 120. The gate trench portion 40 is arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portion 40 in this example may have two extended portions 41 that extend along an extension direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connecting portion 43 that connects the two extended portions 41.

[0064] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extended portions 41 of the gate trench portion 40, electric field concentration at the ends of the extended portions 41 can be mitigated. In the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be electrically connected to the gate conductive portion via the connection portion 25.

[0065] The dummy trench portion 30 is an example of an active trench portion 122 provided on the front surface 21 of the semiconductor substrate 10. That is, the active trench portion 122 may be a trench portion provided on the active portion 120. The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. The dummy trench portion 30, like the gate trench portion 40, is arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). In this example, the dummy trench portion 30 has an I-shape on the front surface 21 of the semiconductor substrate 10, but like the gate trench portion 40, it may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extended portions that extend along the stretching direction and a connecting portion that connects the two extended portions.

[0066] The transistor section 70 in this example has a structure in which two gate trench sections 40 and two dummy trench sections 30 are arranged in a repeating pattern. That is, the transistor section 70 in this example has gate trench sections 40 and dummy trench sections 30 in a 1:1 ratio. For example, the transistor section 70 has one dummy trench section 30 between two extended sections 41.

[0067] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 may be greater than the ratio of the dummy trench portion 30, and vice versa. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 2:3 or 2:4. Furthermore, the transistor portion 70 may have all trenches as gate trench portions 40 and not have dummy trench portions 30.

[0068] The well region 17 is a second conductivity type region located on the front surface 21 side of the semiconductor substrate 10, closer to the drift region 18, which will be described later. The well region 17 is an example of a well region located on the peripheral side of the active portion 120. The well region 17 is, for example, of the P+ type. The well region 17 is formed within a predetermined range from the edge of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. A portion of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 17. The bottom of the extending end of the gate trench portion 40 and the dummy trench portion 30 may be covered by the well region 17.

[0069] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided by extending in the stretching direction.

[0070] The mesa portion 71 is a mesa portion provided adjacent to the trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is the part of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be the portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. The extended portion of each trench portion may be considered as one trench portion. That is, the region sandwiched between two extended portions may be considered as the mesa portion.

[0071] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 are provided alternately in the stretching direction.

[0072] The base region 14 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, P-type. The base region 14 may be provided at both ends of the mesa portion 71 in the Y-axis direction on the front surface 21 of the semiconductor substrate 10. Note that Figure 1A shows only one end of the base region 14 in the Y-axis direction.

[0073] The emitter region 12 is a first conductivity type region with a higher doping concentration than the drift region 18. In this example, the emitter region 12 is N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71, in contact with the gate trench portion 40. The emitter region 12 may extend in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0074] Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0075] The contact region 15 is located above the base region 14 and is a region of a second conductivity type with a higher doping concentration than the base region 14. In this example, the contact region 15 is of type P+. In this example, the contact region 15 is located on the front surface 21 of the mesa portion 71. The contact region 15 may be located in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. In this example, the contact region 15 is in contact with both the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also located below the contact hole 54.

[0076] Figure 1B shows an example of the a-a' cross-section in Figure 1A. The a-a' cross-section is the XZ plane passing through the emitter region 12 in the transistor section 70. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a collector electrode 24, and an active contact portion 124 in the a-a' cross-section. The collector electrode 24 is an example of a back-side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0077] The drift region 18 is a region of a first conductivity type provided on the semiconductor substrate 10. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining on the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0078] The buffer region 20 is a first-conductivity region located on the back surface 23 side of the semiconductor substrate 10, relative to the drift region 18. In this example, the buffer region 20 is N-type. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may function as a field stop layer to prevent the depletion layer extending from the underside of the base region 14 from reaching the collector region 22 of the second-conductivity region. The buffer region 20 may be omitted.

[0079] The collector region 22 is located below the buffer region 20 in the transistor section 70. The collector region 22 has a second conductivity type. In this example, the collector region 22 is of type P+.

[0080] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as metal. The material of the collector electrode 24 may be the same as or different from the material of the emitter electrode 52.

[0081] The base region 14 is a second conductivity type region located above the drift region 18. The base region 14 is located in contact with the gate trench portion 40. The base region 14 may be located in contact with the dummy trench portion 30.

[0082] The emitter region 12 is provided above the base region 14. The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0083] The storage region 16 is a first conductivity type region located on the front surface 21 side of the semiconductor substrate 10, relative to the drift region 18. In this example, the storage region 16 is of type N+. However, the storage region 16 does not necessarily have to be provided.

[0084] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration in the accumulation region 16 is higher than the doping concentration in the drift region 18. The ion implantation dose in the accumulation region 16 is 1.0E+12cm -2 The above is 1.0E+13cm -2 The following may be the case. Also, the ion implantation dose for the accumulation region 16 is 3.0E+12cm². -2 The above is for 6.0E+12cm. -2 The following is also possible: By providing a storage region 16, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced.

[0085] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench may be an active trench 122 of the active section 120. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, contact region 15, and storage region 16 is provided, each trench penetrates these regions as well and reaches the drift region 18. The statement that a trench penetrates a doping region is not limited to those manufactured in the order of forming the doping region before forming the trenches. Even when doping regions are formed between trenches after the trenches have been formed, the trenches are still included in the statement that they penetrate a doping region.

[0086] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, on the inside of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38.

[0087] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that faces an adjacent base region 14 on the mesa portion 71 side, with the gate insulating film 42 in between. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is created on the surface layer of the interface in contact with the gate trench within the base region 14.

[0088] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 may be covered with an interlayer insulating film 38 on the front surface 21.

[0089] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided in contact with the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Similarly, contact holes 55 and 56 may be provided through the interlayer insulating film 38. The interlayer insulating film 38 may be a BPSG (Boro-phospho Silicate Glass) film, a BSG (borosilicate glass) film, a PSG (Phosphosilicate glass) film, an HTO film, or a laminate of these materials. The thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited thereto.

[0090] The active contact portion 124 is provided on the front surface 21 of the semiconductor substrate 10. The active contact portion 124 may have a contact hole 54 and a metal layer filled inside the contact hole 54. The inside of the contact hole 54 may be filled with the same material as the emitter electrode 52, or with a different material than the emitter electrode 52. The active contact portion 124 may include a barrier metal film 1242 provided in the contact hole 54 and in contact with the semiconductor substrate 10. The active contact portion 124 may include a plug portion 1244 that is in contact with the barrier metal film 1242 and is provided to fill the contact hole 54. The barrier metal film 1242 of the active contact portion 124 may contain titanium or a titanium compound. The plug portion 1244 of the active contact portion 124 may contain a plug metal such as tungsten. The contact holes 55 and 56, and the metal layers filled inside the contact holes 55 and 56, may have a similar configuration. The active portion 120 may have a plurality of active contact portions 124 provided on the front surface 21 of the semiconductor substrate 10. An alloy layer may be formed in contact with the barrier metal film 1242, consisting of an alloy of the metal contained in the barrier metal film 1242 and a layer such as the semiconductor substrate 10 located below the contact holes 54, 55, and 56. Furthermore, regions with a high concentration of impurities may be formed in the semiconductor substrate 10 and other layers located below the contact holes 54, 55, and 56, where they are in contact with the alloy layer. While the active contact portions 124 in this example have a planar contact structure, they may also have a trench contact structure as described later.

[0091] The back-side lifetime control region 151 may be provided in the transistor section 70. However, the back-side lifetime control region 151 may be omitted. The back-side lifetime control region 151 is a region in which a lifetime killer is intentionally formed by injecting impurities into the semiconductor substrate 10. In one example, the back-side lifetime control region 151 is formed by injecting helium into the semiconductor substrate 10. The back-side lifetime control region 151 may also be formed by injecting protons. By providing the back-side lifetime control region 151, the turn-off time can be reduced and the tail current suppressed, thereby reducing losses during switching.

[0092] Lifetime killers are carrier recombination centers. Lifetime killers may be lattice defects. For example, lifetime killers may be vacancies, double vacancies, composite defects between these and elements constituting the semiconductor substrate 10, or dislocations. Lifetime killers may also be noble gas elements such as helium and neon, or metallic elements such as platinum. Electron beams or protons may be used to form lattice defects.

[0093] The lifetime killer concentration is the concentration of carrier recombination centers. The lifetime killer concentration may also be the concentration of lattice defects. For example, the lifetime killer concentration may be the concentration of vacancies such as vacancies and double vacancies, the concentration of composite defects between these vacancies and the elements constituting the semiconductor substrate 10, or the concentration of dislocations. Furthermore, the lifetime killer concentration may also be the chemical concentration of noble gas elements such as helium and neon, or the chemical concentration of metallic elements such as platinum.

[0094] The rear-side lifetime control region 151 may be formed by injection from the rear surface 23 side. This makes it easier to avoid affecting the front surface 21 side of the semiconductor device 100. For example, the rear-side lifetime control region 151 is formed by irradiating with helium or protons from the rear surface 23 side. Here, whether the rear-side lifetime control region 151 is formed by injection from the front surface 21 side or the rear surface 23 side can be determined by obtaining the state of the front surface 21 side by the SR method or by measuring the leakage current.

[0095] Figure 2A shows an enlarged top view of a modified example of the semiconductor device 100. The semiconductor device 100 in this example includes a transistor section 70 and a diode section 80. The configuration shown in this figure may be repeatedly provided in the positive and negative directions of the X-axis.

[0096] The semiconductor device 100 in this example includes a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17, all located inside the front surface 21 of the semiconductor substrate 10. The gate trench 40 and the dummy trench 30 are examples of active trenches 122, respectively.

[0097] The dummy trench portion 30 in this example may have a U-shape on the front surface 21 of the semiconductor substrate 10, similar to the gate trench portion 40. That is, the dummy trench portion 30 may have two extended portions 31 that extend along the stretching direction and a connecting portion 33 that connects the two extended portions 31.

[0098] The semiconductor device 100 in this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other. The transistor section 70 in this example includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80. However, the semiconductor device 100 does not necessarily have to include the boundary section 90.

[0099] The boundary portion 90 is provided in the transistor portion 70 and is adjacent to the diode portion 80. The boundary portion 90 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, the boundary portion 90 does not have an emitter region 12. In this example, the trench portion of the boundary portion 90 is a dummy trench portion 30. In this example, the boundary portion 90 is arranged such that both ends in the X-axis direction are dummy trench portions 30.

[0100] The contact holes 54 are located above the base region 14 in the diode section 80. The contact holes 54 are located above the contact region 15 in the boundary section 90. None of the contact holes 54 are located above the well regions 17 located at both ends in the Y-axis direction.

[0101] The mesa portion 91 is provided at the boundary portion 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, the mesa portion 91 has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0102] The mesa portion 81 is provided in the diode portion 80 in the region sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a base region 14 on the front surface 21 of the semiconductor substrate 10. In this example, the mesa portion 81 has a well region 17 on the negative side in the Y-axis direction.

[0103] The emitter region 12 is provided in the mesa portion 71, but it does not need to be provided in the mesa portions 81 and 91. The contact region 15 is provided in the mesa portions 71 and 91, but it does not need to be provided in the mesa portion 81.

[0104] Figure 2B shows an example of a b-b' cross-section in Figure 2A. The semiconductor device 100 in this example includes a rear-side lifetime control region 151 and a front-side lifetime control region 152. However, the semiconductor device 100 does not necessarily have to include either the rear-side lifetime control region 151 or the front-side lifetime control region 152. The semiconductor device 100 in this example includes a collector region 22 and a cathode region 82 on the rear side 23 of the buffer region 20.

[0105] The contact area 15 is provided above the base area 14 in the mesa portion 91. The contact area 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In other cross-sections, the contact area 15 may be provided on the front surface 21 of the mesa portion 71.

[0106] The storage region 16 is provided in the transistor section 70 and the diode section 80. In this example, the storage region 16 is provided across the entire surface of the transistor section 70 and the diode section 80. However, the storage region 16 does not necessarily have to be provided in the diode section 80.

[0107] The cathode region 82 is located below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is located below the boundary 90 in this example.

[0108] The rear-side lifetime control region 151 may be provided in both the transistor section 70 and the diode section 80, in only the transistor section 70, or in only the diode section 80. This allows the semiconductor device 100 in this example to speed up the turn-off operation of the transistor section 70 or the reverse recovery operation of the diode section 80, thereby further improving switching losses. The rear-side lifetime control region 151 may be formed in the same manner as the rear-side lifetime control region 151 in other embodiments.

[0109] The front-side lifetime control region 152 is provided on the front surface 21 side of the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the front-side lifetime control region 152 is provided in the drift region 18. The front-side lifetime control region 152 may be provided in both the transistor section 70 and the diode section 80, or it may be provided only in the diode section 80. The front-side lifetime control region 152 may be provided in the diode section 80 and the boundary section 90, and may not be provided in part of the transistor section 70. The front-side lifetime control region 152 can reduce reverse recovery loss by suppressing hole injection from the transistor section 70 and the diode section 80.

[0110] The front-side lifetime control region 152 may be formed by any method among the methods for forming the back-side lifetime control region 151. The elements and dose amounts used to form the back-side lifetime control region 151 and the front-side lifetime control region 152 may be the same or different.

[0111] The front-side lifetime control region 152 is provided extending from the diode portion 80 to the transistor portion 70. The front-side lifetime control region 152 may be formed by introducing a lifetime killer from the front surface 21 of the semiconductor substrate 10. The front-side lifetime control region 152 may also be formed by irradiation from the back surface 23 of the semiconductor substrate 10. In this example, the front-side lifetime control region 152 is provided below the gate trench portion 40. When particle beams or the like used to form the front-side lifetime control region 152 pass through the MOS gate structure of the semiconductor device 100, defects may occur at the interface between the gate oxide film and the semiconductor substrate.

[0112] The semiconductor device 100 may be a power semiconductor device for controlling power, etc. The semiconductor device 100 in this example may have a vertical semiconductor structure in which a metal layer is provided on the back surface 23 side of the semiconductor substrate 10. However, the semiconductor device 100 may have a horizontal semiconductor structure in which a metal layer is not provided on the back surface 23 side.

[0113] In this example, the semiconductor device 100 is described using an RC-IGBT with a trench gate structure as an example. However, the semiconductor device 100 may also be a semiconductor device with a planar gate structure, or another semiconductor device such as a diode. The semiconductor device 100 may include an N-channel MOSFET or a P-channel MOSFET.

[0114] Figure 3 shows an example of a top view of the semiconductor device 100. The semiconductor device 100 in this example includes a temperature sensing element 180. In this example, only some components of the semiconductor device 100 are shown, and some components have been omitted.

[0115] The semiconductor substrate 10 has edges 102 when viewed from above. In this example, the semiconductor substrate 10 has two pairs of edges 102 that face each other when viewed from above. In this example, the X axis and Y axis are parallel to one of the edges 102.

[0116] The semiconductor substrate 10 is provided with an active section 120. The active section 120 is a region where the main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode 52 is provided above the active section 120, but it is omitted in this figure.

[0117] The active section 120 may be provided with at least one of a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a freewheeling diode (FWD). In the example shown in Figure 3, the transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (in this example, the X-axis direction) on the front surface 21 of the semiconductor substrate 10. In other examples, the active section 120 may be provided with only one of the transistor section 70 and the diode section 80. That is, the active section 120 may be provided with only the transistor section 70 as shown in Figure 1A, or with both the transistor section 70 and the diode section 80 as shown in Figure 2A, or with only the diode section 80.

[0118] In this example, the region where the transistor section 70 is located is denoted by the symbol "I", and the region where the diode section 80 is located is denoted by the symbol "F". The transistor section 70 and the diode section 80 may each have a longitudinal length in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of the gate trench section 40 and the dummy trench section 30.

[0119] The diode portion 80 may be the region obtained by projecting the cathode region 82, which is provided on the back surface 23 of the semiconductor substrate 10, onto the upper surface of the semiconductor substrate 10. The region obtained by projecting the cathode region 82 onto the upper surface of the semiconductor substrate 10 may be located inside the diode portion 80. On the back surface 23 of the semiconductor substrate 10, a P+ type collector region 22 may be provided in the region other than the cathode region 82.

[0120] The edge termination structure 140 is provided on the front surface 21 of the semiconductor substrate 10. In a top view, the edge termination structure 140 is provided between the active portion 120 and the edge 102. The edge termination structure 140 mitigates electric field concentration on the front surface 21 side of the semiconductor substrate 10. The edge termination structure 140 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 120.

[0121] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 includes a gate pad 112, a sense electrode 114, an anode pad 116, and a cathode pad 118. Each pad may be located near an edge 102 of the semiconductor substrate 10. The vicinity of the edge 102 refers to the area between the edge 102 and the emitter electrode 52 in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0122] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the gate conductive portion 44 of the gate trench portion 40 of the active portion 120. The semiconductor device 100 may be provided with gate wiring connecting the gate pad 112 and the gate trench portion 40. The gate wiring may be configured by combining either the gate metal layer 50 or the connection portion 25, or both, as appropriate.

[0123] The sense electrode 114 is electrically connected to a current sensing unit 115 located below the sense electrode 114. The sense electrode 114 detects the current flowing through the current sensing unit 115. The current sensing unit 115 detects the current flowing through the transistor unit 70. The current sensing unit 115 has a structure corresponding to the transistor unit 70. The current flowing through the current sensing unit 115 is smaller than the current flowing through the transistor unit 70. The current sensing unit 115 may have a current flowing through it that is proportional to the current flowing through the transistor unit 70, simulating the operation of the transistor unit 70. The ratio of the current flowing through the current sensing unit 115 to the current flowing through the transistor unit 70 is set appropriately. By using the current sensing unit 115, the current flowing through the transistor unit 70 can be monitored.

[0124] The temperature-sensing element 180 is located on or inside the semiconductor substrate 10. In this example, the temperature-sensing element 180 is located between the transistor sections 70 in the central part of the semiconductor device 100. The temperature-sensing element 180 detects the temperature of the active section 120. The temperature-sensing element 180 may have a diode formed of single-crystal or polycrystalline silicon. The temperature-sensing element 180 is used to detect the temperature of the semiconductor device 100 and protect the semiconductor chip (semiconductor substrate 10) from overheating. The temperature-sensing element 180 is connected to a constant current source. When the temperature of the semiconductor device 100 changes, the forward voltage of the current flowing through the temperature-sensing element 180 changes. The semiconductor device 100 can detect the temperature based on the change in the forward voltage of the temperature-sensing element 180.

[0125] The anode pad 116 is electrically connected to the temperature-sensing anode region 182 of the temperature-sensing unit 180. The anode pad 116 is electrically connected to the temperature-sensing anode region 182 of the temperature-sensing unit 180 by an anode wiring section 117 which is electrically connected to the temperature-sensing anode region 182. The temperature-sensing anode region 182 will be described later.

[0126] The cathode pad 118 is electrically connected to the temperature-sensing cathode region 181 of the temperature-sensing unit 180. The cathode pad 118 is electrically connected to the temperature-sensing cathode region 181 of the temperature-sensing unit 180 by a cathode wiring section 119 which is electrically connected to the temperature-sensing cathode region 181. The temperature-sensing cathode region 181 will be described later.

[0127] Figure 4 shows an example of a cross-section of a semiconductor device 100 equipped with a temperature-sensing section 180. The temperature-sensing section 180 includes a temperature-sensing diode 183, a first interlayer insulating film 36, a temperature-sensing contact section 188, and a housing section 198. The temperature-sensing section 180 may also have a second interlayer insulating film 37.

[0128] The temperature-sensitive diode 183 is provided above the semiconductor substrate 10. The temperature-sensitive diode 183 may be a PN diode including a temperature-sensitive anode region 182 provided above the semiconductor substrate 10 and a temperature-sensitive cathode region 181 provided above the semiconductor substrate 10 and in contact with the temperature-sensitive anode region 182. The temperature-sensitive cathode region 181 may be formed of an N-type semiconductor and function as the cathode of the PN diode. The temperature-sensitive anode region 182 may be formed of a P-type semiconductor and function as the anode of the PN diode. The materials of the temperature-sensitive cathode region 181 and the temperature-sensitive anode region 182 may be polycrystalline semiconductors, and one example may be polysilicon.

[0129] A well region 17 may be provided in the semiconductor substrate 10 below the temperature-sensitive diode 183. The well region 17 provided below the temperature-sensitive diode 183 may be the same as the well region 17 provided on the peripheral side of the active portion 120 in Figure 1A, and may be formed by the same process.

[0130] The first interlayer insulating film 36 is provided above the temperature-sensitive diode 183. Above means in the positive direction in the Z-axis direction with respect to the front surface 21 of the semiconductor substrate 10. The first interlayer insulating film 36 may be an interlayer insulating film 38. That is, the interlayer insulating film 38 may be a concept that includes both the first interlayer insulating film 36 and the second interlayer insulating film 37, which will be described later. The first interlayer insulating film 36 may be a BPSG film, a BSG film, a PSG film, an HTO film, or a laminate of these materials.

[0131] The temperature-sensitive contact portion 188 is provided extending from the upper surface to the lower surface of the first interlayer insulating film 36. The contact hole 58 may be provided penetrating the first interlayer insulating film 36. The temperature-sensitive contact portion 188 may have a contact hole 58 and a metal layer filled inside the contact hole 58. The detailed configuration of the temperature-sensitive contact portion 188 will be described later.

[0132] The cathode wiring section 119 is electrically connected to the temperature-sensitive cathode region 181 via the contact hole 58. The cathode wiring section 119 may be made of a metallic material. The cathode wiring section 119 may be made of the same material as the emitter electrode 52. The temperature-sensitive cathode region 181 may be electrically connected to the cathode pad 118 by the cathode wiring section 119.

[0133] The anode wiring section 117 is electrically connected to the temperature-sensitive anode region 182 via the contact hole 58. The anode wiring section 117 may be made of a metallic material. The anode wiring section 117 may be made of the same material as the emitter electrode 52. The temperature-sensitive anode region 182 may be electrically connected to the anode pad 116 by the anode wiring section 117.

[0134] The housing portion 198 is provided below the temperature-sensitive contact portion 188. The material of the housing portion 198 may be the same as the material of the first interlayer insulating film 36, the same as the material of the second interlayer insulating film 37, and the same as the material of the temperature-sensitive diode 183. The detailed configuration of the housing portion 198 will be described later.

[0135] The second interlayer insulating film 37 may be provided between the temperature-sensitive diode 183 and the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The second interlayer insulating film 37 may be an interlayer insulating film 38. That is, the concept of interlayer insulating film 38 may include both the first interlayer insulating film 36 and the second interlayer insulating film 37. The second interlayer insulating film 37 may be a BPSG film, a BSG film, a PSG film, an HTO film, or a laminate of these materials.

[0136] Figure 5A shows an example of an enlarged cross-sectional view of the semiconductor device 100. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the temperature sensing section 180.

[0137] The bottom corner portion 1880 of the temperature-sensing contact portion 188 may be in contact with the temperature-sensing diode 183. The bottom corner portion 1880 of the temperature-sensing contact portion 188 may be the intersection of the bottom surface of the temperature-sensing contact portion 188 and the side surface of the temperature-sensing contact portion 188. Contact between the bottom corner portion 1880 and the temperature-sensing diode 183 may mean contact with the temperature-sensing diode 183 on its upper surface, contact with the temperature-sensing diode 183 on its side surface, or contact with the temperature-sensing diode 183 in an internal region of the temperature-sensing diode 183. In this example, the bottom corner portion 1880 is in contact with the temperature-sensing diode 183 on its upper surface.

[0138] The temperature-sensitive contact portion 188 in this example has two bottom corner portions 1880. One of the two bottom corner portions 1880 may be in contact with the temperature-sensitive diode 183. The other bottom corner portion 1880 may or may not be in contact with the housing portion 198. In this example, one bottom corner portion 1880a of the temperature-sensitive contact portion 1880a is in contact with the temperature-sensitive cathode region 181 of the temperature-sensitive diode 183, and the other bottom corner portion 1880b is in contact with the housing portion 198.

[0139] The bottom surface of the temperature-sensitive contact portion 188 may be in contact with the housing portion 198. The bottom surface of the temperature-sensitive contact portion 188 may be the surface between the two bottom corner portions 1880 of the temperature-sensitive contact portion 188. When the bottom surface of the temperature-sensitive contact portion 188 is in contact with the housing portion 198, it may be the bottom surface in contact with the housing portion 198 on the upper surface of the housing portion 198, or it may be the bottom surface in contact with the housing portion 198 in an internal region of the housing portion 198. In this example, the bottom surface of the temperature-sensitive contact portion 188 is in contact with the housing portion 198 on the upper surface of the housing portion 198.

[0140] The bottom surface of the temperature-sensing contact portion 188 may be in contact with the temperature-sensing diode 183 and the housing portion 198. In this example, one bottom corner portion 1880a of the temperature-sensing contact portion 188a is in contact with the temperature-sensing cathode region 181 of the temperature-sensing diode 183, and the other bottom corner portion 1880b is in contact with the housing portion 198, so that the bottom surface of the temperature-sensing contact portion 188a is in contact with the temperature-sensing diode 183 and the housing portion 198.

[0141] The thermosensitive diode 183 may be in contact with the bottom surface of the thermosensitive contact portion 188 from the bottom surface corner 1880 to an area of ​​10% to 40% of the bottom surface of the thermosensitive contact portion 188. That is, the ratio of the area of ​​the bottom surface of the thermosensitive contact portion 188 that is in contact with the thermosensitive diode 183 to the area of ​​the bottom surface of the thermosensitive contact portion 188 may be 10% to 40%. Referring to Figure 5A, length L1 is the length of the bottom surface of the thermosensitive contact portion 188 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Length L2 is the length of the bottom surface of the thermosensitive contact portion 188 that is in contact with the thermosensitive diode 183 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L2 to length L1 may be 10% to 40%. In this example, the temperature-sensitive diode 183 is in contact with the bottom surface of the temperature-sensitive contact portion 188a from the bottom corner portion 1880a to 25% of the bottom surface of the temperature-sensitive contact portion 188. That is, the ratio of length L2 to length L1 in this example is 25%.

[0142] In the above explanation, the bottom surface, bottom corner 1880a, and bottom corner 1880b of the temperature-sensitive contact portion 188a that is in contact with the temperature-sensitive cathode region 181 were used as examples, but the same may apply to the temperature-sensitive contact portion 188b that is in contact with the temperature-sensitive anode region 182. That is, the bottom corner 1880 of the temperature-sensitive contact portion 188b may be in contact with the temperature-sensitive diode 183, the bottom surface of the temperature-sensitive contact portion 188b may be in contact with the housing portion 198, the bottom surface of the temperature-sensitive contact portion 188b may be in contact with both the temperature-sensitive diode 183 and the housing portion 198, and the temperature-sensitive diode 183 may be in contact with the bottom surface of the temperature-sensitive contact portion 188b from the bottom corner 1880 to an area of ​​10% to 40% of the bottom surface of the temperature-sensitive contact portion 188b. Furthermore, the lengths L1 and L2 of the temperature-sensitive contact portion 188b may be the same as those of the temperature-sensitive contact portion 188a.

[0143] In this example, the temperature-sensitive contact portion 188 is provided with its bottom corner portion 1880 in contact with the temperature-sensitive diode 183 and its bottom surface in contact with the housing portion 198. This ensures reliable electrical connection between the anode pad 116 and cathode pad 118 and the temperature-sensitive diode 183. If the plug portion 1884 and barrier metal film 1882 near the center of the bottom surface of the temperature-sensitive contact portion 188 are removed by over-etching during the etch-back process of the plug portion 1884, a void may form inside the temperature-sensitive contact portion 188. Even in that case, the electrical connection can be ensured by the barrier metal film 1882 and / or plug portion 1884 remaining on the bottom corner portion 1880 of the temperature-sensitive contact portion 188. The barrier metal film 1882 and plug portion 1884 will be described later.

[0144] In this example, the temperature-sensing contact portion 188 is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the area near the center of the bottom surface of the temperature-sensing contact portion, the impact on the electrical connection between the temperature-sensing contact portion 188 and the temperature-sensing diode 183 at the bottom corner portion 1880 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the temperature-sensing portion 180 ensures the electrical connection between the temperature-sensing contact portion 188 and the temperature-sensing diode 183 at the bottom corner portion 1880, rather than at the center of the bottom surface of the temperature-sensing contact portion 188. As a result, even if a void is formed in the area near the center of the temperature-sensing contact portion 188 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0145] The temperature-sensitive contact portion 188 may have a barrier metal film 1882 and a plug portion 1884. In this example, the barrier metal film 1882 and the plug portion 1884 are formed of different materials, but they may be formed of the same material.

[0146] The barrier metal film 1882 may be provided on the bottom corner portion 1880 of the temperature-sensitive contact portion 188. In this example, the barrier metal film 1882 is provided over the entire side and bottom surface of the temperature-sensitive contact portion 188, but is not limited thereto. The barrier metal film 1882 may be provided covering at least the bottom corner portion 1880, and may not cover the central part of the bottom surface of the temperature-sensitive contact portion 188. The barrier metal film 1882 may extend beyond the contact hole 58 and be provided above the first interlayer insulating film 36. The material of the barrier metal film 1882 may be titanium or a titanium compound, etc.

[0147] The plug portion 1884 may be provided in contact with the inside of the barrier metal film 1882. In this example, the plug portion 1884 is provided by filling the temperature-sensitive contact portion 188, but is not limited to this. The plug portion 1884 may be provided in a part of the temperature-sensitive contact portion 188, and may extend beyond the contact hole 58 and above the first interlayer insulating film 36. When the plug portion 1884 is provided in a part of the temperature-sensitive contact portion 188, the remaining area of ​​the temperature-sensitive contact portion 188 may be filled with the same material as the anode wiring portion 117 or the cathode wiring portion 119. The material of the plug portion 1884 may be a plug metal such as tungsten.

[0148] The side surface of the temperature-sensitive diode 183 may be in contact with the side surface of the housing portion 198. In this example, the temperature-sensitive cathode region 181 and the temperature-sensitive anode region 182 of the temperature-sensitive diode 183 are in contact with the side surface of the housing portion 198.

[0149] The upper surface of the second interlayer insulating film 37 may be in contact with the lower surface of the temperature-sensitive diode 183 and the lower surface of the housing portion 198. In this example, the upper surface of the second interlayer insulating film 37 is in contact with the lower surface of the housing portion 198 which is in contact with the temperature-sensitive cathode region 181, the lower surface of the temperature-sensitive cathode region 181, the lower surface of the temperature-sensitive anode region 182, and the lower surface of the housing portion 198 which is in contact with the temperature-sensitive anode region 182.

[0150] The housing portion 198 may be a region of the first interlayer insulating film 36 located below the temperature-sensitive contact portion 188. The housing portion 198 may be formed in the process of providing the first interlayer insulating film 36, and may be formed from the same material as the first interlayer insulating film 36. When the housing portion 198 is formed as a region of the first interlayer insulating film 36 located below the temperature-sensitive contact portion 188, the housing portion 198 is a virtual region, as shown by the dotted line in Figure 5A. That is, the housing portion 198 may be formed integrally as part of the first interlayer insulating film 36.

[0151] Figure 5B shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the temperature sensing section 180. The semiconductor device 100 in this example differs from the embodiment in Figure 5A in that the shapes of the first interlayer insulating film 36 and the second interlayer insulating film 37 are different. In this example, the differences from the embodiment in Figure 5A will be explained in particular, and other aspects may be the same as those of the embodiment in Figure 5A.

[0152] The second interlayer insulating film 37 may have a recess 200 on its upper surface. The temperature-sensing diode 183 may be provided in the recess 200 of the second interlayer insulating film 37. The recess 200 may be formed by etching the upper surface of the second interlayer insulating film 37. In this example, the upper surface of the temperature-sensing diode 183 may be the same as the upper surface of the recess 200, or it may be lower than the upper surface of the recess 200.

[0153] The housing portion 198 may be a second interlayer insulating film 37 provided above the semiconductor substrate 10. The housing portion 198 may be formed in the process of providing the second interlayer insulating film 37, and may be formed from the same material as the second interlayer insulating film 37. When the housing portion 198 is formed as the second interlayer insulating film 37, the housing portion 198 is a virtual region, as shown by the dotted line in Figure 5B. That is, the housing portion 198 may be formed integrally as part of the second interlayer insulating film 37. Note that if the upper surface of the temperature-sensitive diode 183 is above the upper surface of the recess 200, the lower end of the temperature-sensitive contact portion 188 does not reach the second interlayer insulating film 37, but is located in the first interlayer insulating film 36. The housing portion 198 may be considered as part of the first interlayer insulating film 36, or it may be considered to consist of both the first interlayer insulating film 36 and the second interlayer insulating film 37. Furthermore, even if the portion of the second interlayer insulating film 37 that does not have a recess 200 is narrow, and the lower end of the temperature-sensitive contact portion 188 is located at the boundary between the first interlayer insulating film 36 and the second interlayer insulating film 37, the housing portion 198 may be considered as part of the second interlayer insulating film 37, or it may be considered to consist of both the first interlayer insulating film 36 and the second interlayer insulating film 37.

[0154] Figure 5C shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the temperature sensing portion 180. The semiconductor device 100 in this example differs from the embodiments in Figures 5A and 5B in that a housing portion 198 is provided separately from the first interlayer insulating film 36 and the second interlayer insulating film 37. In this example, the differences from the embodiments in Figures 5A and 5B will be explained in particular, and other aspects may be the same as those in Figures 5A and / or 5B. The housing portion 198 in this example is provided in the region of the first interlayer insulating film 36 corresponding to the housing portion 198 in Figure 5A, but it may also be provided in the region of the second interlayer insulating film 37 corresponding to the housing portion 198 in Figure 5B.

[0155] The housing portion 198 may have a polysilicon of a different conductivity type than the contact region 300 of the temperature-sensitive diode 183. The contact region 300 of the temperature-sensitive diode 183 may be the temperature-sensitive cathode region 181 or the temperature-sensitive anode region 182 of the temperature-sensitive diode 183 in contact with the housing portion 198.

[0156] In this example, the housing portion 198a is in contact with the temperature-sensitive cathode region 181. Therefore, the housing portion 198a may have a different conductivity type of polysilicon than the temperature-sensitive cathode region 181, which is the contact region 300 of the temperature-sensitive diode 183. That is, the housing portion 198a may have P-type polysilicon or undoped polysilicon.

[0157] In this example, the housing portion 198b is in contact with the temperature-sensitive anode region 182. Therefore, the housing portion 198b may have a different conductivity type of polysilicon than the temperature-sensitive anode region 182, which is the contact region 300 of the temperature-sensitive diode 183. That is, the housing portion 198b may have N-type polysilicon or undoped polysilicon.

[0158] In this example, the temperature-sensing contact portion 188 has a bottom corner portion 1880 that contacts the temperature-sensing diode 183. In this example, the temperature-sensing contact portion 188 is provided with its bottom surface in contact with the housing portion 198. The contact area 300 between the housing portion 198 and the housing portion 198 of the temperature-sensing diode 183 may have the same potential.

[0159] When the housing portion 198 and the contact region 300 of the thermosensitive diode 183 are at the same potential, no current flows between the housing portion 198 and the thermosensitive diode 183, and the operation of the thermosensitive diode 183 is not affected by the housing portion 198. For example, when the housing portion 198a has P-type polysilicon, which has a different conductivity type than the thermosensitive cathode region 181, the housing portion 198a and the thermosensitive cathode region 181 are at the same potential, so virtually no current flows through the PN junction at the contact interface. Therefore, the operation of the thermosensitive diode 183 is not affected by the housing portion 198. Similarly, even when the housing portion 198b has N-type polysilicon, which has a different conductivity type than the thermosensitive anode region 182, the housing portion 198b and the thermosensitive anode region 182 are at the same potential, so the PN junction at the contact interface does not function and does not hinder the operation of the thermosensitive diode 183.

[0160] The housing portion 198 may have the same conductivity type as the contact region 300 of the temperature-sensitive diode 183, and may have a polysilicon with a lower doping concentration than the contact region 300. In this example, the housing portion 198a is in contact with the temperature-sensitive cathode region 181. Therefore, the housing portion 198a may have the same conductivity type as the temperature-sensitive cathode region 181, which is the contact region 300 of the temperature-sensitive diode 183, and may have a polysilicon with a lower doping concentration than the temperature-sensitive cathode region 181. That is, the housing portion 198a may have N-type polysilicon. In this example, the housing portion 198b is in contact with the temperature-sensitive anode region 182. Therefore, the housing portion 198b may have the same conductivity type as the temperature-sensitive anode region 182, which is the contact region 300 of the temperature-sensitive diode 183, and may have a polysilicon with a lower doping concentration than the temperature-sensitive anode region 182. That is, the housing portion 198b may have P-type polysilicon.

[0161] Even if the housing portion 198 has the same conductivity type as the contact area 300 of the temperature-sensing diode 183, the doping concentration of the housing portion 198 is lower than that of the contact area 300, so it has little effect on the operation of the temperature-sensing diode 183. Therefore, the housing portion 198 is unlikely to interfere with the operation of the temperature-sensing diode 183.

[0162] As described above, the housing portion 198a in contact with the temperature-sensitive cathode region 181 of the temperature-sensitive diode 183 may have P-type, undoped, or N-type polysilicon, and the housing portion 198b in contact with the temperature-sensitive anode region 182 of the temperature-sensitive diode 183 may have N-type, undoped, or P-type polysilicon. In the case of a narrow polysilicon width, a portion of the lower end of the temperature-sensitive contact portion 188 may overlap the interlayer insulating film 38. In this case, the housing portion 198 can be considered to consist of a mixture of polysilicon and the first interlayer insulating film 36 and / or the second interlayer insulating film 37.

[0163] Figure 5D shows an example of an enlarged cross-sectional view of the semiconductor device 100 when a void 302 occurs in the temperature-sensitive contact portion 188. This example shows a case where the plug portion 1884 near the center of the bottom surface of the temperature-sensitive contact portion 1884 is removed by over-etching during the etch-back process of the plug portion 1884. In this case, it is difficult to fill the temperature-sensitive contact portion 188 with the metal material of the anode wiring portion 117 or cathode wiring portion 119, and a void 302 may occur near the center of the bottom surface of the temperature-sensitive contact portion 188.

[0164] In this example, the temperature-sensing contact portion 188 is provided with its bottom corner portion 1880 in contact with the temperature-sensing diode 183 and its bottom surface in contact with the housing portion 198. Therefore, even if a void 302 is formed inside near the center of the bottom surface of the temperature-sensing contact portion, the impact on the electrical connection between the temperature-sensing contact portion 188 and the temperature-sensing diode 183 at the bottom corner portion 1880 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the temperature-sensing portion 180 ensures the electrical connection between the temperature-sensing contact portion 188 and the temperature-sensing diode 183 at the bottom corner portion 1880, rather than at the center of the bottom surface of the temperature-sensing contact portion 188. As a result, even if a void 302 is formed in the area near the center of the temperature-sensing contact portion 188 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0165] Figure 5E shows another example of an enlarged cross-sectional view of the semiconductor device 100 when a void 302 occurs in the temperature-sensitive contact portion 188. This example shows a case where, during the etch-back process of the plug portion 1884, the plug portion 1884 and barrier metal film 1882 near the center of the bottom surface of the temperature-sensitive contact portion 188 are removed by over-etching, and further over-etching extends to the housing portion 198. In this case, it is difficult to fill the temperature-sensitive contact portion 188 with the metal material of the anode wiring portion 117 or cathode wiring portion 119, and a void 302 may occur near the center of the bottom surface of the temperature-sensitive contact portion 188.

[0166] In this example, the temperature sensing portion 180 ensures that the electrical connection between the temperature sensing contact portion 188 and the temperature sensing diode 183 is made at the bottom corner portion 1880 rather than at the bottom center portion of the temperature sensing contact portion 188. As a result, even if a void 302 is formed in the area near the center of the temperature sensing contact portion 188 that is in contact with the housing portion 198, as in the example of Figure 5D, stable quality can be obtained and yield can be improved.

[0167] Figure 6 shows a cross-section of a modified semiconductor device 100 equipped with a temperature-sensing portion 180. The semiconductor device 100 in this example differs from the embodiment in Figure 4 in that the temperature-sensing contact portion 188 and the active contact portion 124 have a trench contact structure. Other aspects may be the same as those of the embodiment in Figure 4. If the temperature-sensing contact portion 188 has a trench contact structure, the temperature-sensing contact portion 188 may extend from the upper surface of the temperature-sensing diode 183 in the depth direction of the semiconductor substrate 10. If the active contact portion 124 has a trench contact structure, the active contact portion 124 may extend from the front surface 21 in the depth direction of the semiconductor substrate 10. The bottom surface of the active contact portion 124 may be shallower or deeper than the lower end of the emitter region in the depth direction of the semiconductor substrate 10.

[0168] Figure 7A shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the temperature-sensing portion 180. The semiconductor device 100 in this example differs from the embodiment in Figure 5A in that the structure of the temperature-sensing contact portion 188 is different. In this example, the differences from the embodiment in Figure 5A will be explained in particular, and other aspects may be the same as those of the embodiment in Figure 5A.

[0169] The side wall of the temperature-sensing contact portion 188 may have a trench contact structure that contacts the side surface of the temperature-sensing diode 183. In this example, the bottom corner portion 1880 of the temperature-sensing contact portion 188 contacts the temperature-sensing diode 183 at its side surface.

[0170] The sidewall of the temperature-sensitive contact portion 188 may be in contact with the temperature-sensitive diode 183 and the first interlayer insulating film 36. The temperature-sensitive diode 183 may be in contact with the sidewall of the temperature-sensitive contact portion 188 from the bottom corner portion 1880 to an area of ​​10% to 90% of the sidewall of the temperature-sensitive contact portion. That is, the ratio of the area of ​​the sidewall of the temperature-sensitive contact portion 188 that is in contact with the temperature-sensitive diode 183 to the area of ​​the sidewall of the temperature-sensitive contact portion 188 that is in contact with the temperature-sensitive diode 183 may be 10% to 90%. Referring to Figure 7A, length L3 is the length of the sidewall of the temperature-sensitive contact portion 188 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10, and length L4 is the length of the sidewall of the temperature-sensitive contact portion 188 that is in contact with the temperature-sensitive diode 183 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L4 to length L3 may be between 10% and 90%. In this example, the temperature-sensitive diode 183 is in contact with the side wall of the temperature-sensitive contact portion 188 from the bottom corner portion 1880 to 36% of the side wall of the temperature-sensitive contact portion 188. That is, the ratio of length L4 to length L3 in this example is 36%.

[0171] Figure 7B shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the temperature sensing portion 180. The semiconductor device 100 in this example differs from the embodiment in Figure 7A in that the housing portion 198 is a second interlayer insulating film 37 provided above the semiconductor substrate 10. Other aspects may be the same as those of the embodiment in Figure 7A.

[0172] Figure 7C shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the temperature sensing portion 180. The semiconductor device 100 in this example differs from the embodiments in Figures 7A and 7B in that the housing portion 198 has polysilicon. Otherwise, it may be the same as the embodiments in Figures 7A and / or 7B.

[0173] Figure 7D shows an example of an enlarged cross-sectional view of the semiconductor device 100 when a void 302 occurs in the temperature-sensitive contact portion 188. This example shows a case where the plug portion 1884 near the center of the bottom surface of the temperature-sensitive contact portion 1884 is removed by over-etching during the etch-back process of the plug portion 1884. In this case, it is difficult to fill the temperature-sensitive contact portion 188 with the metal material of the anode wiring portion 117 or cathode wiring portion 119, and a void 302 may occur near the center of the bottom surface of the temperature-sensitive contact portion 188.

[0174] In this example, the temperature-sensing contact portion 188 is provided with its bottom corner portion 1880 in contact with the temperature-sensing diode 183 and its bottom surface in contact with the housing portion 198. Therefore, even if a void 302 is formed inside near the center of the bottom surface of the temperature-sensing contact portion, the impact on the electrical connection between the temperature-sensing contact portion 188 and the temperature-sensing diode 183 at the bottom corner portion 1880 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the temperature-sensing portion 180 ensures the electrical connection between the temperature-sensing contact portion 188 and the temperature-sensing diode 183 at the bottom corner portion 1880, rather than at the center of the bottom surface of the temperature-sensing contact portion 188. As a result, even if a void 302 is formed in the area near the center of the temperature-sensing contact portion 188 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0175] Figure 7E shows another example of an enlarged cross-sectional view of the semiconductor device 100 when a void 302 occurs in the temperature-sensitive contact portion 188. This example shows a case where, during the etch-back process of the plug portion 1884, the plug portion 1884 and barrier metal film 1882 near the center of the bottom surface of the temperature-sensitive contact portion 188 are removed by over-etching, and further over-etching extends to the housing portion 198. In this case, it is difficult to fill the temperature-sensitive contact portion 188 with the metal material of the anode wiring portion 117 or cathode wiring portion 119, and a void 302 may occur near the center of the bottom surface of the temperature-sensitive contact portion 188.

[0176] In this example, the temperature sensing portion 180 ensures that the electrical connection between the temperature sensing contact portion 188 and the temperature sensing diode 183 is made at the bottom corner portion 1880 rather than at the bottom center portion of the temperature sensing contact portion 188. As a result, even if a void 302 is formed in the area near the center of the temperature sensing contact portion 188 that is in contact with the housing portion 198, similar to the example in Figure 7D, stable quality can be obtained and yield can be improved.

[0177] Figure 8 is a flowchart showing an example of the manufacturing process for a semiconductor device 100. The manufacturing process in this example includes a step S100 for forming an active portion 120 on a semiconductor substrate 10, and a step S110 for forming a temperature-sensing portion 180 above the semiconductor substrate 10. The order of the steps for forming the active portion 120 (S100) and forming the temperature-sensing portion 180 (S110) is not limited to this. The temperature-sensing portion 180 may be formed before the active portion 120, and a part of the step for forming the active portion 120 and a part of the step for forming the temperature-sensing portion 180 may be the same step.

[0178] Step S110 for forming the temperature-sensing portion 180 includes step S114 for forming the temperature-sensing diode 183, step S116 for forming the first interlayer insulating film 36, step S118 for forming the temperature-sensing contact portion 188, and step S120 for forming the housing portion 198. Step S110 for forming the temperature-sensing portion 180 may include step S112 for forming the second interlayer insulating film 37.

[0179] In step S112, a second interlayer insulating film 37 is formed on top of the semiconductor substrate 10. The second interlayer insulating film 37 may be formed by stacking multiple insulating films. If the semiconductor device 100 does not have a second interlayer insulating film 37, step S112 may be omitted. If the insulating film (thermal oxide film, HTO, etc.) formed in step S100 is used as the second interlayer insulating film 37, step S112 may be omitted.

[0180] In step S114, a thermosensitive diode 183 is formed on top of the semiconductor substrate 10. The thermosensitive diode 183 may be formed by a method that is common to those skilled in the art. For example, the thermosensitive diode 183 may be formed by depositing undoped polysilicon on top of the semiconductor substrate 10, then implanting impurity ions and performing an annealing treatment.

[0181] Step S114 for forming the temperature-sensitive diode 183 may include a step of etching the second interlayer insulating film 37 to form a depression. In this case, as shown in the embodiment of Figure 5B or Figure 7B, the temperature-sensitive diode 183 may be provided in the depression of the second interlayer insulating film 37.

[0182] In step S116, a first interlayer insulating film 36 is formed above the temperature-sensitive diode. The first interlayer insulating film 36 may be formed by stacking multiple insulating films. Step S116, in which the first interlayer insulating film 36 is formed, may be a step in which an interlayer insulating film 38 is formed on the active part 120. However, the first interlayer insulating film 36 and the interlayer insulating film 38 of the active part 120 may be formed by different processes.

[0183] In step S118, a temperature-sensitive contact portion 188 is formed extending from the upper surface to the lower surface of the first interlayer insulating film 36. The step S118 in which the temperature-sensitive contact portion 188 is formed may be the step in the active portion 120 in which an active contact portion 124 is formed extending from the upper surface to the lower surface of the interlayer insulating film 38. However, the temperature-sensitive contact portion 188 and the active contact portion 124 may be formed in different processes.

[0184] Step S118 for forming the temperature-sensitive contact portion 188 may include a step of forming contact holes 58 by etching the first interlayer insulating film 36. In this step, contact holes 54, 55, and 56 may be formed in the interlayer insulating film 38. However, the contact holes 58 of the temperature-sensitive contact portion 188 and the contact holes 54, 55, and 56 may be formed in different steps. Also, in step S116 for forming the first interlayer insulating film 36, the first interlayer insulating film 36 may be formed so as to have contact holes 58.

[0185] Step S118, which forms the temperature-sensitive contact portion 188, may include a step of forming a barrier metal film 1882. The barrier metal film 1882 may be formed by forming a metal film inside the contact hole 58 and then annealing it in a nitrogen atmosphere. For example, the barrier metal film 1882 may be formed by forming a Ti film inside the contact hole 58 and then annealing it in a nitrogen atmosphere. In this case, a TiN film may be formed by annealing the Ti film. In this step, the barrier metal film may be formed on the active contact portion 124.

[0186] Step S118, which involves forming the temperature-sensitive contact portion 188, may include a step of forming the plug portion 1884. For example, the plug portion 1884 may be formed by forming tungsten to fill the inside of the contact hole 58 using the CVD (Chemical Vapor Deposition) method. In this step, the plug portion may be formed on the active contact portion 124.

[0187] Step S118, in which the temperature-sensitive contact portion 188 is formed, may include a step of etching back the plug portion 1884. This may remove any unwanted tungsten film outside the contact hole 58. However, the plug portion 1884 may be provided on a part of the temperature-sensitive contact portion 188, and may extend beyond the contact hole 58 and above the first interlayer insulating film 36. Etching back may be performed by dry etching or CMP (Chemical Mechanical Polishing). When the tungsten film is removed, the barrier metal film 1882 may also be removed. The barrier metal film 1882 may be removed in a separate process from the etching back of the plug portion 1884. In this process, the plug portion of the active contact portion 124 may be etched back.

[0188] If the barrier metal film 1882 and plug portion 1884 are not provided in the temperature-sensitive contact portion 188, the above steps may be omitted. In this case, the inside of the contact hole 58 may be filled and the temperature-sensitive contact portion 188 formed at the same time as the step of providing the anode wiring portion 117 and cathode wiring portion 119.

[0189] In step S118, the temperature-sensitive contact portion 188 may be formed such that the bottom corner portion 1880 of the temperature-sensitive contact portion 188 is in contact with the temperature-sensitive diode 183. In step S118, the temperature-sensitive contact portion 188 may be formed such that the bottom surface of the temperature-sensitive contact portion 188 is in contact with the housing portion 198.

[0190] In this example, the bottom corner portion 1880 of the temperature-sensing contact portion 188 is in contact with the temperature-sensing diode 183, and the bottom surface is in contact with the housing portion 198, thereby ensuring reliable electrical connection between the anode pad 116 and cathode pad 118 and the temperature-sensing diode 183. In this example, since the bottom surface of the temperature-sensing contact portion 188 is in contact with the housing portion 198, even if the plug portion 1884 and barrier metal film 1882 near the center of the bottom surface of the temperature-sensing contact portion 1884 are removed by over-etching during the etch-back process of the plug portion 1884, and a void is created inside the temperature-sensing contact portion 188, the impact on the electrical connection at the bottom corner portion 1880 between the temperature-sensing contact portion 188 and the temperature-sensing diode 183 can be suppressed, thereby improving the yield of semiconductor device 100 having the desired characteristics. In other words, by ensuring the electrical connection between the temperature-sensitive contact portion 188 and the temperature-sensitive diode 183 through the bottom corner portion 1880 rather than the bottom center portion of the temperature-sensitive contact portion 188, stable quality can be obtained and yield can be improved even if a void is formed in the area near the center of the temperature-sensitive contact portion 188 that is in contact with the housing portion 198.

[0191] In step S120, a housing portion 198 is formed below the temperature-sensitive contact portion 188. The order of steps S120 for forming the housing portion 198 is not limited thereto. Step S120 for forming the housing portion 198 may be included in step S112 for forming the second interlayer insulating film 37, in step S114 for forming the temperature-sensitive diode 183, or in step S116 for forming the first interlayer insulating film 36.

[0192] As an example, in the embodiment shown in Figure 5A or Figure 7A, the housing portion 198 is a region of the first interlayer insulating film 36 located below the temperature-sensitive contact portion 188. In this case, the step S120 for forming the housing portion 198 may be included in the step S116 for forming the first interlayer insulating film 36.

[0193] As another example, in the embodiment shown in Figure 5B or Figure 7B, the housing portion 198 is a second interlayer insulating film 37 provided above the semiconductor substrate 10. In this case, the step S120 for forming the housing portion 198 may be included in the step S112 for forming the second interlayer insulating film 37.

[0194] As another example, in the embodiment shown in Figure 5C or Figure 7C, the housing portion 198b has polysilicon. In this case, step S120 for forming the housing portion 198 may be included in step S114 for forming the thermosensing diode 183. The thermosensing diode 183 and the housing portion 198 may be formed by laminating undoped polysilicon in the regions that will become the housing portion 198 and the thermosensing diode 183, implanting impurity ions of the conductivity type corresponding to each region, and performing an annealing treatment. Alternatively, they may be formed by laminating high-concentration N-type or P-type polysilicon in the regions that will become the housing portion 198 and the thermosensing diode 183, and implanting impurity ions into regions having other conductivity types to reverse the conductivity type.

[0195] In the above explanation, the connection between the temperature-sensitive contact portion 188 and the temperature-sensitive diode 183 was used as an example, but the same may apply to contact portions provided in other contact holes. For example, the bottom corner of the contact portion that electrically connects the polysilicon of the connection portion 25 to the gate metal layer 50 may be provided so as to be in contact with the polysilicon. In these cases as well, electrical connection at each contact portion can be ensured. These cases will be described later.

[0196] Figure 9 shows an example of the electrical connections of each part of the semiconductor device 100 shown in Figure 3. In this example, a Zener diode section 170 is provided in antiparallel for voltage withstand protection between the cathode pad 118 and the anode pad 116. The Zener diode section 170 may have the same configuration as the temperature-sensing diode 183. In this case, the forward voltage of the Zener diode section 170 may be different from the forward voltage of the temperature-sensing diode 183. If the temperature-sensing diode 183 consists of a series connection of multiple temperature-sensing cathode regions 181 and temperature-sensing anode regions 182, the Zener diode section 170 may be provided between the temperature-sensing cathode region 181 and the temperature-sensing anode region 182. Also, if a Zener diode section 170 is provided between the temperature-sensing section 180 and the active section 120 for electric field protection, the Zener diode section 170 may have the same configuration as the temperature-sensing diode 183. In this case, the breakdown voltage of the Zener diode section 170 may be different from the breakdown voltage of the temperature-sensing diode 183. The Zener diode section 170 may be configured with multiple sections connected in series. In other examples, the Zener diode section 170 may be connected at different positions, or the Zener diode section 170 may not be provided at all.

[0197] Figure 10A shows an example of an enlarged view of the top surface of the semiconductor device 100. The semiconductor device 100 in this example differs from the embodiment in Figure 1A in that a connection portion 25 is provided between the emitter electrode 52 and the dummy conductive portion 34. In this example, the differences from the embodiment in Figure 1A will be explained in particular, and other aspects may be the same as those of the embodiment in Figure 1A. Similar to the embodiment in Figure 1A, the configuration in this figure may be repeatedly provided in the positive and negative directions of the X axis.

[0198] The semiconductor device 100 comprises an active portion 120, which is the main current-flowing portion between the front surface 21 and the back surface 23 of the semiconductor substrate 10, and an inactive portion 130, which is the other portion. For example, the boundary between the active portion 120 and the inactive portion 130 is the boundary between the base region 14 and the well region 17.

[0199] An interlayer insulating film 38 is provided above the active portion 120 and the inactive portion 130, but the interlayer insulating film 38 is omitted in Figure 10A. Contact holes 54, 55, and 56 are provided through the interlayer insulating film 38.

[0200] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive part 44 in the transistor part 70 via the connecting part 25. The contact hole 56 electrically connects the emitter electrode 52 and the dummy conductive part 34 in the dummy trench part 30 via the connecting part 25. The connecting part 25 is a conductive material such as polysilicon doped with impurities. In this example, the connecting part 25 is polysilicon (N+) doped with N-type impurities. Polysilicon is an example of a polycrystalline semiconductor. The connecting part 25 is an example of a polycrystalline part 132 provided above the semiconductor substrate 10. The connecting part 25 is an example of a polycrystalline part 132 in the inactive part 130.

[0201] Figure 10B shows an example of a c-c' cross-section in Figure 9. The semiconductor device 100 in this example differs from the embodiment in Figure 1B in that the active contact portion 124 has a trench shape. Otherwise, it may be the same as the embodiment in Figure 1B.

[0202] Figure 11 shows an example of a d-d' cross-section in Figure 9. The d-d' cross-section is the YZ plane passing through the contact hole 56 in the inactive portion 130. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a collector electrode 24, and a first inactive contact portion 134 in the d-d' cross-section. In this example, a contact hole 56 having its longitudinal direction in the X-axis direction is used as an example, but the longitudinal direction of the contact hole 56 may be along the Y-axis direction or in other directions.

[0203] The polycrystalline portion 132 is provided above the semiconductor substrate. In this example, the polycrystalline portion 132 is the connecting portion 25. The polycrystalline portion 132 may be provided above the third interlayer insulating film 138. The third interlayer insulating film 138 may be made of the same material as, for example, the dummy insulating film 32. The third interlayer insulating film 138 may be a thermal oxide film. In other examples, the third interlayer insulating film 138 may be made of a different material than the dummy insulating film 32. The interlayer insulating film 38 is provided above the polycrystalline portion 132.

[0204] The first inactive contact portion 134 is provided extending from the upper surface to the lower surface of the interlayer insulating film 38. The contact hole 56 may be provided penetrating the interlayer insulating film 38. The first inactive contact portion 134 may have a contact hole 56 and a metal layer filled inside the contact hole 56. The detailed configuration of the first inactive contact portion 134 will be described later. The housing portion 198 is provided below the first inactive contact portion 134.

[0205] The polycrystalline portion 132 may be connected to the emitter electrode 52 via the first inactive contact portion 134. The polycrystalline portion 132 may also be connected to the dummy conductive portion 34. In this example, the connection portion 25 is connected to the emitter electrode 52 via the first inactive contact portion 134 and is also connected to the dummy conductive portion 34.

[0206] Figure 12A shows an example of an enlarged view of the d-d' cross section in Figure 9. This figure shows the region of the inactive part 130 above the front surface 21 of the semiconductor substrate 10.

[0207] The bottom corner portion 1340 of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132. The bottom corner portion 1340 of the first inactive contact portion 134 may be the intersection of the bottom surface of the first inactive contact portion 134 and the side surface of the first inactive contact portion 134. Contact between the bottom corner portion 1340 and the polycrystalline portion 132 may mean contact with the polycrystalline portion 132 on its upper surface, contact with the polycrystalline portion 132 on its side surface, or contact with the polycrystalline portion 132 in an internal region of the polycrystalline portion 132. In this example, the bottom corner portion 1340 is in contact with the polycrystalline portion 132 on its upper surface.

[0208] The first inactive contact portion 134 in this example has two bottom corner portions 1340. One of the two bottom corner portions 1340 may be in contact with the polycrystalline portion 132. The other of the two bottom corner portions 1340 may or may not be in contact with the housing portion 198. In this example, one bottom corner portion 1340a of the first inactive contact portion 1340 is in contact with the polycrystalline portion 132, and the other bottom corner portion 1340b is in contact with the housing portion 198.

[0209] The bottom surface of the first inactive contact portion 134 may be in contact with the housing portion 198. The bottom surface of the first inactive contact portion 134 may be the surface between the two bottom corner portions 1340 of the first inactive contact portion 134. When the bottom surface of the first inactive contact portion 134 is in contact with the housing portion 198, it may be that the bottom surface is in contact with the housing portion 198 on the upper surface of the housing portion 198, or it may be that the bottom surface is in contact with the housing portion 198 in an area inside the housing portion 198. In this example, the bottom surface of the first inactive contact portion 134 is in contact with the housing portion 198 on the upper surface of the housing portion 198.

[0210] In this example, the first inactive contact portion 134 is provided with its bottom corner portion 1340 in contact with the polycrystalline portion 132 and its bottom surface in contact with the housing portion 198. This ensures reliable electrical connection between the emitter electrode 52 and the polycrystalline portion 132. If the plug portion 1344 and the barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are removed by over-etching during the etch-back process of the plug portion 1344, a void may form inside the first inactive contact portion 134. Even in that case, the electrical connection can be ensured by the barrier metal film 1342 and / or plug portion 1344 remaining on the bottom corner portion 1340 of the first inactive contact portion 134. The barrier metal film 1342 and plug portion 1344 will be described later.

[0211] In this example, the first inactive contact portion 134 is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the first inactive contact portion 134 near the center of its bottom surface, the impact on the electrical connection at the bottom corner portion 1340 between the first inactive contact portion 134 and the polycrystalline portion 132 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the inactive portion 130 ensures the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corner portion 1340 rather than the center of the bottom surface of the first inactive contact portion 134. As a result, even if a void is formed in the region near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0212] The bottom surface of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132 and the housing portion 198. In this example, the bottom surface of the first inactive contact portion 134 is in contact with the polycrystalline portion 132 and the housing portion 198, as one bottom corner 1340a is in contact with the polycrystalline portion 132 and the other bottom corner 1340b is in contact with the housing portion 198.

[0213] The polycrystalline portion 132 may be in contact with the bottom surface of the first inactive contact portion 134 from the bottom surface corner 1340 to an area of ​​10% to 40% of the bottom surface of the first inactive contact portion 134. That is, the ratio of the area of ​​the bottom surface of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 to the area of ​​the bottom surface of the first inactive contact portion 134 may be 10% to 40%. Referring to Figure 12A, length L1 is the length of the bottom surface of the first inactive contact portion 134 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Length L2 is the length of the bottom surface of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L2 to length L1 may be 10% to 40%. In this example, the polycrystalline portion 132 is in contact with the bottom surface of the first inactive contact portion 134 from the bottom surface corner 1340a to 20% of the area of ​​the bottom surface of the first inactive contact portion 134. That is, the ratio of length L2 to length L1 in this example is 20%.

[0214] The first inactive contact portion 134 may have a barrier metal film 1342 and a plug portion 1344. In this example, the barrier metal film 1342 and the plug portion 1344 are formed of different materials, but they may be formed of the same material.

[0215] The barrier metal film 1342 may be provided on the bottom corner portion 1340 of the first inactive contact portion 134. In this example, the barrier metal film 1342 is provided over the entire side and bottom surface of the first inactive contact portion 134, but is not limited thereto. The barrier metal film 1342 may be provided covering at least the bottom corner portion 1340, and may not cover the central part of the bottom surface of the first inactive contact portion 134. The barrier metal film 1342 may extend beyond the contact hole 56 and be provided above the interlayer insulating film 38. The material of the barrier metal film 1342 may be titanium or a titanium compound, etc.

[0216] The plug portion 1344 may be provided in contact with the inside of the barrier metal film 1342. In this example, the plug portion 1344 is provided by filling the first inactive contact portion 134, but is not limited to this. The plug portion 1344 may be provided in a part of the first inactive contact portion 134, and may extend beyond the contact hole 56 and above the interlayer insulating film 38. When the plug portion 1344 is provided in a part of the first inactive contact portion 134, the remaining area of ​​the first inactive contact portion 134 may be filled with the same material as the emitter electrode 52. The material of the plug portion 1344 may be a plug metal such as tungsten.

[0217] The side surface of the polycrystalline portion 132 may be in contact with the side surface of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 located below the first inactive contact portion 134. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed from the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 located below the first inactive contact portion 134, the housing portion 198 is a virtual region, as shown by the dotted line in Figure 12A. That is, the housing portion 198 may be formed integrally as part of the interlayer insulating film 38. In another example, the housing portion 198 may be a third interlayer insulating film 138 located above the semiconductor substrate 10. The housing portion 198 may be formed in the process of providing the third interlayer insulating film 138 and may be formed from the same material as the third interlayer insulating film 138. In other words, the housing portion 198 may be integrally formed as part of the third interlayer insulating film 138. In this case, the polycrystalline portion 132 may be provided in a recess created by etching the upper surface of the thickly provided third interlayer insulating film 138. In yet another example, the housing portion 198 may be polysilicon with a lower impurity concentration than the polycrystalline portion 132, or undoped polysilicon.

[0218] Figure 12B shows an example of an enlarged view of the d-d' cross-section in Figure 9 when a void 302 occurs in the first inactive contact portion 134. This example shows the case where the plug portion 1344 near the center of the bottom surface of the first inactive contact portion 1344 is removed by over-etching during the etch-back process of the plug portion 1344. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the emitter electrode 52, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0219] In this example, the first inactive contact portion 134 is provided with its bottom corner portion 1340 in contact with the polycrystalline portion 132 and its bottom surface in contact with the housing portion 198. Therefore, even if a void 302 is formed inside the area near the center of the bottom surface of the first inactive contact portion 134, the impact on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corner portion 1340 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the inactive portion 130 ensures the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132, not at the center of the bottom surface of the first inactive contact portion 134, but at the bottom corner portion 1340. As a result, even if a void 302 is formed in the area near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0220] Figure 12C shows another example of an enlarged view of the d-d' cross-section in Figure 9 when a void 302 occurs in the first inactive contact portion 134. This example shows a case where, during the etch-back process of the plug portion 1344, the plug portion 1344 and barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are removed by over-etching, and further over-etching extends to the housing portion 198. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the emitter electrode 52, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0221] In this example, the inactive portion 130 ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132, not through the center of the bottom surface of the first inactive contact portion 134, but through the bottom corner portion 1340. As a result, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, similar to the example in Figure 12B, stable quality can be obtained and yield can be improved.

[0222] Figure 13 shows an example of a d-d' cross-section in Figure 9. The semiconductor device 100 in this example differs from the embodiment in Figure 11 in that the first inactive contact portion 134 has a trench contact structure. Otherwise, it may be the same as the embodiment in Figure 11. When the first inactive contact portion 134 has a trench contact structure, the first inactive contact portion 134 may extend from the upper surface of the polycrystalline portion 132 in the depth direction of the semiconductor substrate 10. The active contact portion 124 may have a planar contact structure as shown in Figure 1B, or a trench contact structure as shown in Figure 10B.

[0223] Figure 14A shows an example of an enlarged view of the d-d' cross section in Figure 9. This figure shows the region of the inactive portion 130 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example differs from the embodiment in Figure 12A in that the structure of the first inactive contact portion 134 is different. In this example, the differences from the embodiment in Figure 12A will be explained in particular, and other aspects may be the same as those of the embodiment in Figure 12A.

[0224] The sidewall of the first inactive contact portion 134 may have a trench contact structure that contacts the side surface of the polycrystalline portion 132. In this example, the bottom corner portion 1340 of the first inactive contact portion 134 contacts the polycrystalline portion 132 at the side surface of the polycrystalline portion 132.

[0225] The sidewall of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132 and the interlayer insulating film 38. The polycrystalline portion 132 may be in contact with the sidewall of the first inactive contact portion 134 from the bottom corner portion 1340 to an area of ​​10% to 90% of the sidewall of the first inactive contact portion 134. That is, the ratio of the area of ​​the sidewall of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 to the area of ​​the sidewall of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 may be 10% to 90%. Referring to Figure 14A, length L3 is the length of the side wall of the first inactive contact portion 134 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10, and length L4 is the length of the side wall of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L4 to length L3 may be 10% or more and 90% or less. In this example, the polycrystalline portion 132 is in contact with the side wall of the first inactive contact portion 134 from the bottom corner portion 1340 to 35% of the side wall of the first inactive contact portion 134. That is, the ratio of length L4 to length L3 in this example is 35%.

[0226] Figure 14B shows an example of an enlarged view of the d-d' cross-section in Figure 9 when a void 302 occurs in the first inactive contact portion 134. This example shows a case where the plug portion 1344 near the center of the bottom surface of the first inactive contact portion 1344 is removed by over-etching during the etch-back process of the plug portion 1344. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the emitter electrode 52, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0227] In this example, the first inactive contact portion 134 is provided with its bottom corner portion 1340 in contact with the polycrystalline portion 132 and its bottom surface in contact with the housing portion 198. Therefore, even if a void 302 is formed inside the area near the center of the bottom surface of the first inactive contact portion 134, the impact on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corner portion 1340 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the inactive portion 130 ensures the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132, not at the center of the bottom surface of the first inactive contact portion 134, but at the bottom corner portion 1340. As a result, even if a void 302 is formed in the area near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0228] Figure 14C shows another example of an enlarged view of the d-d' cross-section in Figure 9 when a void 302 occurs in the first inactive contact portion 134. This example shows a case where, during the etch-back process of the plug portion 1344, the plug portion 1344 and barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are removed by over-etching, and further over-etching extends to the housing portion 198. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the emitter electrode 52, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0229] In this example, the inactive portion 130 ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132, not through the center of the bottom surface of the first inactive contact portion 134, but through the bottom corner portion 1340. As a result, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, similar to the example in Figure 14B, stable quality can be obtained and yield can be improved.

[0230] Figure 15 shows an example of the e-e' cross-section in Figure 9. The e-e' cross-section is the YZ plane passing through the contact hole 55 in the inactive portion 130. The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, a gate metal layer 50, a collector electrode 24, and a first inactive contact portion 134 in the e-e' cross-section.

[0231] The polycrystalline portion 132 is provided above the semiconductor substrate. In this example, the polycrystalline portion 132 is the connecting portion 25. The polycrystalline portion 132 may be provided above the third interlayer insulating film 138. The third interlayer insulating film 138 may be made of the same material as, for example, the gate insulating film 42. The third interlayer insulating film 138 may be a thermal oxide film. In other examples, the third interlayer insulating film 138 may be made of a different material than the gate insulating film 42. The interlayer insulating film 38 is provided above the polycrystalline portion 132.

[0232] The first inactive contact portion 134 is provided extending from the upper surface to the lower surface of the interlayer insulating film 38. The contact hole 55 may be provided penetrating the interlayer insulating film 38. The first inactive contact portion 134 may have a contact hole 55 and a metal layer filled inside the contact hole 55. The housing portion 198 is provided below the first inactive contact portion 134.

[0233] The polycrystalline portion 132 may be connected to the gate metal layer 50 via the first inactive contact portion 134. The polycrystalline portion 132 may also be connected to the gate conductive portion 44. In this example, the connection portion 25 is connected to the gate metal layer 50 via the first inactive contact portion 134 and is connected to the gate conductive portion 44.

[0234] Figure 16A shows an example of an enlarged view of the e-e' cross section in Figure 9. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the inactive portion 130.

[0235] The bottom corner portion 1340 of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132. In this example, the bottom corner portion 1340 is in contact with the polycrystalline portion 132 on its upper surface.

[0236] The bottom surface of the first inactive contact portion 134 may be in contact with the housing portion 198. In this example, the bottom surface of the first inactive contact portion 134 is in contact with the housing portion 198 at the top surface of the housing portion 198.

[0237] In this example, the first inactive contact portion 134 is provided with its bottom corner portion 1340 in contact with the polycrystalline portion 132 and its bottom surface in contact with the housing portion 198. This ensures reliable electrical connection between the gate metal layer 50 and the polycrystalline portion 132. If the plug portion 1344 and barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are removed by over-etching during the etch-back process of the plug portion 1344, a void may form inside the first inactive contact portion 134. Even in that case, the electrical connection can be ensured by the barrier metal film 1342 and / or plug portion 1344 remaining on the bottom corner portion 1340 of the first inactive contact portion 134.

[0238] In this example, the first inactive contact portion 134 is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside near the center of the bottom surface of the temperature-sensitive contact portion, the impact on the electrical connection at the bottom surface corner portion 1340 between the first inactive contact portion 134 and the polycrystalline portion 132 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the inactive portion 130 ensures the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom surface corner portion 1340 rather than the bottom surface center of the first inactive contact portion 134. As a result, even if a void is formed in the region near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0239] The bottom surface of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132 and the housing portion 198. In this example, the bottom surface of the first inactive contact portion 134 is in contact with the polycrystalline portion 132 and the housing portion 198, as one bottom corner 1340a is in contact with the polycrystalline portion 132 and the other bottom corner 1340b is in contact with the housing portion 198.

[0240] The polycrystalline portion 132 may be in contact with the bottom surface of the first inactive contact portion 134 from the bottom surface corner 1340 to a region of 10% to 40% of the bottom surface of the first inactive contact portion 134. In this example, the polycrystalline portion 132 is in contact with the bottom surface of the first inactive contact portion 134 from the bottom surface corner 1340a to a region of 20% of the bottom surface of the first inactive contact portion 134. That is, the ratio of length L2 to length L1 in this example is 20%.

[0241] The barrier metal film 1342 may be provided on the bottom corner portion 1340 of the first inactive contact portion 134. In this example, the barrier metal film 1342 is provided over the entire side and bottom surface of the first inactive contact portion 134, but is not limited thereto. The barrier metal film 1342 may be provided covering at least the bottom corner portion 1340, and may not cover the central part of the bottom surface of the first inactive contact portion 134. The barrier metal film 1342 may extend beyond the contact hole 55 and be provided above the interlayer insulating film 38. The material of the barrier metal film 1342 may be titanium or a titanium compound, etc.

[0242] The plug portion 1344 may be provided in contact with the inside of the barrier metal film 1342. In this example, the plug portion 1344 is provided by filling the first inactive contact portion 134, but is not limited to this. The plug portion 1344 may be provided in a part of the first inactive contact portion 134, and may extend beyond the contact hole 55 and above the interlayer insulating film 38. When the plug portion 1344 is provided in a part of the first inactive contact portion 134, the remaining area of ​​the first inactive contact portion 134 may be filled with the same material as the gate metal layer 50. The material of the plug portion 1344 may be a plug metal such as tungsten.

[0243] The side surface of the polycrystalline portion 132 may be in contact with the side surface of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 located below the first inactive contact portion 134. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed from the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 located below the first inactive contact portion 134, the housing portion 198 is a virtual region, as shown by the dotted line in Figure 16A. That is, the housing portion 198 may be formed integrally as part of the interlayer insulating film 38. In another example, the housing portion 198 may be a third interlayer insulating film 138 located above the semiconductor substrate 10. The housing portion 198 may be formed in the process of providing the third interlayer insulating film 138 and may be formed from the same material as the third interlayer insulating film 138. In other words, the housing portion 198 may be integrally formed as part of the third interlayer insulating film 138. In yet another example, the housing portion 198 may be polysilicon with a lower impurity concentration than the polycrystalline portion 132, or undoped polysilicon.

[0244] Figure 16B shows an example of an enlarged view of the e-e' cross-section in Figure 9 when a void 302 occurs in the first inactive contact portion 134. This example shows a case where the plug portion 1344 near the center of the bottom surface of the first inactive contact portion 1344 is removed by over-etching during the etch-back process of the plug portion 1344. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the gate metal layer 50, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0245] In this example, the first inactive contact portion 134 is provided with its bottom corner portion 1340 in contact with the polycrystalline portion 132 and its bottom surface in contact with the housing portion 198. Therefore, even if a void 302 is formed inside the area near the center of the bottom surface of the first inactive contact portion 134, the impact on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corner portion 1340 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the inactive portion 130 ensures the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132, not at the center of the bottom surface of the first inactive contact portion 134, but at the bottom corner portion 1340. As a result, even if a void 302 is formed in the area near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0246] Figure 16C shows another example of an enlarged view of the e-e' cross-section in Figure 9 when a void 302 occurs in the first inactive contact portion 134. This example shows a case where, during the etch-back process of the plug portion 1344, the plug portion 1344 and barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are removed by over-etching, and further over-etching extends to the housing portion 198. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the gate metal layer 50, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0247] In the non-active portion 130 of this example, among the electrical connections between the first non-active contact portion 134 and the polycrystalline portion 132, electrical connection is ensured by the bottom surface corner portion 1340 instead of the central portion of the bottom surface of the first non-active contact portion 134. By this, similar to the example of FIG. 16B, even when a void 302 is formed in the region near the center of the first non-active contact portion 134 that contacts the housing portion 198, stable quality can be obtained and the yield can be improved.

[0248] FIG. 17 shows an example of the e-e' cross-section in FIG. 9. The semiconductor device 100 of this example is different from the embodiment of FIG. 15 in that the first non-active contact portion 134 has a trench contact structure. Others may be the same as the embodiment of FIG. 15.

[0249] FIG. 18A shows an example of an enlarged view of the e-e' cross-section in FIG. 9. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the non-active portion 130. The semiconductor device 100 of this example is different from the embodiment of FIG. 16A in that the structure of the first non-active contact portion 134 is different. In this example, the points different from the embodiment of FIG. 16A will be particularly described, and others may be the same as the embodiment of FIG. 16A.

[0250] The side wall of the first non-active contact portion 134 may have a trench contact structure that contacts the side surface of the polycrystalline portion 132. The bottom surface corner portion 1340 of the first non-active contact portion 134 of this example contacts the polycrystalline portion 132 on the side surface of the polycrystalline portion 132.

[0251] The side wall of the first non-active contact portion 134 may contact the polycrystalline portion 132 and the interlayer insulating film 38. The polycrystalline portion 132 may contact the side wall of the first non-active contact portion 134 from the bottom surface corner portion 1340 to a region of 10% or more and 90% or less of the side wall of the first non-active contact portion 134. The polycrystalline portion 132 of this example contacts the side wall of the first non-active contact portion 134 from the bottom surface corner portion 1340 to a region of 35% of the side wall of the first non-active contact portion 134. That is, the ratio of the length L4 to the length L3 of this example is 3%.

[0252] FIG. 18B shows an example of an enlarged view of the e-e' cross-section in FIG. 9 when a void 302 occurs in the first non-active contact portion 134. This example shows a case where, in the etch-back process of the plug portion 1344, the plug portion 1344 near the center of the bottom surface of the first non-active contact portion 134 is removed by over-etching. In this case, it is difficult to fill the first non-active contact portion 134 with the metal material of the gate metal layer 50, and a void 302 may occur near the center of the bottom surface of the first non-active contact portion 134.

[0253] In the first non-active contact portion 134 of this example, the bottom surface corner portion 1340 is in contact with the polycrystalline portion 132, and the bottom surface is provided in contact with the housing portion 198. Therefore, even when a void 302 occurs inside near the center of the bottom surface of the first non-active contact portion 134, the influence on the electrical connection at the bottom surface corner portion 1340 between the first non-active contact portion 134 and the polycrystalline portion 132 is suppressed. Thereby, the yield of the semiconductor device 100 having desired characteristics can be improved. The non-active portion 130 of this example ensures an electrical connection by the bottom surface corner portion 1340 rather than the center portion of the bottom surface of the first non-active contact portion 134 in the electrical connection between the first non-active contact portion 134 and the polycrystalline portion 132. Thus, even when a void 302 is formed in the region near the center of the first non-active contact portion 134 in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0254] FIG. 18C shows another example of an enlarged view of the e-e' cross-section in FIG. 9 when a void 302 occurs in the first non-active contact portion 134. This example shows a case where, in the etch-back process of the plug portion 1344, the plug portion 1344 near the center of the bottom surface of the first non-active contact portion 134 and the barrier metal film 1342 are removed by over-etching, and further over-etched to the housing portion 198. In this case, it is difficult to fill the first non-active contact portion 134 with the metal material of the gate metal layer 50, and a void 302 may occur near the center of the bottom surface of the first non-active contact portion 134.

[0255] In this example, the inactive portion 130 ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132, not through the center of the bottom surface of the first inactive contact portion 134, but through the bottom corner portion 1340. As a result, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, similar to the example in Figure 18B, stable quality can be obtained and yield can be improved.

[0256] Figure 19A shows an example of a top view of a semiconductor device 100. In this example, the semiconductor device 100 includes a guard ring 142 in the edge termination structure 140. The semiconductor device 100 may have multiple guard rings 142.

[0257] The guard ring 142 is a region of second conductivity type provided on the front surface 21 of the semiconductor substrate 10, between the active portion 120 and the edge 102 of the semiconductor substrate 10. The guard ring 142 is, for example, of P+ type. The guard ring 142 may surround the active portion 120 when viewed from above. In this example, the well region 17 adjacent to the active portion 120 may also be included in the guard ring 142. In addition, multiple guard rings 142 may be provided. The guard ring 142 located on the outside may surround the guard ring 142 located on the inside. The outside refers to the side closer to the edge 102, and the inside refers to the side closer to the center when viewed from above of the semiconductor substrate 10. By providing the guard ring 142, the depletion layer on the front surface 21 side of the active portion 120 can be extended towards the edge 102, thereby improving the breakdown voltage of the semiconductor device 100. The guard ring 142, which is spaced apart from the well region 17 adjacent to the active region 120, may also be formed by the same diffusion process as the well region 17, and the diffusion shapes on the inside and outside may be substantially identical. In another example, the guard ring 142 may be a VLD that becomes shallower towards the outside. In yet another example, the guard ring 142 may be formed by the same diffusion process as the base region 14. The semiconductor device 100 may further include at least one field plate or resurf provided surrounding the active region 120 in the edge termination structure 140.

[0258] Figure 19B shows an example of region R in Figure 19A. The semiconductor device 100 in this example includes a guard ring 142 and a field plate 144 in the edge termination structure 140. The edge termination structure 140 is an example of the inactive portion 130. The semiconductor device 100 may include an interlayer insulating film 38, an edge metal layer 146, and a field insulating film 148 in the edge termination structure 140. The interlayer insulating film 38 and the field insulating film 148 are omitted in Figure 19B. Contact holes 57 and 59 are provided through the interlayer insulating film 38.

[0259] The field plate 144 is a conductive member provided above the semiconductor substrate 10. In this example, the field plate 144 is made of polysilicon with impurities added. The field plate 144 is an example of a polycrystalline portion 132. The field plate 144 is provided above the guard ring 142. The field plate 144 may be electrically connected to the corresponding guard ring 142.

[0260] The guard ring 142 has a non-corner region 1420 and a corner region 1422. The non-corner region 1420 is, for example, a region of the guard ring 142 that extends along the edge 102 of the semiconductor substrate 10, and the corner region 1422 is, for example, a portion of the guard ring 142 that connects the regions that extend along the edge 102 of the semiconductor substrate 10.

[0261] The contact hole 57 connects the edge metal layer 146 and the field plate 144. A barrier metal film made of titanium or a titanium compound and / or a plug made of tungsten may be formed inside the contact hole 57.

[0262] The contact hole 59 connects the edge metal layer 146 and the guard ring 142. A barrier metal film made of titanium or a titanium compound and / or a plug made of tungsten may be formed inside the contact hole 59. A field plate 144 does not need to be provided around the contact hole 59.

[0263] Contact holes 57 and 59 may be located above the corner region 1422 of the guard ring 142. However, at least one of contact holes 57 or 59 may be located above the non-corner region 1420 of the guard ring 142, or both contact holes 57 and 59 may be located above the non-corner region 1420 of the guard ring 142. In this example, contact holes 57 and 59 have a longitudinal direction in the direction of progression of the guard ring 142 and the field plate 144, and are located side by side with each other, from the center side to the edge 102 side. In other examples, contact holes 57 and 59 may be arranged in the direction of progression of the guard ring 142 and the field plate 144, the longitudinal direction of each contact hole may be from the center side to the edge 102 side, and each contact hole may consist of multiple holes.

[0264] The width d2 of the corner region 1422 may be wider than the width d1 of the non-corner region 1420. That is, the radius of curvature r1 on the edge 102 side (outside) may be smaller than the sum of the radius of curvature r2 on the center side (inside) and d1. In this example, r1 is smaller than r2. The edge metal layer 146 may be provided at the widest part of the corner region 1422, or in its vicinity. In other examples, the width d2 of the corner region 1422 may be equal to the width d1 of the non-corner region 1420. In yet another example, the edge metal layer 146 may be provided in the non-corner region 1420, or it may span both the non-corner region 1420 and the corner region 1422.

[0265] Figure 20 shows an example of the f-f' cross-section in Figure 19B. The f-f' cross-section is a plane in the inactive portion 130 that passes through the contact holes 57 and 59 and is parallel to the Z-axis direction. The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, a field insulating film 148, an edge metal layer 146, a collector electrode 24, a first inactive contact portion 134, and a second inactive contact portion 135 in the f-f' cross-section.

[0266] The field insulating film 148 is provided above the semiconductor substrate 10. The field insulating film 148 may be provided to cover the drift region 18 exposed on the front surface 21 of the semiconductor substrate 10 between the well region 17 adjacent to the active portion 120 and the guard ring 142, and between the guard rings 142 themselves. The field insulating film 148 may be provided to surround the active portion 120 along the guard ring 142.

[0267] The field insulating film 148 may have an insulating film obtained by oxidizing or nitriding the semiconductor substrate 10, an insulating film deposited by CVD or the like, or other insulating films. The field insulating film 148 may be a single-layer insulating film, or an insulating film obtained by laminating multiple films formed by different methods.

[0268] The edge metal layer 146 is provided above the semiconductor substrate 10 and is electrically connected to the guard ring 142. The edge metal layer 146 is provided above the semiconductor substrate 10, with the interlayer insulating film 38 in between. The edge metal layer 146 may be electrically connected to the field plate 144. The edge metal layer 146 may be electrically floating. For example, when a voltage V is applied to the collector electrode 24 with the gate of the semiconductor device 100 turned off, the edge metal layer 146 will have a predetermined voltage lower than the voltage V. If the guard ring 142 is a well region 17 adjacent to the active portion 120, the edge metal layer 146 may be at the same potential as the emitter electrode 52.

[0269] The edge metal layer 146 is formed from a material containing metal. At least a portion of the edge metal layer 146 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu).

[0270] The polycrystalline portion 132 is provided above the semiconductor substrate. In this example, the polycrystalline portion 132 is a field plate 144. The polycrystalline portion 132 may be provided above the third interlayer insulating film 138. The third interlayer insulating film 138 may be made of the same material as, for example, the gate insulating film 42 and / or the dummy insulating film 32. The third interlayer insulating film 138 may be a thermal oxide film. In other examples, the third interlayer insulating film 138 may be made of a different material from the gate insulating film 42 and / or the dummy insulating film 32. The interlayer insulating film 38 is provided above the polycrystalline portion 132.

[0271] The first inactive contact portion 134 is provided extending from the upper surface to the lower surface of the interlayer insulating film 38. The contact hole 57 may be provided penetrating the interlayer insulating film 38. The first inactive contact portion 134 may have the contact hole 57 and a metal layer filled inside the contact hole 57. The housing portion 198 is provided below the first inactive contact portion 134. The field insulating film 148 may be provided below the interlayer insulating film 38. The polycrystalline portion 132 may be connected to the edge metal layer 146 via the first inactive contact portion 134. In this example, the field plate 144 is connected to the edge metal layer 146 via the first inactive contact portion 134.

[0272] The second non-active contact portion 135 is provided to extend from the upper surface to the lower surface of the interlayer insulating film 38. The contact hole 59 may be provided to penetrate the interlayer insulating film 38. The second non-active contact portion 135 may have a contact hole 59 and a metal layer filled inside the contact hole 59. The guard ring 142 may be connected to the edge metal layer 146 via the second non-active contact portion 135. In this example, the guard ring 142 is connected to the edge metal layer 146 via the second non-active contact portion 135. The second non-active contact portion 135 may have the same configuration as the active contact portion 124. That is, the second non-active contact portion 135 may include a barrier metal film 1352 and a plug portion 1354.

[0273] FIG. 21A shows an example of an enlarged view of the f-f' cross-section in FIG. 19B. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the non-active portion 130.

[0274] The bottom corner portion 1340 of the first non-active contact portion 134 may contact the polycrystalline portion 132. In this example, the bottom corner portion 1340 contacts the polycrystalline portion 132 on the upper surface of the polycrystalline portion 132.

[0275] The bottom surface of the first non-active contact portion 134 may contact the housing portion 198. In this example, the bottom surface of the first non-active contact portion 134 contacts the housing portion 198 on the upper surface of the housing portion 198.

[0276] In this example, the first inactive contact portion 134 is provided with its bottom corner portion 1340 in contact with the polycrystalline portion 132 and its bottom surface in contact with the housing portion 198. This ensures reliable electrical connection between the edge metal layer 146 and the polycrystalline portion 132. If the plug portion 1344 and barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are removed by over-etching during the etch-back process of the plug portion 1344, a void may form inside the first inactive contact portion 134. Even in that case, the electrical connection can be ensured by the barrier metal film 1342 and / or plug portion 1344 remaining on the bottom corner portion 1340 of the first inactive contact portion 134.

[0277] In this example, the first inactive contact portion 134 is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside near the center of the bottom surface of the temperature-sensitive contact portion, the impact on the electrical connection at the bottom surface corner portion 1340 between the first inactive contact portion 134 and the polycrystalline portion 132 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the inactive portion 130 ensures the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom surface corner portion 1340 rather than the bottom surface center of the first inactive contact portion 134. As a result, even if a void is formed in the region near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0278] The bottom surface of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132 and the housing portion 198. In this example, the bottom surface of the first inactive contact portion 134 is in contact with the polycrystalline portion 132 and the housing portion 198, as one bottom corner 1340a is in contact with the polycrystalline portion 132 and the other bottom corner 1340b is in contact with the housing portion 198.

[0279] The polycrystalline portion 132 may be in contact with the bottom surface of the first inactive contact portion 134 from the bottom surface corner 1340 to a region of 10% to 40% of the bottom surface of the first inactive contact portion 134. In this example, the polycrystalline portion 132 is in contact with the bottom surface of the first inactive contact portion 134 from the bottom surface corner 1340a to a region of 20% of the bottom surface of the first inactive contact portion 134. That is, the ratio of length L2 to length L1 in this example is 20%.

[0280] The barrier metal film 1342 may be provided on the bottom corner portion 1340 of the first inactive contact portion 134. In this example, the barrier metal film 1342 is provided over the entire side and bottom surface of the first inactive contact portion 134, but is not limited thereto. The barrier metal film 1342 may be provided covering at least the bottom corner portion 1340, and may not cover the central part of the bottom surface of the first inactive contact portion 134. The barrier metal film 1342 may extend beyond the contact hole 57 and be provided above the interlayer insulating film 38. The material of the barrier metal film 1342 may be titanium or a titanium compound, etc.

[0281] The plug portion 1344 may be provided in contact with the inside of the barrier metal film 1342. In this example, the plug portion 1344 is provided by filling the first inactive contact portion 134, but is not limited to this. The plug portion 1344 may be provided in a part of the first inactive contact portion 134, and may extend beyond the contact hole 57 and above the interlayer insulating film 38. When the plug portion 1344 is provided in a part of the first inactive contact portion 134, the remaining area of ​​the first inactive contact portion 134 may be filled with the same material as the edge metal layer 146. The material of the plug portion 1344 may be a plug metal such as tungsten.

[0282] The side surface of the polycrystalline portion 132 may be in contact with the side surface of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 located below the first inactive contact portion 134. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed from the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 located below the first inactive contact portion 134, the housing portion 198 is a virtual region, as shown by the dotted line in Figure 21A. That is, the housing portion 198 may be integrally formed as part of the interlayer insulating film 38. In another example, the housing portion 198 may be a third interlayer insulating film 138 located above the semiconductor substrate 10. The housing portion 198 may be formed in the process of providing the third interlayer insulating film 138 and may be formed from the same material as the third interlayer insulating film 138. In other words, the housing portion 198 may be integrally formed as part of the third interlayer insulating film 138.

[0283] Figure 21B shows an example of an enlarged view of the f-f' cross section in Figure 19B. This figure shows the region of the inactive portion 130 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example differs from the embodiment in Figure 21A in that the housing portion 198 is located below the first inactive contact portion 134 of the field insulating film 148. Other aspects may be the same as those of the embodiment in Figure 21A.

[0284] Figure 21C shows an example of an enlarged view of the f-f' cross section in Figure 19B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the inactive portion 130. The semiconductor device 100 in this example differs from the embodiments in Figures 21A and 21B in that a housing portion 198 is provided separately from the interlayer insulating film 38 and the field insulating film 148. In this example, the differences from the embodiments in Figures 21A and 21B will be explained in particular, and other aspects may be the same as those in the embodiments in Figures 21A and / or 21B.

[0285] The housing portion 198 may have polysilicon with a lower impurity concentration than the contact region 300 of the polycrystalline portion 132. The contact region 300 of the polycrystalline portion 132 may be the region of the polycrystalline portion 132 in contact with the housing portion 198. For example, the housing portion 198 may have polysilicon or undoped polysilicon with a lower impurity concentration than the polycrystalline portion 132.

[0286] Figure 21D shows an example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134. This example shows a case where the plug portion 1344 near the center of the bottom surface of the first inactive contact portion 1344 is removed by over-etching during the etch-back process of the plug portion 1344. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0287] In this example, the first inactive contact portion 134 is provided with its bottom corner portion 1340 in contact with the polycrystalline portion 132 and its bottom surface in contact with the housing portion 198. Therefore, even if a void 302 is formed inside the area near the center of the bottom surface of the first inactive contact portion 134, the impact on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corner portion 1340 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the inactive portion 130 ensures the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132, not at the center of the bottom surface of the first inactive contact portion 134, but at the bottom corner portion 1340. As a result, even if a void 302 is formed in the area near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0288] Figure 21E shows another example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134. This example shows a case where, during the etch-back process of the plug portion 1344, the plug portion 1344 and barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are removed by over-etching, and further over-etching extends to the housing portion 198. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0289] In this example, the inactive portion 130 ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132, not through the center of the bottom surface of the first inactive contact portion 134, but through the bottom corner portion 1340. As a result, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, similar to the example in Figure 21D, stable quality can be obtained and yield can be improved.

[0290] Figure 22 shows an example of the f-f' cross-section in Figure 19B. The semiconductor device 100 in this example differs from the embodiment in Figure 20 in that the first inactive contact portion 134 has a trench contact structure. Otherwise, it may be the same as the embodiment in Figure 20.

[0291] Figure 23A shows an example of an enlarged view of the f-f' cross-section in Figure 19B. This figure shows the region of the inactive portion 130 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example differs from the embodiment in Figure 21A in that the structure of the first inactive contact portion 134 is different. In this example, the differences from the embodiment in Figure 21A will be explained in particular, and other aspects may be the same as those of the embodiment in Figure 21A.

[0292] The sidewall of the first inactive contact portion 134 may have a trench contact structure that contacts the side surface of the polycrystalline portion 132. In this example, the bottom corner portion 1340 of the first inactive contact portion 134 contacts the polycrystalline portion 132 at the side surface of the polycrystalline portion 132.

[0293] The sidewall of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132 and the interlayer insulating film 38. The polycrystalline portion 132 may be in contact with the sidewall of the first inactive contact portion 1340 from the bottom corner portion 1340 to a region of 10% to 90% of the sidewall of the first inactive contact portion 134. In this example, the polycrystalline portion 132 is in contact with the sidewall of the first inactive contact portion 1340 from the bottom corner portion 1340 to a region of 35% of the sidewall of the first inactive contact portion 134. That is, the ratio of length L4 to length L3 in this example is 35%.

[0294] Figure 23B shows an example of an enlarged view of the f-f' cross section in Figure 19B. This figure shows the region of the inactive portion 130 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example differs from the embodiment in Figure 23A in that the housing portion 198 is located below the first inactive contact portion 134 of the field insulating film 148. Other aspects may be the same as those of the embodiment in Figure 23A.

[0295] Figure 23C shows an example of an enlarged view of the f-f' cross section in Figure 19B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the inactive portion 130. The semiconductor device 100 in this example differs from the embodiments in Figures 23A and 23B in that a housing portion 198 is provided separately from the interlayer insulating film 38 and the field insulating film 148, and the housing portion 198 has polysilicon with a lower impurity concentration than the contact region 300 of the polycrystalline portion 132. Otherwise, it may be the same as the embodiments in Figures 23A and / or 23B.

[0296] Figure 23D shows an example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134. This example shows a case where the plug portion 1344 near the center of the bottom surface of the first inactive contact portion 1344 is removed by over-etching during the etch-back process of the plug portion 1344. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0297] In this example, the first inactive contact portion 134 is provided with its bottom corner portion 1340 in contact with the polycrystalline portion 132 and its bottom surface in contact with the housing portion 198. Therefore, even if a void 302 is formed inside the area near the center of the bottom surface of the first inactive contact portion 134, the impact on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corner portion 1340 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the inactive portion 130 ensures the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132, not at the center of the bottom surface of the first inactive contact portion 134, but at the bottom corner portion 1340. As a result, even if a void 302 is formed in the area near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0298] Figure 23E shows another example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134. This example shows a case where, during the etch-back process of the plug portion 1344, the plug portion 1344 and barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are removed by over-etching, and further over-etching extends to the housing portion 198. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0299] In this example, the inactive portion 130 ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132, not through the center of the bottom surface of the first inactive contact portion 134, but through the bottom corner portion 1340. As a result, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, similar to the example in Figure 23D, stable quality can be obtained and yield can be improved.

[0300] Figure 24 shows an example of the f-f' cross-section in Figure 19B. The semiconductor device 100 in this example differs from the embodiment in Figure 20 in that the first inactive contact portion 134 is provided above the polycrystalline portion 132 above the field insulating film 148. Otherwise, it may be the same as the embodiment in Figure 20.

[0301] The first inactive contact portion 134 in Figure 20 and the first inactive contact portion 134 in Figure 24 may be provided separately or in combination. For example, as the first inactive contact portion 134 connecting the edge metal layer 146 and the polycrystalline portion 132, the first inactive contact portion 134 may be provided only at the end of the field plate 144 on the guard ring 142 side, as shown in Figure 20; the first inactive contact portion 134 may be provided only at the end of the field plate 144 that is separated from the guard ring 142, as shown in Figure 24; or the first inactive contact portion 134 may be provided at both the end of the field plate 144 on the guard ring 142 side and the end that is separated from the guard ring 142. The first inactive contact portion 134 may be provided only at the end of one of the field plates 144 that is separated from the guard ring 142, as viewed from the contact hole 59. The edge metal layer 146 and the guard ring 142 are electrically connected via a contact hole 59 in which a second inactive contact portion 135 is embedded.

[0302] Figure 25A shows an example of an enlarged view of the f-f' cross section in Figure 19B. This figure shows the region of the inactive portion 130 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example differs from the embodiment in Figure 21A in that the first inactive contact portion 134 is provided above the polycrystalline portion 132 above the field insulating film 148. Otherwise, it may be the same as the embodiment in Figure 21A.

[0303] Figure 25B shows an example of an enlarged view of the f-f' cross section in Figure 19B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the inactive portion 130. The semiconductor device 100 in this example differs from the embodiment in Figure 25A in that a housing portion 198 is provided separately from the interlayer insulating film 38, and the housing portion 198 has polysilicon with a lower impurity concentration than the contact region 300 of the polycrystalline portion 132. Other aspects may be the same as the embodiment in Figure 25A.

[0304] Figure 25C shows an example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134. This example shows a case where the plug portion 1344 near the center of the bottom surface of the first inactive contact portion 1344 is removed by over-etching during the etch-back process of the plug portion 1344. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0305] In this example, the first inactive contact portion 134 is provided with its bottom corner portion 1340 in contact with the polycrystalline portion 132 and its bottom surface in contact with the housing portion 198. Therefore, even if a void 302 is formed inside the area near the center of the bottom surface of the first inactive contact portion 134, the impact on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corner portion 1340 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the inactive portion 130 ensures the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132, not at the center of the bottom surface of the first inactive contact portion 134, but at the bottom corner portion 1340. As a result, even if a void 302 is formed in the area near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0306] Figure 25D shows another example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134. This example shows a case where, during the etch-back process of the plug portion 1344, the plug portion 1344 and barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are removed by over-etching, and then the housing portion 198 is further over-etched. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0307] In this example, the inactive portion 130 ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132, not through the center of the bottom surface of the first inactive contact portion 134, but through the bottom corner portion 1340. As a result, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, similar to the example in Figure 25C, stable quality can be obtained and yield can be improved.

[0308] Figure 26 shows an example of the f-f' cross-section in Figure 19B. The semiconductor device 100 in this example differs from the embodiment in Figure 22 in that the first inactive contact portion 134 is provided above the polycrystalline portion 132 above the field insulating film 148. Otherwise, it may be the same as the embodiment in Figure 22.

[0309] The first inactive contact portion 134 in Figure 22 and the first inactive contact portion 134 in Figure 26 may be provided separately or in combination. For example, as the first inactive contact portion 134 connecting the edge metal layer 146 and the polycrystalline portion 132, the first inactive contact portion 134 may be provided only at the end of the field plate 144 on the guard ring 142 side, as shown in Figure 22; the first inactive contact portion 134 may be provided only at the end of the field plate 144 that is separated from the guard ring 142, as shown in Figure 26; or the first inactive contact portion 134 may be provided at both the end of the field plate 144 on the guard ring 142 side and the end that is separated from the guard ring 142. The first inactive contact portion 134 may be provided only at the end of one of the field plates 144 that is separated from the guard ring 142, as viewed from the contact hole 59. The edge metal layer 146 and the guard ring 142 are electrically connected via a contact hole 59 in which a second inactive contact portion 135 is embedded.

[0310] Figure 27A shows an example of an enlarged view of the f-f' cross section in Figure 19B. This figure shows the region of the inactive portion 130 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example differs from the embodiment in Figure 23A in that the first inactive contact portion 134 is provided above the polycrystalline portion 132 above the field insulating film 148. Otherwise, it may be the same as the embodiment in Figure 23A.

[0311] Figure 27B shows an example of an enlarged view of the f-f' cross section in Figure 19B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the inactive portion 130. The semiconductor device 100 in this example differs from the embodiment in Figure 27A in that a housing portion 198 is provided separately from the interlayer insulating film 38, and the housing portion 198 has polysilicon with a lower impurity concentration than the contact region 300 of the polycrystalline portion 132. Other aspects may be the same as the embodiment in Figure 27A.

[0312] Figure 27C shows an example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134. This example shows a case where the plug portion 1344 near the center of the bottom surface of the first inactive contact portion 1344 is removed by over-etching during the etch-back process of the plug portion 1344. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0313] In this example, the first inactive contact portion 134 is provided with its bottom corner portion 1340 in contact with the polycrystalline portion 132 and its bottom surface in contact with the housing portion 198. Therefore, even if a void 302 is formed inside the area near the center of the bottom surface of the first inactive contact portion 134, the impact on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corner portion 1340 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the inactive portion 130 ensures the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132, not at the center of the bottom surface of the first inactive contact portion 134, but at the bottom corner portion 1340. As a result, even if a void 302 is formed in the area near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0314] Figure 27D shows another example of an enlarged view of the f-f' cross-section in Figure 19B when a void 302 occurs in the first inactive contact portion 134. This example shows a case where, during the etch-back process of the plug portion 1344, the plug portion 1344 and barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are removed by over-etching, and further over-etching extends to the housing portion 198. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0315] In this example, the inactive portion 130 ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132, not through the center of the bottom surface of the first inactive contact portion 134, but through the bottom corner portion 1340. As a result, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, similar to the example in Figure 27C, stable quality can be obtained and yield can be improved.

[0316] Figure 28 shows an example of the g-g' cross-section of Figure 19A. The g-g' cross-section is the XZ plane passing through the gate pad 112 in the inactive portion 130. The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, a pad electrode 51, a collector electrode 24, and a first inactive contact portion 134 in the g-g' cross-section. The gate pad 112 is an example of the pad electrode 51.

[0317] The pad electrode 51 is provided above the semiconductor substrate 10. The pad electrode 51 may be provided above the interlayer insulating film 38. In this example, the gate pad 112 is provided above the interlayer insulating film 38. The material of the pad electrode 51 may be the same metal as the material of the emitter electrode 52.

[0318] The inactive portion 130 has a polycrystalline portion 132 provided above the semiconductor substrate 10. In this example, the polycrystalline portion 132 is a pad connection portion 125.

[0319] The inactive portion 130 may have a third interlayer insulating film 138 on the upper surface of the semiconductor substrate 10. The third interlayer insulating film 138 may be made of the same material as, for example, the gate insulating film 42 and / or the dummy insulating film 32. As an example, the third interlayer insulating film 138 may be a thermal oxide film. The polycrystalline portion 132 may be provided above the third interlayer insulating film 138. In other examples, the third interlayer insulating film 138 may be made of a different material from the gate insulating film 42 and / or the dummy insulating film 32. In this example, the pad connection portion 125 is provided above the third interlayer insulating film 138.

[0320] The first inactive contact portion 134 is electrically connected to the polycrystalline portion 132. In this example, the first inactive contact portion 134 is electrically connected to the pad connection portion 125. The first inactive contact portion 134 may electrically connect the pad electrode 51 and the pad connection portion 125.

[0321] The first inactive contact portion 134 is provided extending from the upper surface to the lower surface of the interlayer insulating film 38. The contact hole 53 may be provided penetrating the interlayer insulating film 38. The first inactive contact portion 134 may have a contact hole 53 and a metal layer filled inside the contact hole 53. The housing portion 198 is provided below the first inactive contact portion 134.

[0322] The polycrystalline portion 132 may be connected to the pad electrode 51 via the first inactive contact portion 134. In this example, the pad connection portion 125 is connected to the pad electrode 51 via the first inactive contact portion 134.

[0323] The bottom corner portion 1340 of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132. The bottom corner portion 1340 of the first inactive contact portion 134 may be the intersection of the bottom surface of the first inactive contact portion 134 and the side surface of the first inactive contact portion 134. Contact between the bottom corner portion 1340 and the polycrystalline portion 132 may mean contact with the polycrystalline portion 132 on its upper surface, contact with the polycrystalline portion 132 on its side surface, or contact with the polycrystalline portion 132 in an internal region of the polycrystalline portion 132. In this example, the bottom corner portion 1340 is in contact with the polycrystalline portion 132 on its upper surface.

[0324] The first inactive contact portion 134 in this example has two bottom corner portions 1340. One of the two bottom corner portions 1340 may be in contact with the polycrystalline portion 132. The other of the two bottom corner portions 1340 may or may not be in contact with the housing portion 198. In this example, one bottom corner portion 1340a of the first inactive contact portion 1340 is in contact with the polycrystalline portion 132, and the other bottom corner portion 1340b is in contact with the housing portion 198.

[0325] The bottom surface of the first inactive contact portion 134 may be in contact with the housing portion 198. The bottom surface of the first inactive contact portion 134 may be the surface between the two bottom corner portions 1340 of the first inactive contact portion 134. When the bottom surface of the first inactive contact portion 134 is in contact with the housing portion 198, it may be that the bottom surface is in contact with the housing portion 198 on the upper surface of the housing portion 198, or it may be that the bottom surface is in contact with the housing portion 198 in an area inside the housing portion 198. In this example, the bottom surface of the first inactive contact portion 134 is in contact with the housing portion 198 on the upper surface of the housing portion 198.

[0326] In this example, the first inactive contact portion 134 is provided with its bottom corner portion 1340 in contact with the polycrystalline portion 132 and its bottom surface in contact with the housing portion 198. This ensures reliable electrical connection between the pad electrode 51 and the polycrystalline portion 132. If the plug portion 1344 and the barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are removed by over-etching during the etch-back process of the plug portion 1344, a void may form inside the first inactive contact portion 134. Even in that case, the electrical connection can be ensured by the barrier metal film 1342 and / or plug portion 1344 remaining on the bottom corner portion 1340 of the first inactive contact portion 134.

[0327] In this example, the first inactive contact portion 134 is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the first inactive contact portion 134 near the center of its bottom surface, the impact on the electrical connection at the bottom corner portion 1340 between the first inactive contact portion 134 and the polycrystalline portion 132 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the inactive portion 130 ensures the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corner portion 1340 rather than the center of the bottom surface of the first inactive contact portion 134. As a result, even if a void is formed in the region near the center of the first inactive contact portion 134 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0328] The bottom surface of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132 and the housing portion 198. In this example, the bottom surface of the first inactive contact portion 134 is in contact with the polycrystalline portion 132 and the housing portion 198, as one bottom corner 1340a is in contact with the polycrystalline portion 132 and the other bottom corner 1340b is in contact with the housing portion 198.

[0329] The polycrystalline portion 132 may be in contact with the bottom surface of the first inactive contact portion 134 from the bottom surface corner 1340 to an area of ​​10% to 40% of the bottom surface of the first inactive contact portion 134. That is, the ratio of the area of ​​the bottom surface of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 to the area of ​​the bottom surface of the first inactive contact portion 134 may be 10% to 40%. Referring to Figure 28, length L1 is the length of the bottom surface of the first inactive contact portion 134 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Length L2 is the length of the bottom surface of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L2 to length L1 may be 10% to 40%. In this example, the polycrystalline portion 132 is in contact with the bottom surface of the first inactive contact portion 134 from the bottom surface corner 1340a to 20% of the area of ​​the bottom surface of the first inactive contact portion 134. That is, the ratio of length L2 to length L1 in this example is 20%.

[0330] The side surface of the polycrystalline portion 132 may be in contact with the side surface of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 located below the first inactive contact portion 134. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed from the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 located below the first inactive contact portion 134, the housing portion 198 may be a virtual region. That is, the housing portion 198 may be integrally formed as part of the interlayer insulating film 38. In other examples, the housing portion 198 may be polysilicon with a lower impurity concentration than the polycrystalline portion 132 or undoped polysilicon. In other examples, the housing portion 198 may be a third interlayer insulating film 138 located above the semiconductor substrate 10. In this case, the housing portion 198 may be formed in the step of providing the third interlayer insulating film 138, and may be formed from the same material as the third interlayer insulating film 138. That is, the housing portion 198 may be integrally formed as part of the third interlayer insulating film 138.

[0331] The first inactive contact portion 134 may include a barrier metal film 1342 provided in the contact hole 53 and a plug portion 1344. The barrier metal film 1342 of the first inactive contact portion 134 may contain titanium or a titanium compound. The plug portion 1344 of the first inactive contact portion 134 may contain a plug metal such as tungsten. In this example, the barrier metal film 1342 is provided above the interlayer insulating film 38 and is in contact with the pad electrode 51. In the active portion 120 or other inactive portions 130 such as the edge termination structure portion 140 or the temperature sensing portion 180, a barrier metal film 1242, a barrier metal film 1342, and / or a barrier metal film 1882 may also be provided above the interlayer insulating film 38. In this example, the plug portion 1344 is provided inside the contact hole 53. If the plug portion 1344 is provided on a part of the first inactive contact portion 134, the remaining area of ​​the first inactive contact portion 134 may be filled with the same material as the pad electrode 51. In other examples, the plug portion 1344 may be provided outside the contact hole 53, above the barrier metal film 1342, and in contact with the pad electrode 51. In the active portion 120 or other inactive portion 130, plug portions 1244, 1344, and / or 1884 may be provided outside the contact hole 54, contact hole 55, contact hole 56, contact hole 57, contact hole 58, and / or contact hole 59, above the barrier metal film 1242, barrier metal film 1342, and / or barrier metal film 1882. In yet another example, the barrier metal film 1342 may not be provided above the interlayer insulating film 38, but only inside the contact hole 53.

[0332] The polycrystalline portion 132 may be connected to the pad electrode 51 through a contact hole 53 provided in the interlayer insulating film 38. In this example, the pad connection portion 125 is connected to the pad electrode 51 through a contact hole 53 provided in the interlayer insulating film 38.

[0333] In this example, the polycrystalline portion 132 may be formed below the gate pad 112. In the cross-section of Figure 28, the pad connection portions 125 are provided discretely, but as will be described later, the pad connection portions 125 may be connected to each other in different cross-sections.

[0334] The pad connection portion 125 may be made of the same polycrystalline material as the gate conductive portion 44 and the dummy conductive portion 34. In other examples, the pad connection portion 125 may be made of polycrystalline material deposited simultaneously with the polycrystalline material constituting the temperature-sensing diode 183, and made conductive by ion implantation or other means as needed. The insulating film below the polycrystalline portion 132 may not be made of the same insulating film material as the gate insulating film 42, etc., but may have the same configuration as the second interlayer insulating film 37 of the temperature-sensing portion 180. The pad connection portion 125 does not have to be electrically connected to anything other than the pad electrode 51. In this case, the pad electrode 51 may be directly connected to the gate metal layer 50. Also, the pad connection portion 125 does not have to be conductive. In other examples, the pad connection portion 125 may be electrically connected to anything other than the pad electrode 51. For example, the pad connection portion 125 may be connected to the connection portion 25. Also, the pad electrode 51 may not be directly connected to the gate metal layer 50 but connected via the pad connection portion 125. In this case, the pad connection portion 125 is conductive and may be connected to the gate metal layer 50 outside the gate pad 112 in a top view, and may be connected to the gate metal layer 50 in the same manner as the connection to the pad electrode 51.

[0335] The barrier metal film 1342 may be provided up to the end of the pad electrode 51. The pad electrode 51 may be provided wider than the end of the pad connection portion 125. In other examples, the pad electrode 51 may not be provided up to the end of the pad connection portion 125.

[0336] Figure 29A shows an example of a region P including a part of the g-g' cross-section in Figure 19A and its surroundings. In this figure, the polycrystalline portion 132 and the housing portion 198 are repeatedly arranged in the X-axis direction on and around the g-g' cross-section. Each polycrystalline portion 132 is connected to one another at a location away from the g-g' cross-section in the Y-axis direction. The polycrystalline portions 132 may be arranged in a comb-like pattern as described above. By providing multiple contact holes 53 across the housing portion 198 and the polycrystalline portion 132, the polycrystalline portions 132 arranged repeatedly in the X-axis direction can be connected to the pad electrode 51. Alternatively, the arrangement shown in this example may be repeatedly arranged by translating or inverting it along the X or Y axis.

[0337] Figure 29B shows another example of region P, including a part of the g-g' cross-section shown in Figure 19A and its surroundings. In this figure, the polycrystalline portion 132 and the housing portion 198 are repeatedly arranged in the X-axis direction on and around the g-g' cross-section. Each polycrystalline portion 132 is connected to one another at a location away from the g-g' cross-section in the Y-axis direction. As described above, the polycrystalline portion 132 may be arranged to have a plurality of housing portions 198 discretely inside. By providing a plurality of contact holes 53 across the housing portion 198 and the polycrystalline portion 132, the polycrystalline portions 132 arranged repeatedly in the X-axis direction and the pad electrode 51 can be connected. Alternatively, the arrangement shown in this example may be repeatedly arranged by translating or inverting it along the X or Y axis. The arrangement of the polycrystalline portion 132 shown in Figures 29A and 29B may be applied not only to the arrangement of the pad connection portion 125 and the contact hole 53, but also to the arrangement of the connection portion 25, the contact hole 55 and the contact hole 56 in the other inactive portion 130, the arrangement of the field plate 144 and the contact hole 57, and the arrangement of the temperature-sensing anode region 182, the temperature-sensing cathode region 181 and the contact hole 58 in the temperature-sensing portion 180.

[0338] Figure 29C shows another example of region P, which includes a part of the g-g' cross-section shown in Figure 19A and its surroundings. In this figure, the polycrystalline portion 132 and the housing portion 198 are repeatedly arranged in the X-axis direction on and around the g-g' cross-section. Each polycrystalline portion 132 is not connected to one another. As described above, the polycrystalline portions 132 may be arranged discretely. By providing multiple contact holes 53 across the housing portion 198 and the polycrystalline portion 132, the polycrystalline portions 132 that are repeatedly arranged in the X-axis direction can be connected to the pad electrodes 51. If the pad connection portion 125 is not connected to other components of the semiconductor device 100, each polycrystalline portion 132 may not be connected to one another. The polycrystalline portions 132 may also be arranged discretely in the Y-axis direction.

[0339] Figure 30 shows another example of the g-g' cross section in Figure 19A. The semiconductor device 100 in this example differs from the embodiment in Figure 28 in that the first inactive contact portion 134 has a trench contact structure. Otherwise, it may be the same as the embodiment in Figure 28. When the first inactive contact portion 134 has a trench contact structure, the first inactive contact portion 134 may extend from the upper surface of the polycrystalline portion 132 in the depth direction of the semiconductor substrate 10. The active contact portion 124 may have the planar contact structure in Figure 1B or the trench contact structure in Figure 10B.

[0340] The semiconductor device 100 in this example differs from the embodiment in Figure 28 in that the structure of the first inactive contact portion 134 is different. In this example, the differences from the embodiment in Figure 28 will be explained in detail, and other aspects may be the same as those of the embodiment in Figure 28.

[0341] The sidewall of the first inactive contact portion 134 may have a trench contact structure that contacts the side surface of the polycrystalline portion 132. In this example, the bottom corner portion 1340 of the first inactive contact portion 134 contacts the polycrystalline portion 132 at the side surface of the polycrystalline portion 132.

[0342] The sidewall of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132 and the interlayer insulating film 38. The polycrystalline portion 132 may be in contact with the sidewall of the first inactive contact portion 134 from the bottom corner portion 1340 to an area of ​​10% to 90% of the sidewall of the first inactive contact portion 134. That is, the ratio of the area of ​​the sidewall of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 to the area of ​​the sidewall of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 may be 10% to 90%. Referring to Figure 30, length L3 is the length of the side wall of the first inactive contact portion 134 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10, and length L4 is the length of the side wall of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L4 to length L3 may be 10% or more and 90% or less. In this example, the polycrystalline portion 132 is in contact with the side wall of the first inactive contact portion 134 from the bottom corner portion 1340 to 35% of the side wall of the first inactive contact portion 134. That is, the ratio of length L4 to length L3 in this example is 35%.

[0343] In the etch-back process of the plug portion 1344, if the plug portion 1344 near the center of the bottom surface of the first inactive contact portion 134 is removed by over-etching, it becomes difficult to fill the first inactive contact portion 134 with the metal material of the pad electrode 51, and a void may be formed near the center of the bottom surface of the first inactive contact portion 134. In this example, the first inactive contact portion 134 is provided with its bottom corner portion 1340 in contact with the polycrystalline portion 132 and its bottom surface in contact with the housing portion 198. Therefore, even if a void is formed inside near the center of the bottom surface of the first inactive contact portion 134, the impact on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corner portion 1340 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the inactive portion 130 ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132, not through the center of the bottom surface of the first inactive contact portion 134, but through the bottom corner portion 1340. This allows for stable quality and improved yield even if a void is formed in the region near the center of the first inactive contact portion 134 that is in contact with the housing portion 198.

[0344] Although Figures 28 to 30 illustrate the gate pad 112, the configuration described for the gate pad 112 may also be applied to other pads. For example, it may be used for the anode pad 116, cathode pad 118, sense electrode 114, and / or any other pad not shown, as depicted in Figure 19A. The pad electrode 51 may be in direct contact with the anode wiring section 117 or cathode wiring section 119, etc., or it may be connected indirectly via the polycrystalline section 132. Although Figure 28 illustrates an example using an XZ cross-section, the longitudinal direction of the contact hole 53 does not have to be the Y-axis direction. For example, the longitudinal direction of the contact hole 53 may be the X-axis direction, or any other direction, and contact holes 53 with different orientations may be combined and used.

[0345] Figure 31 is a flowchart showing an example of the manufacturing process for a semiconductor device 100. The manufacturing process in this example includes a step S200 for forming an active part 120 and a step S210 for forming an inactive part 130. The order of the steps S200 for forming the active part 120 and S210 for forming the inactive part 130 is not limited to this. The inactive part 130 may be formed before the active part 120, and some or all of the steps for forming the active part 120 and some of the steps for forming the inactive part 130 may be the same step.

[0346] Step S210 for forming the inactive portion 130 includes step S212 for forming the third interlayer insulating film 138, step S214 for forming the polycrystalline portion 132, step S216 for forming the interlayer insulating film 38, step S218 for forming the first inactive contact portion 134, and step S220 for forming the housing portion 198.

[0347] In step S212, a third interlayer insulating film 138 is formed on top of the semiconductor substrate 10. The third interlayer insulating film 138 may be an insulating film that insulates the semiconductor substrate 10 from the connection portion 25, an insulating film that insulates the semiconductor substrate 10 from the field plate 144, or an insulating film that insulates the semiconductor substrate 10 from the pad connection portion 125. The third interlayer insulating film 138 may be formed by a method that is common to those skilled in the art. For example, step S212 may be a step in which a gate insulating film 42 is formed in the active portion 120, and the third interlayer insulating film 138 may be a thermal oxide film formed by heating the semiconductor substrate 10. As another example, step S212 may be step S112 in which a second interlayer insulating film 37 is formed in the temperature-sensing portion 180.

[0348] In step S214, a polycrystalline portion 132 is formed above the semiconductor substrate 10. The polycrystalline portion 132 may be formed above the third interlayer insulating film 138. The polycrystalline portion 132 may be a connection portion 25 that electrically connects the emitter electrode 52 and the dummy conductive portion 34, a connection portion 25 that electrically connects the gate metal layer 50 and the gate conductive portion 44, a field plate 144, or a pad connection portion 125 provided below the pad electrode 51. The polycrystalline portion 132 may be formed by a method common to those skilled in the art. For example, step S214 may be a step in which the gate conductive portion 44 in the active portion 120 is formed, and the polycrystalline portion 132 may be formed by depositing impurity-doped polysilicon above the semiconductor substrate 10. As another example, step S212 may be step S114, in which undoped polysilicon is deposited above the semiconductor substrate 10 in the temperature-sensing portion 180, followed by implantation of impurity ions and annealing treatment.

[0349] In step S216, an interlayer insulating film 38 is formed above the polycrystalline portion 132. The interlayer insulating film 38 may be formed by stacking multiple insulating films. Step S216, in which the interlayer insulating film 38 is formed, may be a step in which the interlayer insulating film 38 is formed on the active portion 120.

[0350] In step S218, a first inactive contact portion 134 is formed extending from the upper surface to the lower surface of the interlayer insulating film 38. Step S218, in which the first inactive contact portion 134 is formed, may be the step in which an active contact portion 124 is formed in the active portion 120 extending from the upper surface to the lower surface of the interlayer insulating film 38. However, the first inactive contact portion 134 and the active contact portion 124 may be formed in different processes.

[0351] Step S218, which forms the first inactive contact portion 134, may include a step of forming contact holes 53, 55, 56, and / or 57 by etching the interlayer insulating film 38. Contact hole 59 may also be formed in this step. Contact hole 54 may also be formed in the interlayer insulating film 38 of the active portion 120. Contact hole 58 may also be formed in the interlayer insulating film 38 of the temperature-sensing portion 180. However, these contact holes may be formed in different steps.

[0352] Step S218, which involves forming the first inactive contact portion 134, may include a step of forming a barrier metal film 1342. The barrier metal film 1342 may be formed by forming a metal film inside the contact holes 53, 55, 56, and / or 57, and then annealing in a nitrogen atmosphere. For example, the barrier metal film 1342 may be formed by forming a Ti film inside the contact holes 53, 55, 56, and / or 57, and then annealing in a nitrogen atmosphere. In this case, a TiN film may be formed by annealing the Ti film. In this step, a barrier metal film may be formed on the active contact portion 124 and / or the second inactive contact portion 135.

[0353] Step S218, which involves forming the first inactive contact portion 134, may include a step of forming the plug portion 1344. For example, the plug portion 1344 may be formed by forming tungsten to fill the inside of the contact holes 53, 55, 56, and / or 57 by the CVD (Chemical Vapor Deposition) method. In this step, the plug portion may be formed in the active contact portion 124 and / or the second inactive contact portion 135.

[0354] Step S218, which forms the first inactive contact portion 134, may include a step of etching back the plug portion 1344. This may remove any unwanted tungsten film outside the contact holes 53, 55, 56, and / or 57. However, the plug portion 1344 may be provided on a part of the first inactive contact portion 134, and may extend beyond the contact holes 53, 55, 56, and / or 57, reaching above the interlayer insulating film 38. Etching back may be performed by dry etching or CMP (Chemical Mechanical Polishing). When the tungsten film outside the contact holes is removed, the barrier metal film 1342 outside the contact holes may also be removed. The barrier metal film 1342 may be removed in a separate step from the etching back of the plug portion 1344. The barrier metal film 1342 may not be removed. In this process, the plug portions of the active contact portion 124 and / or the second inactive contact portion 135 may be etched back.

[0355] If the barrier metal film 1342 and / or plug portion 1344 are not provided on the first inactive contact portion 134, the above steps may be omitted. In this case, the insides of the contact holes 53, 55, 56, and / or contact holes 57 may be filled at the same time as the step of providing the pad electrode 51, emitter electrode 52, gate metal layer 50 and / or edge metal layer 146, thereby forming the first inactive contact portion 134.

[0356] In step S218, in which the first inactive contact portion 134 is formed, the first inactive contact portion 134 may be formed such that the bottom corner portion 1340 of the first inactive contact portion 134 is in contact with the polycrystalline portion 132. In step S218, in which the first inactive contact portion 134 is formed such that the bottom surface of the first inactive contact portion 134 is in contact with the housing portion 198.

[0357] In this example, the bottom corner portion 1340 of the first inactive contact portion 134 is in contact with the polycrystalline portion 132, and the bottom surface is in contact with the housing portion 198. This ensures reliable electrical connection between the pad electrode 51, emitter electrode 52, gate metal layer 50 and / or edge metal layer 146 and the polycrystalline portion 132. In this example, since the bottom surface of the first inactive contact portion 134 is in contact with the housing portion 198, even if the plug portion 1344 and barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 1344 are removed by over-etching during the etch-back process of the plug portion 1344, and a void is created inside the first inactive contact portion 134, the impact on the electrical connection at the bottom corner portion 1340 between the first inactive contact portion 134 and the polycrystalline portion 132 can be suppressed, thereby improving the yield of semiconductor device 100 having the desired characteristics. In other words, by ensuring the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 through the bottom corner portion 1340 rather than the bottom center portion of the first inactive contact portion 134, stable quality can be obtained and yield can be improved even if a void is formed in the region near the center of the first inactive contact portion 134 that is in contact with the housing portion 198.

[0358] In step S220, a housing portion 198 is formed below the first inactive contact portion 134. The order of the steps S220 for forming the housing portion 198 is not limited thereto. The step S220 for forming the housing portion 198 may be included in the step S214 for forming the polycrystalline portion 132, or in the step S216 for forming the interlayer insulating film 38.

[0359] For example, in the embodiments shown in Figures 12A, 14A, 16A, 18A, 21A, 23A, 25A, 27A, or 28 to 30, the housing portion 198 is a region of the interlayer insulating film 38 located below the first inactive contact portion 134. In this case, the step S220 for forming the housing portion 198 may be included in the step S216 for forming the interlayer insulating film 38.

[0360] As another example, in the embodiment shown in Figures 21C, 23C, 25B, 27B, or 28 to 30, the housing portion 198 has polysilicon. In this case, step S220 for forming the housing portion 198 may be included in step S214 for forming the polycrystalline portion 132. The polycrystalline portion 132 and the housing portion 198 may be formed by laminating undoped polysilicon in the regions that will become the housing portion 198 and the polycrystalline portion 132, implanting impurity ions into each region, and performing an annealing treatment.

[0361] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0362] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be performed in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, this does not mean that it is mandatory to perform the operations in that order. [Explanation of symbols]

[0363] 10...Semiconductor substrate, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 17...Well region, 18...Drift region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 30...Dummy trench portion, 31...Extended portion, 32...Dummy insulating film, 33...Connection portion, 34...Dummy conductive portion, 36...First interlayer insulating film, 37...Second interlayer insulating film, 38...Interlayer insulating film, 40...Gate trench 41... Extended portion, 42... Gate insulating film, 43... Connection portion, 44... Gate conductive portion, 50... Gate metal layer, 51... Pad electrode, 52... Emitter electrode, 53... Contact hole, 54... Contact hole, 55... Contact hole, 56... Contact hole, 57... Contact hole, 58... Contact hole, 59... Contact hole, 70... Transistor portion, 71... Mesa portion, 80... Diode portion, 81... Mesa portion, 82... Cathode region, 90... Boundary portion, 91... Mesa section, 100... Semiconductor device, 102... Edge, 112... Gate pad, 114... Sense electrode, 115... Current sense section, 116... Anode pad, 117... Anode wiring section, 118... Cathode pad, 119... Cathode wiring section, 120... Active section, 122... Active trench section, 124... Active contact section, 125... Pad connection section, 130... Inactive section, 132... Polycrystalline section, 134... First inactive contact section, 135... Second inactive contact section, 138... Third interlayer insulating film, 140... Edge termination structure, 142...guard ring, 144...field plate, 146...edge metal layer, 148...field insulating film, 151...backside lifetime control region, 152...frontside lifetime control region, 170...Zener diode section, 180...temperature sensing section, 181...temperature sensing cathode region, 182...temperature sensing anode region, 183...temperature sensing diode, 188...temperature sensing contact section, 198...housing section, 200...recess, 300...contact region, 302...void, 1340...bottom corner section,1242... Barrier metal film, 1244... Plug section, 1342... Barrier metal film, 1344... Plug section, 1352... Barrier metal film, 1354... Plug section, 1420... Non-corner area, 1422... Corner area, 1880... Bottom corner section, 1882... Barrier metal film, 1884... Plug section,

Claims

1. An active part provided on a semiconductor substrate, A temperature-sensing section provided above the semiconductor substrate, Equipped with, The aforementioned temperature sensing element is A temperature-sensitive diode is provided above the semiconductor substrate, A first interlayer insulating film is provided above the temperature-sensitive diode, A temperature-sensitive contact portion is provided extending from the upper surface to the lower surface of the first interlayer insulating film, A housing portion provided below the temperature-sensing contact portion, It has, The bottom corner of the temperature-sensing contact portion is in contact with the temperature-sensing diode. The bottom surface of the temperature-sensing contact portion is in contact with the housing portion. Semiconductor equipment.

2. The side surface of the temperature-sensing diode is in contact with the side surface of the housing portion. The semiconductor device according to claim 1.

3. The semiconductor substrate comprises a second interlayer insulating film provided between the temperature-sensitive diode and the semiconductor substrate in the depth direction. The semiconductor device according to claim 1.

4. The upper surface of the second interlayer insulating film is in contact with the lower surface of the temperature-sensitive diode and the lower surface of the housing portion. The semiconductor device according to claim 3.

5. The housing portion is a region of the first interlayer insulating film located below the temperature-sensitive contact portion. The semiconductor device according to claim 1.

6. The housing portion is the second interlayer insulating film provided above the semiconductor substrate. The semiconductor device according to claim 3.

7. The second interlayer insulating film has a recess on its upper side, The temperature-sensing diode is provided in the recess of the second interlayer insulating film. The semiconductor device according to claim 3.

8. The temperature-sensing diode has a contact area that is in contact with the housing portion, The housing portion has a polycrystalline semiconductor with a different conductivity type than the contact region of the temperature-sensing diode. The semiconductor device according to claim 1.

9. The temperature-sensing diode has a contact area that is in contact with the housing portion, The housing portion has the same conductivity type as the contact region of the temperature-sensing diode and comprises a polycrystalline semiconductor with a lower doping concentration than the contact region. The semiconductor device according to claim 1.

10. The aforementioned temperature-sensitive diode is A temperature-sensitive anode region provided above the semiconductor substrate, A temperature-sensitive cathode region is provided above the semiconductor substrate and is in contact with the temperature-sensitive anode region, has The semiconductor device according to claim 1.

11. The aforementioned temperature-sensing contact portion is A barrier metal film provided at the bottom corner of the temperature-sensing contact portion, A plug portion provided in contact with the inside of the barrier metal film, has The semiconductor device according to claim 1.

12. The active portion has a plurality of active contact portions provided on the front surface of the semiconductor substrate. The semiconductor device according to claim 1.

13. The bottom surface of the temperature-sensing contact portion is in contact with the temperature-sensing diode and the housing portion. The semiconductor device according to any one of claims 1 to 12.

14. The temperature-sensing diode is in contact with the bottom surface of the temperature-sensing contact portion from the bottom corner to an area of ​​10% to 40% of the bottom surface of the temperature-sensing contact portion. The semiconductor device according to claim 13.

15. The side wall of the temperature-sensing contact portion has a trench contact structure that contacts the side surface of the temperature-sensing diode. The semiconductor device according to any one of claims 1 to 12.

16. The side wall of the temperature-sensing contact portion is in contact with the temperature-sensing diode and the first interlayer insulating film. The temperature-sensing diode is in contact with the side wall of the temperature-sensing contact portion from the bottom corner to an area of ​​10% to 90% of the side wall of the temperature-sensing contact portion. The semiconductor device according to claim 15.

17. The steps include forming an active portion on a semiconductor substrate, The steps include forming a temperature-sensing portion on top of the semiconductor substrate, Equipped with, The step of forming the temperature-sensing part is, The steps include forming a temperature-sensitive diode on top of the semiconductor substrate, The steps include forming a first interlayer insulating film above the temperature-sensitive diode, The steps include forming a temperature-sensitive contact portion extending from the upper surface to the lower surface of the first interlayer insulating film, The steps include forming a housing portion below the temperature-sensing contact portion, It has, The bottom corner of the temperature-sensing contact portion is in contact with the temperature-sensing diode. The bottom surface of the temperature-sensing contact portion is in contact with the housing portion. A method for manufacturing a semiconductor device.

18. A semiconductor device comprising an active portion and an inactive portion, The inactive portion is A polycrystalline portion provided above the semiconductor substrate, An interlayer insulating film provided above the polycrystalline portion, A first inactive contact portion is provided extending from the upper surface to the lower surface of the interlayer insulating film, A housing portion provided below the first inactive contact portion, It has, The bottom corner of the first inactive contact portion is in contact with the polycrystalline portion, The bottom surface of the first inactive contact portion is in contact with the housing portion. Semiconductor equipment.

19. The side surface of the polycrystalline portion is in contact with the side surface of the housing portion. The semiconductor device according to claim 18.

20. The housing portion is a region of the interlayer insulating film located below the first inactive contact portion. The semiconductor device according to claim 18.

21. The first inactive contact portion is A barrier metal film provided at the bottom corner of the first inactive contact portion, A plug portion provided in contact with the inside of the barrier metal film, has The semiconductor device according to claim 18.

22. The active portion has a plurality of active contact portions provided on the front surface of the semiconductor substrate. The semiconductor device according to claim 18.

23. The bottom surface of the first inactive contact portion is in contact with the polycrystalline portion and the housing portion. The semiconductor device according to claim 18.

24. The polycrystalline portion is in contact with the bottom surface of the first inactive contact portion from the bottom surface corner to an area of ​​10% to 40% of the bottom surface of the first inactive contact portion. The semiconductor device according to claim 23.

25. The sidewall of the first inactive contact portion has a trench contact structure that is in contact with the side surface of the polycrystalline portion. The semiconductor device according to claim 18.

26. The sidewall of the first inactive contact portion is in contact with the polycrystalline portion and the interlayer insulating film, The polycrystalline portion is in contact with the side wall of the first inactive contact portion from the bottom corner to a region of 10% to 90% of the side wall of the first inactive contact portion. The semiconductor device according to claim 25.

27. A gate trench portion having a gate conductive portion is provided on the front surface of the semiconductor substrate, A gate metal layer provided above the semiconductor substrate and electrically connected to the gate conductive portion, Equipped with, The aforementioned polycrystalline portion is The gate metal layer is connected via the first inactive contact portion, The gate conductive part is connected to the gate conductive part. The semiconductor device according to any one of claims 18 to 26.

28. A dummy trench portion having a dummy conductive portion is provided on the front surface of the semiconductor substrate, An emitter electrode provided above the semiconductor substrate and electrically connected to the semiconductor substrate, Equipped with, The aforementioned polycrystalline portion is The emitter electrode is connected via the first inactive contact portion, The dummy conductive part is connected to The semiconductor device according to any one of claims 18 to 26.

29. On the front surface of the semiconductor substrate, a second conductive type guard ring is provided between the active portion and the edge of the semiconductor substrate, An edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring, Equipped with, The polycrystalline portion is connected to the edge metal layer via the first inactive contact portion. The semiconductor device according to any one of claims 18 to 26.

30. A field insulating film is provided below the interlayer insulating film, The first inactive contact portion is provided above the polycrystalline portion above the field insulating film. The semiconductor device according to claim 29.

31. On the front surface of the semiconductor substrate, a second conductive type guard ring is provided between the active portion and the edge of the semiconductor substrate, An edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring, A field insulating film provided below the interlayer insulating film, Equipped with, The polycrystalline portion is connected to the edge metal layer via the first inactive contact portion, The housing portion is a region of the field insulating film located below the first inactive contact portion. The semiconductor device according to any one of claims 18, 19, or 21 to 26.

32. On the front surface of the semiconductor substrate, a second conductive type guard ring is provided between the active portion and the edge of the semiconductor substrate, An edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring, Equipped with, The polycrystalline portion is connected to the edge metal layer via the first inactive contact portion, The polycrystalline portion has a contact area that is in contact with the housing portion, The housing portion has a polycrystalline semiconductor with a lower impurity concentration than the contact region of the polycrystalline portion. The semiconductor device according to any one of claims 18, 19, or 21 to 26.

33. The semiconductor substrate is provided with pad electrodes located above it, The aforementioned polycrystalline portion is The first inactive contact portion is connected to the pad electrode. The semiconductor device according to any one of claims 18 to 26.

34. The step of forming the active site, The step of forming an inactive part, Equipped with, The step of forming the inactive portion is: The steps include forming a polycrystalline portion on top of the semiconductor substrate, The steps include forming an interlayer insulating film above the polycrystalline portion, The steps include forming a first inactive contact portion extending from the upper surface to the lower surface of the interlayer insulating film, The steps include forming a housing portion below the first inactive contact portion, It has, The bottom corner of the first inactive contact portion is in contact with the polycrystalline portion, The bottom surface of the first inactive contact portion is in contact with the housing portion. A method for manufacturing a semiconductor device.

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