Inductive coupling structure for reducing crosstalk effects in parallel bus technology

Abstract

To provide an inductive coupling structure for reducing crosstalk effect in a parallel bus technology.SOLUTION: A device including a circuit board according to an embodiment includes a circuit board having a parallel bus with a first trace and a second trace, a first induction coil coupled to the first trace, and a second induction coil coupled to the second trace, and the first induction coil and the second induction coil are arranged to be inductively coupled to each other to reduce crosstalk effect in the parallel bus.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] The present disclosure relates generally to the field of computer systems, and more particularly to inductive coupling structures for parallel bus technology.

Background Art

[0002] One issue in high-speed parallel bus design is to mitigate crosstalk resulting from, for example, high-density routing and vertical transitions on a circuit board in a system-on-chip (SoC) die, package, and / or motherboard. Both channel loss and impedance discontinuities can contribute to additional problems caused by inter-symbol interference (ISI) and crosstalk.

Brief Description of the Drawings

[0003] [Figure 1A] FIG. 1A shows exemplary parallel bus systems with and without an inductive coupling structure according to the present disclosure. [Figure 1B] FIG. 1B shows exemplary parallel bus systems with and without an inductive coupling structure according to the present disclosure. [Figure 1C] FIG. 1C shows exemplary parallel bus systems with and without an inductive coupling structure according to the present disclosure. [Figure 1D] FIG. 1D shows exemplary parallel bus systems with and without an inductive coupling structure according to the present disclosure. [Figure 2A] FIG. 2A shows an exemplary inductive coupling structure of opposite polarities. [Figure 2B] FIG. 2B shows an exemplary inductive coupling structure of opposite polarities. [Figure 3A] FIG. 3A shows an exemplary inductive coupling structure according to the present disclosure. [Figure 3B] FIG. 3B shows exemplary invasive waveforms and victim waveforms on the exemplary inductive coupling structure of FIG. 3A. [Figure 4] FIG. 4 shows exemplary channel response waveforms with and without an inductive coupling structure according to an embodiment of the present disclosure. ​ [Figure 5] Figure 5 shows an exemplary ISI eye diagram illustrating the simulation results of systems with and without an inductively coupled structure according to embodiments of the present disclosure. [Figure 6] Figure 6 shows an exemplary tapped coil system that can be used in the inductive coupling structure of this disclosure. [Figure 7] Figure 7 shows an exemplary circuit board including an inductively coupled structure according to an embodiment of the present disclosure. [Figure 8A] Figure 8A shows an exemplary coil shape that may be implemented within the inductive coupling structure of this disclosure. [Figure 8B] Figure 8B shows an exemplary coil shape that may be implemented within the inductive coupling structure of this disclosure. [Figure 8C] Figure 8C shows an exemplary coil shape that may be implemented within the inductive coupling structure of this disclosure. [Figure 9] Figure 9 illustrates a processor according to one embodiment. [Figure 10] Figure 10 shows a computer system arranged in a PtP configuration according to one embodiment.

[0004] Similar reference numerals and names in various drawings refer to the same elements. [Modes for carrying out the invention]

[0005] The following description includes numerous specific details, such as examples of particular configurations, structures, and architectural details, in order to provide a complete understanding of the disclosure. However, it will be apparent to those skilled in the art that these specific details are not necessarily required to implement embodiments of the disclosure. In some examples, well-known components or methods can be utilized, and such details are not described in detail to avoid unnecessarily obscuring embodiments of the disclosure.

[0006] In parallel bus channels (e.g., memory bus channels), far-end crosstalk (FEXT) can be dominated by inductive crosstalk. This can result from crosstalk from vias and connectors, microstrip segments, or from vertical transitions that are inherently inductive (due to longer return loops). Furthermore, in many memory circuit board packets (e.g., dynamic random-access memory packages), mutual inductance effects are observed to be more dominant than mutual capacitance effects, and overall, channels tend to be dominated by inductive FEXT.

[0007] Symmetrical stripline structures with a uniform medium result in near-zero FEXT, so current design practices may include stripline routing on the motherboard to minimize crosstalk. However, at the same time, uniform, symmetrical striplines do not contribute to neutralizing existing channel crosstalk from the rest of the channel. This necessitates expensive platform solutions that enable high-density parallel bus routing, while miniaturizing the system involves reducing motherboard layers and platform real estate (which may have bill of materials (BOM) relevance).

[0008] Other proposed solutions to the crosstalk problem include: SoC receiver (Rx) side crosstalk cancellation circuits: HPF + adder in the preamplifier or sampler; SoC transmitter (Tx) side phase-based crosstalk cancellation circuits to negate the timing shift resulting from crosstalk; SoC Tx side derived crosstalk cancellation circuits with capacitive coupling; SoC Tx side voltage mode cancellation by sign swing modulation; and stubby lines on the motherboard / PCB to increase capacitive coupling to reduce the overall FEXT. However, the above circuit designs cannot equalize the channel response (the embodiments herein can be used to equalize channel loss / distortion by tuning the series inductance in addition to the crosstalk cancellation capability by tuning the mutual inductance). Furthermore, stubby lines require very complex routing of guidelines on the platform and are therefore difficult to implement.

[0009] Embodiments described herein incorporate a passive, coupled inductive coil structure (e.g., similar to a transformer) on a die that can mitigate a significant amount of inductive crosstalk supplied, for example, in an SoC package or motherboard, resulting in a significant reduction in FEXT across the entire channel. In certain embodiments, for example, the coupled inductive coil structure can be incorporated into active silicon or a passive interposer (designed at the output of a buffer) that, by optimizing the coil winding direction, can generate a neutralizing coupled signal on the damaged trace, which tends to cancel out coupled noise generated from the channel (e.g., SoC package, motherboard, memory device (e.g., DRAM package)), resulting in a significant reduction in overall FEXT within the channel. In some cases, certain embodiments can enable equalization on the transmit (Tx) and / or receive (Rx) sides of the bus to flatten the overall channel response and minimize incident wave distortion that may arise from crosstalk effects.

[0010] This enables cost-effective platform solutions, smaller motherboard sizes, and high-performance, compact form factor systems. Furthermore, the inductive properties of the coupled inductive coil structure described herein can help improve overall ISI behavior by compensating for or equating the channel's inherent low-pass filter (LPF) tendency. Certain embodiments can also compensate for excessive inductive crosstalk in end-to-end channels, enabling higher density routing, for example, pushing higher data rates, enabling smaller motherboards with fewer layers that are not possible with current design techniques, enabling smaller form factors, and / or reducing the risk of higher crosstalk in Type 3 platforms.

[0011] Figures 1A to 1D illustrate exemplary parallel bus systems with and without inductive coupling according to the present disclosure. The illustrated scenarios represent, for example, a processor or system-on-a-chip (SoC) (as a transmitter) writing to memory (as a receiver) in Figures 1A, 1B, and 1D, or a processor / SoC reading from memory in Figure 1C.

[0012] Figure 1A shows an exemplary parallel bus system 100A in which crosstalk effects are observed within a channel. The exemplary system 100A includes two lines 102 and 104, where, in the illustrated example, line 102 is an "aggressor" line that refers to a line that causes crosstalk effects in other lines of the parallel bus, and line 104 is a "victim" line that refers to a line in the parallel bus in which crosstalk effects are observed (e.g., from the aggressor line 102). Lines 102 and 104 can be any suitable electrical path for transmitting signals on the parallel bus. For example, lines 102 and 104 may include traces on a circuit board (e.g., a printed circuit board (PCB)). Each line includes a transmitter circuit (e.g., 112 for line 102 and 114 for line 104) and a receiver circuit (e.g., 122 for line 102 and 124 for line 104).

[0013] In the embodiment shown here, when a signal (e.g., step signal 110) is introduced into the infringement line 102 by the transmitter circuit 112, the signal is generated within the infringement line 104 due to electromagnetic coupling between lines 102 and 104. As a result, the receiver circuit 124 sees a signal (e.g., signal 115) even though the signal was not introduced onto line 104 by the transmitter circuit 114 (i.e., a digital "0" signal). If the signal is introduced onto line 104 (i.e., a digital "1" signal), noise may also be present. These effects can be referred to as crosstalk effects. Furthermore, the signal received by the receiver circuit 122 (e.g., signal 120) is distorted from the original signal (e.g., 110) due to channel loss and intersymbol interference (ISI).

[0014] To neutralize inductive crosstalk generated within a parallel bus (e.g., negative peak noise from a positive rising aggressor), a transmitter-side inductive coupling structure can be introduced in certain embodiments, for example, as shown in Figure 1B and described below. In other embodiments, the inductive coupling structure may be included on the receiver side in addition to or instead of the transmitter-side coupling structure. By correctly selecting the transformer loop direction, the coupling signal polarity can be controlled (either positive or negative amplitude), and solid crosstalk within the channel can be neutralized, as further described below with respect to Figure 2.

[0015] Figure 1B shows an exemplary parallel bus system 100B that includes an inductive coupling structure. In particular, exemplary system 100B includes the same lines 102, 104, transmitter circuits 112, 114 and receiver circuits 122, 124 as system 100A, but also includes inductive coils 142, 144 between the transmitter circuits and the lines. As shown, the introduction of transmitter-side coupling coils 142, 144 results in a more equalized receiver-side waveform and cancellation of crosstalk. In particular, when a signal (e.g., step signal 110) is introduced into line 102 by transmitter circuit 112, the inductive coils 142, 144 generate a signal (e.g., signal 152) and introduce it into line 104 via the inductive coupling of coils 142, 144. The same crosstalk effect as in Figure 1A generates a signal (e.g., 115) as before, but the signal introduced by inductive coupling mixes with this crosstalk-introduced signal (as shown in signal 162 obtained from the combination of 115 and 152) to neutralize the crosstalk effect in the channel. In addition, the signal received by the receiver circuit 122 of line 102 (e.g., 160) is less distorted and more similar to the input signal (e.g., 110).

[0016] FIG. 1C shows an exemplary parallel bus system 100B, but the step signal 110 is introduced at 122 instead of 112 as in FIG. 1B. As shown, regardless of whether the inductive coupling structure is placed on the transmitter side (FIG. 1B) or the receiver side (FIG. 1C), the crosstalk effect can be reduced or neutralized in the same way, showing that only including the inductive coupling structure on one side is sufficient to reduce the crosstalk effect. This can enable backward compatibility in certain scenarios, for example, using a SoC with an inductive coupling structure of the present disclosure that interfaces with a legacy memory without an inductive coupling structure. In some examples, however, the inductive coupling structure can be included on both sides of the bus as in FIG. 1D.

[0017] FIG. 1D shows an exemplary parallel bus system 100C that includes inductive coupling structures on both the transmitting and receiving sides. It will be understood that certain embodiments can include one or both of the receiver and / or transmitter side inductive coupling structures shown in FIG. 1D.

[0018] Exemplary system 100C includes the same lines 102, 104, transmitter circuits 112, 114, receiver circuits 122, 124, and coils 142, 144 as system 100B, but also includes additional inductive coils 146, 148 in front of the receiver circuits. As shown, the introduction of the transmitter-side coupling coils 146, 148 results in more equalized receiver-side waveforms and cancellation of crosstalk. In particular, when a signal (e.g., step signal 110) is introduced onto line 102 by transmitter circuit 112, inductive coils 142, 144 generate a signal (e.g., signal 152) and also introduce it onto line 104 via inductive coupling, and inductive coils 146, 148 generate an additional signal (e.g., signal 154) and introduce it onto line 104 via inductive coupling. The crosstalk effect as in FIG. 1A generates a signal (e.g., 115) as before, but the signals introduced by the inductive coupling structure mix with this crosstalk-introduced signal (as shown by signal 166 obtained from the combination of, e.g., 115, 152, and 154) to neutralize the crosstalk effect within the channel. In addition to this, the signal (e.g., 164) received by receiver circuit 122 on line 102 is less distorted and more similar to the input signal (e.g., 110).

[0019] FIGS. 2A - 2B show exemplary inductive coupling structures of opposite polarities. In particular, FIG. 2A shows an inductive coupling structure with coils 210, 220 having an "opposite" winding direction, i.e., a "differential" winding configuration. As shown, this differential winding configuration of the inductive coupling structure results in a waveform (e.g., 212) with a positive magnitude on the sacrifice line based on a positive step input waveform (e.g., 202). FIG. 2B shows an inductive coupling structure with the same coils 210, 220 but a "derivative" winding structure, i.e., the coils having the same winding direction. As shown, this derivative winding configuration of the inductive coupling structure results in a waveform (e.g., 214) with a negative magnitude on the sacrifice line based on the same positive step input waveform (e.g., 202).

[0020] In some cases, the inductively coupled structure can be deployed on an active die or silicon interposer. The self-inductance can be optimized to extend the transmission bandwidth, e.g., by 3 dB, and the C-die capacitance (LPF) impact can be equalized. Furthermore, the mutual inductance between the coils of the structure can be adjusted to optimize the neutralization pulse amplitude to cancel all-channel crosstalk. As a result, a good ISI response and improved crosstalk cancellation are obtained, increasing the signal-to-noise ratio (SNR) of the parallel bus.

[0021] Figure 3A shows an exemplary inductive coupling structure 300 according to the present disclosure. The exemplary inductive coupling structure includes rectangular coil traces 302, 304, each connected to a reference node trace 306 (which may be connected to ground in a particular example). In particular, the exemplary inductive coupling structure 300 includes the parallel coupling of the coil traces 302, 304 and is implemented on the bottom back metal layer (BM) of a circuit board or die. The coil traces 302, 304 may be selected to be oriented in opposite directions so that the distal end coupling / crosstalk signature is essentially positive.

[0022] A simulation of the exemplary structure 300 shown in Figure 3 was performed. In the simulation, the inductively coupled structure 300 achieves inductance values ​​of approximately 0.3 nH for coils 302 and 304 with dimensions (i.e., 40 μm × 40 μm) as shown in Figure 3. The simulation results are shown in Figure 3B, where the upper waveform 310 represents a 1 V infringement step pulse, and the lower waveform 320 represents the resulting pulse on the infringement line with a relatively low amplitude (approximately 0.04 V at the peak).

[0023] In further simulations, the addition of inductively coupled structures on the LP5 platform operating at 8533MTs speed was studied. An exemplary step response is shown in waveform 412 of Figure 4, simulated to be input to an infringement line (e.g., 102 in Figure 1B). The resulting infringement waveform is shown in the chart below Figure 4. In particular, waveform 414 shows the full channel response of an infringement line where the inductively coupled structure is not in place (e.g., the scenario shown in Figure 1A). As illustrated, the full channel response shown by waveform 416 includes a large negative peak due to the dominant intrinsic accumulated inductive coupling. In contrast, waveform 416 shows the full channel response of an infringement line with the inductively coupled structure, in particular the derived configuration described above, in place (e.g., the scenario shown in Figure 1B). As shown by waveform 416, the addition of inductively coupled structures in the transmitter circuit helps improve the overall channel response.

[0024] Furthermore, high-volume manufacturing (HVM) bit error rate (BER)16 analysis of the channel was performed with and without the inductively coupled structure. The trend of the obtained eye height / eye width is shown in Figure 5, and the numerical results corresponding to Figure 5 are shown in Table 1 below. [Table 1]

[0025] In Table 1 above, the ISI eye height (EH), eye height center (EHC), and eye width (EW) values ​​on the left side of the table represent the eye height, eye height center, and eye width measured without crosstalk (e.g., on the transmitter side). These parameters indicate opportunities to fine-tune the equalization with the optimal inductance of the coils in the inductively coupled structure. The EH, EHC, and EW values ​​on the right side of the table represent the eye parameters convolved with the crosstalk signature to understand the opportunity for crosstalk cancellation with the crosstalk transformer by fine-tuning the mutual coupling of the coils in the inductively coupled structure. The results showed a gain of ~30mV / 12ps with the addition of the inductively coupled structure at 8533MT speed on the LP5 topology.

[0026] In some cases, inductively coupled coils can be implemented to have multiple tap / escape points from the coil, which can implement intermediate coil taps that can be used to selectively adjust the inductance of the coil. Intermediate coil taps can enable control and fine-tuning of the coupled inductance between coils without substantially penalizing the substantially equivalent driver Ron, for example, because the back metal layer used by the coil is a low-resistance metal. These intermediate taps can be routed via a multiplexer that allows selection of a specific tap from a number of taps, providing control over the final coil inductance.

[0027] Figure 6 shows an exemplary tapped coil system 600 that can be used in the inductively coupled structure of the present disclosure. In the illustrated example, the tapped coil system 600 includes a coil 602 with three taps 610, 620, and 630. The taps represent different output paths for a signal input at input 604 (which can be mounted on a Tx circuit (e.g., a Tx pad) as shown). That is, when tap 610 is selected, portion 612 of coil 602 is the effective inductor of the inductively coupled structure appearing at output 606. Similarly, when tap 620 is selected, portions 612 and 622 of coil 602 are the effective inductors of the inductively coupled structure for output 606, and when tap 630 is selected, all portions 612, 622, and 632 of coil 602 are the effective inductors of the inductively coupled structure for output 606.

[0028] In the illustrated example, tap selection is provided by the multiplexer 640 based on a selection signal 642, which is 2 bits in the illustrated example (however, any suitable selection signal may be used in other embodiments). sel0 and sel1 indicate the bit inputs of the selection signal 642 to the multiplexer 640, for example, "00" selects tap 0, "01" selects tap 1, and "10" selects tap 2. In certain embodiments, tap selection can be optimized by specific selection signals provided to the multiplexer 640. In other embodiments, selection can be trained with full platform I / O margin training in other examples. In some examples, taps can be used to change the ratio between coils in an inductively coupled structure, for example, from 1:1 to 2:1 (or any other suitable ratio). It will be understood that any number of taps may be included in the tapped coil system (e.g., fewer or more than the three taps shown in Figure 6).

[0029] Figure 7 shows an exemplary circuit board 710 including an inductively coupled structure according to an embodiment of the present disclosure. For simplicity, it will be understood that Figure 7 does not show each element of the circuit board 710 or the inductively coupled structure, but rather shows a particular part of a circuit board mounting that shows an exemplary arrangement or positioning of an inductive coil structure between existing pads of the circuit board. The exemplary circuit board 710 includes a pad or bump 712, a ground pad 714, and a coil 716 of the inductively coupled structure of the present disclosure. The ground pad 714 may be mounted in some cases to control the inductance of the coil or to shield the coil from other circuit components. Although one coil is shown, it will be understood that other coils may also be included on the circuit board, for example on adjacent layers of the circuit board (for example, as shown in Figure 3). As indicated by the keys in Figure 7, each of these items may be mounted on different layers of the circuit board 710 (for example, the pad 712 on layer 1, the ground pad 714 on layer 2, the coil 716 on layer 3, and a specific trace on layer 4) and may be connected by vias.

[0030] Figures 8A–8C show exemplary coil shapes that can be implemented within the inductive coupling structure of this disclosure. In particular, Figures 8A and 8B show rectangularly molded coils 810 and 820 with different orientations, and Figure 8C shows a coil 830 having a non-uniform shape. Any other suitable molded coils, such as circularly molded coils, elliptically molded coils, hexagonal molded coils, and octagonal molded coils, can be used in the inductive coupling structure of this disclosure.

[0031] Figures 9-10 are block diagrams of exemplary computer architectures that may be used by embodiments disclosed herein. For example, in some embodiments, a computer system may include one or more of the embodiments shown in Figures 9-10 and implement one or more of the embodiments of this disclosure described above. Other computer architecture designs known in the art may also be used for processors and computer systems. In general, suitable computer architectures for embodiments disclosed herein may include, but are not limited to, the configurations shown in Figures 9-10.

[0032] Figure 9 illustrates a processor according to one embodiment. Processor 900 is an example of the type of hardware device that can be used in connection with the above implementation. Processor 900 can be any type of processor, such as a microprocessor, embedded processor, digital signal processor (DSP), network processor, multicore processor, single-core processor, or other device for executing code. Although only one processor 900 is shown in Figure 9, the processor elements may instead include one or more of the processors 900 shown in Figure 9. Processor 900 can be a single-threaded core, and in at least one embodiment, processor 900 may be multithreaded in that it may include two or more hardware thread contexts (or “logical processors”) per core.

[0033] Figure 9 also shows a memory 902 coupled to a processor 900 according to one embodiment. The memory 902 may be any of the broad types of memory (including various layers of the memory hierarchy) known to those skilled in the art or otherwise available. Such memory elements include, but are not limited to, random access memory (RAM), read-only memory (ROM), field-programmable gate array logic blocks (FPGA), erasable programmable read-only memory (EPROM), and electrically erasable programmable ROM (EEPROM).

[0034] The processor 900 can execute any type of instruction relating to the algorithms, processes, or operations detailed herein. In general, the processor 900 can transform elements or articles (e.g., data) from one state or thing to another.

[0035] Code 904 may be one or more instructions executed by processor 900, stored in memory 902, or stored in software, hardware, firmware, or any suitable combination thereof, or, where appropriate, stored in any other internal or external component, device, element, or object based on specific needs. In one example, processor 900 may follow a program sequence of instructions indicated by code 904. Each instruction enters front-end logic 906 and is processed by one or more decoders 908. The decoders may, as their output, generate microoperations such as fixed-width microoperations in a given format, or other instructions, microinstructions, or control signals that reflect the original code instruction. Front-end logic 906 also includes register rename logic 910 and scheduling logic 912, which generally allocate resources and queue operations corresponding to instructions for execution.

[0036] The processor 900 may also include an execution logic 914 having a set of execution units 916a, 916b, 916n, etc. Some embodiments may include a number of execution units dedicated to a particular function or set of functions. Other embodiments may include only one execution unit or just one execution unit capable of performing a particular function. The execution logic 914 performs the operations specified by the code instructions.

[0037] After the execution of the operation specified by the code instruction is complete, the backend logic 918 can retire the instruction of code 904. In one embodiment, the processor 900 allows non-sequential execution but requests instruction retirement in order. The retirement logic 920 can take various known forms (e.g., a reorder buffer). In this way, during the execution of code 904, the processor 900 is converted with respect to at least the output generated by the decoder, the hardware registers and tables used by the register rename logic 910, and any registers (not shown) modified by the execution logic 914.

[0038] Although not shown in Figure 9, the processing element may include other elements on the chip having the processor 900. For example, the processing element may include memory control logic together with the processor 900. The processing element may include I / O control logic and / or input / output control logic integrated with the memory control logic. The processing element may also include one or more caches. In some embodiments, non-volatile memory (such as flash memory or fuses) may also be included on the chip together with the processor 900.

[0039] Figure 10 shows a computer system arranged in a point-to-point (PtP) configuration according to one embodiment. In particular, Figure 10 shows a system in which a processor, memory, and input / output devices are interconnected by multiple point-to-point interfaces. Generally, one or more computing systems described herein may be configured in the same or similar manner as computer system 1000.

[0040] Processors 1070 and 1080 may also include integrated memory controller logic (MC) 1072 and 1082, respectively, to communicate with memory elements 1032 and 1034. In an alternative embodiment, the memory controller logic 1072 and 1082 may be discrete logic separate from processors 1070 and 1080. Memory elements 1032 and / or 1034 can store various data used by processors 1070 and 1080 in achieving the operations and functionalities outlined herein.

[0041] Processors 1070 and 1080 may be any type of processor, such as those described in relation to other figures. Processors 1070 and 1080 may exchange data via point-to-point (PtP) interface 1050 using point-to-point interface circuits 1078 and 1088, respectively. Processors 1070 and 1080 may exchange data with chipset 1090 via individual point-to-point interfaces 1052 and 1054 using point-to-point interface circuits 1076, 1086, 1094, and 1098, respectively. Chipset 1090 may also exchange data with coprocessor 1038, such as a high-performance graphics circuit, a machine learning accelerator, or another coprocessor 1038, via interface 1039, which may be a PtP interface circuit. In alternative embodiments, any or all of the PtP links shown in Figure 10 may be implemented as a multidrop bus rather than a PtP link.

[0042] The chipset 1090 may communicate with the bus 1020 via the interface circuit 1096. The bus 1020 may have one or more devices that communicate through it, such as the bus bridge 1018 and the I / O device 1016. Through the bus 1010, the bus bridge 1018 can communicate with other devices such as the user interface 1012 (such as a keyboard, mouse, touchscreen, or other input device), the communication device 1026 (such as a modem, network interface device, or other type of communication device that can communicate via the computer network 1060), the audio I / O device 1016, and / or the data storage device 1028. The data storage device 1028 can store code 1030 that can be executed by the processors 1070 and / or 1080. In alternative embodiments, any part of the bus architecture can be implemented with one or more PtP links.

[0043] The computer system shown in Figure 10 is a schematic diagram of an embodiment of a computer system that may be used to carry out the various embodiments described herein. It will be understood that the various components of the system shown in Figure 10 can be combined in a system-on-chip (SoC) architecture or in any other suitable configuration that can achieve the functions and features of the embodiments and implementations provided herein.

[0044] Some of the systems and solutions described and illustrated herein have been described as including or relating to multiple elements, but not all elements explicitly illustrated or described may be used in each alternative embodiment of this disclosure. Furthermore, one or more of the elements described herein may be located outside of a system, but in other examples, some elements may be included within or as part of one or more other described elements, and as other elements not described in the illustrated embodiments. Furthermore, some elements may be combined with other components in addition to the purposes described herein, and may be used for alternative or additional purposes.

[0045] Furthermore, it should be understood that the embodiments described above are non-limiting embodiments provided solely for the purpose of illustrating certain principles and features, and do not necessarily limit or restrict potential embodiments of the concepts described herein. For example, various different embodiments can be realized by utilizing various combinations of the features and components described herein, including combinations realized through various implementations of the components described herein. Other implementations, features, and details should be understood from the contents of this specification.

[0046] While this disclosure has described specific implementations and generally related methods, modifications and substitutions of these implementations and methods will be apparent to those skilled in the art. For example, the actions described herein may be performed in a different order than described, and the desired results may still be achieved. In one embodiment, the process shown in the accompanying drawings does not necessarily require the specific order or sequence shown to achieve the desired results. In certain implementations, multitasking and parallel processing may be advantageous. Furthermore, other user interface layouts and functions may be supported. Other modifications are within the scope of the following claims.

[0047] This specification includes many specific implementation details, but these should not be interpreted as limiting the scope of any embodiment or what can be claimed, but rather as a description of features specific to a particular embodiment of a particular invention. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable subcombination. Furthermore, features are described above as acting in a particular combination and may be initially claimed as such, but one or more features from a claimed combination may, in some cases, be extracted from the combination, and the claimed combination may be directed to a subcombination or a variation of a subcombination.

[0048] Similarly, while the drawings show operations or actions in a specific order, this should not be understood as requiring such actions to be performed in the specific order shown or in a sequential order, or to perform all the exemplified actions, in order to achieve the desired result. Under certain circumstances, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated within a single software product or packaged within multiple software products.

[0049] The following examples relate to embodiments in accordance with this specification. It will be understood that in certain embodiments, certain embodiments may be combined with certain other embodiments.

[0050] Embodiment 1 is an apparatus comprising a circuit board, the circuit board comprising a parallel bus having a first trace and a second trace, a first induction coil coupled to the first trace, and a second induction coil coupled to the second trace, wherein the first induction coil and the second induction coil are arranged to be inductively coupled to each other.

[0051] Embodiment 2 includes the subject matter of Embodiment 1, wherein the first coil is located on the first layer of the circuit board and the second coil is located on the second layer of the circuit board.

[0052] Example 3 includes the subject matter described in Example 2, wherein the first and second layers are multiple layers on the circuit board that are separated from each other.

[0053] Embodiment 4 includes the subject of Embodiment 1, wherein the first coil comprises one or more taps for selecting between two or more different winding configurations of the first coil.

[0054] Embodiment 5 further comprises a multiplexer coupled to one or more taps, which selects the winding configuration of the first coil based on an input signal to the multiplexer, Includes the subject matter of Example 4.

[0055] Embodiment 6 includes the subject matter of Embodiment 5, wherein the multiplexer is for selecting the winding configuration based on a set of bits input to the multiplexer.

[0056] Example 7 includes the subject of any of Examples 1 to 6, wherein the first coil is wound in the same direction as the second coil.

[0057] Example 8 includes the subject of any of Examples 1 to 6, wherein the first coil is wound in the opposite direction to the second coil.

[0058] Example 9 includes the subject of any of Examples 1 to 8, wherein the first coil and the second coil have the same number of turns.

[0059] Example 10 includes the subject of any of Examples 1 to 9, wherein the first coil and the second coil each have a rectangular shape.

[0060] Example 11 further comprises the subject of any one of Examples 1 to 10, further comprising a grounding pad adjacent to the first induction coil and the second induction coil.

[0061] Embodiment 12 further comprises a transmitter circuit coupled to the parallel bus, the transmitter circuit transmitting a signal on the trace of the parallel bus, and includes the subject matter of any one of Embodiments 1 to 11.

[0062] Example 13 includes the subject of any one of Examples 1 to 11, further comprising a receiver circuit coupled to the parallel bus, the receiver circuit being for receiving signals on the trace of the parallel bus.

[0063] Example 14 includes the subject matter of any of Examples 1 to 13, wherein the device is one or more of a system-on-a-chip (SoC), processor, motherboard, or memory device.

[0064] Embodiment 15 includes a system comprising a transmitter device, a receiver device, and a parallel bus having a set of traces that communicatively couples the transmitter device and the receiver device, wherein the transmitter device comprises an inductive coil coupled to each of the traces of the parallel bus, and the inductive coils are arranged to inductively couple to each other.

[0065] Embodiment 16 includes the subject matter of Embodiment 15, wherein the transmitter device has a circuit board, the first coil of the induction coil is on the first layer of the circuit board, and the second coil of the induction coil is on the second layer of the circuit board.

[0066] Example 17 includes the subject matter of Example 16, wherein the first layer and the second layer are adjacent to each other within the circuit board.

[0067] Example 18 includes the subject of any of Examples 15 to 17, wherein the induction coil has a set of taps, and the transmitter device further has one or more multiplexers for selecting winding configurations of the induction coil.

[0068] Example 19 includes the subject of any of Examples 15 to 17, wherein the induction coil is wound in a derivative configuration.

[0069] Example 20 includes the subject matter of any of Examples 15 to 17, wherein the induction coil is wound in a differential configuration.

[0070] Example 21 includes the subject matter of any of Examples 15 to 20, wherein the induction coil is a first induction coil, the receiver device has second induction coils coupled to each trace of the parallel bus, and the second induction coils are arranged to be inductively coupled to one another.

[0071] Example 22 includes the subject matter of any of Examples 15 to 21, wherein the system is a system-on-a-chip (SoC) or a computer system.

[0072] Example 23 includes the subject matter of any of Examples 15 to 22, wherein the transmitter device is one or more processors or memory devices.

[0073] Example 24 is a circuit board having a parallel bus, wherein the parallel bus has a first trace and a second trace, and a system comprising a circuit board and passive means for inductively coupling the first trace and the second trace.

[0074] Example 25 includes the subject matter of Example 24, further comprising means for selecting the amount of inductive coupling between the first trace and the second trace.

[0075] Example 26 includes the subject matter of Example 24 or 25, wherein the system is a system-on-a-chip (SoC) or a computer system.

[0076] Accordingly, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions described in the claims may be performed in a different order and still achieve the desired results. Furthermore, the processes shown in the accompanying drawings do not necessarily require the specific order or sequence shown to achieve the desired results.

Claims

1. A device equipped with a circuit board, The aforementioned circuit board is A parallel bus having a first trace and a second trace, A first induction coil coupled to the first trace, The device comprises a second induction coil coupled to the second trace, The first induction coil and the second induction coil are arranged to be inductively coupled to each other. The first induction coil is provided with one or more taps for selecting between two or more different winding configurations of the first induction coil. The apparatus further comprises a multiplexer coupled to one or more taps, for selecting the winding configuration of the first induction coil based on an input signal to the multiplexer. Device.

2. The first induction coil is located on the first layer of the circuit board, and the second induction coil is located on the second layer of the circuit board. The apparatus according to claim 1.

3. The first and second layers are multiple layers that are separated from each other in the circuit board. The apparatus according to claim 2.

4. The multiplexer is for selecting the winding configuration based on a set of bits input to the multiplexer. The apparatus according to claim 1.

5. The first induction coil is wound in the same direction as the second induction coil. The apparatus according to any one of claims 1 to 4.

6. The first induction coil is wound in the opposite direction to the second induction coil. The apparatus according to any one of claims 1 to 5.

7. The first induction coil and the second induction coil have the same number of windings. The apparatus according to any one of claims 1 to 6.

8. The first induction coil and the second induction coil are each rectangular in shape. The apparatus according to any one of claims 1 to 7.

9. The grounding pads adjacent to the first induction coil and the second induction coil are further provided. The apparatus according to any one of claims 1 to 8.

10. A transmitter circuit coupled to the parallel bus, the transmitter circuit further comprising a transmitter circuit for transmitting a signal on the trace of the parallel bus, The apparatus according to any one of claims 1 to 9.

11. A receiver circuit coupled to the parallel bus, the receiver circuit further comprises a receiver circuit that receives a signal on the trace of the parallel bus. The apparatus according to any one of claims 1 to 9.

12. The aforementioned device is one or more of a system-on-a-chip (SoC), processor, motherboard, or memory device. The apparatus according to any one of claims 1 to 11.

13. Transmitter device and Receiver device and A parallel bus that communicatively connects the transmitter device and the receiver device, comprising a parallel bus having a set of traces, A system equipped with, The transmitter device comprises a plurality of induction coils coupled to each of the traces of the parallel bus, The plurality of induction coils are arranged to be inductively coupled to one another. At least one of the plurality of induction coils has a set of taps for selecting between two or more different winding configurations of the at least one induction coil. The transmitter device further comprises a multiplexer configured to select the winding configuration of the at least one induction coil based on an input signal to the multiplexer. system.

14. The transmitter device has a circuit board, The first coil of the induction coil is located on the first layer of the circuit board. The second coil of the induction coil is located on the second layer of the circuit board. The system according to claim 13.

15. The first layer and the second layer are adjacent to each other within the circuit board. The system according to claim 14.

16. The plurality of induction coils are wound in the derivation structure, The system according to any one of claims 13 to 15.

17. The aforementioned plurality of induction coils are wound in a differential structure. The system according to any one of claims 13 to 16.

18. The aforementioned at least one induction coil is a first induction coil, The receiving device has a second induction coil coupled to each trace of the parallel bus, The second induction coils are arranged to be inductively coupled to each other. The system according to any one of claims 13 to 17.

19. The aforementioned system is a system-on-a-chip (SoC) or a computer system. The system according to any one of claims 13 to 18.

20. The transmitting device is one or more processors or memory devices. The system according to any one of claims 13 to 19.

21. A circuit board having a first trace and a second trace, Passive means for inductively coupling the first trace and the second trace, Means for selecting the amount of inductive coupling between the first trace and the second trace, A system equipped with, The passive means comprises a first induction coil coupled to the first trace and a second induction coil coupled to the second trace. The means for selecting the amount of inductive coupling comprises a multiplexer coupled to one or more taps provided on the first induction coil, which select between two or more different winding configurations of the first induction coil, and the multiplexer is configured to select the amount of inductive coupling by selecting the winding configuration of the first induction coil based on an input signal to the multiplexer. system.

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