Semiconductor substrate, method for manufacturing a semiconductor substrate and manufacturing equipment, method for manufacturing a semiconductor device

Abstract

The present invention comprises: a template substrate that includes a growth suppression region and a first seed region aligned in a first direction; and a first semiconductor part that is positioned above the template substrate and that includes a nitride semiconductor. The first semiconductor part has: a first protruding portion that extends from the first seed region to a position nearer the upper side than the growth suppression region; a growth suppression film in contact with the first protruding portion; a first base section positioned above the first protruding portion; and a first wing section that is connected to the first base section, and is positioned over a gap, apart from the growth suppression region.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor substrates, etc. [Background technology]

[0002] When a GaN layer is deposited on a different type of substrate, for example, on a sapphire substrate, 10 8 cm -2 On the silicon substrate, 10 9 cm -2 At high defect densities, through-dislocations occur at the interface between dissimilar materials, degrading the properties of semiconductor devices formed on the GaN layer. Therefore, the ELO (Epitaxial Lateral Overgrowth) method has been investigated as a technique for forming a low-defect-density nitride semiconductor layer (e.g., a GaN layer) on a dissimilar substrate. For example, by forming a mask pattern on a base substrate including a dissimilar substrate and a seed layer in which the nitride semiconductor layer does not grow, and growing the nitride semiconductor layer laterally on the mask portion using the seed layer exposed in the opening without a mask portion as a growth starting point, the defect density of the nitride semiconductor layer on the mask portion can be reduced (Patent Document 1). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2013-251304 [Overview of the project] [Problems that the invention aims to solve]

[0004] In the technology described in Patent Document 1, there is a problem in that the planarness of the nitride semiconductor layer decreases when the nitride semiconductor layer growing laterally comes into contact with the mask. [Means for solving the problem]

[0005] The semiconductor substrate according to this disclosure comprises a template substrate including a growth-inhibiting region and a first seed region aligned in a first direction, and a first semiconductor portion located above the template substrate and containing a nitride semiconductor, wherein the first semiconductor portion has a first raised portion extending from the first seed region to a position above the growth-inhibiting region, a growth-inhibiting film in contact with the first raised portion, a first base portion located above the first raised portion, and a first wing portion connected to the first base portion and separated from the growth-inhibiting region and located in a void. [Effects of the Invention]

[0006] The first semiconductor portion containing the nitride semiconductor can be given a low defect density and high flatness. [Brief explanation of the drawing]

[0007] [Figure 1] This is a plan view showing the configuration of the semiconductor substrate according to this embodiment. [Figure 2] This is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. [Figure 3] This is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. [Figure 4] This is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. [Figure 5] This is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. [Figure 6] This is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. [Figure 7] This is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. [Figure 8] This is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to this embodiment. [Figure 9] This flowchart shows the method for manufacturing a semiconductor substrate according to this embodiment. [Figure 10] This is a block diagram of a semiconductor substrate manufacturing apparatus according to this embodiment. [Figure 11] This is a cross-sectional view showing the configuration of the semiconductor substrate in Example 1. [Figure 12] It is a cross-sectional view showing another configuration of the semiconductor substrate of Example 1. [Figure 13] It is a cross-sectional view showing a manufacturing method of the semiconductor substrate of Example 1. [Figure 14] It is a cross-sectional view showing a manufacturing method of the semiconductor substrate of Example 1. [Figure 15] It is a cross-sectional view showing another configuration of the semiconductor substrate of Example 1. [Figure 16] It is a graph showing the scan measurement results of XRD in the comparative example. [Figure 17] It is a graph showing the scan measurement results of XRD of Example 1. [Figure 18] It is a plan view of a semiconductor substrate including an upper layer portion. [Figure 19] It is a cross-sectional view of a semiconductor substrate including an upper layer portion. [Figure 20] It is a plan view showing a method of element isolation in Example 1. [Figure 21] It is a cross-sectional view showing a method of element isolation in Example 1. [Figure 22] It is a schematic diagram showing the configuration of an electronic device according to Example 1. [Figure 23] It is a cross-sectional view showing the configuration of the semiconductor substrate of Example 2. [Figure 24] It is a cross-sectional view showing the configuration of the semiconductor substrate of Example 4. [Figure 25] It is a plan view showing the configuration of the semiconductor substrate of Example 5. [Figure 26] It is a cross-sectional view showing the configuration of the semiconductor substrate of Example 5. [Figure 27] It is a cross-sectional view showing a manufacturing method of a semiconductor substrate. [Figure 28] It is a cross-sectional view showing a manufacturing method of a template substrate. [Figure 29] It is a cross-sectional view showing a manufacturing method of a template substrate. [Figure 30] It is a cross-sectional view showing a manufacturing method of a template substrate. [Figure 31] It is a cross-sectional view showing the configuration of the semiconductor substrate of Example 6. [Figure 32]This is a cross-sectional view showing the configuration of the semiconductor substrate of Embodiment 6. [Figure 33] This is a flowchart showing the method for manufacturing the semiconductor device according to Example 7. [Figure 34] This is a cross-sectional view showing the method for manufacturing the semiconductor device according to Example 7. [Modes for carrying out the invention]

[0008] Figure 1 is a plan view showing the configuration of a semiconductor substrate according to this embodiment. Figure 2 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in Figures 1 and 2, the semiconductor substrate 10 comprises a template substrate TS having a mask pattern 6 including a mask portion 5 and a first opening K1 arranged in a first direction X1, and a first semiconductor portion 8A located above the template substrate TS and containing a nitride semiconductor. The first semiconductor portion 8A has a first raised portion R1 extending from a first seed region S1 located below the first opening K1 to a position above the upper surface of the mask portion 5, a first base portion B1 located above the first raised portion R1, and a first wing portion F1 connected to the first base portion B1 and separated from the mask portion 5 and located on the void JD. The semiconductor substrate 10 may include a growth-inhibiting film 7 in contact with the first raised portion R1. The orientation from the main substrate 1 to the first semiconductor portion 8A is "upward". Viewing an object from a line of sight parallel to the normal direction of the semiconductor substrate 10 (including perspective views) is sometimes called a "planar view." The mask portion 5 and the first opening K1 only need to be aligned in the first direction X1 in the planar view.

[0009] The template substrate TS may have a main substrate 1 with a different lattice constant from the first semiconductor portion 8A, and a seed portion 3 including a first seed region S1. The first opening K1, the first raised portion R1, and the first base portion B1 may overlap in a plan view, and the mask portion 5 and the first wing portion F1 may overlap in a plan view. The first wing portion F1 does not have to be in contact with the side surface of the first raised portion R1.

[0010] As shown in Figures 1 and 2, the semiconductor substrate 10 comprises a template substrate TS including a first seed region S1 (exposed surface of seed portion 3) and a growth suppression region DA (mask portion 5) aligned in a first direction X1, and a first semiconductor portion 8A located above the template substrate TS and containing a nitride semiconductor. The first semiconductor portion 8A has a first raised portion R1 extending from the first seed region S1 to a position above the growth suppression region DA, a first base portion B1 located above the first raised portion R1, and a first wing portion F1 connected to the first base portion B1 and separated from the growth suppression region DA and located on the void JD. The semiconductor substrate 10 may have a growth suppression film 7 in contact with the first raised portion R1 at a position above the growth suppression region DA. The first wing portion F1 does not need to be in contact with the side surface of the first raised portion R1. The first seed region S1 and the growth suppression region DA only need to be aligned in the first direction X1 in a plan view.

[0011] The first semiconductor section 8A mainly contains a nitride semiconductor. Nitride semiconductors can be expressed as, for example, AlxGayInzN (0≦x≦1;0≦y≦1;0≦z≦1;x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0012] The first semiconductor section 8A may be doped (e.g., n-type including a donor) or undoped. A semiconductor substrate means a substrate containing a semiconductor, and the main substrate 1 of the template substrate TS may contain a semiconductor (e.g., silicon, silicon carbide) or it may not contain a semiconductor. An example of a main substrate 1 that does not contain a semiconductor is a sapphire substrate. The main substrate 1 may be a self-supporting substrate (wafer). The main substrate 1 and the seed section 3 together are sometimes called a base substrate. The template substrate TS including the base substrate and the mask pattern 6 is sometimes called a growth substrate.

[0013] The first direction X1 may be the a-axis direction (<11-20> direction) of the first semiconductor part 8A. The second direction X2 may be the m-axis direction (<1-100> direction) of the first semiconductor part 8A (nitride semiconductor such as GaN). The thickness direction Z of the first semiconductor part 8A may be the c-axis direction ( <0001> It can be a direction.

[0014] The first semiconductor portion 8A can be formed by the ELO (Epitaxial Lateral Overgrowth) method, starting from the first raised portion R1 that grew from the seed portion 3 exposed below the first opening K1. Of the first semiconductor portion 8A, the base portion B1 located above the first opening K1 becomes a dislocation inheritance portion with many through dislocations, while the first wing portion F1 located above the mask portion 5 becomes a low-defect portion with a smaller through dislocation density compared to the dislocation inheritance portion.

[0015] In this way, by forming a first raised portion R1, and a first wing portion F1 that extends laterally (parallel to the first direction X1) from the first base portion B1 on the first raised portion R1, and is separated from the mask portion 5 and located on the void JD, a wide first wing portion F1 with low defect density and high flatness can be formed. The entire first wing portion F1 may be separated from the mask portion 5. That is, the entire first wing portion F1 does not have to be in contact with the mask portion 5. This makes it possible to form a wide first wing portion F1 with low defect density and high flatness.

[0016] The semiconductor substrate 10 may include a second semiconductor portion 8C located above the template substrate TS. The template substrate TS has a second seed region S2 adjacent to the first seed region S1 via a mask portion 5, and the second semiconductor portion 8C may include a second raised portion R2 extending from the second seed region S2 to a position above the mask portion 5, a second base portion B2 located above the second raised portion R2, and a second wing portion F2 connected to the second base portion B2, separated from the mask portion 5 and located on the gap JD. The first wing portion F1 and the second wing portion F2 may be aligned in a first direction X1 via a gap GP.

[0017] Hereinafter, the first raised portion R1 and the second raised portion R2 will be collectively referred to as raised portion R, the first semiconductor portion 8A and the second semiconductor portion 8C will be collectively referred to as semiconductor portion 8, the first wing portion F1 and the second wing portion F2 will be collectively referred to as wing portion F, the first base portion B1 and the second base portion B2 will be collectively referred to as base portion B, the first opening K1 and the second opening K2 of the mask pattern 6 will be collectively referred to as opening K, and the first seed region S1 and the second seed region S2 will be collectively referred to as seed region S.

[0018] The growth-inhibiting film 7 may be in contact with the upper surface 5T (growth-inhibiting region DA) of the mask portion 5. The first raised portion R1 may be in contact with the upper surface 5T (growth-inhibiting region DA) of the mask portion 5. The first raised portion R1 may overlap the end portion 5E of the mask portion 5. The mask portion 5 and the growth-inhibiting film 7 can be formed from the same silicon nitride, for example, but in such a case, it is difficult to observe the growth-inhibiting film 7 on the mask portion 5 separately from the mask portion 5. The first wing section F1 may have an edge E1 located above the mask section 5.

[0019] The growth-inhibiting film 7 may be in contact with the side surface RS of the first raised portion R1. This suppresses the growth of the semiconductor portion 8 from the side surface RS, making it easier for voids JD to form. In order to achieve the effects of this embodiment, the growth-inhibiting film 7 only needs to be formed on a part of the side surface RS of the first raised portion R1, and may include a first film portion 7j in contact with the side surface RS of the first raised portion R1 and a second film portion 7i in contact with the upper surface RT of the first raised portion R1. The growth-inhibiting film 7 does not need to be a perfect film, and may be a film containing one or more minute openings (a film with an incomplete shape). By forming the second film portion 7i, the second film portion 7i suppresses penetration dislocations and the like that propagated from the seed portion 3 to the first raised portion R1, and a new effect is obtained in which the surface flatness and crystallinity of the upper surface RT of the first raised portion R1 is improved.

[0020] The side surface RS of the first raised portion R1 may be a tapered surface that narrows towards the top. This allows the width of the void JD facing the back surface of the first wing portion F1 to be wider than the width facing the upper surface 5T of the mask portion 5, thereby enabling the formation of a wide first wing portion F1 with fewer defects. The tapered side surface RS may intersect with the upper surface 5T of the mask portion 5 (growth suppression region DA). The growth suppression film 7 may be in contact with the upper surface RT of the first raised portion R1. Of the growth suppression film 7 in contact with the first raised portion R1, the second film portion 7i located on the upper surface RT of the first raised portion R1 (the portion in contact with the upper surface RT of the first raised portion R1) may be embedded in the first semiconductor portion 8A. This relieves stress from the template substrate TS.

[0021] The first raised portion R1 may have a nitride semiconductor growth starting point PG at a position above the mask portion 5. The growth starting point PG may not be in contact with the growth-inhibiting film 7, or it may be in contact with a portion where the growth-inhibiting film 7 is locally thinned. The corner RC where the upper surface RT and side surface RS of the first raised portion R1 intersect may be included in the growth starting point PG. The corner RC may be located above the mask portion 5. That is, the corner RC and the mask portion 5 may overlap in a plan view.

[0022] In this way, a mask pattern 6 having an opening K is formed, and then a first raised portion R1 is formed, thereby creating a corner portion RC on the first raised portion R1. Then, by forming a growth-inhibiting film 7 in contact with the first raised portion R1, the corner portion RC of the first raised portion R1 can be utilized as a growth-starting point PG. It was found that by forming the first raised portion R1 of the nitride semiconductor by crystal growth from a seed portion 3 (seed region) exposed in the opening K, or by pattern formation by dry etching, etc., and by forming a growth-starting point PG at the upper end of the first raised portion R1 (for example, both corners), a good nitride semiconductor layer (first base portion B1 and first wing portion F1) can be grown even after the growth-inhibiting film 7 is formed on the first raised portion R1, and the number of threading dislocations on the first raised portion R1 can be reduced.

[0023] By using the two corners of the first raised portion R1 (the two corners RC aligned in the first direction X1) as growth starting points PG, lateral film deposition occurs from both sides, and voids can be formed in the first base portion B1 (especially the central portion). Thus, the first base portion B1 may contain voids, which relieves stress from the template substrate TS. The voids may be located above the second film portion 7i of the growth-suppressing film 7. The growth-suppressing film 7 may be a silicon nitride film. The first direction X1 is the <11-20> direction, the upper surface of the first raised portion R1 is a polar surface, and the side surface of the first raised portion R1 may be a semi-polar or non-polar surface. In this way, by using the raised portion R and forming the growth-suppressing film 7 on the upper part of the raised portion R, lateral film deposition (growth) of the nitride semiconductor becomes possible even above the opening K, and defects can be effectively suppressed in the portion of the semiconductor portion 8 located above the growth-suppressing film 7 above the opening K (for example, the base portion B).

[0024] The mask portion 5 and the first opening K1 may each have a shape in which the second direction X2, which is perpendicular to the first direction X1, is the longitudinal direction. The main substrate 1 is a silicon substrate, a sapphire substrate, or a silicon carbide substrate, and the nitride semiconductor included in the first semiconductor portion 8A may be a GaN-based semiconductor.

[0025] Seed section 3 contains argon or oxygen, which are impurities, in a 2 × 10 18 / cm 3 The material may be composed of a nitride semiconductor containing the above components. The thickness of the mask portion 5 may be 50 nm or less. The thickness of the growth-inhibiting film 7 may be thinner than that of the mask portion 5. This suppresses growth on the mask portion while facilitating the growth of the wing portion F from the raised portion R. The thickness of the growth-inhibiting film 7 may be 1 / 3 or less of the thickness of the mask portion 5.

[0026] When the ELO layer is in contact with the mask, the mask must be at least 100 nm thick, and interference between the mask and the ELO layer can impair the surface flatness of the ELO layer. However, in Example 1, the wing portion F is suspended in the hollow and does not come into contact with the mask portion 5, so even if the mask portion 5 is made very thin, the growth of the wing portion F is not inhibited. By thinning the mask portion 5, the flatness of the back surface of the wing portion F is improved. The flatness is improved when the thickness of the mask portion 5 is 50 nm or less, and it can also be set to 30 nm or less.

[0027] The deviation between the c-axis direction of the first base B1 and the c-axis direction of the edge of the first wing F1 may be 0.2 degrees or less. The penetrating dislocation density in the first base B1 and the penetrating dislocation density in the first wing F1 are both 5 × 10 6 [pcs / cm 2 The following may apply: The first semiconductor portion 8A may have two pairs of first wing portions F1 extending from the first base portion B1 in a first direction X1 and in the opposite direction.

[0028] The void JD may have a ratio of 5.0 or greater to the width in the first direction X1 (aspect ratio of the void). The void JD is the space sandwiched between the mask portion 5 (growth suppression region DA) and the first wing portion F1. The ratio of the width of the first wing portion F1 to the thickness in the first direction X1 may be 2.0 or greater, 5.0 or greater, 10 or greater, 20 or greater, or 50 or greater. The width of the first wing portion F1 (width in the first direction X1) may be 7.0 [μm] or greater, 10.0 [μm] or greater, 20.0 [μm] or greater, or 40.0 [μm] or greater. The width of the first wing portion F1 is preferably 80.0 [μm] or less. This reduces the risk of the semiconductor portion 8 bending upward due to gravity. The thickness of the first wing portion F1 may be 10.0 [μm] or less, 5.0 [μm] or less, or 2.0 [μm] or less. As shown in Figure 2, the width of the gap GP may be greater than the thickness of the void JD. The ratio of the width of the first wing portion F1 to the width of the first base portion B1 may be 3.0 or more. The thickness of the void JD may be 3.0 [μm] or less. The thickness (height) of the void JD is the distance from the upper surface (growth suppression region DA) of the mask portion 5 to the lower surface (back surface) of the semiconductor portion 8. The width of the void JD is the distance in the first direction X1 from the side surface of the first raised portion R1 to the edge E1 of the semiconductor portion 8.

[0029] Figures 3 and 4 are cross-sectional views showing alternative configurations of the semiconductor substrate according to this embodiment. As shown in Figure 3, the seed portion 3 may be formed in a pattern (for example, in a stripe pattern aligned in the first direction X1), and the seed portion 3 does not need to be located under the mask portion 5. As shown in Figure 4, a buffer portion 2 may be formed between the seed portion 3 and the main substrate 1. The buffer portion 2 may be planar as shown in Figure 4, or it may be patterned. As shown in Figure 4, the buffer portion 2 and the seed portion 3 may be planar, the buffer portion 2 and the seed portion 3 may have the same pattern, or the buffer portion 2 may be planar and the seed portion 3 may be patterned. In Figures 3 and 4, a silicon substrate may be used for the main substrate 1, AlN may be used for the buffer portion 2, and a GaN-based semiconductor may be used for the seed portion 3.

[0030] Figure 5 is a cross-sectional view showing an alternative configuration of the semiconductor substrate according to this embodiment. As shown in Figure 5, the first wing portion F1 may be separated into a plurality of parts PA arranged in a second direction X2 perpendicular to the first direction X1.

[0031] Figure 6 is a cross-sectional view showing an alternative configuration of the semiconductor substrate according to this embodiment. Figure 7 is a plan view showing an alternative configuration of the semiconductor substrate according to this embodiment. As shown in Figures 6 and 7, the semiconductor substrate 10 may be located above the first semiconductor portion 8A and include an upper layer 9 containing an active layer and a p-type layer. An anode EA and a cathode EC may be provided on the upper layer 9.

[0032] Figure 8 is a cross-sectional view showing a semiconductor substrate manufacturing method according to this embodiment. Figure 9 is a flowchart showing a semiconductor substrate manufacturing method according to this embodiment. As shown in Figures 8 and 9, the semiconductor substrate manufacturing method according to this embodiment includes a step S10 of preparing a template substrate TS including a growth suppression region DA (mask portion 5) and a first seed portion S1 (first opening K1 that exposes the seed portion 3) aligned in a first direction X1; a step S20 of forming a first raised portion R1 containing a nitride semiconductor, extending from the first seed region S1 to a position above the growth suppression region DA (upper surface 5T of the mask portion 5); a step S30 of forming a growth suppression film 7 in contact with the first raised portion R1; and a step S40 of forming a first base portion B1 located above the first raised portion R1 and a first wing portion F1 connected to the first base portion B1, separated from the growth suppression region DA (mask portion 5) and located on the void JD, such that each contains a nitride semiconductor.

[0033] The first base B1 and first wing portion F1 may be formed using the corner RC where the upper surface RT and side surface RS of the first raised portion R1 intersect as the growth starting point PG. As described above, the first base B1 and first wing portion F1 may be formed using the corner RC as the growth starting point PG, but are not limited to this. There is no problem in forming a defect (for example, a minute opening) in the growth-inhibiting film 7 and using the defect in the growth-inhibiting film 7 as the growth starting point for the first base B1 and first wing portion F1.

[0034] The first raised portion R1, the growth-inhibiting film 7, and the first base portion B1 and first wing portion F1 may be continuously formed using an MOCVD apparatus. The first raised portion R1 may contain a GaN-based semiconductor and the growth-inhibiting film 7 may be silicon nitride. The first raised portion R1 may be formed by supplying a gallium source material and a nitrogen source material. The growth-inhibiting film 7 may be formed by maintaining the supply of the nitrogen source material, stopping the supply of the gallium source material, and supplying a silicon-based material. The first base portion B1 and the first wing portion F1 may contain a GaN-based semiconductor. The first base portion B1 and the first wing portion F1 may be formed by maintaining the supply of the nitrogen source material, stopping the supply of the silicon-based material, and supplying a gallium source material. Alternatively, a small amount of silicon-based material may be continued to be supplied at a doping level.

[0035] The growth of the first wing portion F1 and the second wing portion F2, which grows in the direction approaching the first wing portion F1, may be stopped before they meet. The template substrate TS has a seed portion 3 including a first seed region S1, and the seed portion 3 may be formed by sputtering.

[0036] Figure 10 is a block diagram showing a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 50 includes an apparatus M10 that performs process S10 in Figure 9, an apparatus M45 that performs processes S20, S30, and S40 in Figure 9, and a control device MC that controls apparatus M10 and apparatus M45. Apparatus M45 may be an MOCVD apparatus.

[0037] [Example 1] As the main substrate 1, silicon substrates, silicon carbide substrates (4H-SiC, 6H-SiC substrates), sapphire substrates, nitride substrates (GaN, AlN substrates, etc.), ScMgAlO substrates, etc. can be used.

[0038] The seed portion 3 is formed above the main substrate 1 and serves as the starting point for the growth of the semiconductor portion 8. The seed portion 3 only needs to be formed in a part of the opening K (of the mask pattern 6), and may be planar or patterned (for example, striped). As the seed portion 3, a GaN layer, AlN layer, AlGaN layer, AlInN layer, AlGaInN, Al, etc., formed at a low temperature (500°C or below) may be used. The thickness of the seed portion 3 is approximately 10 nm to 500 nm.

[0039] A buffer portion 2 may be formed between the main substrate 1 and the seed portion 3 (e.g., a GaN layer), and the buffer portion 2 improves the crystallinity and flatness of the seed portion 3. The buffer portion 2 may be planar or patterned (e.g., stripe-shaped) to match the seed portion 3. As the buffer portion 2, a GaN layer, AlN layer, AlGaN layer, AlInN layer, AlGaInN, Al, etc., formed at low temperatures (500°C or below) may be used. The thickness of the buffer portion 2 is approximately 10 nm to 500 nm. When a silicon substrate is used for the main substrate 1, it is desirable that the buffer portion 2 in contact with the silicon substrate does not contain gallium in order to suppress meltback.

[0040] The layer between the main substrate 1 and the semiconductor portion 8 is sometimes referred to as the underlayer (including at least one of the buffer portion 2 and the seed portion 3). A GaN layer may be formed as the underlayer (e.g., the seed portion 3) by sputtering. In this case, for example, a sputtering target mainly composed of gallium nitride (containing 25 atm% or more gallium) with an oxygen content of 5 atm% or less may be used, and the sputtering gas pressure may be less than 0.3 Pa. As for the sputtering method, DC sputtering, RF sputtering, AC sputtering, DC magnetron sputtering, ECR (Electron cyclotron Resonance) sputtering, RF magnetron sputtering method, PSD (Pulse sputter deposition) method, laser ablation method, etc., can be appropriately selected.

[0041] The sputtering target to be used may have an oxygen content of 5 atm% or less, 3 atm% or less, or 1 atm% or less in order to enhance the crystallinity of the entire film. It is desirable that the purity be as high as possible, and the content of metallic impurities may be less than 0.1% or less than 0.01%. When forming a GaN layer by the sputtering method, by using a gallium nitride target with a low oxygen content, effects such as improved surface flatness, improved crystallinity, and suppression of the generation of surface hillocks (protrusions) can be observed.

[0042] When forming a nitride semiconductor (AlN, GaN, etc.) as an underlying layer by sputtering, the degree of vacuum in the apparatus before film formation may be -5 3 × 10 -5 Pa or less or 1 × 10

[0043] The power density during discharge may be 2 5 W / cm 2 or less or 1.5 W / cm 2 or less. The lower limit of the power density may be 2 0.1 W / cm

[0044] In Example 1, a GaN underlayer (e.g., seed layer) was formed using the RF sputtering method. A gallium nitride target (oxygen content: 0.4 atom%) was used, the deposition pressure was set to 0.1 Pa, and nitrogen gas was introduced at a rate of 20-40 sccm. Although argon gas was not used in Example 1, it may, of course, be introduced. The discharge density was 125 W / cm². 2 The film deposition temperature was room temperature.

[0045] When forming a base layer (including at least one of the buffer portion 2 and the seed portion 3) using sputtering, laser ablation, or the like, the internal stress can be controlled from compressive stress to tensile stress depending on the film deposition conditions, thus enabling control of the stress on the semiconductor portion 8. The internal stress can also be controlled by the amount of argon incorporated into the base layer. The stress on the semiconductor portion 8 may also be controlled by forming the base layer locally (in a pattern) on the substrate.

[0046] The mask pattern 6 is formed on the base substrate using a material that suppresses the longitudinal growth (growth in the c-axis direction) of the nitride semiconductor, and enables lateral growth (for example, growth in the a-axis direction). The opening K of the mask pattern 6 (the exposed part of the seed part 3) becomes the starting point for the growth of the semiconductor part 8. Examples of materials for the mask part 5 of the mask pattern 6 include silicon nitride, silicon carbide, silicon carbonitride, diamond-like carbon, silicon oxide, silicon oxynitride, etc., as well as silicon-free materials such as titanium nitride, molybdenum nitride, tungsten nitride, tantalum carbide, and high-melting-point metals (molybdenum, tungsten, platinum, etc.). The mask part 5 may be a single layer film made of one of these materials, or a multilayer film made by combining multiple of these materials. The thickness of the mask part 5 may be about 5 nm to 2 μm.

[0047] Figure 11 is a cross-sectional view showing the configuration of a semiconductor substrate in Example 1. In Example 1, a silicon substrate was used as the main substrate 1, and an AlN layer, which is the seed portion 3, was formed on a part of the main substrate. By forming an Al layer of about 1 to 5 nm as a buffer portion 2 between the seed portion 3 (AlN layer) and the main substrate 1 (silicon substrate), the crystallinity of the seed portion 3 (AlN layer) can be increased.

[0048] A mask pattern 6 having a first opening K1 is formed on the seed portion 3. A raised portion R is formed from the opening K. The surface of the raised portion R is at a height of H1 from the upper surface 5T of the mask portion 5, and from the viewpoint of ensuring the crystallinity and surface flatness of the semiconductor portion 8,

[0049] ​The base portion B and the wing portion F are formed above the growth-inhibiting film 7 on the raised portion R and are completely separated from the mask portion 5. The wing portion F of the semiconductor portion 8 has a defect density approximately two orders of magnitude lower than the base portion B on the opening K and also has good crystallinity, making it suitable for forming the active region of the upper layer (device layer). The wing portion F is the region from the upper surface edge of the raised portion R to the edge of the semiconductor portion 8, and this region may be used as the device region. Since the back surface of the wing portion F is separated from the mask portion 5, the formation of the wing portion F can be carried out without the influence of the mask portion 5. In Example 1, adjacent semiconductor portions 8 are not joined together but are separated, so stress from the main substrate 1 and seed portion 3, which are made of different materials from the semiconductor portion 8, can be effectively relieved. This makes it possible to suppress crack generation and ensure the surface flatness of the semiconductor portion 8. It is also possible to join adjacent semiconductor portions 8 together.

[0050] In Example 1, the width of the opening K was 5 μm, the width of the mask portion 5 was 50 μm, the pitch width RP of the raised portion R was 55 μm, and the height H1 of the raised portion R was 1.5 μm. The back surface of the semiconductor portion 8 was the same height as the top surface RT of the raised portion R, and the thickness (height) of the void JD was 1.5 μm. Furthermore, the growth of the semiconductor portion 8 was stopped so that the width of the gap GP between adjacent semiconductor portions 8 was 10 μm.

[0051] Figure 12 is a cross-sectional view showing an alternative configuration of the semiconductor substrate of Example 1. After the formation of the semiconductor portion 8, an upper layer 9 (device layer) is formed on the semiconductor portion 8. Specifically, a stacked structure such as an LED, laser, PD, or power device can be formed using MOCVD, MBE, sputtering, etc. At least a portion of the active region of the upper layer 9 may be formed on the wing portion F (device region), and in Example 1, the entire active region is formed on the wing portion F. Electrodes ET (anode, cathode, gate, etc.) may be provided on the upper layer 9.

[0052] Figures 13 and 14 are cross-sectional views showing the manufacturing method of a semiconductor substrate in Example 1. As shown in Figure 13, an AlN layer, which is the seed portion 3, is formed on the main substrate 1 (silicon substrate) to a thickness of 100 nm by sputtering. Next, a mask layer MF (e.g., SiN) with a thickness of 10 nm is formed on the seed portion 3 (AlN layer) using sputtering. Then, the resist Z coated on the mask layer MF is patterned in a stripe pattern using a general photolithography method. After that, openings K and mask portions 5 are formed in the mask layer MF by dry etching (e.g., ICP: Ion Coupled Plasma, etc.) to expose the seed portion 3 (AlN layer). After that, the resist Z is removed to create a template substrate TS.

[0053] After the template substrate TS is transported to the MOCVD apparatus, the first step of film deposition for ELO is performed as shown in Figure 14. This forms raised portions R (first raised portion R1 and second raised portion R2). The deposition conditions were a deposition temperature of 1100°C, an ammonia flow rate of 7.5 slm, and a TMG (trimethylgallium) flow rate of 5 sccm.

[0054] The raised portion R only needs to extend beyond the upper surface of the mask portion 5, and may either slightly protrude laterally from the opening K or remain within the opening K. In Figure 14, the growth of the raised portion R was stopped when the film thickness reached 1.5 μm, with the raised portion R slightly protruding laterally from the edge of the opening.

[0055] Next, the deposition temperature is lowered by about 150°C from the initial growth temperature, the supply of TMG is stopped, and SiH4 (silane) at a flow rate of 400 sccm and ammonia (NH3) at a flow rate of 7.5 slm are supplied to deposit a thin SiN layer (approximately 1 nm). As a result, a growth-inhibiting film 7 is formed on the side RS and top RT of the raised portion R.

[0056] Next, the film deposition temperature is increased by 250°C, and TMG and ammonia are supplied again to deposit the semiconductor portion 8. At this time, it was found that the growth-inhibiting film 7 greatly affected the deposition of the semiconductor portion 8, and that the wing portion F was formed on the raised portion R, floating away from the mask portion 5. In other words, the back surface of the wing portion F of the semiconductor portion 8 is completely separated from the mask portion 5.

[0057] It was found that the raised portion R has a convex shape and possesses upper surface RT and side surface RS, which are different crystal orientation planes, as well as a corner portion RC, which effectively suppresses the growth of the raised portion R toward the side surface RS compared to its upper surface RT. This unique crystal growth is a new discovery by the inventors. It is thought that the fact that the upper surface RT of the raised portion R is a c-plane (polar plane) and the side surface RS is a semi-polar plane ("(11-22) plane, etc.") or a non-polar plane ("(11-20) plane, etc.") affects the formation state of the growth-suppressing film 7 and the crystal growth state of the semiconductor portion 8, and as a result, the semiconductor portion 8 is formed preferentially over the upper surface RT.

[0058] Figure 15 is a cross-sectional view showing an alternative configuration of the semiconductor substrate of Example 1. In Figure 11, the height of the back surface of the semiconductor portion 8 is formed at approximately the same height as the upper surface RT of the raised portion R. However, in Figure 15, the height of the semiconductor portion 8 is lowered to a position below the upper surface of the raised portion R, and the semiconductor portion 8 is deposited there. This can be selected by controlling the deposition conditions of the semiconductor portion 8 and the deposition conditions of the growth-inhibiting film 7 (deposition temperature, deposition time, gas flow rate, etc.). In either case, the effects of Example 1 are obtained. In Figure 15, the height H1 of the raised portion R was 1.5 μm, but because the back surface of the semiconductor portion 8 was formed at a location 100 nm below the height of the upper surface RT of the raised portion R, the thickness (height) of the void JD became 1.4 μm.

[0059] From Example 1, it was found that forming the wing portion F without interference from the main substrate 1, seed portion 3, and mask portion 5 is very effective in suppressing misalignment of the crystal axis of the wing portion F. In other words, in order to suppress misalignment of the crystal axis, the wing portion F may be completely separated from the mask portion 5. In this case, the wing portion F is formed by the raised portion R and the growth-inhibiting film 7. It is preferable that it is in contact only with base B.

[0060] Figure 16 is a graph showing the XRD scan measurement results in the comparative example. Figure 17 is a graph showing the XRD scan measurement results in Example 1. Figures 16 and 17 show the measurement results for the (002) plane, and the incident direction of the X-rays is <11-20>. In Example 1, a 1.5 μm GaN layer was used for the seed portion 3 and a 200 nm AlN layer was used for the buffer portion 2. In the comparative example, the same buffer portion and seed portion as in Example 1 were used, and the ELO layer was formed so as to be in contact with the mask portion.

[0061] In Figure 16, three peaks are visible. The central peak is the peak of the GaN layer (base) on the seed portion, where the crystal axis of the c-plane is almost perpendicular to the surface of the mask portion. The remaining two peaks are the peaks of the GaN layer in the wing portions, and a Δ (angle difference between peaks) of 0.8 degrees was observed. This means that the c axes of the two wing portions on both sides of the base are growing with a displacement of approximately 0.4° each from the center, indicating low flatness of the semiconductor portion 8. In contrast, in Figure 17 of Example 1, the peaks are not separated and are essentially a single peak. This indicates that the crystal axes of the two wing portions F on both sides of the base portion B are aligned and the displacement is very small.

[0062] The results shown in Figure 17 are very good for the semiconductor portion 8 with wide wing portions F. It is thought that at least one of the following factors—the separation of the back surface of the wing portions F of the semiconductor portion 8 from the mask portion 5, and the fact that the semiconductor portion 8 is in contact only with the raised portion R—contributes to suppressing the misalignment of the crystal axes of the two wing portions F on both sides of the base portion B. In Example 1, it was also found that the incorporation of indium (In) during the formation of the upper layer 9 became uniform on the surface of the semiconductor portion 8, improving, for example, the yield and luminous efficiency of the light-emitting element.

[0063] The growth-inhibiting film 7 in contact with the raised portion R has effects other than lifting the semiconductor portion 8 from the mask portion 5. When a different material is used for at least one of the main substrate 1, seed portion 3, and buffer portion 2 than the semiconductor portion 8, stress may occur in the semiconductor portion 8 due to differences in thermal expansion coefficients and lattice constants. However, it has been found that the positioning of the growth-inhibiting film 7 between the raised portion R and the semiconductor portion 8 alleviates such stress, significantly suppressing defects and cracks in the semiconductor portion 8. This effect is extremely important for improving the quality and yield of the upper layer 9.

[0064] In Example 1, it was found that the defect density of the base B and wing F was significantly reduced. Depending on the formation state of the growth-inhibiting film 7, as shown in Figure 14, the growth of the base B and wing F can begin from the ends (corners RC) on both sides of the raised portion R, and the crystals that grow from these ends (corners RC) toward the center can meet near the center of the upper surface of the raised portion R. This reduces the defect density of the base B (crystals on the raised portion R). By significantly reducing the defect density across the entire area of ​​the semiconductor portion 8 (the entire width spanning the base B and wing F), it becomes possible to form an active region of the upper layer 9 even on the base above the opening. Such a method is not known to date and is considered to be a very effective technology for industry.

[0065] In Example 1, the growth-inhibiting film 7 was formed by supplying silane gas and ammonia gas, but it can also be formed by other methods. For example, by flowing only ammonia gas and not silane gas for several minutes after the raised portion R has been formed, a silicon-containing film (growth-inhibiting film 7) can be formed in contact with the raised portion R by residual silicon in the apparatus. Alternatively, after forming the raised portion R, the substrate can be removed from MOCVD and the surface of the raised portion can be slightly oxidized to form a growth-inhibiting film 7 containing silicon and oxygen. In Example 1, a silicon substrate was used for the main substrate 1, but SiC substrates and sapphire substrates can also be suitably used.

[0066] Figure 18 is a plan view of the semiconductor substrate including the upper layer. Figure 19 is a cross-sectional view of the semiconductor substrate including the upper layer. The upper layer 9 may be formed on the semiconductor portion 8 after stopping the growth of the semiconductor portion 8 by changing the film deposition conditions (for example, by lowering the film deposition temperature by about 100°C). In addition to the active layer, the upper layer 9 may include at least one of a p-type layer, an n-type layer, and an electron blocking layer. Even when the upper layer 9 is formed on the semiconductor substrate 10, the back-side flow phenomenon, in which the upper layer material is supplied to the back side of the semiconductor portion 8, is greatly suppressed, and problems such as light absorption caused by the back-side flow phenomenon are also resolved.

[0067] In the semiconductor substrate 10 shown in Figures 18 and 19, the anode EA and cathode EC are formed above the wing portion F of the semiconductor portion 8. In a typical LED, the active region (light-emitting region) is directly below the anode EA, which is composed of a transparent electrode such as ITO (indium tin oxide). In Example 1, the back-turn phenomenon is suppressed, thus eliminating the problem of light emitted from the active region being absorbed on the back surface of the wing portion F. At least a portion of the anode EA may be located above the wing portion F, or the entire anode EA may be located above the wing portion F. Since the area directly below the cathode EC is generally not an active region, the cathode EC may be formed above the base portion B. In Figures 18 and 19, the anode EA and cathode EC are formed above the same wing portion F, but this is not the case. As shown in Figures 6 and 7, the anode EA may be formed above one of two wing portions F facing each other across the base portion B, and the cathode EC may be formed above the other.

[0068] In conventional ELO methods, cracks may occur in the semiconductor layer due to differences in the thermal expansion coefficients of dissimilar substrates and semiconductor layers. In contrast, in Example 1, the semiconductor portion 8 is located on a void and is physically separated from the mask portion 5; the bond between the raised portion R and the semiconductor portion 8 is weak due to the growth-inhibiting film 7; and adjacent semiconductor portions 8 do not meet (they have a gap GP). These three factors effectively relieve internal stress and suppress crack formation, even when using dissimilar substrates (Si substrate, SiC substrate, etc.). Furthermore, stress relief by the wing portion F can be achieved by widening the width of the wing portion F (for example, to 7 μm or more).

[0069] Figure 20 is a plan view showing the method of element separation in Example 1. Figure 21 is a cross-sectional view showing the method of element separation in Example 1. As shown in Figures 20 and 21, the element body 20 (including the wing portion F, upper layer portion 9, anode EA, and cathode EC) is separated from the template substrate. Since there is a gap JD under the wing portion F, by applying downward pressure to the element body 20 with an adhesive pressing body YS (adhesive plate, adhesive sheet, etc.), the base portion of the element body 20 (the connection portion with the template substrate TS) breaks easily, and the element body 20 is separated from the template substrate TS. Specifically, the element body 20 is peeled off the template substrate TS while being held by the pressing body YS. In this way, the gap JD also functions effectively in element separation, and the element body 20 can be peeled off without damaging the element body 20.

[0070] Specific examples of the element 20 include light-emitting diodes (LEDs), semiconductor lasers, Schottky diodes, photodiodes, and transistors (including power transistors and high electron mobility transistors).

[0071] Figure 22 is a schematic diagram showing the configuration of an electronic device according to Embodiment 1. The electronic device 30 includes an element body 20, a drive board 23 on which the element body 20 is mounted, and a control circuit 25 that controls the drive board 23. The control circuit 25 may also include a processor. Examples of the electronic device 30 include a display device, a laser emitter (including Fabry-Perot type and surface-emitting type), a lighting device, a communication device, an information processing device, a sensing device, a power control device, and the like.

[0072] In Figure 22, the element body 20 is bonded and electrically connected to the drive substrate 23 while detached from the template substrate TS. However, it is also possible for the element body 20 to be bonded and electrically connected to the drive substrate 23 while not detached (the template substrate TS and the element body 20 on it).

[0073] [Example 2] Figure 23 is a cross-sectional view showing the configuration of the semiconductor substrate in Example 2. In Example 2, the seed layer 3 does not cover the entire surface of the main substrate 1, but has a stripe shape. The opening K of the mask pattern 6 is located on the seed portion 3 (AlN layer). In Example 2, the width of the opening K is slightly narrower than the width of the seed portion 3, and the AlN layer (seed portion 3) is located below the opening K across its entire width. Therefore, the raised portion R, which is the GaN layer, and the silicon substrate, which is the main substrate 1, are spatially separated by the AlN layer, and meltback of Ga and silicon is suppressed.

[0074] By using a buffer layer locally, stress from the buffer layer can be relieved. By depositing the semiconductor portion 8 and the growth-inhibiting film 7 using the method shown in Example 1, the wing portion F is completely separated from the mask portion 5, and the wing portion F is in contact only with the raised portion R, so that the misalignment of the crystal axis of the wing portion F can be suppressed to the same level as in Example 1. In Example 2, a silicon substrate was used for the main substrate 1, but SiC substrates and sapphire substrates are also suitable for the main substrate 1.

[0075] [Example 3] In Example 3, the semiconductor substrate shown in Figure 4 was fabricated. In Example 3, a GaN layer was formed as a seed portion 3 on the AlN layer which is the buffer portion 2. The GaN layer which is the seed portion 3 was deposited by, for example, sputtering. By depositing the semiconductor portion 8 and the growth suppression film 7 using the method shown in Example 1, the wing portion F was completely separated from the mask portion 5, and the wing portion F was in contact only with the raised portion R, so that the misalignment of the crystal axis of the wing portion F could be suppressed to the same level as in Example 1. In Example 2, a silicon substrate was used for the main substrate 1, but SiC substrates and sapphire substrates are also suitable for the main substrate 1.

[0076] [Example 4] Figure 24 is a cross-sectional image showing the configuration of the semiconductor substrate of Example 4. In the semiconductor substrate 10 shown in Figure 24, the width Ws (length in the first direction) of the first semiconductor portion 8A is 50.9 [μm], the thickness of the void JD is 347 [nm], the thickness of the first wing portion F1 is 3.52 [μm], and the aperture width (seed region width) is 3.13 [μm]. The penetration dislocation density of the first base portion B1 and the first wing portion F1 is 5 × 10⁻¹⁶ 6 [pcs / cm 2 The following may be the case: The total width Ws (length in the first direction) of the first semiconductor part 8A may be 5 times or more, 10 times or more, 20 times or more, or 50 times or more the thickness of the first wing part F1.

[0077] [Example 5] Figure 25 is a plan view showing the configuration of the semiconductor substrate of Example 5. Figure 26 is a cross-sectional view showing the configuration of the semiconductor substrate of Example 5. As shown in Figures 25 and 26, the semiconductor substrate 10 comprises a template substrate TS including a first seed region S1 and a growth suppression region (non-seed region) DA aligned in a first direction X1, and a first semiconductor portion 8A located above the template substrate TS. The first semiconductor portion 8A has a first raised portion R1 extending from the first seed region S1 to a position above the growth suppression region DA, a growth suppression film 7 in contact with the first raised portion R1, a first base portion B1 located above the first raised portion R1, and a first wing portion F1 connected to the first base portion B1 and separated from the growth suppression region DA and located on a void JD. The first wing portion F1 may include a wing end (edge) E1 located above the growth suppression region DA. This makes it possible to improve the flatness on the first wing portion F1.

[0078] The first semiconductor portion 8A may have a raised portion R1 that is formed in a mesa-like manner on the first seed region S1 and connected to the first base portion B1. The growth-inhibiting film 7 may be in contact with the side and top surfaces of the raised portion R1 and may be located on the growth-inhibiting region DA.

[0079] In the semiconductor substrate 10, the template substrate TS includes the main substrate 1 and the underlayer 4. In the first seed region S1, the underlayer 4 is unmodified, while in the growth suppression region DA, the underlayer 4 may be modified. The void JD may have a ratio of the width in the first direction X1 to the thickness (e.g., the thickness below the wing end E1) TJ of 5.0 or more.

[0080] Figure 27 is a cross-sectional view showing a method for manufacturing a semiconductor substrate. Figure 27 includes the steps of: preparing a template substrate TS including a first seed region S1 and a growth inhibition region DA; forming a raised portion R1 on the template substrate TS from the first region S1; forming a growth inhibition film 7 in contact with the raised portion R1; and forming a first base portion B1 located above the raised portion R1, and a first wing portion F1 connected to the first base portion B1, separated from the growth inhibition region DA, and located on the void JD.

[0081] As shown in Figure 27, the first base B1 and the first wing F1 may be formed with the corner RC of the raised portion R1 as the growth starting point. While the corner RC may be used as the growth starting point in this way, the method is not limited to this. Defects (e.g., minute openings) can also be formed in the growth-inhibiting film 7 on the first raised portion R1, and these defects in the growth-inhibiting film 7 can be used as the growth starting points for the first base B1 and the first wing F1.

[0082] The raised portion R1, the growth-inhibiting film 7, and the first base portion B1 and first wing portion F1 may be continuously formed using an MOCVD apparatus. The first raised portion R1 may contain a GaN-based semiconductor, and the growth-inhibiting film 7 may be silicon nitride. The first raised portion R1 may be formed by supplying a gallium source raw material (organic raw material such as trimethylgallium (TMG) or triethylgallium (TEG)) and a nitrogen source raw material (ammonia gas (NH3)). The growth-inhibiting film 7 may be formed by maintaining the supply of the nitrogen source raw material, stopping the supply of the gallium source raw material, and supplying a silicon-based material (e.g., SiH4). The first base portion B1 and first wing portion F1 may contain a GaN-based semiconductor. The first base portion B1 and first wing portion F1 may be formed by maintaining the supply of the nitrogen source raw material, stopping the supply of the silicon-based material, and supplying a gallium source raw material. Alternatively, a small amount of silicon-based material may be continued to be supplied at a doping level.

[0083] By forming the growth-inhibiting film 7 in this manner, the film can be continuously deposited while forming a void DJ under the wing portion F without removing it from the MOCVD apparatus, thereby reducing manufacturing time and costs. By forming the void DJ and forming the wing portion F so as not to come into contact with the underlying layer 4 (growth-inhibiting region DA), stresses on the semiconductor portion 8 from the main substrate 1 and the underlying layer 4 can be effectively relieved.

[0084] Figure 28 is a cross-sectional view showing a method for manufacturing a template substrate. As shown in Figure 28, the template substrate TS shown in Figure 26 may be obtained by performing the following steps: forming a base layer 4 containing a base material, depositing a resist RZ on the base layer 4, patterning the resist RZ, applying plasma treatment to the exposed base material, and removing the resist RZ. The base layer 4 may be formed by sputtering.

[0085] In plasma treatment, for example, the surface of the irradiated area is modified by irradiating the exposed surface 4D of the underlying layer 4 with argon plasma, thereby forming a growth-inhibiting region DA. By introducing oxygen gas, nitrogen gas, hydrogen gas, etc., in addition to argon gas, the plasma treatment can also use oxygen plasma, nitrogen plasma, hydrogen plasma, or a mixture thereof. As a result, the growth-inhibiting region DA may contain argon, oxygen, or nitrogen as impurities. In such cases, the underlying material may be aluminum nitride, and the growth-inhibiting region DA may be aluminum oxynitride. Alternatively, the underlying material may be AlScN (aluminum scandium nitride), and the growth-inhibiting region DA may be AlScON (aluminum scandium oxynitride).

[0086] Figure 29 is a cross-sectional view showing a method for manufacturing a template substrate. As shown in Figure 29, the process may include: patterning a resist RZ on a base layer 4 (e.g., an AlN layer); forming a coating CM (e.g., a silicon nitride film of about 10 nm) covering the base layer 4 and the resist RZ; removing the resist RZ (lift-off patterning of the coating CM); annealing the coating CM and the base layer 4 (e.g., heat treatment at 1000°C); and removing the coating CM (e.g., removing the silicon nitride film by BHF). In this way, due to the interdiffusion phenomenon between the coating CM and the base layer 4 during annealing, a growth-inhibiting region DA located beneath the coating CM can be formed on the surface of the base layer 4. Alternatively, the surface modification beneath the coating CM can be performed without annealing by sputtering the coating CM. The base material may be AlScN, ScN, ZnO, CrN, etc., containing dissimilar materials such as Sc (scandium), Zn, Cr, etc. (for example, metal elements other than Group III). The base layer 4 may be a single layer or a multilayer structure. It may also be a multilayer structure including a periodic structure.

[0087] Figure 30 is a cross-sectional view showing a method for manufacturing a template substrate. As shown in Figure 30, the method may include steps of patterning a resist RZ on a base layer 4 (e.g., an AlN layer), implanting impurity ions into the exposed base material, and removing the resist RZ. Examples of impurities include Si (silicon), Fe (iron), Mg (magnesium), etc. In the implantation treatment, surface modification is performed by embedding impurity ions into the exposed surface 4D of the base layer 4, thereby forming a growth-inhibiting region DA. The base material may be AlScN, ScN, ZnO, CrN, etc., containing dissimilar materials such as Sc (scandium), Zn, Cr, etc. (e.g., metal elements other than group III). The base layer 4 may be a single-layer structure or a multilayer structure. It may also be a multilayer structure including a periodic structure.

[0088] [Example 6] Figures 31 and 32 are cross-sectional views showing the configuration of a semiconductor substrate of Example 6. As shown in Figures 31 and 32, the semiconductor substrate 10 comprises a template substrate TS including a first seed region S1 and a growth suppression region (non-seed region) DA aligned in a first direction X1, and a first semiconductor portion 8A located above the template substrate TS. The first semiconductor portion 8A has a first raised portion R1 extending from the first seed region S1 to a position above the growth suppression region DA, a growth suppression film 7 in contact with the first raised portion R1, a first base portion B1 located above the first raised portion R1, and a first wing portion F1 connected to the first base portion B1 and separated from the growth suppression region DA and located on a void JD. The first wing portion F1 may include a wing end E1 located above the growth suppression region DA. This makes it possible to improve the flatness on the first wing portion F1.

[0089] The template substrate TS in Figure 31 includes a main substrate 1, a buffer layer 2, and a seed portion 3, wherein the buffer layer 2 may be a growth suppression layer (a layer that suppresses the growth of nitride semiconductor crystals). The buffer layer 2 may include at least one of a 4H-SiC layer, a 6H-SiC layer, a 3C-SiC layer, a sapphire layer, a diamond layer, and a ScAlMgO layer. A seed portion 3 (e.g., AlN) including a first seed region S1 is locally formed on the buffer layer 2, and the region of the buffer layer 2 that does not overlap with the seed portion 3 functions as a growth suppression region DA. The main substrate 1 can be a Si substrate, a SiC substrate, a sapphire substrate, etc.

[0090] The template substrate TS in Figure 32 includes a main substrate 1 and a seed portion 3. The main substrate 1 may be a growth-inhibiting substrate (a substrate that inhibits the growth of nitride semiconductor crystals), such as a 3C-SiC substrate, for example, a 4H-SiC substrate, a 6H-SiC substrate, a 3C-SiC substrate, a sapphire substrate, a diamond substrate, or a ScAlMgO substrate. A seed portion 3 (for example, AlN) including a first seed region S1 is locally formed on the main substrate 1, and the region of the upper surface of the main substrate 1 that does not overlap with the seed portion 3 functions as a growth-inhibiting region DA.

[0091] [Example 7] Figure 33 is a flowchart showing the method for manufacturing a semiconductor device according to Example 7. Figure 34 is a cross-sectional view showing the method for manufacturing a semiconductor device according to Example 7. As shown in Figures 33 and 34, by performing the steps of preparing a semiconductor substrate 10 (S60), forming an upper layer 9 above the first wing portion F1 (S70), and peeling the first wing F1 from the template substrate TS while the first wing portion F1 and the upper layer 9 are held on the transfer substrate PS (S80), an element body 20 (semiconductor device) or a semiconductor device 21 including the element body 20 and the transfer substrate PS can be obtained. The upper layer 9 (functional layer) may be, for example, a nitride semiconductor layer (for example, a GaN-based semiconductor layer) including an active layer, and the semiconductor devices (20 and 21) may include electrodes, insulating films, etc. located on the upper layer 9.

[0092] In the semiconductor substrate 10 shown in Figure 34, the growth-inhibiting film 7 is located on the raised portion R1, resulting in a weak bond between the raised portion R1 and the first wing portion F1, making it easy to peel off the first wing portion F1. The first wing F1 and the first base portion B1 may also be peeled off from the template substrate TS by cleaving at the boundary between the first base portion B1 and the first raised portion R1.

[0093] (Additional items) The foregoing disclosures are for illustrative and explanatory purposes only, and not for limitation. Many variations will be obvious to those skilled in the art based on these examples and descriptions, and therefore, these variations are also included in the embodiments. [Explanation of symbols]

[0094] 1 Main board 2. Buffer section (buffer layer) 3. Seed section 5 Mask section 6 Mask Patterns 7 Growth inhibition film 8A First Semiconductor Section 8C Semiconductor Section 2 10 Semiconductor substrates 20 Semiconductor devices (element bodies) 25 Semiconductor Devices 50 Semiconductor substrate manufacturing equipment DA growth suppression area R1 1st raised part R2 2nd raised part E1 Edge of the first semiconductor section B1 1st base B2 2nd base F1 1st Wing F2 Second Wing Section JD void S1 1st Seed Area S2 Second Seed Area DA growth suppression area TS template substrate

Claims

1. The invention comprises a template substrate including a first seed region and a non-seed region aligned in a first direction, and a first semiconductor portion located above the template substrate and containing a nitride semiconductor, The first semiconductor portion is a semiconductor substrate having a first raised portion extending upward from the first seed region, a growth-inhibiting film in contact with the first raised portion, a first base portion located above the first raised portion, and a first wing portion extending in the first direction from the first base portion and separated from the non-seed region.

2. The semiconductor substrate according to claim 1, wherein the first wing portion has a wing end located above the non-seed region.

3. The semiconductor substrate according to claim 2, wherein the growth-inhibiting film is a film having one or more openings.

4. The semiconductor substrate according to claim 1, wherein the first wing portion is not in contact with the side surface of the first raised portion.

5. The semiconductor substrate according to claim 4, wherein the first raised portion rests on the edge of the non-seed region.

6. The template substrate has a mask portion that functions as the non-seed region and a first opening without the mask portion. The semiconductor substrate according to claim 1, wherein the first opening overlaps with the first seed region.

7. It comprises a second semiconductor section located above the template substrate, The template substrate has a second seed region adjacent to the first seed region via the non-seed region, The second semiconductor portion has a second raised portion extending upward from the second seed region, a second base portion located above the second raised portion, and a second wing portion extending in the first direction from the second base portion and separated from the non-seed region. The semiconductor substrate according to claim 1, wherein the first wing portion and the second wing portion are aligned in the first direction with a gap between them.

8. The semiconductor substrate according to claim 1, wherein the growth-inhibiting film is in contact with the side surface of the first raised portion.

9. The semiconductor substrate according to claim 8, wherein the aforementioned side surface is a tapered surface that narrows towards the top.

10. The semiconductor substrate according to claim 9, wherein the tapered surface intersects with the upper surface of the non-seed region.

11. The growth-inhibiting film is in contact with the upper surface of the first raised portion, as described in claim 8.

12. The semiconductor substrate according to claim 11, wherein the portion of the growth-inhibiting film that contacts the upper surface of the first raised portion is enclosed within the first semiconductor portion.

13. The semiconductor substrate according to claim 8, wherein the first raised portion has a growth initiation point for the nitride semiconductor at a position above the non-seed region.

14. The semiconductor substrate according to claim 13, wherein the growth initiation point is not in contact with the growth-inhibiting film, or is in contact with a portion where the growth-inhibiting film is locally thinned.

15. The semiconductor substrate according to claim 13, wherein the corner where the upper surface and side surface of the first raised portion intersect is included in the growth starting point.

16. The semiconductor substrate according to claim 15, wherein the corner portion is located above the non-seed region.

17. The semiconductor substrate according to claim 2, wherein the first base portion includes a void.

18. The semiconductor substrate according to claim 2, wherein the growth-inhibiting film is a silicon nitride film.

19. The first direction is the <11-20> direction, The upper surface of the first raised portion is a polar surface, The semiconductor substrate according to claim 1, wherein the side surface of the first raised portion is a semipolar surface or a nonpolar surface.

20. The semiconductor substrate according to claim 1, wherein the non-seed region and the first seed region each have a shape in which the second direction perpendicular to the first direction is the longitudinal direction.

21. The semiconductor substrate according to claim 20, wherein the first wing portion is separated into a plurality of parts arranged in the second direction.

22. The semiconductor substrate according to claim 1, wherein the template substrate has a main substrate with a lattice constant different from that of the first semiconductor portion, and a seed portion including the first seed region.

23. The semiconductor substrate according to claim 22, wherein the main substrate is a silicon substrate, a sapphire substrate, or a silicon carbide substrate, and the nitride semiconductor is a GaN-based semiconductor.

24. The semiconductor substrate according to claim 22, wherein the seed portion is not located below the non-seed region.

25. The aforementioned seed portion contains argon or oxygen, which are impurities, in a 2 × 10 １８ / cm ３ The semiconductor substrate according to claim 22, comprising a nitride semiconductor containing the above.

26. The semiconductor substrate according to claim 6, wherein the thickness of the mask portion is 50 nm or less.

27. The semiconductor substrate according to claim 6, wherein the growth-inhibiting film is thinner than the mask portion.

28. The semiconductor substrate according to claim 2, wherein the deviation between the c-axis direction of the first base and the c-axis direction of the wing end is 0.2 degrees or less.

29. The semiconductor substrate according to claim 1, comprising an upper layer located above the first semiconductor portion and including an active layer and a p-type layer.

30. The penetration dislocation density in the first base and the penetration dislocation density in the first wing are each 5 × 10 ６ [pcs / cm ２ The semiconductor substrate according to claim 1, wherein the following conditions apply.

31. The semiconductor substrate according to claim 1, wherein the first semiconductor portion has a pair of first wing portions extending from the first base portion in a first direction and in the opposite direction.

32. The template substrate includes a main substrate and a base layer. In the first seed region, the underlying layer is left unmodified. The semiconductor substrate according to claim 1, wherein the underlying layer is modified in the non-seed region.

33. The template substrate has a buffer layer and a seed portion located locally on the buffer layer and including the first seed region. The semiconductor substrate according to claim 1, wherein a region of the buffer layer that does not overlap with the seed portion functions as the non-seed region.

34. A step of preparing a template substrate including non-seed regions and a first seed region aligned in a first direction, A step of forming a first raised portion that extends upward from the first seed region and contains a nitride semiconductor, A step of forming a growth-inhibiting film in contact with the first raised portion, A method for manufacturing a semiconductor substrate, comprising the step of forming a first base portion located above the first raised portion and a first wing portion extending from the first base portion in the first direction and separated from the non-seed region, such that each of these portions contains a nitride semiconductor.

35. A method for manufacturing a semiconductor substrate according to claim 34, wherein the first base portion and the first wing portion are formed with the corner where the upper surface and side surface of the first raised portion intersect as the growth starting point.

36. A method for manufacturing a semiconductor substrate according to claim 34, wherein the first raised portion, the growth-inhibiting film, and the first base portion and the first wing portion are continuously formed using a MOCVD apparatus.

37. The first raised portion contains a GaN-based semiconductor, The growth-inhibiting film is a silicon nitride, By supplying raw materials that serve as a gallium source and raw materials that serve as a nitrogen source, the first raised portion is formed. A method for manufacturing a semiconductor substrate according to claim 36, wherein the supply of the raw material that serves as the nitrogen source is maintained, while the supply of the raw material that serves as the gallium source is stopped and a silicon-based material is supplied to form the growth-inhibiting film.

38. The first base and the first wing portion include a GaN-based semiconductor, A method for manufacturing a semiconductor substrate according to claim 37, wherein the supply of the silicon-based material is stopped while the supply of the gallium-based material is supplied, thereby forming the first base and the first wing portion.

39. The template substrate has a second seed region adjacent to the first seed region via the non-seed region, A second raised portion extending upward from the second seed region, a second base portion located above the second raised portion, and a second wing portion extending in the first direction from the second base portion and separated from the non-seed region are each formed to contain a nitride semiconductor. A method for manufacturing a semiconductor substrate according to claim 34, wherein the growth of the first wing portion and the second wing portion, which grows in a direction approaching the first wing portion, is stopped before they meet.

40. The template substrate has a seed portion including the first seed region, The method for manufacturing a semiconductor substrate according to claim 34, wherein the seed portion is formed by a sputtering method.

41. A step of preparing a semiconductor substrate according to any one of claims 1 to 33, The process of forming an upper layer above the first wing portion, A method for manufacturing a semiconductor device, comprising the step of peeling the first wing portion from the template substrate while the first wing portion and the upper layer portion are held on the transfer substrate.

42. A method for manufacturing a semiconductor device according to claim 41, wherein the first wing portion is peeled off from the template substrate by performing cleavage at the boundary between the first base portion and the first raised portion.

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