DC-DC converter, its control method, and control program

Abstract

To provide a DC / DC converter suitable for improving power efficiency.SOLUTION: A DC / DC converter comprises: a first switch element which is provided between an external input terminal and an inductor of a smoothing filter; a second switch element which is provided between the inductor and a reference voltage terminal; a lower limit detection circuit which detects that output voltage is lowered to be equal to or lower than a lower limit value; a voltage detection circuit which detects voltage corresponding to an upper limit value of the output voltage; a control circuit which controls the first switch element to on, and the second switch element to off for a predetermined period in timing in which it is detected that the output voltage is lowered to be equal to or lower than the lower limit value, controls the first switch element to off and the second switch element to on after the predetermined period elapses, and controls both of the first switch element and the second switch element to off in timing in which the voltage corresponding to the upper limit value of the output voltage is detected; and a period determination circuit which determines the predetermined period on the basis of the voltage corresponding to the upper limit value of the output voltage.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a DC-DC converter, a control method thereof, and a control program, and more particularly, to a DC-DC converter, a control method thereof, and a control program suitable for improving power efficiency while generating a stable output voltage.

Background Art

[0002] Non-Patent Document 1 discloses a DC-DC converter that detects the start of charging of an inductor using a dynamic comparator. Here, the DC-DC converter disclosed in Non-Patent Document 1 reduces the consumption current by reducing the frequency of the clock supplied to the dynamic comparator at low load.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, there has been a demand for further improvements in the power efficiency of DC-DC converters at low loads. However, attempting to reduce the current consumption of a DC-DC converter at low loads results in ripple in the output voltage, making it difficult to generate a stable output voltage. Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0005] The DC-DC converter according to this disclosure includes an inductor and a first capacitance element, a smoothing filter for smoothing the output voltage of an external output terminal, a first switch element provided between the external input terminal to which an input voltage is supplied and the inductor, a second switch element provided between the inductor and a reference voltage terminal to which a reference voltage is supplied, a lower limit detection circuit for detecting when the output voltage has fallen below a lower limit, a voltage detection circuit for detecting a voltage corresponding to the upper limit of the output voltage, and controls the first switch element to be turned on and the second switch element to be turned off for a predetermined period of time when the lower limit detection circuit detects that the output voltage has fallen below a lower limit. The device comprises a control circuit that supplies current from the external input terminal to the external output terminal via the first switch element and the inductor, and after the predetermined period has elapsed, controls the first switch element to be turned off and the second switch element to be turned on, thereby supplying current from the reference voltage terminal to the external output terminal via the second switch element and the inductor, and controls both the first switch element and the second switch element to be turned off at the timing when the voltage detection circuit detects a voltage corresponding to the upper limit of the output voltage, and a period determination circuit that determines the predetermined period based on the voltage corresponding to the upper limit of the output voltage detected by the voltage detection circuit.

[0006] A control method for a DC-DC converter according to this disclosure comprises at least: a smoothing filter having an inductor and a first capacitance element for smoothing the output voltage of an external output terminal; a first switch element provided between an external input terminal to which an input voltage is supplied and the inductor; a second switch element provided between the inductor and a reference voltage terminal to which a reference voltage is supplied; a lower limit detection circuit for detecting when the output voltage has fallen below a lower limit; and a voltage detection circuit for detecting a voltage corresponding to the upper limit of the output voltage, wherein, at the timing when the lower limit detection circuit detects that the output voltage has fallen below a lower limit, the first switch element is turned ON and the second switch element is turned OFF for a predetermined period, thereby supplying current from the external input terminal to the external output terminal via the first switch element and the inductor. The system supplies current to the external output terminal via the second switch element and the inductor by controlling the first switch element to turn off and the second switch element to turn on after the predetermined period has elapsed. At the timing when the voltage detection circuit detects a voltage corresponding to the upper limit of the output voltage, both the first switch element and the second switch element are controlled to turn off. Based on the voltage corresponding to the upper limit of the output voltage detected by the voltage detection circuit, the predetermined period is determined. At the timing when the lower limit detection circuit detects that the output voltage has next fallen below the lower limit, the system controls the first switch element to turn on and the second switch element to turn off for the newly determined predetermined period, thereby supplying current to the external output terminal via the first switch element and the inductor from the external input terminal.

[0007] The control program according to this disclosure is a control program that causes a computer to execute control processing for a DC-DC converter comprising at least an inductor and a first capacitance element, a smoothing filter for smoothing the output voltage of an external output terminal, a first switch element provided between an external input terminal to which an input voltage is supplied and the inductor, a second switch element provided between the inductor and a reference voltage terminal to which a reference voltage is supplied, a lower limit detection circuit for detecting when the output voltage has fallen below a lower limit, and a voltage detection circuit for detecting a voltage corresponding to the upper limit of the output voltage, wherein, at the timing when the lower limit detection circuit detects that the output voltage has fallen below a lower limit, the program controls the first switch element to be on and the second switch element to be off for a predetermined period of time, thereby supplying current from the external input terminal to the external output terminal via the first switch element and the inductor, and The computer is instructed to perform the following processes: after a predetermined period has elapsed, control the first switch element to be off and the second switch element to be on, thereby supplying current from the reference voltage terminal to the external output terminal via the second switch element and the inductor; control both the first and second switch elements to be off when the voltage detection circuit detects a voltage corresponding to the upper limit of the output voltage; determine the predetermined period based on the voltage corresponding to the upper limit of the output voltage detected by the voltage detection circuit; and, when the lower limit detection circuit detects that the output voltage has next fallen below the lower limit, control the first switch element to be on and the second switch element to be off for a newly determined predetermined period, thereby supplying current from the external input terminal to the external output terminal via the first switch element and the inductor. [Effects of the Invention]

[0008] This disclosure provides a DC-DC converter, a control method therefor, and a control program suitable for improving power efficiency while generating a stable output voltage. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 shows an example configuration of a DC-DC converter according to Embodiment 1. [Figure 2] Figure 2 is a timing chart showing the operation of the DC-DC converter shown in Figure 1. [Figure 3] Figure 3 shows the relationship between the current supplied to the load and the output voltage ripple. [Figure 4] Figure 4 shows a first specific configuration example of a voltage comparison circuit provided in the DC-DC converter shown in Figure 1. [Figure 5] Figure 5 shows a first specific configuration example of the on-period determination circuit provided in the DC-DC converter shown in Figure 1. [Figure 6] Figure 6 shows a second specific configuration example of the voltage comparison circuit provided in the DC-DC converter shown in Figure 1. [Figure 7] Figure 7 shows a second specific configuration example of the ON-Time Determination Circuit provided in the DC-DC converter shown in Figure 1. [Figure 8] Figure 8 is a diagram illustrating the problem. [Figure 9] Figure 9 is a diagram illustrating the problem. [Modes for carrying out the invention]

[0010] The embodiments will be described below with reference to the drawings. Note that the drawings are simplified, and the technical scope of the embodiments should not be narrowly interpreted based on their depiction. Furthermore, the same elements are denoted by the same reference numerals, and redundant explanations are omitted.

[0011] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. However, unless otherwise specified, they are not unrelated, and one may be a modification, application, detailed explanation, or supplementary explanation of part or all of the other. Furthermore, in the following embodiments, when referring to the number of elements (including number, numerical value, quantity, range, etc.), unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number, and may be greater than or less than that specific number.

[0012] Furthermore, in the following embodiments, the components (including operation steps, etc.) are not necessarily essential unless specifically stated or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the components, etc., it shall include those that substantially approximate or resemble the shape, etc., unless specifically stated or considered to be not in principle. The same applies to the numbers, etc. (including the number of items, numerical values, quantities, ranges, etc.) mentioned above.

[0013] <Embodiment 1> Figure 1 shows an example of the configuration of the DC-DC converter 1 according to Embodiment 1. As shown in Figure 1, the DC-DC converter 1 comprises a control circuit 11, a drive circuit 12, a lower limit detection circuit 13, a reverse current detection circuit 14, a voltage comparison circuit 15, an on-time determination circuit 16, a transistor (first switch element) MP1, a transistor (second switch element) MN1, an inductor L1, a capacitive element C1, and a resistive element R1. The reverse current detection circuit 14 and the voltage comparison circuit 15 constitute the voltage detection circuit 20. A load Ld is also shown in Figure 1.

[0014] Transistor MP1 is a P-channel MOS transistor, which is switched on and off by the pulse signal P1 output from the drive circuit 12. Specifically, in transisor MP1, the source is connected to the input terminal IN to which the input voltage VI is supplied, the drain is connected to one terminal (node N1) of the inductor L1, and the pulse signal P1 is supplied to the gate. Transistor MP1 turns on when the pulse signal P1 is at the L level and turns off when the pulse signal P1 is at the H level.

[0015] Transistor MN1 is an N-channel MOS transistor, which is switched on and off by the pulse signal P2 output from the drive circuit 12. Specifically, in transisor MN1, the source is connected to the reference voltage terminal (hereinafter referred to as the reference voltage terminal VSS) to which the reference voltage VSS is supplied, the drain is connected to one terminal (node N1) of the inductor L1, and the pulse signal P2 is supplied to the gate. Transistor MN1 turns on when the pulse signal P2 is at the H level and turns off when the pulse signal P2 is at the L level.

[0016] The inductor L1 is provided between the node N1 between the transisors MP1 and MN1 and the output terminal OUT. The capacitive element C1 is provided between the output terminal OUT and the reference voltage terminal VSS. The inductor L1 and the capacitive element C1 constitute a smoothing filter for smoothing the output voltage VO. Hereinafter, the voltage of the output terminal OUT is referred to as the output voltage VO. In the example of FIG. 1, the output voltage VO is supplied to the load Ld.

[0017] The control circuit 11 uses the drive circuit 12 to control the on / off switching of the transisors MP1 and MN1 by the PFM control method (Pulse Frequency Modulation). Specifically, the control circuit 11 adjusts the duty ratio of the pulse signal P1 by changing only the period of either the H level or the L level (in this example, the L level) of the pulse signal P1, thereby stabilizing the output voltage VO at a desired level.

[0018] The lower limit detection circuit 13 is a so-called comparator that detects when the output voltage VO drops below the lower limit value. Specifically, the lower limit detection circuit 13 compares the voltage obtained by dividing the output voltage VO by a part of the resistor element R1 (i.e., the voltage corresponding to the output voltage VO) with the reference voltage VREF1, and outputs a detection result LL indicating whether the output voltage VO is below the lower limit value. Generally, since the decrease rate of the output voltage VO is slow, the response speed of the lower limit detection circuit 13 does not need to be high. Therefore, the lower limit detection circuit 13 can be configured such that, instead of having a slow response speed, the power consumption is reduced.

[0019] For example, when the output voltage VO drops below the lower limit value, the lower limit detection circuit 13 switches the detection result LL from the H level to the L level. Also, when the output voltage VO rises and becomes higher than the lower limit value, the lower limit detection circuit 13 switches the detection result LL from the L level to the H level.

[0020] Here, when the control circuit 11 detects that the output voltage VO has dropped below the lower limit value by the lower limit detection circuit 13, it uses the drive circuit 12 to control the transistor MP1 to turn on and the transistor MN1 to turn off, thereby starting the charging of the inductor L1. At this time, since current flows from the input terminal IN through the transistor MP1 and the inductor L1 to the output terminal OUT, the output voltage VO gradually rises. After that, when the set period TO has elapsed, the control circuit 11 uses the drive circuit 12 to switch the transistor MP1 from on to off, thereby stopping the charging of the inductor L1. At this time, due to the back electromotive force of the inductor L1, current flows from the reference voltage terminal VSS through the transistor MN1 and the inductor L1 to the output terminal OUT, so the output voltage VO continues to rise.

[0021] The voltage detection circuit 20 detects a voltage corresponding to the upper limit of the output voltage VO. In the voltage detection circuit 20, the reverse current detection circuit 14 is an upper limit detection circuit that detects when the output voltage VO has reached the voltage corresponding to the upper limit. Also in the voltage detection circuit 20, the voltage comparison circuit 15 is an upper limit detection circuit that detects a voltage corresponding to the upper limit of the output voltage VO. The reverse current detection circuit 14 and the voltage comparison circuit 15 will be described in detail below.

[0022] The reverse current detection circuit 14 is a so-called comparator that detects when the current IL, which was flowing forward from transistor MN1 through inductor L1 towards load Ld, begins to flow in the reverse direction from load Ld through inductor L1 towards transistor MN1. Specifically, the reverse current detection circuit 14 compares the voltage LX at node N1 between transistors MP1 and MN1 (the drain voltage of transistor MN1) with the source voltage of transistor MN1, and switches the detection result BS from L level to H level when the drain voltage of transistor MN1 becomes greater than or equal to the source voltage.

[0023] Here, when the reverse current detection circuit 14 detects a reverse current flow IL through inductor L1, the control circuit 11 uses the drive circuit 12 to control both transistors MP1 and MN1 to turn off, thereby preventing the reverse current flow IL through inductor L1. At this time, the flow of current from inductor L1 to the output terminal OUT stops, and the output voltage VO gradually decreases. When the reverse current flow IL through inductor L1 stops due to the transistors MP1 and MN1 being turned off, the reverse current detection circuit 14 switches the detection result BS from a high level to a low level. As the control circuit 11 repeatedly switches transistors MP1 and MN1 on and off as described above, the output voltage VO stabilizes at the desired level.

[0024] The voltage comparison circuit 15 compares the feedback voltage FBIN of the output voltage VO with the reference voltage VREF2 when the reverse current detection circuit 14 detects a reverse current IL flowing through the inductor L1 (i.e., when the detection result BS of the reverse current detection circuit 14 switches from L level to H level), and outputs the comparison result AJ. The feedback voltage FBIN is the voltage obtained by dividing the output voltage VO by a portion of the resistor R1.

[0025] The ON-period determination circuit 16 determines the set period TO set in the control circuit 11. The set period TO is the ON period of transistor MP1. In other words, the set period TO is the period (pulse width) of the pulse signal P1 at the L level.

[0026] Specifically, the ON-period determination circuit 16 receives the rising edge of the signal DI output from the control circuit 11 at the timing when the reverse current detection circuit 14 detects a reverse current IL flowing through the inductor L1. The ON-period determination circuit 16 then adds a delay amount corresponding to the comparison result AJ of the voltage comparison circuit 15 to the signal DI and outputs it to the control circuit 11 as the signal DO. In other words, the ON-period determination circuit 16 determines the period from the rising edge of the signal DI to the rising edge of the signal DO as the set period TO.

[0027] For example, if the feedback voltage FBIN (the voltage corresponding to the output voltage VO) is greater than or equal to the reference voltage VREF2, it means that the output voltage VO is higher than the expected value, so the on-period determination circuit 16 reduces the amount of delay added to the signal DI. In other words, the on-period determination circuit 16 shortens the set period TO by one step. Conversely, if the feedback voltage FBIN (the voltage corresponding to the output voltage VO) is less than the reference voltage VREF2, it means that the output voltage VO is lower than the expected value, so the on-period determination circuit 16 increases the amount of delay added to the signal DI. In other words, the on-period determination circuit 16 lengthens the set period TO by one step. Then, when the control circuit 11 next turns on transistor MP1, it turns it on for the length of the set period TO determined by the on-period determination circuit 16.

[0028] As described above, the DC-DC converter 1 according to this embodiment samples the output voltage VO (upper limit of the output voltage VO) at the timing when it detects the reverse flow of the current IL flowing through the inductor L1, and determines the charging period of the inductor L1 (on-period of the transistor MP1) for the next cycle based on the sampled output voltage VO. Here, the DC-DC converter 1 according to this embodiment detects the upper limit of the output voltage VO only at the timing when it detects the reverse flow of the current IL flowing through the inductor L1, without using a high-speed clock signal, thus reducing power consumption. Furthermore, compared to the case where the charging period of the inductor L1 is fixed, the DC-DC converter 1 according to this embodiment can adjust the charging period of the inductor L1 so that it does not become unnecessarily long, thereby suppressing ripple generated in the output voltage. Moreover, since the DC-DC converter 1 according to this embodiment performs feedback control to determine the charging period of the inductor L1 for the next cycle based on the sampled output voltage VO, sufficient time necessary for feedback control can be secured. In other words, the DC-DC converter 1 according to this embodiment can generate a stable output voltage while improving power efficiency even at low loads.

[0029] (Operation of DC-DC converter 1) Next, in addition to Figure 1, Figure 2 will be used to explain the operation of the DC-DC converter 1.

[0030] In the DC-DC converter 1, the lower limit detection circuit 13 switches the detection result LL from H level to L level when the output voltage VO falls below the lower limit (time t11). When the lower limit detection circuit 13 detects that the output voltage VO has fallen below the lower limit, the control circuit 11 uses the drive circuit 12 to turn on transistor MP1 and turn off transistor MN1, thereby starting the charging of inductor L1 (time t11). At this time, current flows from the input terminal IN to the output terminal OUT via transistor MP1 and inductor L1, so the output voltage VO gradually rises (times t11~t12).

[0031] Subsequently, when the set period TO has elapsed, the control circuit 11 stops charging the inductor L1 by switching transistor MP1 from on to off using the drive circuit 12 (time t12). At this time, current flows from the reference voltage terminal VSS through transistor MN1 and inductor L1 to the output terminal OUT due to the back electromotive force of inductor L1. As a result, the output voltage VO continues to rise (times t12-t13).

[0032] Subsequently, if the reverse current detection circuit 14 detects a reverse current flow IL through inductor L1, the control circuit 11 prevents the reverse current flow IL through inductor L1 by controlling both transistors MP1 and MN1 to be turned off using the drive circuit 12 (time t13). At this time, the flow of current from inductor L1 to the output terminal OUT stops, and the output voltage VO gradually decreases (times t13-t14).

[0033] The DC-DC converter 1 stabilizes the output voltage VO to a desired level by repeatedly controlling the on / off state of transistors MP1 and MN1 from time t11 to t14 (time t11 to t14). The output voltage VO is smoothed by the capacitive element C1.

[0034] Here, in the DC-DC converter 1, the voltage comparison circuit 15, at the timing when the reverse current detection circuit 14 detects a reverse current IL flowing through the inductor L1, compares the feedback voltage FBIN of the output voltage VO with the reference voltage VREF2 and outputs the comparison result AJ (time t13).

[0035] Furthermore, the ON-period determination circuit 16 receives the rising edge of the signal DI output from the control circuit 11 at the timing when the reverse current detection circuit 14 detects a reverse current IL flowing through the inductor L1. The ON-period determination circuit 16 then adds a delay amount corresponding to the comparison result AJ of the voltage comparison circuit 15 to the signal DI and outputs it to the control circuit 11 as the signal DO. In other words, the ON-period determination circuit 16 determines the period from the rising edge of the signal DI to the rising edge of the signal DO as the set period TO.

[0036] In the example in Figure 5, the feedback voltage FBIN (voltage corresponding to the output voltage VO) is greater than or equal to the reference voltage VREF2, and the output voltage VO is higher than the expected value, so the on-period determination circuit 16 reduces the amount of delay added to the signal DI. In other words, the on-period determination circuit 16 shortens the set period TO by one step. Then, when the control circuit 11 turns on transistor MP1 next, it turns it on for the length of the set period TO determined by the on-period determination circuit 16 (times t14 to t15).

[0037] As described above, the DC-DC converter 1 according to this embodiment samples the output voltage VO (upper limit of the output voltage VO) at the timing when it detects the reverse flow of the current IL flowing through the inductor L1, and determines the charging period of the inductor L1 (on-period of the transistor MP1) for the next cycle based on the sampled output voltage VO. Here, the DC-DC converter 1 according to this embodiment detects the upper limit of the output voltage VO only at the timing when it detects the reverse flow of the current IL flowing through the inductor L1, without using a high-speed clock signal, thus reducing power consumption. Furthermore, compared to the case where the charging period of the inductor L1 is fixed, the DC-DC converter 1 according to this embodiment can adjust the charging period of the inductor L1 so that it does not become unnecessarily long, thereby suppressing ripple generated in the output voltage. Moreover, since the DC-DC converter 1 according to this embodiment performs feedback control to determine the charging period of the inductor L1 for the next cycle based on the sampled output voltage VO, sufficient time necessary for feedback control can be secured. In other words, the DC-DC converter 1 according to this embodiment can generate a stable output voltage while improving power efficiency even at low loads.

[0038] Furthermore, the DC-DC converter 1 according to this embodiment can improve power efficiency at low loads, and can therefore be used as a substitute for an LDO (Low Dropout) at low loads such as standby mode. As a result, devices equipped with the DC-DC converter 1 can reduce their circuit size and shorten mode transition times.

[0039] (Comparison of the DC-DC converter 1 according to this embodiment with related technologies) For example, in the first related technology, which has a configuration that switches transistor MP1 from on to off when the upper limit of the output voltage VO is detected, a fast response is required, making it difficult to reduce power consumption (see Figure 8). In the second related technology, which has a configuration that fixes the on period of transistor MP1, it is possible to reduce power consumption by setting a longer on period, but ripple occurs in the output voltage (see Figure 9). In contrast, the DC-DC converter 1 according to this embodiment, as described above, differs from the first and second related technologies in that it can improve power efficiency while generating a stable output voltage.

[0040] Figure 3 shows the relationship between the current supplied to the load Ld and the ripple of the output voltage VO. In the example in Figure 3, the solid line represents the experimental results of the DC-DC converter 1 according to this embodiment, and the dashed line represents the experimental results of the DC-DC converter of the first related technology. As shown in Figure 3, in the DC-DC converter 1 according to this embodiment, the ripple generated in the output voltage VO is suppressed regardless of the response performance (i.e., even when the response performance is low).

[0041] <Embodiment 2> In this embodiment, first specific configuration examples of the voltage comparison circuit 15 and the on-period determination circuit 16 provided in the DC-DC converter 1 will be described. Figure 4 is a diagram showing the first specific configuration example of the voltage comparison circuit 15 as voltage comparison circuit 15a. Figure 5 is a diagram showing the first specific configuration example of the on-period determination circuit 16 as on-period determination circuit 16a.

[0042] First, the voltage comparison circuit 15a will be explained using Figure 4. As shown in Figure 4, the voltage comparison circuit 15a is a so-called dynamic comparator and has transistors TR11 to TR15, TR21 to TR25, and TR31. In this embodiment, we will explain using the example where each transistor TR11, TR13, TR14, TR21, TR23, and TR24 are P-channel MOS transistors, and each transistor TR12, TR15, TR22, TR25, and TR31 are N-channel MOS transistors.

[0043] In transistor TR11, the source is connected to the power supply voltage terminal (hereinafter referred to as the power supply voltage terminal VDD) to which the power supply voltage VDD is supplied, the drain is connected to node N11, and the gate is connected to node N21. In transistor TR12, the source is connected to node N12, the drain is connected to node N11, and the gate is connected to node N21. In transistor TR21, the source is connected to the power supply voltage terminal VDD, the drain is connected to node N21, and the gate is connected to node N11. In transistor TR22, the source is connected to node N22, the drain is connected to node N21, and the gate is connected to node N11. In other words, the memory circuit is formed by the loop-connection of the first inverter INV1 consisting of transistors TR11 and TR12, and the second inverter consisting of transistors TR21 and TR22.

[0044] In transistor TR15, the source is connected to node N31, the drain is connected to node N12, and the gate is supplied with a reference voltage VREF2. In transistor TR25, the source is connected to node N31, the drain is connected to node N22, and the gate is supplied with a feedback voltage FBIN (the voltage corresponding to the output voltage VO).

[0045] In transistor TR13, the source is connected to the power supply voltage terminal VDD, the drain is connected to node N11, and the gate is supplied with the detection result BS from the reverse current detection circuit 14. In transistor TR14, the source is connected to the power supply voltage terminal VDD, the drain is connected to node N12, and the gate is supplied with the detection result BS from the reverse current detection circuit 14. In transistor TR23, the source is connected to the power supply voltage terminal VDD, the drain is connected to node N21, and the gate is supplied with the detection result BS from the reverse current detection circuit 14. In transistor TR24, the source is connected to the power supply voltage terminal VDD, the drain is connected to node N22, and the gate is supplied with the detection result BS from the reverse current detection circuit 14. In transistor TR31, the source is connected to the reference voltage terminal VSS, the drain is connected to node N31, and the gate is supplied with the detection result BS from the reverse current detection circuit 14.

[0046] In other words, during periods when the reverse current detection circuit 14 does not detect reverse current IL flowing through inductor L1, transistors TR13, TR14, TR23, and TR24 are turned on and transistor TR31 is turned off. Then, when the reverse current detection circuit 14 detects reverse current IL flowing through inductor L1, transistors TR13, TR14, TR23, and TR24 are turned off and transistor TR31 is turned on, causing the voltage comparison circuit 15 to temporarily perform a comparison operation.

[0047] For example, if the feedback voltage FBIN is greater than or equal to the reference voltage VREF2, the on-resistance of transistor TR25 becomes smaller than that of transistor TR15. As a result, the charge accumulated in the drain of transistor TR25 (node ​​N22) is drawn out faster than the charge accumulated in the drain of transistor TR15 (node ​​N12). Consequently, transistor TR22 turns on earlier than transistor TR12, causing the voltage level at node N21 (output of the second inverter INV2) to be low, and the voltage level at node N11 (output of the first inverter INV1, and comparison result AJ) to be high. In other words, if the feedback voltage FBIN is greater than or equal to the reference voltage VREF2, the voltage comparison circuit 15a outputs a high-level comparison result AJ.

[0048] Conversely, when the feedback voltage FBIN is less than the reference voltage VREF2, the on-resistance of transistor TR15 becomes smaller than that of transistor TR25. As a result, the charge accumulated at the drain of transistor TR15 (node ​​N12) is drawn out faster than the charge accumulated at the drain of transistor TR25 (node ​​N22). Consequently, transistor TR12 turns on earlier than transistor TR22, causing the voltage level at node N11 (output of the first inverter INV1, and comparison result AJ) to be low, and the voltage level at node N21 (output of the second inverter INV2) to be high. In other words, when the feedback voltage FBIN is less than the reference voltage VREF2, the voltage comparison circuit 15a outputs a comparison result AJ at a low level.

[0049] Next, the ON-period determination circuit 16a will be described using Figure 5. As shown in Figure 5, the ON-period determination circuit 16a comprises an up / down counter 161, an inverter group 162, and a selector 163.

[0050] When the reverse current detection circuit 14 detects a reverse current flow IL through the inductor L1, the up / down counter 161 receives the rising edge of the signal DI output from the control circuit 11 and counts up or down a preset count value (specifically, the previously set count value) according to the comparison result AJ of the voltage comparison circuit 15a.

[0051] For example, if the comparison result AJ is at a high level (i.e., the output voltage VO is greater than the expected value), the up / down counter 161 counts down by one and outputs it as the selection signal S1. Conversely, if the comparison result AJ is at a low level (i.e., the output voltage VO is less than the expected value), the up / down counter 161 counts up by one and outputs it as the selection signal S1.

[0052] The inverter group 162 is composed of multiple inverters connected in series and outputs the signal DI with a delay. The selector 163 selects the output of one of the multiple inverters constituting the inverter group 162 based on the selection signal S1 and outputs it as the signal DO. In other words, the selector 163 adds a delay amount corresponding to the selection signal S1 to the signal DI and outputs it as the signal DO.

[0053] For example, when the count value of the up / down counter 161 is counted down, the selector 163 selects a signal with a small amount of delay added to the signal DI and outputs it as the signal DO. Conversely, when the count value of the up / down counter 161 is counted up, the selector 163 selects a signal with a large amount of delay added to the signal DI and outputs it as the signal DO. In other words, if the output voltage VO is greater than the expected value, the selector 163 shortens the setting period TO by one step, and if the output voltage VO is less than the expected value, it lengthens the setting period TO by one step. Then, when the control circuit 11 next turns on the transistor MP1, it turns it on for the length of the setting period TO determined by the on-period determination circuit 16a.

[0054] Furthermore, the voltage comparison circuit 15a and the on-period determination circuit 16a can both be appropriately changed to other configurations having equivalent functions.

[0055] <Embodiment 3> In this embodiment, a second specific configuration example of the voltage comparison circuit 15 and the on-period determination circuit 16 provided in the DC-DC converter 1 will be described. Figure 6 is a diagram showing a second specific configuration example of the voltage comparison circuit 15 as voltage comparison circuit 15b. Figure 7 is a diagram showing a second specific configuration example of the on-period determination circuit 16 as on-period determination circuit 16b.

[0056] First, the voltage comparison circuit 15b will be explained using Figure 6. As shown in Figure 6, the voltage comparison circuit 15b is a so-called integrator and includes an operational amplifier 151, a capacitive element 152, a capacitive element 153, a switch element 154, and a switch element 155.

[0057] In the operational amplifier 151, a reference voltage VREF2 is supplied to the inverting input terminal, and the voltage at node N41 is supplied to the non-inverting input terminal. Capacitor element 152 is located between the output terminal and the non-inverting input terminal of the operational amplifier 151. The output of the operational amplifier 151 is used as the comparison result AJ of the voltage comparison circuit 15b. Switch elements 154 and 155 are located in series between the input terminal of the voltage comparison circuit 15b, to which the feedback voltage FBIN is supplied, and the non-inverting input terminal (node ​​N41) of the operational amplifier 151. Capacitor element 153 is located between node N42 between switch elements 154 and 155 and the reference voltage terminal VSS. Switch element 154 switches on and off based on the inverting signal of the detection result BS of the reverse current detection circuit 14. Switch element 155 switches on and off based on the detection result BS of the reverse current detection circuit 14.

[0058] During periods when the reverse current detection circuit 14 does not detect reverse current IL flowing through inductor L1, switch element 154 is ON and switch element 155 is OFF, so the charge of the feedback voltage FBIN is accumulated in the capacitive element 153. Then, when the reverse current detection circuit 14 detects reverse current IL flowing through inductor L1, switch element 154 turns OFF and switch element 155 turns OFF, and a voltage corresponding to the charge accumulated in the capacitive element 153 (voltage at node N42) is supplied to the non-inverting input terminal of the operational amplifier 151. The integrator consisting of the operational amplifier 151 and the capacitive element 152 then outputs the integration result corresponding to the feedback voltage FBIN and the reference voltage VREF2 as the comparison result AJ. Note that the comparison result AJ is an analog voltage. For example, the larger the feedback voltage FBIN, the smaller the potential of the comparison result AJ, and the smaller the feedback voltage FBIN, the larger the potential of the comparison result AJ.

[0059] Next, the ON-period determination circuit 16b will be described using Figure 7. As shown in Figure 7, the ON-period determination circuit 16b includes a constant current source 164, a capacitive element 165, a switching element 166, and a comparator 167.

[0060] The constant current source 164 is located between the power supply voltage terminal VDD and node N51 and supplies a constant current to node N51. The capacitive element 165 is located between node N51 and the reference voltage terminal VSS. The switch element 166 is located in parallel with the capacitive element 165 and switches on and off based on the signal DI. The comparator 167 compares the potential of node N51 with the comparison result AJ of the voltage comparison circuit 15b and outputs the comparison result as the signal DO.

[0061] When the reverse current detection circuit 14 detects a reverse current flow IL through inductor L1, the rising edge of the signal DI output from the control circuit 11 is received, and the switch element 166 switches from on to off. As a result, the potential of node N51 gradually rises. Then, when the potential of node N51 rises to the potential of comparison result AJ, the comparator 167 raises the signal DO. The ON period determination circuit 16 determines the period from the rising edge of signal DI to the rising edge of signal DO as the set period TO.

[0062] For example, the smaller the potential of comparison result AJ (i.e., the larger the output voltage VO is than the expected value), the shorter the time it takes for the potential of node N51 to rise and reach the potential of comparison result AJ, so the rise time of signal DO becomes slower. Conversely, the larger the potential of comparison result AJ (i.e., the smaller the output voltage VO is than the expected value), the longer the time it takes for the potential of node N51 to rise and reach the potential of comparison result AJ, so the rise time of signal DO becomes faster. In other words, the reverse current detection circuit 14 shortens the setting period TO the larger the output voltage VO is than the expected value, and shortens the setting period TO the smaller the output voltage VO is than the expected value. Then, when the control circuit 11 turns on transistor MP1 next, it turns it on for the length of the setting period TO determined by the on-period determination circuit 16b.

[0063] Furthermore, the voltage comparison circuit 15b and the on-period determination circuit 16b can both be appropriately changed to other configurations having equivalent functions.

[0064] As described above, the DC-DC converter 1 according to the above embodiment samples the output voltage VO (upper limit of the output voltage VO) at the timing when it detects the reverse flow of the current IL flowing through the inductor L1, and determines the charging period of the inductor L1 (on-period of the transistor MP1) for the next cycle based on the sampled output voltage VO. Here, the DC-DC converter 1 according to the above embodiment detects the upper limit of the output voltage VO only at the timing when it detects the reverse flow of the current IL flowing through the inductor L1, without using a high-speed clock signal, so power consumption can be reduced. Furthermore, compared to the case where the charging period of the inductor L1 is fixed, the DC-DC converter 1 according to this embodiment can adjust the charging period of the inductor L1 so that it does not become unnecessarily long, thus suppressing ripple generated in the output voltage. Moreover, since the DC-DC converter 1 according to the above embodiment performs feedback control to determine the charging period of the inductor L1 for the next cycle based on the sampled output voltage VO, sufficient time necessary for feedback control can be secured. In other words, the DC-DC converter 1 according to the above embodiment can generate a stable output voltage while improving power efficiency even at low loads.

[0065] The present invention has been described in detail above based on embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the spirit of the invention.

[0066] Furthermore, this disclosure can be implemented by having a CPU execute a computer program to perform some or all of the control processing of the DC-DC converter.

[0067] The program described above includes, when loaded into a computer, a set of instructions (or software code) for causing the computer to perform one or more of the functions described in the embodiments. The program may be stored in a non-temporary computer-readable medium or a physical storage medium. Examples, but not limited to, include RAM (Random-Access Memory), ROM (Read-Only Memory), flash memory, SSD (Solid-State Drive), or other memory technologies, CD-ROM, DVD (Digital Versatile Disc), Blu-ray® disc, or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage, or other magnetic storage devices. The program may be transmitted over a temporary computer-readable medium or a communication medium. Examples, but not limited to, include temporary computer-readable medium or a communication medium that includes electrically, optically, acoustically, or otherwise propagating signals. [Explanation of Symbols]

[0068] 1 DC-DC converter 11 Control circuits 12 Drive Circuit 13 Lower limit detection circuit 14. Reverse current detection circuit 15 Voltage comparison circuit 15A Voltage Comparison Circuit 15b Voltage comparison circuit 16 ON-period determination circuit 16a ON-period determination circuit 16b ON-period determination circuit 20 Voltage detection circuit 151 Op-amps 152 Capacitive elements 153 Capacitive elements 154 Switching elements 155 Switching element 161 Up / Down Counter 162 Inverter Group 163 Selector 164 Constant current source 165 Capacitive elements 166 Switching elements 167 Comparator C1 Capacitive element L1 Inductor Ld load INV1 First Inverter INV2 Second Inverter MN1 transistor MP1 Transistor R1 Resistor TR11~TR15 Transistors TR21~TR25 Transistors TR31 Transistor

Claims

1. A smoothing filter having an inductor and a first capacitance element, which smooths the output voltage of the external output terminal, A first switch element is provided between an external input terminal to which an input voltage is supplied and the inductor, A second switch element is provided between the inductor and a reference voltage terminal to which a reference voltage is supplied, A lower limit detection circuit that detects when the output voltage drops below a lower limit, A voltage detection circuit that detects a voltage corresponding to the upper limit of the output voltage, A control circuit controls the first switch element to be turned on and the second switch element to be turned off for a predetermined period of time when the lower limit detection circuit detects that the output voltage has fallen below the lower limit, thereby supplying current from the external input terminal to the external output terminal via the first switch element and the inductor; after the predetermined period has elapsed, controls the first switch element to be turned off and the second switch element to be turned on, thereby supplying current from the reference voltage terminal to the external output terminal via the second switch element and the inductor; and controls both the first switch element and the second switch element to be turned off when the voltage detection circuit detects a voltage corresponding to the upper limit of the output voltage. A period determination circuit that determines the predetermined period based on the voltage corresponding to the upper limit of the output voltage detected by the voltage detection circuit, A DC-DC converter equipped with [specific features / equipment].

2. The voltage detection circuit is An upper limit detection circuit that detects when the output voltage reaches a voltage corresponding to the upper limit, At the timing when the upper limit detection circuit detects that the output voltage has reached the voltage corresponding to the upper limit, an upper limit detection circuit detects the voltage corresponding to the upper limit of the output voltage, Having, The DC-DC converter according to claim 1.

3. The aforementioned upper limit detection circuit is This is a reverse current detection circuit that detects the reverse flow of current through the inductor. The DC-DC converter according to claim 2.

4. The aforementioned reverse current detection circuit is A first comparator compares the voltage at the node between the first and second switch elements with the reference voltage at the reference voltage terminal and outputs a comparison result indicating whether or not the current flowing through the inductor is flowing in reverse. The DC-DC converter according to claim 3.

5. The aforementioned upper limit detection circuit is, A dynamic comparator that, at the timing when the upper limit detection circuit detects that the output voltage has reached a voltage corresponding to the upper limit, compares the feedback voltage of the output voltage with a reference voltage and outputs the comparison result, The aforementioned period determination circuit is Based on the comparison result output from the upper limit detection circuit, the predetermined period is determined. The DC-DC converter according to claim 2.

6. The aforementioned period determination circuit is If the upper limit detection circuit outputs a comparison result indicating that the feedback voltage is equal to or greater than the reference voltage, the predetermined period is reduced by one step; if the upper limit detection circuit outputs a comparison result indicating that the feedback voltage is less than the reference voltage, the predetermined period is increased by one step. The DC-DC converter according to claim 5.

7. The aforementioned period determination circuit is An up-down counter that counts up or counts down the count value according to the comparison result output from the upper limit detection circuit, A group of inverters that output the first signal with multiple delays of different amounts added, A selector that selects the first signal to which a delay amount corresponding to the count value of the up / down counter has been added and outputs it as a second signal, It has, The delay difference between the first signal and the second signal is determined as the predetermined period. The DC-DC converter according to claim 5.

8. The aforementioned upper limit detection circuit is, The upper limit detection circuit detects that the output voltage has reached a voltage corresponding to the upper limit, and the integrator outputs an integral result corresponding to the feedback voltage of the output voltage and a reference voltage. The aforementioned period determination circuit is A constant current source, A second capacitance element that converts the current supplied from the constant current source into a voltage, A second comparator compares the voltage converted by the second capacitance element with the integral result output from the upper limit detection circuit and outputs a comparison result representing the predetermined period, Having, The DC-DC converter according to claim 2.

9. A smoothing filter having an inductor and a first capacitance element, which smooths the output voltage of the external output terminal, A first switch element is provided between an external input terminal to which an input voltage is supplied and the inductor, A second switch element is provided between the inductor and a reference voltage terminal to which a reference voltage is supplied, A lower limit detection circuit that detects when the output voltage drops below a lower limit, A voltage detection circuit that detects a voltage corresponding to the upper limit of the output voltage, A control method for a DCDC converter, comprising at least the following: When the lower limit detection circuit detects that the output voltage has fallen below the lower limit, the first switch element is controlled to be on and the second switch element to be off for a predetermined period of time, thereby supplying current from the external input terminal to the external output terminal via the first switch element and the inductor. After the predetermined period has elapsed, the first switch element is controlled to be turned off and the second switch element to be turned on, thereby supplying current from the reference voltage terminal to the external output terminal via the second switch element and the inductor. When the voltage detection circuit detects a voltage corresponding to the upper limit of the output voltage, both the first switch element and the second switch element are controlled to be turned off. Based on the voltage corresponding to the upper limit of the output voltage detected by the voltage detection circuit, the predetermined period is determined. When the lower limit detection circuit detects that the output voltage has fallen below the lower limit, the first switch element is controlled to be on and the second switch element to be off for a newly determined predetermined period, thereby supplying current from the external input terminal to the external output terminal via the first switch element and the inductor. Control method for a DC-DC converter.

10. A smoothing filter having an inductor and a first capacitance element, which smooths the output voltage of the external output terminal, A first switch element is provided between an external input terminal to which an input voltage is supplied and the inductor, A second switch element is provided between the inductor and a reference voltage terminal to which a reference voltage is supplied, A lower limit detection circuit that detects when the output voltage drops below a lower limit, A voltage detection circuit that detects a voltage corresponding to the upper limit of the output voltage, A control program that causes a computer to perform control processing for a DC-DC converter, comprising at least the following: When the lower limit detection circuit detects that the output voltage has fallen below the lower limit, the first switch element is controlled to be on and the second switch element to be off for a predetermined period of time, thereby supplying current from the external input terminal to the external output terminal via the first switch element and the inductor. After the predetermined period has elapsed, the process involves controlling the first switch element to be turned off and the second switch element to be turned on, thereby supplying current from the reference voltage terminal to the external output terminal via the second switch element and the inductor. The process involves controlling both the first and second switch elements to turn off when the voltage detection circuit detects a voltage corresponding to the upper limit of the output voltage, A process to determine the predetermined period based on the voltage corresponding to the upper limit of the output voltage detected by the voltage detection circuit, When the lower limit detection circuit detects that the output voltage has fallen below the lower limit, the first switch element is controlled to be on and the second switch element to be off for a newly determined predetermined period, thereby supplying current from the external input terminal to the external output terminal via the first switch element and the inductor. A control program that causes a computer to execute a command.

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