Information processing device and control method for the information processing device
The controller in the information processing device addresses the issue of lost logs by transferring data from volatile to non-volatile memory upon abnormality detection, ensuring data preservation and enabling post-hang-up analysis.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- レノボ·ジャパン合同会社
- Filing Date
- 2025-05-14
- Publication Date
- 2026-07-29
AI Technical Summary
When an operating system (OS) or application hangs up in an information processing device, the logs stored in the temporary memory on the SSD are erased upon system restart, making it difficult to identify the cause of the hang-up.
An information processing device equipped with a controller that outputs a command to store data from volatile memory to non-volatile memory when an abnormality is detected, such as a heartbeat cessation, ensuring data preservation.
Data stored in volatile memory is safely transferred to non-volatile memory, preserving it even after a system reset or abnormality, facilitating post-hang-up analysis.
Smart Images
Figure 0007897382000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an information processing apparatus and a control method for an information processing apparatus.
Background Art
[0002] In recent years, information processing apparatuses such as personal computers (PCs) equipped with solid state drives (SSDs) have become widespread. When an SSD communicates with an operating system (OS), data related to the communication (logs and cache data) is stored in a temporary memory within the SSD.
[0003] There are cases where an OS or an application operating in an information processing apparatus hangs up. By analyzing logs indicating the content of communication executed between the information processing apparatus and the SSD, etc., there is a possibility of identifying the cause of the hang-up.
[0004] Patent Document 1 discloses an information processing apparatus including a processor in a main chipset and a sub-processor in a sub-chipset. When an abnormality occurs in the operation of the sub-processor, the output destination of log information indicating the operation status of the sub-processor switches from a RAM in the sub-chipset to a log management memory in a log management chipset. Also, when an abnormality occurs in the operation of the processor in the main chipset, the log information stored in the RAM in the sub-chipset is stored in the ROM in the sub-chipset.
Prior Art Documents
Patent Documents
[0005]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0006] If the OS or application hangs, it may be possible to identify the cause of the hang by analyzing logs stored in temporary memory on the SSD. However, when the user restarts the system to restore it, the logs stored in temporary memory on the SSD are erased.
[0007] The present invention aims to provide an information processing device and a control method for the information processing device that can store data stored in memory within a storage device. [Means for solving the problem]
[0008] One aspect of the present invention is an information processing device that can connect to storage, wherein after the OS (Operating System) of the information processing device starts communicating with the storage, The aforementioned OS This information processing device includes a controller that, when an abnormality is detected, outputs a command to the storage to store data stored in the volatile memory of the storage in the non-volatile memory of the storage.
[0011] In one embodiment of the present invention, the controller may receive a heartbeat output by the OS when the OS is operating normally, and output the command to the storage when the OS stops outputting the heartbeat.
[0012] One aspect of the present invention This is an information processing device that can connect to storage, wherein after the OS (Operating System) of the information processing device starts communicating with the storage, When the OS receives an abnormality signal that it outputs when it detects an abnormality in the application of the information processing device, The data stored in the volatile memory of the storage device is stored in the non-volatile memory of the storage device. Output the instruction to the storage. It is an information processing device equipped with a controller. .
[0013] In one embodiment of the present invention, the controller may output the command to the storage when it detects an abnormality in the storage.
[0014] In one embodiment of the present invention, the controller may receive a heartbeat output by the storage when the storage is operating normally, and output the command to the storage when the storage stops outputting the heartbeat.
[0015] In one embodiment of the present invention, the controller may reset the storage after outputting the instruction to the storage.
[0016] One aspect of the present invention is a control method for an information processing device that can connect to storage, wherein after the OS (Operating System) of the information processing device starts communicating with the storage, The aforementioned OS This is a control method for an information processing device that, when an abnormality is detected, outputs a command to the storage device to store the data stored in the volatile memory of the storage device in the non-volatile memory of the storage device.
[0017] One aspect of the present invention is a control method for an information processing device that can connect to storage, wherein the OS (Operating System) of the information processing device starts communicating with the storage. After that, the OS receives an error signal that it outputs when it detects an abnormality in the application of the information processing device. When that happened, The data stored in the volatile memory of the aforementioned storage is stored in the non-volatile memory of the aforementioned storage. This is a control method for an information processing device that outputs a command to the storage device. [Effects of the Invention]
[0018] According to the above embodiment of the present invention, data stored in the memory of the storage device can be saved. [Brief explanation of the drawing]
[0019] [Figure 1] This figure shows an example of the main hardware configuration of a notebook PC according to the first embodiment. [Figure 2] This is a functional block diagram showing an example of the functional configuration of a notebook PC according to the first embodiment. [Figure 3]It is a flowchart showing an example of the operation of an embedded controller of a notebook PC according to the first embodiment. [Figure 4] It is a flowchart showing an example of the operation of an embedded controller of a notebook PC according to the first embodiment. [Figure 5] It is a flowchart showing an example of the operation of an embedded controller of a notebook PC according to the first embodiment. [Figure 6] It is a flowchart showing an example of the operation of an embedded controller of a notebook PC according to the second embodiment. [Figure 7] It is a flowchart showing an example of the operation of an embedded controller of a notebook PC according to the second embodiment. [Figure 8] It is a flowchart showing an example of the operation of an embedded controller of a notebook PC according to the second embodiment.
Embodiments for Carrying Out the Invention
[0020] Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0021] (First Embodiment) FIG. 1 is a diagram showing an example of the main hardware configuration of a notebook PC 1 according to the first embodiment. As shown in FIG. 1, a notebook PC 1 (notebook personal computer) includes a CPU 11, a main memory 12, a video subsystem 13, a display unit 14, a chipset 21, a BIOS memory 22, an embedded controller 31, an input unit 32, a power supply circuit 33, and an SSD 40. In this embodiment, as an example of an information processing apparatus, the case where the information processing apparatus is the notebook PC 1 will be described.
[0022] The CPU (Central Processing Unit) 11 executes various arithmetic processes under program control and controls the entire notebook PC 1.
[0023] Main memory 12 is writable memory used as a reading area for the CPU 11's executable program, or as a work area for writing processing data for the executable program. Main memory 12 is composed of, for example, multiple DRAM (Dynamic Random Access Memory) chips. This executable program includes the OS (operating system), various drivers for hardware operation of peripheral devices, various services / utilities, application programs, etc.
[0024] The video subsystem 13 is a subsystem for implementing functions related to image display and includes a video controller. This video controller processes drawing commands from the CPU 11, writes the processed drawing information to video memory, reads this drawing information from video memory, and outputs it to the display unit 14 as drawing data (display data).
[0025] The display unit 14 is, for example, a liquid crystal display, and displays a screen based on drawing data (display data) output from the video subsystem 13.
[0026] The chipset 21 includes controllers for USB (Universal Serial Bus), Serial ATA (AT Attachment), SPI (Serial Peripheral Interface) bus, PCI (Peripheral Component Interconnect) bus, PCI-Express bus (PCIe bus), and LPC (Low Pin Count) bus, and multiple devices are connected to it. In Figure 1, as examples of devices, the BIOS memory 22 and SSD 40 are connected to the chipset 21. In this embodiment, the CPU 11 and the chipset 21 correspond to the main control unit 10.
[0027] The BIOS (Basic Input Output System) memory 22 consists of electrically rewritable non-volatile memory such as EEPROM (Electrically Erasable Programmable Read Only Memory) or flash ROM (flash memory). The BIOS memory 22 stores the BIOS and system firmware for controlling the embedded controller 31, etc.
[0028] The embedded controller 31 is a one-chip microcomputer that monitors and controls various devices (peripherals, sensors, etc.) regardless of the system state of the notebook PC 1. The embedded controller 31 also has a power management function that controls the power supply circuit 33. The embedded controller 31 consists of a CPU, ROM, RAM, etc. (not shown), and is equipped with multiple channels of A / D input terminals, D / A output terminals, a timer, and digital input / output terminals. The embedded controller 31 is connected to, for example, the input unit 32 and the power supply circuit 33 via these input / output terminals, and the embedded controller 31 controls the operation of these components.
[0029] The input unit 32 is, for example, an input device such as a keyboard or a pointing device such as a touchpad.
[0030] The power supply circuit 33 includes, for example, a DC / DC converter, a charge / discharge unit, and an AC / DC adapter, and converts a DC voltage supplied from an external power source via an AC / DC adapter or from a battery into multiple voltages necessary to operate the notebook PC 1. The power supply circuit 33 also supplies power to various parts of the notebook PC 1 based on control from the embedded controller 31.
[0031] The SSD (Solid State Drive) 40 is a memory drive device with rewritable non-volatile memory that stores the OS, various drivers, various services / utilities, application programs, and various data. The notebook PC 1 uses the data stored in the SSD 40 to perform various information processing tasks. The SSD 40 is connected to the chipset 21, for example, via a PCI-Express bus (hereinafter sometimes referred to as a PCIe bus).
[0032] In addition to the PCIe bus interface (first interface), the SSD 40 can communicate via an SMBus (System Management Bus) interface (second interface) through the embedded controller 31. The SSD 40 is connected to the chipset 21, for example, via a PCI-Express bus. The SSD 40 also includes flash memory 41, temporary memory 42, and a memory controller 43.
[0033] Flash memory 41 is an example of a non-volatile storage medium, such as NAND flash memory. Flash memory 41 includes, for example, a floating-gate memory cell, a charge-trap memory cell that stores data by trapping electrons in a charge-trap layer without a floating gate, and the like. Temporary memory 42 is an example of a volatile storage medium, such as SRAM (Static Random Access Memory) or DRAM.
[0034] The memory controller 43 is a processor that includes, for example, a CPU, ROM, RAM, etc. (not shown), and comprehensively controls the SSD 40. The memory controller 43 performs processes such as controlling the host interface (host I / F) between the chipset 21 and the embedded controller 31, controlling the memory interface (memory I / F) between the flash memory 41 and the temporary memory 42, and data management processing for the flash memory 41 and the temporary memory 42.
[0035] Next, the functional configuration of the notebook PC 1 according to this embodiment will be described with reference to Figure 2. Figure 2 is a functional block diagram showing an example of the functional configuration of the notebook PC 1 according to this embodiment.
[0036] As shown in Figure 2, the notebook PC 1 comprises a main control unit 10, an embedded controller 31, and an SSD 40.
[0037] The main control unit 10 is a functional unit realized by the CPU 11 and chipset 21 executing programs stored in the main memory 12, and performs various processes (information processing) based on the OS. For example, the main control unit 10 performs various processes based on data stored in the SSD 40 and management processes for managing the SSD 40. The main control unit 10 includes an application 101 and an OS 102. As mentioned above, the SSD 40 includes a flash memory 41, a temporary memory 42, and a memory controller 43.
[0038] Application 101 performs various processes, including communication with SSD 40. The main control unit 10 may have multiple applications 101. The OS 102 manages the status of the processes performed by application 101 and controls application 101.
[0039] When application 101 writes data it has processed to SSD 40, or when application 101 reads data from SSD 40, OS 102 outputs a command to SSD 40 regarding the writing or reading of the data.
[0040] The memory controller 43 writes data to the flash memory 41 or reads data from the flash memory 41 according to instructions output from the OS 102. The memory controller 43 also stores a log of communication between the OS 102 and the memory controller 43, as well as cache data frequently used by the memory controller 43, in the temporary memory 42.
[0041] The embedded controller 31 monitors the status of the OS 102, application 101, or SSD 40. If the OS 102 or the other system hangs up, the embedded controller 31 instructs the SSD 40 to store the data stored in the temporary memory 42 into the flash memory 41.
[0042] Next, with reference to Figures 3 to 5, the operation of the embedded controller 31 when the OS 102 or the like hangs up will be described. Figures 3 to 5 are flowcharts showing an example of the operation of the embedded controller 31 according to this embodiment. After the OS 102 starts communicating with the SSD 40, the processes shown in Figures 3 to 5 are executed.
[0043] First, let's explain the case where OS102 hangs up. Figure 3 shows an example of the operation of the embedded controller 31 in this case.
[0044] (Step S100) The embedded controller 31 connects to the OS102.
[0045] (Step S105) The embedded controller 31 receives a signal output from the OS 102 and determines whether the OS 102 has hung up based on that signal.
[0046] For example, in the Windows® OS, while OS102 is operating normally, OS102 periodically generates a heartbeat, for example, once per second. If a heartbeat is received within a predetermined period (for example, 1 second), the embedded controller 31 determines that OS102 is not hung up. If OS102 hangs up, OS102 stops generating heartbeats. If no heartbeat is received within a predetermined period (for example, 1 second or more), the embedded controller 31 determines that OS102 has hung up.
[0047] If OS102 is not hung up, the embedded controller 31 executes step S105 again. If OS102 is hung up, the embedded controller 31 executes step S110 below.
[0048] (Step S110) The embedded controller 31 outputs a command to the SSD 40 to store the data stored in the temporary memory 42 in the flash memory 41. The memory controller 43 receives the command and stores the log data stored in the temporary memory 42 in the flash memory 41. The memory controller 43 may also store cache data in the flash memory 41 in addition to the log data.
[0049] Even if OS102 hangs up, SSD40 continues to operate normally. The embedded controller31 can store data stored in temporary memory42 in flash memory41.
[0050] Next, we will explain the case where application 101 hangs up. Figure 4 shows an example of the operation of the embedded controller 31 in this case. The explanation of the same process as shown in Figure 3 will be omitted.
[0051] (Step S120) The embedded controller 31 receives a signal output from the OS 102 and determines whether or not the application 101 has hung up based on that signal.
[0052] For example, while application 101 is running normally, application 101 periodically generates heartbeats. For example, in the Windows® OS, System Center Operations Manager (SCOM) monitors these heartbeats. When the heartbeats stop, SCOM outputs an alert. If no alert is received, the embedded controller 31 determines that application 101 is not hung up. If an alert is received, the embedded controller 31 determines that application 101 is hung up.
[0053] In the Windows® operating system, when application 101 hangs, the Desktop Window Manager outputs a signal indicating that application 101 has hung. If this signal is not received, the embedded controller 31 may determine that application 101 has not hung. If this signal is received, the embedded controller 31 may determine that application 101 has hung.
[0054] Steps S100 and S110 are the same as the steps shown in Figure 3.
[0055] Even if application 101 hangs up, SSD 40 continues to operate normally. The embedded controller 31 can store data stored in temporary memory 42 in flash memory 41.
[0056] Next, we will explain the case where SSD40 hangs up. Figure 5 shows an example of the operation of the embedded controller 31 in this case. The explanation of the same process as shown in Figure 3 will be omitted.
[0057] (Step S130) The embedded controller 31 connects to the SSD 40.
[0058] (Step S135) The embedded controller 31 receives a signal output from the SSD 40 and determines whether or not the SSD 40 has hung up based on that signal.
[0059] For example, while SSD40 is operating normally, it periodically generates heartbeats. If heartbeats are received within a predetermined period, the embedded controller 31 determines that SSD40 is not hung up. If SSD40 hangs up, it stops generating heartbeats. If no heartbeats are received within a predetermined period, the embedded controller 31 determines that SSD40 has hung up.
[0060] If SSD40 is not hung up, the embedded controller 31 executes step S135 again. If SSD40 is hung up, the embedded controller 31 executes step S110. Step S110 is the same as step S110 shown in Figure 3.
[0061] (Step S140) After step S110 is performed, the embedded controller 31 resets the SSD 40. Specifically, the embedded controller 31 shuts off the power to the SSD 40 and then restarts the power to the SSD 40.
[0062] (Step S145) The embedded controller 31 notifies the OS 102 that the SSD 40 has been reset. The OS 102 can then resume communication with the SSD 40 without resetting it.
[0063] Even if SSD40 hangs up, some of its functions may still be operating. If the memory controller 43 can control the flash memory 41 and the temporary memory 42, the embedded controller 31 can store the data stored in the temporary memory 42 in the flash memory 41.
[0064] In this embodiment, an example of applying the present invention to an SSD 40 has been described, but the invention is not limited to this. The present invention may also be applied to storage such as a hard disk drive (HDD) or a USB key.
[0065] As described above, Notebook PC 1 (information processing device) is connectable to SSD 40 (storage) and is equipped with an embedded controller 31 (controller). After OS 102 starts communicating with SSD 40, if an abnormality is detected, the embedded controller 31 outputs a command to SSD 40 to store the data stored in temporary memory 42 (volatile memory) in flash memory 41 (non-volatile memory). With this configuration, Notebook PC 1 can save the data stored in temporary memory 42 within SSD 40. Even after SSD 40 is reset, the data stored in flash memory 41 remains available.
[0066] When the embedded controller 31 detects an abnormality in the OS 102, it outputs the above command to the SSD 40. If an abnormality such as a hang-up occurs in the OS 102, the notebook PC 1 can save the data stored in the temporary memory 42 in the SSD 40.
[0067] The embedded controller 31 receives the heartbeat output by OS102 when OS102 is operating normally. When OS102 stops outputting heartbeats, the embedded controller 31 outputs the above command to SSD40. Notebook PC1 can detect abnormalities such as OS102 hanging up by monitoring the heartbeat output by OS102.
[0068] When the embedded controller 31 receives an error signal output by the OS 102 when it detects an abnormality in application 101 on notebook PC 1, it outputs the above command to SSD 40. If an abnormality such as a hang-up occurs in application 101, notebook PC 1 can save the data stored in the temporary memory 42 in SSD 40.
[0069] The embedded controller 31 outputs the above command to the SSD 40 when it detects an abnormality in the SSD 40. If an abnormality such as a hang-up occurs in the SSD 40, the notebook PC 1 can save the data stored in the temporary memory 42 within the SSD 40.
[0070] After outputting the above command to the SSD 40, the embedded controller 31 resets the SSD 40. If an abnormality such as a hang-up occurs in the SSD 40, the notebook PC 1 can restore the SSD 40 to a normal state.
[0071] The embedded controller 31 receives the heartbeat output by the SSD 40 when it is operating normally. When the SSD 40 stops outputting heartbeats, the embedded controller 31 outputs the above command to the SSD 40. The notebook PC 1 can detect abnormalities such as a hang-up of the SSD 40 by monitoring the heartbeat output by the SSD 40.
[0072] (Second embodiment) Normally, repeated overwriting of data in non-volatile memory degrades the memory, so the number of times data can be written to non-volatile memory is limited. For this reason, volatile memory is used to temporarily store data that is frequently generated or updated. On the other hand, it is also possible to use non-volatile memory, which does not degrade easily even when data is repeatedly overwritten. In the second embodiment, flash memory 41 is used instead of temporary memory 42 as memory for temporarily storing data. In the second embodiment, temporary memory 42 is not essential.
[0073] If OS102 or other systems do not hang up, the embedded controller 31 instructs SSD40 to store data related to communication between OS102 and SSD40 in flash memory 41. If OS102 or other systems hang up, the embedded controller 31 instructs SSD40 to prevent overwriting of data in flash memory 41. When overwriting of data in flash memory 41 is prohibited, data already stored in flash memory 41 is not erased.
[0074] Referring to Figures 6 to 8, the operation of the embedded controller 31 when the OS 102 or the like hangs up will be explained. Figures 6 to 8 are flowcharts showing an example of the operation of the embedded controller 31 according to this embodiment. After the OS 102 starts communicating with the SSD 40, the processes shown in Figures 6 to 8 are executed.
[0075] Immediately after the process shown in Figures 6 to 8 begins, data writing to the flash memory 41 is enabled. Therefore, log and cache data are stored in the flash memory 41.
[0076] Figure 6 shows an example of the operation of the embedded controller 31 when OS102 hangs up. The embedded controller 31 executes the following step S150 instead of step S110 shown in Figure 3. In all other respects, the process shown in Figure 6 is the same as the process shown in Figure 3.
[0077] (Step S150) If OS102 hangs up, the embedded controller 31 outputs a command to SSD40 to prohibit overwriting data in flash memory 41. The memory controller 43 receives this command and sets the flash memory 41 to prohibit overwriting data.
[0078] Figure 7 shows an example of the operation of the embedded controller 31 when application 101 hangs up. The embedded controller 31 executes step S150 instead of step S110 shown in Figure 4. Step S150 shown in Figure 7 is the same as step S150 shown in Figure 6. In all other respects, the process shown in Figure 7 is the same as the process shown in Figure 4.
[0079] Figure 8 shows an example of the operation of the embedded controller 31 when the SSD 40 hangs up. The embedded controller 31 executes step S150 instead of step S110 shown in Figure 5. Step S150 shown in Figure 8 is the same as step S150 shown in Figure 6. In all other respects, the process shown in Figure 8 is the same as the process shown in Figure 5.
[0080] As described above, Notebook PC 1 (information processing unit) is connectable to SSD 40 (storage) and is equipped with an embedded controller 31 (controller). After OS 102 starts communicating with SSD 40 and data storage in flash memory 41 (non-volatile memory) begins, if an abnormality is detected, the embedded controller 31 outputs a command to SSD 40 to prohibit overwriting the data in flash memory 41. With this configuration, Notebook PC 1 can save the data stored in flash memory 41 within SSD 40. Even after SSD 40 is reset, the data stored in flash memory 41 remains usable.
[0081] While embodiments of the present invention have been described in detail above with reference to the drawings, the specific configuration is not limited to the embodiments described above, and may include design changes and the like that do not depart from the spirit of the present invention. [Explanation of Symbols]
[0082] 1. Laptop 10 Main Control Unit 11 CPU 12 Main Memory 13 Video Subsystems 14 Display section 21 Chipset 22 BIOS memory 31 Embedded Controllers 32 Input section 33 Power supply circuit 40 SSD 41 Flash memory 42 Temporary memory 43 Memory Controller
Claims
1. An information processing device that can be connected to storage, When the operating system (OS) of the information processing device starts communicating with the storage device and then detects an abnormality in the OS, the controller outputs a command to the storage device to store the data stored in the volatile memory of the storage device in the non-volatile memory of the storage device. An information processing device equipped with the following features.
2. The aforementioned controller, When the OS is operating normally, the system receives the heartbeat output by the OS. When the OS stops outputting the heartbeat, the command is output to the storage. The information processing apparatus according to claim 1.
3. An information processing device that can be connected to storage, After the operating system (OS) of the information processing device begins communicating with the storage device, when the OS receives an error signal that it outputs when it detects an abnormality in the application of the information processing device, the controller outputs a command to the storage device to store the data stored in the volatile memory of the storage device in the non-volatile memory of the storage device. An information processing device equipped with the following features.
4. The controller outputs the command to the storage when it detects an abnormality in the storage. The information processing apparatus according to any one of claims 1 to 3.
5. The aforementioned controller, When the storage is operating normally, the heartbeat output by the storage is received. When the storage stops outputting the heartbeat, the command is output to the storage. The information processing apparatus according to claim 4.
6. The controller outputs the command to the storage and then resets the storage. The information processing apparatus according to claim 4.
7. A method for controlling an information processing device that can be connected to storage, After the operating system (OS) of the information processing device begins communicating with the storage device, if it detects an abnormality in the OS, it outputs a command to the storage device to store the data stored in the volatile memory of the storage device in the non-volatile memory of the storage device. A method for controlling an information processing device.
8. A method for controlling an information processing device that can be connected to storage, After the operating system (OS) of the information processing device begins communicating with the storage device, when the OS receives an error signal that it outputs when it detects an abnormality in the application of the information processing device, it outputs a command to the storage device to store the data stored in the volatile memory of the storage device in the non-volatile memory of the storage device. A method for controlling an information processing device.