Semiconductor equipment

Abstract

One of the problems is to suppress a decrease in the potential of the gate of the pull-up transistor. . 【Solution】For the first transistor included in the drive circuit, the first terminal is electrically connected to the second wiring, the second terminal is electrically connected to the first wiring, and the gate is electrically connected to the first terminals of the second circuit and the third transistors. For the second transistor, the first terminal is electrically connected to the first wiring, the second terminal is electrically connected to the sixth wiring, and the gate is electrically connected to the gates of the first circuit and the third transistor. For the third transistor , the second terminal is electrically connected to the sixth wiring. The first circuit is electrically connected to the third wiring, the fourth wiring , the fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.

Description

Technical Field

[0001] Relates to a semiconductor device, a display device, a liquid crystal display device, a driving method thereof, or a method for producing them. In particular, it relates to a semiconductor device, a display device, a liquid crystal display device having a driving circuit formed on the same substrate as the pixel portion, or a driving method thereof. Or, it relates to an electronic device having the semiconductor device, the display device, or the liquid crystal display device.

Background Art

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as liquid crystal TVs. In particular, a technique for configuring a driving circuit such as a gate driver on the same substrate as the pixel portion using a transistor composed of a non-monocrystalline semiconductor greatly contributes to cost reduction and reliability improvement, and thus is actively developed. A transistor composed of a non-monocrystalline semiconductor may cause deterioration such as an increase in threshold voltage or a decrease in mobility. As this transistor deteriorates, there is a problem that the driving circuit malfunctions and an image cannot be displayed. Therefore, Patent Document 1 discloses a shift register capable of suppressing the deterioration of a transistor. In particular, in FIG. 7 of Patent Document 1, two transistors are used to suppress the characteristic deterioration of the transistor. One transistor is connected between the output terminal of the flip-flop and the wiring to which VSS (hereinafter, a negative power supply is supplied). The other transistor is connected between the output terminal of the flip-flop and the gate of the pull-up transistor. And, during the period when the output signal of the flip-flop becomes the L level, these two transistors are alternately turned on.

[0003] ​ When one transistor turns on, VSS is flipped through the other transistor. It is supplied to the output terminal of the ROP. When the other transistor turns on, the pull-up transistor The VSS supplied to the gate of one transistor is passed through the other transistor to the output of the flip-flop. It is supplied to the terminals. In this way, the degradation of the transistor can be suppressed. Furthermore, Since VSS is always supplied to the output terminal of the flip-flop, the output signal of the flip-flop This makes it easier to maintain the L level. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2005-50502 [Overview of the project] [Problems that the invention aims to solve]

[0005] In the configuration shown in Patent Document 1, during the period when the output signal of the flip-flop is at a high level... And because the other transistor turns on for a short time, the pull-up transistor The terminal and the output terminal of the flip-flop become conductive for a short time. At this time, pull up The gate potential of the transistor is high, and the output terminal of the flip-flop The potential is low. One aspect of the present invention is the gate of a pull-up transistor. The objective is to increase the potential of [the element].

[0006] Alternatively, when the gate potential of the pull-up transistor decreases, the pull-up transistor It may turn off. One aspect of the present invention aims to prevent malfunction of the shift register. do.

[0007] Alternatively, the pull-up transistor may turn on, allowing the shift register to function correctly. Even so, the gate potential of the pull-up transistor will still decrease. One manifestation involves increasing the potential difference (Vgs) between the gate and source of the pull-up transistor. The task is to listen.

[0008] Alternatively, if the Vgs of the pull-up transistor decreases, the pull-up transistor's O The resistance becomes large. One aspect of the present invention aims to make the display device smaller. Alternatively, one aspect of the present invention aims to make the display device high-resolution.

[0009] Alternatively, when the Vgs of the pull-up transistor decreases, the output signal of the flip-flop decreases. The rise time or fall time becomes longer. One aspect of the present invention relates to the pixel This prevents the writing of invalid signals (for example, video signals to pixels belonging to a different row) to the display product. The goal is to raise one's rank.

[0010] Alternatively, if the Vgs of the pull-up transistor decreases, the pull-up transistor's The channel width needs to be increased. And the channel width of the pull-up transistor needs to be large. When this happens, the channel width of other transistors also needs to be increased. One aspect of the present invention is The objective is to reduce the layout area. Alternatively, one aspect of the present invention relates to a display device. The challenge is to make the picture frame narrower.

[0011] Alternatively, as the channel width of the transistor increases, the gate and source of the transistor become more distinct. This makes the drain and short circuit more likely. One aspect of the present invention aims to improve yield. The problem is as follows. Or, one aspect of the present invention aims to reduce costs.

[0012] Or, when the channel width of the transistor increases, the parasitic capacitance of the shift register increases and ends up doing so. One aspect of the present invention aims to reduce distortion or delay in the signal input to the shift register and the like. Or, one aspect of the present invention aims to reduce power consumption and the like. To improve this, as a circuit for supplying a signal or voltage to the shift register [[ID=Eleven]] and the like, it is necessary to use a circuit having a large current capacity. One aspect of the present invention aims to reduce the size of the external circuit and the like. Or, one aspect of the present invention aims to reduce the size of the display device and the like.

[0013] Note that the description of the above problems does not prevent the existence of other problems.

Means for Solving the Problem

[0014] One aspect of the present invention includes a drive circuit having a first transistor, a second transistor, a third transistor, a first circuit, and a second circuit, and a pixel having a liquid crystal element. The first transistor has its first terminal electrically connected to a second wiring having a function as a signal line or a clock signal line, and its second terminal electrically connected to a first wiring having a function as a signal line, a gate line, a scanning line, or an output signal line. The gate is electrically connected to the first terminals of the second circuit and the third transistor. The second transistor has its first terminal electrically connected to the first wiring, and its second terminal electrically connected to a sixth wiring having a function as a power supply line or a ground line. The gate is the gate of the first circuit and the third transistor and is electrically connected to the first terminals of the first circuit and the third transistor. The third transistor is electrically connected to the second terminal, and the second terminal is electrically connected to the sixth wire. The second circuit is a third wire that functions as a signal line or a clock signal line. A fourth wiring that functions as a line, a fifth wiring that functions as a signal line, and The first circuit is electrically connected to the wiring of 6, and the first circuit is connected to the first wiring, the second wiring, and the wiring of 6. It is a liquid crystal display device that is electrically connected to it.

[0015] In one embodiment of the present invention, the first transistor is configured such that the potential of the gate of the first transistor is Accordingly, a bootstrap controls the timing of supplying the signal from the second wiring to the first wiring. It may also function as a transistor.

[0016] In one embodiment of the present invention, the second transistor receives the output signal of the first circuit, or the second transistor The conductivity between the sixth wire and the first wire is controlled according to the potential of the lamp gate. It can also function as a switch.

[0017] In one embodiment of the present invention, the third transistor, in response to the output signal of the first circuit, outputs a sixth transistor. It also functions as a switch that controls the conductivity between the wiring and the gate of the first transistor. That is also acceptable.

[0018] In one embodiment of the present invention, the first circuit responds to the signal of the first wiring or the signal of the second wiring. This controls the timing of supplying the voltage from the sixth wiring to the gate of the second transistor. Therefore, the function of raising, decreasing, or maintaining the gate potential of the second transistor, or the second It may also function as a control circuit that puts the gate of the transistor into a floating state.

[0019] In one embodiment of the present invention, the second circuit supplies signals to the third wiring, and supplies signals to the fourth wiring. Depending on the signal being supplied, or the signal supplied to the fifth wiring, the gate of the first transistor This controls the timing of supplying the signal to the fourth wiring or the voltage to the sixth wiring, Function to raise, decrease, or maintain the gate potential of the first transistor, or the first It may also function as a control circuit that puts the gate potential of a transistor into a floating state. .

[0020] In one embodiment of the present invention, the first circuit includes a fourth transistor, a fifth transistor, and It has 6 transistors and 7 transistors, and the 4th transistor is at the 1st terminal It is electrically connected to the second wiring, and the second terminal is electrically connected to the gate of the second transistor. The fifth transistor is connected, with the first terminal electrically connected to the sixth wire, and the second The terminal is electrically connected to the gate of the second transistor, and the gate is electrically connected to the first wiring. The sixth transistor is connected, with the first terminal electrically connected to the second wiring, and the second The terminal is electrically connected to the gate of the fourth transistor, and the gate is electrically connected to the second wiring. The seventh transistor is connected, with the first terminal electrically connected to the sixth wire, and the second The terminal is electrically connected to the gate of the fourth transistor, and the gate is electrically connected to the first wiring. The things that are connected are ramen.

[0021] In one embodiment of the present invention, the second circuit includes an eighth transistor, a ninth transistor, and It has 10 transistors, an 11th transistor, and a 12th transistor, and an 8th The transistor has its first terminal electrically connected to the fourth wire, and its second terminal connected to the first transistor. The gate of the inverter is electrically connected, the gate is electrically connected to the third wiring, and the ninth A transistor has a first terminal that is electrically connected to the gate of the first transistor, and a second terminal that is electrically connected to the gate of the first transistor. The terminal is electrically connected to the fourth wire, the gate is electrically connected to the fourth wire, and the tenth The transistor has a first terminal that is electrically connected to the gate of the first transistor, and a second terminal. The terminal is electrically connected to the sixth wire, the gate is electrically connected to the fifth wire, and the first Transistor 1 has its first terminal electrically connected to the first wire, and its second terminal connected to the sixth The wiring is electrically connected, the gate is electrically connected to the fifth wiring, and the twelfth transistor The first terminal is electrically connected to the first wiring, and the second terminal is electrically connected to the sixth wiring. The gate may be connected and electrically connected to a third wiring.

[0022] In one embodiment of the present invention, the drive circuit may be formed on the same substrate as the pixel. .

[0023] In one embodiment of the present invention, the channel width of the first transistor is the channel width of the second transistor and It may be larger than the channel width of the third transistor.

[0024] Note that various types of switches can be used. For example, electrical switches These include switches and mechanical switches. In other words, anything that can control the flow of electric current will work. It is not limited to specific things. For example, a transistor (e.g., bipod) can be used as a switch. (e.g., transistors, MOS transistors), diodes (e.g., PN diodes), PIN diode, Schottky diode, MIM (Metal Insulator) Metal diode, MIS (Metal Insulator Semiconductor) It is possible to use ductors (diodes, diode-connected transistors, etc.) It comes. Alternatively, a logic circuit combining these can be used as a switch.

[0025] Examples of mechanical switches include digital micromirror devices (DMDs). Switches using MEMS (Micro-Electro-Mechanical Systems) technology are available. ru.

[0026] Furthermore, using both N-channel and P-channel transistors, CMO An S-type switch may also be used as the switch.

[0027] Furthermore, when explicitly stating that A and B are connected, it means that A and B are electrically connected. When they are connected, when A and B are functionally connected, and when A and B are directly connected This includes cases where the object is present. Here, A and B are the object (for example, a device, an element, a rotation). (Let it be a path, wiring, electrode, terminal, conductive film, layer, etc.) Therefore, a predetermined connection relationship For example, not limited to the connection relationships shown in the diagram or text, but the connections shown in the diagram or text This includes things other than relationships.

[0028] For example, if A and B are electrically connected, the electrical connection between A and B is possible. Elements that perform this function (for example, switches, transistors, capacitive elements, inductors, resistive elements, etc.) One or more ions (such as ions) may be connected between A and B. Alternatively, A and B and As an example of a functionally connected system, a circuit that enables a functional connection between A and B (for example) For example, logic circuits (inverters, NAND gates, NOR gates, etc.) and signal conversion circuits (DA conversion). Circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits) (Step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources Switching circuits, amplification circuits (circuits that can increase signal amplitude or current, etc., operational amplifiers) (Differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, One or more control circuits (such as) may be connected between A and B. For example, between A and B Even if another circuit is in between, if the signal output from A is transmitted to B, then A and B and They are assumed to be functionally connected.

[0029] Furthermore, if it is explicitly stated that A and B are electrically connected, then A and B are electrically connected. When connected electrically (that is, when another element or circuit is placed between A and B) (when they are separated) and when A and B are functionally connected (that is, when there is no separate connection between A and B) (When they are functionally connected with a circuit in between) and when A and B are directly connected ( In other words, this includes cases where A and B are connected without any other element or circuit in between. In other words, if you explicitly state that they are electrically connected, then simply state that they are connected. This is equivalent to the case where it is explicitly stated only that it is included.

[0030] Furthermore, a display element, a display device having a display element, a light-emitting element, and a device having a light-emitting element A light-emitting device can take on various forms and contain various elements. For example For example, as a display element, display device, light-emitting element, or light-emitting device, EL (electroluminescent) EL elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LE D (white LED, red LED, green LED, blue LED, etc.), transistor (current-dependent) Transistors that emit light, electron-emitting elements, liquid crystal elements, electronic inks, electrophoretic elements, etc. Rating Light Bulb (GLV), Plasma Display (PDP), Digital Microwave Chromiller devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, Displays where contrast, brightness, reflectance, transmittance, etc., change due to electromagnetic effects. It can have a medium.

[0031] Liquid crystal elements control the transmission or non-transmission of light through the optical modulation effect of liquid crystals. It is an element composed of a pair of electrodes and liquid crystal. The optical modulation effect of the liquid crystal is as follows: Controlled by the electric field applied to the liquid crystal (including the electric field in the horizontal direction, the electric field in the vertical direction, or the electric field in the diagonal direction) It is controlled. Furthermore, liquid crystal elements include nematic liquid crystals, cholesteric liquid crystals, and smectic liquid crystals. Liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal Polymer liquid crystals, polymer dispersed liquid crystals (PDLCs), ferroelectric liquid crystals, antiferroelectric liquid crystals, main-chain liquid crystals Examples include side-chain polymer liquid crystals, plasma-addressable liquid crystals (PALC), and banana-shaped liquid crystals. This is possible. Furthermore, the LCD driving method is TN (Twisted Nematic) Code, STN (Super Twisted Nematic) mode, IPS (In- Plane-Switching) mode, FFS (Fringe Field Switching) tching) mode, MVA (Multi-domain Vertical Ali gnment) mode, PVA(Patterned Vertical Alignm) ent) mode, ASV (Advanced Super View) mode, ASM ( Axially Symmetrically aligned Micro-cell) mode , OCB (Optically Compensated Birefringence) ) Mode, ECB (Electrically Controlled Birefringence ngence) mode, FLC (Ferroelectric Liquid Crystal tal) mode, AFLC(AntiFerroelectric Liquid Cr (ystal) mode, PDLC (Polymer Dispersed Liquid) Crystal mode, guest host mode, Blue Phase mode The following can be used: However, this is not limited to liquid crystal elements and their driving methods. This allows you to use various things.

[0032] The light sources include electroluminescence, cold cathode fluorescent lamps, hot cathode fluorescent lamps, LEDs, and lasers. A light source such as a mercury lamp can be used. However, it is not limited to this, and other light sources may be used. Various materials can be used.

[0033] Furthermore, transistor configurations can take various forms and are not limited to a specific configuration. For example, a multi-gate structure with two or more gate electrodes can be applied. In a gate structure, the channel regions are connected in series, so multiple transistors are connected in series. This configuration will result in a connection to [the specified location].

[0034] As another example, a structure can be applied in which gate electrodes are positioned above and below the channel. ru.

[0035] Structures where the gate electrode is positioned above the channel region, and structures where the gate electrode is positioned below the channel region. Structures in which elements are arranged, positive staggered structure, inverse staggered structure, and channel regions divided into multiple regions A structure in which channel regions are connected in parallel, or a configuration in which channel regions are connected in series. This can also be applied. Furthermore, source electrodes and drain electrodes can be placed in the channel region (or a part thereof). Structures where these overlap can also be applied. Alternatively, a structure with an LDD (Long-Density Diagram) area can be applied.

[0036] Furthermore, if B is formed on top of A, or if B is formed on top of A, When describing this, it is not limited to the case that B is formed in direct contact with A. This also includes cases where this does not occur, i.e., when another object is intervening between A and B. Here, A and B are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers). (etc.)

[0037] Therefore, for example, explicitly stating that layer B is formed on top of layer A (or on top of layer A) If described, this applies to cases where layer B is formed in direct contact with layer A, and where layer A is formed on top of layer B. Another layer (such as layer C or layer D) is formed in direct contact with it, and layer B is formed in direct contact with it on top of that. This includes cases where a layer is formed. Note that other layers (e.g., layer C or layer D) are: It can be single-layered or multi-layered.

[0038] Furthermore, the same applies when it is explicitly stated that B is formed above A. It is not limited to B being in direct contact with A, but rather there may be another object between A and B. This includes cases where intervening layers are present. For example, if layer B is formed above layer A, In this case, there are two possibilities: when layer B is formed in direct contact with layer A, and when layer B is formed in direct contact with layer A. Then another layer (for example, layer C or layer D) is formed, and layer B is formed directly in contact with it. This includes cases where it is a single layer. Note that other layers (for example, layer C or layer D) may also be single layers. That's fine, and multiple layers are also acceptable.

[0039] Furthermore, B is formed on top of A, B is formed on top of A, or B is formed above A. When explicitly stating that something has been done, this includes cases where B is formed diagonally upwards. .

[0040] The same applies when B is below A, or when B is below A.

[0041] Furthermore, it is preferable that any terms explicitly stated as singular remain singular. However, this is not the only option; there can be multiple instances. Similarly, explicitly specifying the number of instances is also possible. For items that are listed as such, it is preferable that there be multiple items. However, this is not limited to these items. It can also be singular.

[0042] Note that in the diagram, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0043] Note that the figure is a schematic representation of an ideal example and is not limited to the shapes or values ​​shown in the figure. It cannot be fixed. For example, variations in shape due to manufacturing technology, variations in shape due to errors, noise Variations in signals, voltages, or currents, or signals, voltages, due to timing differences. Alternatively, it may include variations in current, etc.

[0044] Note that technical terms may be used to describe specific embodiments or examples. Many, but not limited to, this applies.

[0045] Furthermore, terms that are not defined (including scientific and technical terms such as specialized or academic terms) are generally... It can be used with the same meaning as the general meaning understood by those who are normally skilled in the art. (Dictionaries, etc.) The terminology defined therein should be interpreted in a way that is consistent with the context of the related technology. It is preferable.

[0046] Note that terms such as "1st," "2nd," and "3rd" refer to various elements, components, areas, layers, and regions that are separate from each other. It is used to distinguish and describe things. Therefore, terms such as "first," "second," and "third" refer to elements and parts. It does not limit the number of materials, areas, layers, zones, etc. Furthermore, for example, "the first" It can be replaced with "second" or "third," etc. [Effects of the Invention]

[0047] One aspect of the present invention makes it possible to increase the potential of the gate of a transistor. One aspect of the present invention can prevent malfunctions. Alternatively, one aspect of the present invention can prevent the transient The Vgs of the transistor can be increased. Alternatively, one aspect of the present invention is the ON of the transistor. The resistance can be reduced. Alternatively, in one aspect of the present invention, the channel width of the transistor This can be made smaller. Alternatively, one aspect of the present invention suppresses transistor degradation or This can be mitigated. Alternatively, in one aspect of the present invention, the layout area can be reduced. Yes, it is possible. Alternatively, one aspect of the present invention relates to a flip-flop, a shift register, or a scanline drive. To shorten the fall time or rise time of the output signal of a drive circuit, such as a motor circuit. This is possible. Alternatively, one aspect of the present invention makes the display device larger. Alternatively, this One aspect of the invention makes the display device high-resolution. Alternatively, one aspect of the invention is that the display The frame of the display device can be narrowed. Alternatively, in one aspect of the present invention, accurate signals can be sent to the pixels. It can be written on. Alternatively, one aspect of the present invention can improve the display quality. Alternatively, one aspect of the present invention can increase the yield. Alternatively, one aspect of the present invention This can reduce costs. Alternatively, one aspect of the present invention involves inputting into a shift register. The distortion or delay of the signal can be reduced. Alternatively, one aspect of the present invention is to eliminate Power consumption can be reduced. Alternatively, in one aspect of the present invention, the current capacity of the external circuit can be reduced. It can be cut. Alternatively, one aspect of the present invention relates to the size of the external circuit, or the external circuit The size of the display device with a path can be reduced. [Brief explanation of the drawing]

[0048] [Figure 1] A circuit diagram of a semiconductor device and a timing chart explaining its driving method. [Figure 2] A schematic diagram illustrating the driving method of a semiconductor device. [Figure 3] A schematic diagram illustrating the driving method of a semiconductor device. [Figure 4] A timing chart explaining the driving method of a semiconductor device. [Figure 5] Circuit diagram of a semiconductor device. [Figure 6] Circuit diagram of a semiconductor device. [Figure 7] Circuit diagram of a semiconductor device. [Figure 8] A circuit diagram of a semiconductor device and a timing chart explaining its driving method. [Figure 9] A schematic diagram illustrating the driving method of a semiconductor device. [Figure 10]Circuit diagram of a semiconductor device. [Figure 11] Circuit diagram of a semiconductor device. [Figure 12] A schematic diagram illustrating the circuit diagram of a semiconductor device and its driving method. [Figure 13] A schematic diagram illustrating the driving method of a semiconductor device. [Figure 14] Circuit diagram of a semiconductor device. [Figure 15] Circuit diagram of a semiconductor device. [Figure 16] Circuit diagram of a semiconductor device. [Figure 17] Circuit diagram of a semiconductor device. [Figure 18] Circuit diagram of a semiconductor device. [Figure 19] Circuit diagram of a shift register. [Figure 20] A timing chart explaining how to drive the shift register. [Figure 21] A timing chart explaining how to drive the shift register. [Figure 22] Circuit diagram of a shift register. [Figure 23] System block diagram of a display device. [Figure 24] A diagram illustrating the configuration of a display device. [Figure 25] A circuit diagram of a signal line drive circuit and a timing chart explaining its drive method. [Figure 26] A circuit diagram of a pixel and a timing chart explaining its driving method. [Figure 27] Pixel circuit diagram. [Figure 28] Circuit diagram of a semiconductor device. [Figure 29] A top view and a cross-sectional view of the display device. [Figure 30] Cross-section of a transistor. [Figure 31] Layout diagram of a shift register. [Figure 32] Layout diagram of a shift register. [Figure 33] A diagram illustrating electronic devices. [Figure 34]A diagram illustrating electronic devices. [Modes for carrying out the invention]

[0049] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiments are numerous. It can be implemented in several different ways, without deviating from its purpose and scope. Those skilled in the art will readily understand that the form and details can be changed in various ways. The interpretation is not limited to the description of the form of implementation. Similarly, symbols indicating the same thing are shown using common symbols across different drawings, and the same part or the same Detailed explanations of the parts with similar functions will be omitted.

[0050] Furthermore, the content described in one embodiment (even a part of it) may vary depending on the form of its implementation. Other content (even partial content) described in the tone, and / or one or more other implementations To apply, combine, or replace the content described in the form (even if only a part of it is acceptable), It is possible to do things like this.

[0051] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content stated, or the content stated using the text described in the specification.

[0052] Furthermore, a diagram (even a partial one) described in one embodiment may refer to another part of that diagram. Further figures (even partial ones) described in that embodiment, and / or one or more figures. In another embodiment, the diagram (or even just a part of it) described above can be combined by This allows for the creation of even more diagrams.

[0053] (Embodiment 1) This embodiment describes an example of a semiconductor device. The semiconductor device of this embodiment is For example, it can be used in shift registers, gate drivers, source drivers, or display devices. It is possible to do so. Furthermore, the semiconductor device in question may be referred to as a flip-flop or a drive circuit. It is possible.

[0054] First, an example of the semiconductor device of this embodiment will be described with reference to Figure 1(A). Figure 1 (A) shows circuit 100. Note that circuit 100 is a semiconductor device, a drive circuit, or flip It can be described as a pflop.

[0055] Circuit 100 includes transistor 101 (also called the first transistor) and transistor 10 2 (also called the second transistor), transistor 103 (also called the third transistor) ), circuit 104 (also called the first circuit), and circuit 105 (also called the second circuit) Circuit 104 has terminals 104a, 104b, 104c, and 104d. It has multiple terminals. Circuit 105 has terminals 105a, terminal 105b, terminal 105c, terminal It has multiple terminals, namely child 105d, terminal 105e, and terminal 105f. However, this Not limited to, any of these transistors or any of these circuits may be omitted. Alternatively, various elements such as capacitive elements, resistive elements, or diodes, or among these. It is possible to replace it with a circuit that combines any of the elements. Or, Various elements such as diodes, capacitive elements, resistive elements, or diodes, or these It is possible to add a new circuit by combining any of these elements. Alternatively, Depending on the configuration of path 104 and circuit 105, terminals may be added or omitted. It is possible.

[0056] For example, transistors 101-103 are assumed to be N-channel type. In a channel-type transistor, the potential difference (Vgs) between the gate and source is equal to the threshold voltage (V It shall turn on when it exceeds th. However, it shall not be limited to this, the transistor Numbers 101-103 can be P-channel type. P-channel transistors are The device turns on when the potential difference (Vgs) between the gate and source falls below the threshold voltage (Vth). It shall be done.

[0057] For example, as shown in Figure 28(A), circuit 104 has two input AND and NOT gates. This combinational logic circuit is assumed to be a combination of two signals. The inverted signal of the other input signal (e.g., the signal from wiring 113) The logical AND operation with the specified number shall be taken. However, it is not limited to this, and as for circuit 104, see Figure 2 As shown in 8(B), it is possible to use a 2-input NOR gate. Also, circuit 104 Various circuits can be used for this purpose.

[0058] For example, circuits 104 and 105 each have one or more transistors. Let it be assumed that the polarity of these transistors is the same as that of transistors 101-103. Assume they have the same polarity. By making the polarity of the transistors the same, manufacturing process It is possible to reduce the amount, improve yield, improve reliability, or reduce costs. And, without limiting thereto, circuits 104 and 105 are N-channel transistors and P It is possible to have a channel-type transistor. That is, circuits 104 and 105 This can be a CMOS circuit.

[0059] For example, terminals 104a to 104c function as input terminals, and terminal 104d is , and shall function as output terminals. And, as an example, terminals 105a to 105d are Terminals 105e and 105f function as input terminals, while terminals 105e and 105f function as output terminals. This shall apply. However, it is not limited to this.

[0060] Furthermore, circuits 104 and / or 105 can have even more terminals. Alternatively, circuits 104 and / or 105 may omit some of their terminals. be.

[0061] Next, an example of the connection relationship of circuit 100 will be described. The first terminal of transistor 101 The second terminal of transistor 101 is connected to wiring 112, and the second terminal of transistor 101 is connected to wiring 111. The first terminal of transistor 102 is connected to the wiring 116, and the transistor 102 The second terminal is connected to wiring 111. The first terminal of transistor 103 is connected to wiring 11 The second terminal of transistor 103 is connected to 6, and the gate of transistor 101 is connected to the gate of transistor 101. The gate of transistor 103 is then connected to the gate of transistor 102. Terminal 104a of circuit 104 is connected to wiring 112, and terminal 104b of circuit 104 is connected to wiring 1 Terminal 104c of circuit 104 is connected to 11, and terminal 104c of circuit 104 is connected to wiring 116, and terminal 104 of circuit 104 is connected to wiring 116. Child 104d is connected to the gate of transistor 102. Terminal 105a of circuit 105 is , connected to wiring 113, terminal 105b of circuit 105 is connected to wiring 114, circuit 1 Terminal 105c of circuit 05 is connected to wiring 115, and terminal 105d of circuit 105 is connected to wiring 11 6 is connected, and terminal 105e of circuit 105 is connected to the gate of transistor 101. Terminal 105f of circuit 105 is connected to wiring 111. However, it is not limited to this, other It is also possible to create various connection configurations.

[0062] Note that the gate of transistor 101, the second terminal of transistor 103, or circuit 10 The connection point of terminal 105e of 5 is indicated as node A. Then, the gate of transistor 102, The connection point between terminal 104d of circuit 104, or the gate of transistor 103, and node B. This is shown. Furthermore, nodes A and B can be shown as wiring or terminals.

[0063] Note that wiring 111, wiring 112, wiring 113, wiring 114, wiring 115, and wiring 116 It is possible to indicate this as a terminal.

[0064] As previously mentioned, new terminals are added to circuit 104 and / or circuit 105. It is possible to do so. In such cases, the terminal can connect to various wires or various elements. It is possible to continue.

[0065] Furthermore, any of the wirings 111 to 116 may be omitted, and / or new wiring may be added. This is possible.

[0066] Next, an example of a signal or voltage input to or output to wiring 111-116 will be described. As an example, let's assume that signal OUT is output from wiring 111. Signal OUT is H Often, it is a digital signal having a level and an L level, and the output signal of circuit 100, select Functions as a selector signal, transfer signal, start signal, reset signal, gate signal, or scan signal. It is possible to do so. For example, the wiring 112 is to which signal IN1 is input. Signal IN1 is often a digital signal and can function as a clock signal. It is possible. Let's assume that signal IN2 is input to wiring 113 as an example. Signal I N2 is the inverted signal of signal IN1, or a signal that is 180° out of phase with signal IN1. There are many combinations, and it can function as an inverting clock signal. Wiring 114 is an example and Then, assume that signal IN3 is input. Signal IN3 is often a digital signal. It can function as a start signal or a vertical synchronization signal. Or, circuit 1 When 00 is used in a shift register or display device, signal IN3 is used in another stage (e.g., before) It can function as a transfer signal from a row, or as a signal to select another row (e.g., the previous row). It is possible. As an example, signal IN4 will be input to wiring 115. Signal 4 is often a digital signal and can function as a reset signal. Alternatively, if circuit 100 is used as a shift register or display device, signal IN4 is different It can function as a signal to select a row (for example, the next row). Wiring 116 As an example, let's assume that voltage V1 is input. Voltage V1 is an L-level signal OUT. If the value is approximately equal to that of signal IN1, signal IN2, signal IN3, or signal IN4 In many cases, it can function as ground voltage, power supply voltage, or negative power supply voltage. And, not limited to this, wiring 111-116 can also carry various other signals, various currents, or Various voltages can be input. For example, wiring 112, wiring 113, wiring 114 , and / or, a voltage such as voltage V1 or voltage V2 may be supplied to wiring 115. Alternatively, the wiring 116 can be connected to signal OUT, signal IN1, signal IN2, signal IN3, or Signals such as signal IN4 can be input to this. Alternatively, wiring 111, wiring 11 2. Signals or voltages etc. are transmitted to wiring 113, wiring 114, wiring 115, and / or wiring 116. It is possible to leave these wires in a floating state without inputting any power.

[0067] Note that "approximately" refers to errors due to noise, errors due to process variations, and manufacturing errors of the element. This includes errors due to variations in degree and / or various other errors such as measurement errors.

[0068] Note that wiring 111 (also called the first wiring) is a signal line, gate line, scan line, or output signal line. It can function as a line. Wiring 112 (also called the second wiring) is a signal line, or This can function as a clock signal line. Wiring 113 (also called the third wiring) It can function as a signal line or a clock signal line. Wiring 114 (4th Wiring (also called a signal line) can function as a signal line. Wiring 115 (the fifth wiring and Wiring 116 (also called the sixth wiring) can function as a signal line. ) can function as a power line or a ground line. However, it is not limited to this. Furthermore, wires 111-116 can function as various other types of wiring. For example Then, voltage is supplied to wiring 112, wiring 113, wiring 114, and / or wiring 115. In this case, these wires can function as power lines. Or, wire 116 If a signal is input, wiring 116 can function as a signal line. Alternatively, wiring 114 and / or wiring 115 are signal lines, gate lines, similar to wiring 111. It can function as a scan line or an output signal line.

[0069] Furthermore, it is possible to input a multiphase clock signal to circuit 100. For example, n( When we refer to an n-phase clock signal as a clock signal with n being a natural number, an n-phase clock signal is one in each phase. This refers to n clock signals that are shifted by n periods. Alternatively, it refers to a multiphase clock signal. Either two of these can be input to wiring 112 and wiring 113, respectively.

[0070] Furthermore, a balanced clock signal can be used as signal IN1 or signal IN2. Yes, and it is possible to use unbalanced (also called unbalanced) clock signals. Balanced means This refers to a state in which the period of time when the temperature is at the H level is equal to the period when it is at the L level. Balance refers to a state in which the period of time when the temperature is at the H level and the period when it is at the L level are different within a single cycle. .

[0071] For example, let V1 be the potential of an L-level signal, and V2 be the potential of an H-level signal. Let it be assumed that V2 > V1. And when we refer to the voltage as V2, The voltage V2 is assumed to be approximately equal to the signal's H level. However, it is not limited to this. Furthermore, the potential of an L-level signal can be lower than V1, and it can also be higher than V1. This is possible. Alternatively, the potential of the H-level signal can be lower than V2. It is possible to achieve a higher level than V2.

[0072] Next, we will describe an example of the functions of transistors 101-103 and circuits 104 and 105. I will explain.

[0073] Transistor 101 transmits a high-level signal IN1 to wiring 111, depending on the potential of node A. By controlling the timing of the supply, the timing at which the signal OUT becomes high can be controlled. It has a control function and is a pull-up transistor or bootstrap transistor. It is possible for it to function. Transistor 102 receives the output signal of circuit 104, or the noise. By controlling the conductivity between wiring 116 and wiring 111 according to the potential of B, It has the function of controlling the timing of supplying voltage V1 to line 111 and functions as a switch. It is possible to do so. Transistor 103 receives the output signal of circuit 104, or the power of node B. Depending on the position, the conductivity state between wiring 116 and node A is controlled to supply power to node A. It has a function to control the timing of supplying pressure V1 and can function as a switch. That is the case.

[0074] Circuit 104 sends signal IN3 or voltage V1 to node B depending on whether signal OUT or signal IN1 is present. By controlling the timing of supply, the potential of node B can be increased, decreased, or maintained. It has the function of holding, or the function of putting node B into a floating state, and can function as a control circuit. It is possible. And, by controlling the potential of node B, circuit 104 can It is possible to have a function to control the conduction state of sta 102 and transistor 103. For example, in circuit 104, when signal IN2 becomes low level, voltage V1 or low level signal It has the function of reducing the potential of node B by supplying IN2 to node B. As another example, circuit 104, when signal OUT becomes high level, has a voltage V1 or low level It has the function of reducing the potential of node B by supplying a signal to node B. As an example, when signal OUT is at a low level, and signal IN2 is at a high level, the voltage V2 Alternatively, by supplying an H-level signal IN2 to node B, the potential of node B can be increased. It has the function of being able to do so.

[0075] Circuit 105 sends signal I to node A according to signal IN2, signal IN3, or signal IN4. By controlling the timing of supplying N3 or voltage V1, the potential of node A is increased. It has a function to reduce or maintain, or a function to put node A into a floating state, and the control circuit and It is possible for it to function as follows: Alternatively, circuit 105 can receive signals IN2, IN3, or By controlling the timing of supplying voltage V1 to wiring 111 in accordance with signal IN4, The function of reducing or maintaining the potential of wiring 111, or the function of making wiring 111 float. It has the ability to, for example, when signal IN2 or signal IN3 reaches a high level, circuit 105 will By supplying a level signal IN3 or voltage V2 to node A, the potential of node A is controlled. It has a function to raise the level. As another example, circuit 105 has a function to raise the level when signal IN2 or signal IN4 is H When the level is reached, supply a voltage V1 or L level signal to node A or wiring 111. This has the function of reducing the potential of node A or the potential of wiring 111.

[0076] However, this is not limited to the transistors 101-103 and circuits 104-105, It is also possible to have various other functions. Alternatively, these elements or circuits may have the above-mentioned functions. It is possible to have a function that does not exist.

[0077] Next, regarding the operation of the semiconductor device in Figure 1(A), see Figure 1(B), and Figures 2(A) and 2(B) This will be explained with reference to Figures 2(C), 3(A), and 3(B). Figure 1(B) shows a semiconductor This is an example of a timing chart used to explain the operation of a device. Figure 1(B) shows 1 movement During the operation period, the signals IN1, IN2, IN3, IN4, and the potential Va of node A An example of the potential Vb at node B and the signal OUT is shown. And the timing in Figure 1(B) One operating period of the chart consists of periods T1, T2, T3, T4, and T5. Figure 2(A) is an example of a schematic diagram of the operation of the semiconductor device in Figure 1(A) during period T1. Yes. Figure 2(B) is an example of a schematic diagram of the operation of the semiconductor device in Figure 1(A) during period T2. Yes. Figure 2(C) is an example of a schematic diagram of the operation of the semiconductor device in Figure 1(A) during period T3. Yes. Figure 3(A) is an example of a schematic diagram of the operation of the semiconductor device in Figure 1(A) during period T4. Yes. Figure 3(B) is an example of a schematic diagram of the operation of the semiconductor device in Figure 1(A) during period T5. be.

[0078] For example, when signal IN3 reaches a high level, the semiconductor device in Figure 1(A) will operate during period T. The actions in step 1, the actions in period T2, and the actions in period T3 shall be performed in that order. And then, until signal IN3 reaches a high level again, the semiconductor device in Figure 1(A) The operation in period T4 and the operation in period T5 are repeated in order. However, The semiconductor device shown in Figure 1(A) operates in various ways during periods T1 to T5. It is possible to do it in this order.

[0079] First, during period T1, signal IN1 becomes low and signal IN2 becomes high. Signal IN3 becomes high level, and signal IN4 becomes low level. Therefore, circuit 105 begins to raise the potential of node A. At this time, signal IN1 is L As it becomes a bell, circuit 104 begins to decrease the potential of node B to V1. So, transistors 102 and 103 turn off, and wire 116 and wire 111 becomes non-conductive, and wiring 116 and node A become non-conductive. After that, The potential of line A is equal to the potential of wiring 112 (V1) and the threshold voltage of transistor 101 (Vth1) When the sum of (V1 + Vth101) is reached, transistor 101 turns on. Then, since wire 112 and wire 111 become conductive, the L-level signal IN1 is, Wiring 112 is supplied to wiring 111 via transistor 101. Therefore, wiring 11 The potential at 1 becomes V1, so the signal OUT becomes L level. After that, circuit 105 is no The potential of node A continues to rise further. And circuit 105 raises the potential of node A to a certain extent. Once the value reaches at least V1+Vth101 or higher, the signal to node A is sent. Alternatively, the voltage supply is stopped. Therefore, the potential at node A at this time (for example, V1 + Vth1) It remains in a floating state while maintaining a value of 01 or higher.

[0080] During period T1, circuit 105 outputs a voltage V1 or an L-level signal to wiring 111. In many cases, it is supplied. However, it is not limited to this, and circuit 105 supplies voltage or By not supplying signals, the circuit 105 and the wiring 111 are made non-conductive. This is possible.

[0081] Next, during period T2, signal IN1 becomes high level and signal IN2 becomes low level. Signal IN3 becomes low, and signal IN4 remains low. Circuit 105 is voltage Or, in many cases, signals etc. are not supplied to node A, so node A during period T1 It remains in a floating state while maintaining a potential (V1 + Vth101 or higher). Therefore, Since the transistor 101 remains on, wiring 112 and wiring 111 remain electrically connected. This is what happens. At this time, the signal IN1 rises from L level to H level, so the power of wiring 111 The rank begins to rise from V1. Then, since node A is in a floating state, node A The potential increases due to the parasitic capacitance between the gate and the second terminal of transistor 101. This is what is known as bootstrap operation. In this way, the potential of node A becomes V2 + Vth10 It rises to 1 + α (where α is a positive number). Then the potential of wiring 111 is at the H level of signal IN2. The potential rises to V2, so the signal OUT becomes high. At this point, the signal O Since UT becomes high level, circuit 104 sends a voltage V1 or low level signal to node B. By supplying this, the potential of node B is maintained at V1. Therefore, transistor 10 2. And transistor 103 remains off, so wiring 116 and wiring 111 are deconducted. The current state remains open, and the connection between wiring 116 and node A remains non-conductive.

[0082] During period T2, circuit 104 shall not supply signals or voltages to node B. This makes it possible to make circuit 104 and node B non-conductive. 104 can make node B float. Even in this case, node B floats In this state, the potential of node B is often maintained at V1.

[0083] Furthermore, during period T2, circuit 105 does not supply signals or voltages to wiring 111. This makes it possible to make circuit 105 and wiring 111 non-conductive. However, Without limiting itself, circuit 105 supplies voltage V2 or an H-level signal to wiring 111. It is possible to do so.

[0084] Next, during period T3, signal IN1 becomes low and signal IN2 becomes high. Signal IN3 remains at a low level, while signal IN4 becomes high. Therefore, circuit 105 reduces the potential of node A to V1. Thus, Since transistor 101 is turned off, wiring 112 and wiring 111 become non-conductive. Here, the potential of node A is controlled by a voltage or signal supplied via circuit 105. Therefore, the timing at which transistor 101 turns off is when signal IN1 is at a low level. Often slower than Ming. That is, when transistor 101 is ON. The signal IN1 may be at a low level. In this case, the low-level signal IN1 is connected to wiring 11 The current is supplied from 2 to wiring 111 via transistor 101. Therefore, the potential of wiring 111 is Since it becomes V1, signal OUT becomes L level. At this time, signal IN1 is L level. Then, circuit 104 supplies an L-level signal IN2 or voltage V1 to node B. Therefore, the potential of node B is maintained at V1. Thus, transistor 102 and transistor Since 103 remains off, wires 116 and 111 remain non-conductive. Wiring 116 and node A remain in a non-conductive state.

[0085] Furthermore, during period T3, circuit 104 shall not supply signals or voltages to node B. This makes it possible to make circuit 104 and node B non-conductive. 104 can make node B float. Even in this case, node B floats In this state, the potential of node B is often maintained at V1.

[0086] During period T2, circuit 105 supplies voltage V1 or an L-level signal to wiring 111. It is possible to supply it. Alternatively, circuit 105 can supply voltage or signals etc. to wiring 111. By not doing so, it is possible to make the circuit 105 and the wiring 111 non-conductive. ru.

[0087] Next, during period T4, signal IN1 becomes high level and signal IN2 becomes low level. Signal IN3 remains at a low level, and signal IN4 becomes low. Signal OUT becomes low. As long as the signal IN1 remains at a high level, circuit 104 will receive the high-level signal IN1 or By supplying voltage V2 to node B, the potential of node B is raised to V2. This will turn on transistors 102 and 103, so wiring 11 6 and wiring 111 become conductive, and wiring 116 and node A become conductive. Since voltage V1 is supplied from wiring 116 to wiring 111 via transistor 102, The potential of wiring 111 is maintained at V1. Then, voltage V1 is transmitted from wiring 116 to the transistor Since it is supplied to node A via 103, the potential of node A is maintained at V1. Therefore, the signal OUT remains at a low level.

[0088] Circuit 105 supplies voltage V1 or an L-level signal to wiring 111 or node A. It is possible to do so. Alternatively, circuit 105 may be wired to 111 or no. By not supplying power to node A, it is possible to make circuit 105 and node A non-conductive. Therefore, it is possible to make the circuit 105 and the wiring 111 non-conductive.

[0089] Next, during period T5, signal IN1 becomes low and signal IN2 becomes high. Signal IN3 remains at a low level, and signal IN4 remains at a low level. Signal IN1 Since it becomes L level, circuit 104 supplies an L level signal IN1 or voltage V1 to node B. By supplying it, the potential of node B is reduced to V1. Therefore, the transient Since transistor 102 and transistor 103 are turned off, wiring 116 and wiring 111 are deconnected. The circuit becomes conductive, and wiring 116 and node A become non-conductive. At this point, circuit 105 has a voltage If a V1 or L level signal, etc., is supplied to wiring 111 or node A, then wiring 111 Alternatively, the potential of node A is maintained at V1. However, if circuit 105 distributes voltage or signals, Even if no power is supplied to line 111 or node A, the potential of wiring 111 or node A is V It remains at 1. This is because wiring 111 and node A are in a floating state, so for period T This is because the potential (V1) at point 4 is maintained. Thus, the signal OUT remains at the low level. This is the result.

[0090] The operation of the semiconductor device shown in Figure 1(A) has been explained above. During period T2, a decrease in the potential of node A can be prevented. In conventional techniques, At interval T2, until the potential of wiring 111 rises to a certain value, node A and wiring 1 11 was in a conductive state. Therefore, the potential of node A was decreasing. However, Figure 1( In semiconductor device A), during period T2, node A and wiring 111 are in a conductive state. No. Therefore, the decrease in the potential of node A can be prevented. As a result, the transient This can prevent a decrease in the Vgs of transistor 101. Or, the Vgs of transistor 101 It can be increased. Or, a malfunction caused by the potential of node A decreasing too much. This can prevent the decrease in Vgs of transistor 101. Therefore, the channel width (W) of transistor 101 can be reduced. The output area can be reduced. Alternatively, the Vgs of transistor 101 can be increased. This allows us to reduce the on-resistance of transistor 101. This results in a reduction in the falling or rising time of the signal OUT, or a delay in the signal OUT. This can lead to a reduction in [the number of cases].

[0091] Alternatively, in the semiconductor device shown in Figure 1(A), the polarity of all transistors can be set to N-channel or P It is possible to use a channel type. Therefore, the number of processes can be reduced, the yield can be improved, and reliability can be increased. This can improve performance or reduce costs. In particular, if all transistors are N-channel In the case of the L-type transistor, the semiconductor layer can be made of non-single-crystal semiconductors, microcrystalline semiconductors, or organic semiconductors. It becomes possible to use materials or oxide semiconductors. Therefore, the number of processes and yield can be reduced. This can lead to improvements in performance, increased reliability, or reduced costs. However, it is not limited to these. First, the semiconductor device in Figure 1(A) consists of a P-channel transistor and an N-channel transistor. It is possible to have a CMOS circuit composed of transistors. Alternatively, a transistor As the semiconductor layer, it is possible to use a single-crystal semiconductor or a polycrystalline semiconductor.

[0092] Alternatively, in the semiconductor device shown in Figure 1(A), at least one of period T4 and period T5 And transistors 101-103 turn off. Therefore, the transistors operate for one period. Because it does not remain in an on state continuously, transients such as an increase in threshold voltage or a decrease in mobility occur. This can suppress the degradation of the transistor's characteristics. In particular, non-single crystal semiconductors can be used as the semiconductor layer of a transistor. When semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors are used, The degradation of the characteristics of the transistor is often quite noticeable. However, in the semiconductor device shown in Figure 1(A), Because it can suppress the degradation of the transistor's characteristics, it can be used as a semiconductor layer for transistors. It becomes easy to use crystalline semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors. However, it is not limited to this, and the semiconductor layer may be a polycrystalline semiconductor or a single-crystal semiconductor. It is possible to use it.

[0093] Note that period T2 is indicated as the selected period, and the other periods (periods T1, T3, T4, and It is possible to indicate period T5) as a non-selective period. Alternatively, period T1, period T2, period T3, period T4, and period T5 are defined as set period, output period, reset period, and first It is possible to refer to this as a non-selection period or a second non-selection period.

[0094] Note that in the example timing chart in Figure 1(B), signals IN1 and IN2 are in equilibrium. While one case has been shown, it is not limited to this. As already mentioned, signal IN1 and signal IN2 can be non-balanced. Alternatively, the timing chart in Figure 1(B) In this case, the time at which signal IN1 (or signal IN2) is at a high level, and the time at which signal IN1 (or signal When the time that IN2) is at a low level is approximately equal, that is, when the time that signal IN1 and signal IN The example shown assumes that the duty cycle of component 2 is approximately 50%, but it is not limited to this case. The duty cycles of signals IN1 and IN2 can be 50% or more. It is possible for it to be 50% or less. In Figure 4(A), signals IN1 and IN2 are non-linear. The timing is when the balance is maintained and the duty cycles of signals IN1 and IN2 are not 50%. A timing chart is shown. In the timing chart of Figure 4(A), during period T2, signal I When N1 reaches a high level, the potential of node A rises due to the bootstrap action, and the signal OUT becomes high level. Then, signal IN1 becomes low level. Timing in Figure 1(B) In the chart, simultaneously or with a slight delay, the potential of node A decreases to V1. To be precise, that is, as soon as signal IN1 becomes low, or with a slight delay, the transition The starter 101 is turned off. However, in the timing chart in Figure 4(A), the signal IN4 is The potential of node A remains high until it reaches a high level, or until signal IN2 reaches a high level. It even goes that far. In other words, even after the signal IN1 goes to a low level, transistor 101 remains on. Therefore, since wiring 112 and wiring 111 remain in a conductive state, the signal is at an L level. IN1 is supplied from wiring 112 to wiring 111 via transistor 101. Then, Since the channel width (W) of transistor 101 is often large, the potential of wiring 111 is It quickly decreases to V1. Therefore, the falling edge time of the signal OUT can be shortened.

[0095] In FIG. 4(A), one period of signal IN1 is denoted as period Tck. And, among one period, the period during which signal IN1 is at the H level is denoted as period Tck(H), and among one period, the period during which signal IN1 is at the L level is denoted as period Tck(L). Similarly, one period of signal IN2 is denoted as period Tckb. And, among one period, the period during which signal IN2 is at the H level is denoted as period Tckb(H), and the period during which signal IN2 is at the L level among one period is denoted as period Tckb(L). The relationship between period Tck and period Tckb, the relationship between period Tck(H) and period Tckb(H), and the relationship between period Tck(L) and period Tckb(L) are often Tck≈Tckb, Tck(H)≈Tckb(H), and Tck(L)≈Tckb(L), respectively. However, it is not limited to this.

[0096] In FIG. 4(A), the relationship between period Tck(H) and period Tck(L) is preferably Tck( H)<Tck(L). Similarly, the relationship between period Tckb(H) and period Tckb (L) is preferably Tckb(H)<Tckb(L). By doing so, as described above, the fall time of signal OUT can be shortened. However, it is not limited to this, and it is possible that Tck(H)>Tck(L), and it is possible that Tckb(H)>Tckb(L).

[0097] As shown in the timing chart of FIG. 4(A), it is possible to set signal OUT to the L level in the middle of period T2. To achieve this, signal IN4 is set to the H level in the middle of period T2. Then, circuit 100 in FIG. 1(A) forcibly operates in period T3, or ​​It will start an operation corresponding to this. First, since signal IN4 becomes high level, circuit 105 By supplying a voltage V1 or L-level signal to node A and wiring 111, The potential of node A and wiring 111 is reduced to V1. Therefore, signal OUT is The signal becomes L level. Then, the signal OUT becomes L level, and the signal IN1 remains H level. Therefore, circuit 104 supplies a high-level signal IN1 to node B, similar to the period T4. Therefore, the potential of node B is set to V2. Then, transistor 102 and the transistor When the starter 103 is turned on, wire 116 and wire 111 become electrically connected, and wire 116 and Node A and the other node become conductive. Therefore, voltage V1 is transmitted from wiring 116 to transistor 102. Since it is supplied to wiring 111 via this, the potential of wiring 111 is maintained at V1. On the other hand, voltage Since V1 is supplied from wiring 116 to node A via transistor 103, node A The potential of node A is maintained at V1. At this time, the potential of node A is V1, so the transistor 101 is turned off. Therefore, wires 112 and 111 become non-conductive. Therefore, the period during which signal OUT is at a high level is shorter than the time during which signal IN1 is at a high level. This can be done. As a result, the time during which signal IN1 is at a high level and the time during which signal OUT is at a high level can be reduced. Compared to the case where the time it takes for the bell to ring is roughly the same, the drive frequency becomes slower. Therefore, This can help reduce electricity consumption.

[0098] For example, among transistors 101 to 103, or in Figure 1(A) Among the transistors in the semiconductor device, transistor 101 has the largest channel width. This is preferable. By doing so, the on-resistance of transistor 101 becomes smaller. Therefore, the rise time or fall time of the signal OUT can be shortened. Furthermore, and not limited to this, the channel width of transistor 101 is such that the semiconductor device in Figure 1(A) It is possible for it to be smaller than any of the transistors it contains.

[0099] Note that when referring to the channel width of a transistor, this is referred to as the W / L of the transistor (W: channel width). This can be rephrased as the ratio of channel width (L: channel length).

[0100] For example, the channel width of transistor 102 is equal to the channel width of transistor 103. It is preferable that it be larger than the width. This is because the wiring 111 is connected to gate wires or pixels, etc. Because this is often the case, the load on wiring 111 is often greater than the load on node A. And transistor 102 has the function of supplying voltage V1 to wiring 111. This is because transistor 103 has the function of supplying voltage V1 to node A. Furthermore, and not limited to this, the channel width of transistor 102 is the channel width of transistor 103. It is possible to make it smaller than the channel width.

[0101] For example, in transistor 101, the parasitic capacitance between the gate and the second terminal. It is preferable that this is greater than the parasitic capacitance between the gate and the first terminal. This is because, In T2, the potential of node A tends to increase due to the bootstrap operation. Therefore, a conductive layer that functions as a gate and a layer that functions as a source or drain. The area where the conductive layer overlaps is preferably larger on the second terminal side than on the first terminal side. Yes. However, it is not limited to this.

[0102] Note that the wiring can be divided into a plurality of wirings. And, the same signal or voltage can be input to the plurality of wirings, or different signals or voltages can be input. Alternatively, the plurality of wirings can be connected to the same wiring or the same element, or the plurality of wirings can be connected to different wirings or different elements. An example in FIG. 5(A) shows a configuration in the case where wiring 112 is divided into a plurality of wirings 112A to 112B, and wiring 116 is divided into a plurality of wirings 116A to 116D. The first terminal of transistor 101 is connected to wiring 112A, and terminal 104 a of circuit 104 is connected to wiring 112B. The first terminal of transistor 102 is connected to wiring 116A, the first terminal of transistor 103 is connected to wiring 116B, terminal 104 c of circuit 104 is connected to wiring 116C, and terminal 105d of circuit 105 is connected to wiring 116D. However, it is not limited thereto, and wiring 111, wiring 113, wiring 114, and / or wiring 115 can be divided into a plurality of wirings. Or only one of wiring 112 and wiring 116 can be divided into a plurality of wirings.

[0103] Note that in FIG. 5(A), wirings 112A to 1l2B correspond to wiring 112 in FIG. 1(A). Therefore, signal IN1 can be input to wirings 112A to 112B, and wirings 112A to 112B can function as signal lines or clock signal lines. However, it is not limited thereto, and any voltage such as voltage V1 or voltage V2 can be supplied to wirings 112A to 112B, and wirings 112A to 112B can function as power supply lines. It is possible to do so. Alternatively, separate signals or separate electrical signals can be connected to wiring 112A~112B. It is possible to input voltage. Alternatively, wiring 112A~112B can also handle various other signals. It is possible to input various voltages or various currents.

[0104] Note that in Figure 5(A), wiring 116A to 116D corresponds to wiring 116 in Figure 1(A). Therefore, it is possible to supply voltage V1 to wiring 116A~116D, Lines 116A to 116D can function as power lines. However, this is not limited to them. Wiring 116A~116D is not connected to signal OUT, or signal IN1~signal IN4, etc. Signals can be input, and wiring 116A~116D functions as signal lines. This is possible. Alternatively, separate voltages or separate signals can be applied to wiring 116A~116D. It is possible to input this. Alternatively, various other signals can be input to wiring 116A~116D. It is possible to input various voltages or various currents.

[0105] In Figure 5(A), wiring 116A and wiring 116B are connected during period T4. It is possible to input a signal that will be at L level. For example, wiring 116A and wiring 11 It is possible to input signal IN2 to 6B. In this case, as shown in Figure 5(B), The first terminal of transistor 102 and the first terminal of transistor 103 are connected to wiring 113 It is possible to connect them. In this way, transistor 102 and transistor 10 Since a reverse bias can be applied to 3, transistor 102 and transistor 1 The characteristic degradation of 03 can be mitigated. However, it is not limited to this, and the wiring 116A and Signal IN2 is input to one of the wires 116A and 116B, and only one of the wires 116A and 116B It can be connected to wiring 113, or wiring 116A, and / or wiring 1 Signal OUT, Signal IN3, Signal IN4, or other signals can be input to 16B. It is possible. In this case, the first terminal of transistor 103, and / or transistor 10 The first terminal of 2 can be connected to wiring 111, wiring 114, or wiring 115. Alternatively, connect signal OUT, signal IN2, signal to wiring 116C and / or wiring 116D. It is possible to input signal IN3, signal IN4, or other signals. In this case, the circuit Terminal 104c of circuit 104, and / or terminal 105d of circuit 105, are connected to wiring 111 and wiring 1 13. It can be connected to wiring 114 or wiring 115.

[0106] Furthermore, as shown in Figure 6(A), between the gate and the second terminal of transistor 101, It is possible to connect a new element 121. By doing so, during period T2 During the bootstrap operation, the potential of node A can be increased. As the Vgs of the radiator 101 increases, the falling or rising time of the signal OUT will increase. The buffering time can be shortened. However, this is not limited to this, and the capacitive element 121 can be used as follows: It is possible to use a transistor as a MOS capacitor. In this case, as a MOS capacitor In order to increase the capacitance value of the transistor used, the gate of the transistor is set to node A. The transistor is connected to the first or second terminal, and the first or second terminal of the transistor is connected to the wiring 111. It is preferable.

[0107] Furthermore, similar to Figure 6(A), in Figures 5(A) and 5(B), the gate of transistor 101 It is possible to newly connect a capacitive element 121 between terminal T and the second terminal. Alternatively, The first and second terminals are connected to wiring 111, and the gate is connected to node A. It is possible to add new verifiers.

[0108] As shown in Figure 6(B), the first terminal is connected to wiring 111, and the second terminal is connected to A new transistor 122 is added, which is connected to A and whose gate is connected to wiring 112. This is possible. The polarity of transistor 122 is the same as that of transistors 101-103. It is preferable that it be of a certain type, and often of the N-channel type. However, it is not limited to this. The polarity of transistor 122 can be P-channel type. Transistor 12 2 controls the timing at which node A and wiring 111 become conductive in response to signal IN2. It has the function of being able to function as a switch. Transistor 122 is It is turned on at interval T4, creating a conductive state between node A and wiring 111.

[0109] Furthermore, similar to Figure 6(B), in Figures 5(A)-(B) and Figure 6(A), the first edge The child is connected to wiring 111, the second terminal is connected to node A, and the gate is connected to wiring 112. It is possible to add a new transistor 122.

[0110] Furthermore, as shown in Figure 6(C), transistor 103 can be omitted. In this case, node A is often in a floating state during period T4. However, this is not limited to this case. Therefore, transistor 102 can be omitted. In this case, during period T4, In many cases, the wiring 111 is in a floating state. Thus, transistor 102 and transistor By omitting one of the transistors (103 or 103), the number of transistors can be reduced. This allows for a reduction in layout area or an improvement in yield.

[0111] Furthermore, similar to Figure 6(C), in Figures 5(A)-(B) and 6(A)-(B), Transistor 102 or transistor 103 can be omitted. In particular, see Figure 6. In (B), it is preferable to omit either transistor 102 or transistor 103. Yes. Because in Figure 6(B), during period T4, node A and wiring 111 are in a conductive state. Therefore, node A or wiring 111 will not be in a floating state.

[0112] Furthermore, as shown in Figure 7(A), transistor 102 is connected to one terminal (hereinafter referred to as the positive terminal). (u) is connected to wiring 111, and the other terminal (hereinafter also called the negative terminal) is connected to node B. It is possible to replace it with diode 102a. Alternatively, transistor 103 can be replaced with One terminal (hereinafter also referred to as the positive terminal) is connected to node A, and the other terminal (hereinafter also referred to as the negative terminal) This can be replaced with diode 103a connected to node B. In this case, circuit 104 reduces the potential of node B to V1 during period T4, The potential of node B is raised to V2 during interval T1, period T2, and period T5. This is possible. However, it is not limited to this, and transistors 102 and 103 It is possible to replace only one of them with a diode. Alternatively, diode 102a, and Alternatively, a diode 103a can be added.

[0113] Furthermore, similar to Figure 7(A), the same applies to Figures 5(A)-(B) and 6(A)-(C). Transistor 102 is connected to wiring 111 at one terminal and to node B at the other terminal. It is possible to replace the following diode 102a. Alternatively, transistor 10 3 is a diode in which one terminal is connected to node A and the other terminal is connected to node B. It can be replaced with diode 103a, or diode 102a, and / or Iode 103a can be added as a new option.

[0114] Although not shown in the diagrams, please refer to Figures 1(A), 5(A)-(B), 6(A)-(C), and Figure In 7(A), transistor 102 or transistor 103 is connected in a diode configuration. This is possible. In this case, the first terminal of transistor 102 is connected to node B, The second terminal of transistor 102 is connected to wire 111, and the gateway of transistor 102 The first terminal of transistor 103 is connected to node B or wiring 111. The second terminal of transistor 103 is connected to node B, and the transistor The gate of TA103 is connected to either node A or node B. However, it is not limited to this. It is possible to connect only one of transistors 102 and 103 to a diode. be.

[0115] As shown in Figure 7(B), terminal 104b of circuit 104 is connected to node A. This is possible. By doing so, during period T2, terminal 104b of circuit 104 This prevents an L-level signal from being input, thus maintaining the potential of node B at V1. This makes it easier. Therefore, the potential of node B rises instantaneously, and transistor 102 and This prevents the Rangista 103 from turning on.

[0116] Furthermore, similar to Figure 7(B), Figures 5(A)-(B), 6(A)-(C), and 7(A) In this case, terminal 104b of circuit 104 can be connected to node A.

[0117] Furthermore, as shown in Figure 7(C), circuit 105 can be omitted.

[0118] Furthermore, similar to Figure 7(C), Figures 5(A)-(B), 6(A)-(C), and 7(A) In (B) as well, circuit 105 can be omitted.

[0119] As shown in Figure 28(B), terminal 104a of circuit 104 is connected to wiring 113. It is possible to do so. However, it is not limited to this, and terminal 104a of circuit 104 can also It can be connected to various wires, terminals, or nodes. (See Figure 28(B) for details.) Similarly, in Figures 5(A)-(B), 6(A)-(C), and 7(A)-(B), Terminal 104a of circuit 104 can be connected to wiring 113.

[0120] As shown in Figure 8(A), transistors 101 to 103 are P-channel type transistors. It is possible to use transistors. Transistor 101p, transistor 102p, and Transistor 103p is connected to transistor 101, transistor 102, and transistor 103p respectively. It corresponds to ST103 and is a P-channel type. And, as shown in Figure 8(B), the transition If the polarity of the sta is P-channel type, voltage V2 is supplied to wiring 116, signal OUT, signal Signal IN1, Signal IN2, Signal IN3, Signal IN4, Potential of Node A, and Potential of Node B It should be noted that this is reversed compared to the timing chart in Figure 1(B).

[0121] In Figure 8(A), the polarity of the transistors in circuits 104 and 105 is It is preferable that it be a P-channel type. However, it is not limited to this, and the circuit 104 and the turn The transistor in path 105 can be of the N-channel type.

[0122] Furthermore, similar to Figures 8(A) and 8(B), Figures 5(A)-(B) and 6(A)-(C) In Figures 7(A) to (C), transistors 101 to 103 are P-channel. It is possible to use type transistors.

[0123] (Embodiment 2) In this embodiment, a specific example of the circuit 104 described in Embodiment 1 will be explained. Circuit 104 can be described as a semiconductor device, a drive circuit, or a gate driver. The details described in Embodiment 1 will be omitted from this explanation. This can be freely combined with the contents described in this embodiment.

[0124] First, an example of circuit 104 will be explained with reference to Figure 9(A). Circuit 104 is transistor 201 (also called the fourth transistor), transistor 202 (also known as the fifth transistor), transistor 203 (also known as the sixth transistor) It has (also called), and transistor 204 (also called the seventh transistor). However, It is not limited to these, and any of these transistors can be omitted. , any of these transistors can be used as a capacitive element, a resistive element, or a diode, etc. It can be replaced with various elements, or circuits that combine any of these elements. It is possible. Or, various transistors, capacitive elements, resistive elements, or diodes. Adding a new element, or a circuit combining any of these elements It is possible.

[0125] For example, transistors 201-204 are assumed to be N-channel type. Furthermore, if the transistors 101 to 103 described in Embodiment 1 are of the N-channel type, It is preferable that the transistors 201-204 are of the N-channel type. In this way, all transistors The transistor can be an N-channel type. However, it is not limited to this, Numbers 201-204 can be P-channel type.

[0126] Next, an example of the connection relationship of circuit 104 will be described. The first terminal of transistor 201 It is connected to wiring 112, and the second terminal of transistor 201 is connected to node B. The first terminal of transistor 202 is connected to wiring 116, and the second terminal of transistor 202 Terminal 2 is connected to node B, and the gate of transistor 202 is connected to wiring 111. The first terminal of transistor 203 is connected to wiring 112, and transistor 203 The second terminal is connected to the gate of transistor 201 and the gate of transistor 203. It is connected to wiring 112. The first terminal of transistor 204 is connected to wiring 116. The second terminal of transistor 204 is connected to the gate of transistor 201, The gate of inverter 204 is connected to wiring 111. However, it is not limited to this, and other connections may be made. It is also possible to create various connection configurations.

[0127] Note that the gate of transistor 201, the second terminal of transistor 203, or the transistor The connection point of the second terminal of sta204 is indicated as node C. Note that node C is connected to the wiring or terminal. It is possible to demonstrate this.

[0128] Furthermore, wiring 111, wiring 112, or wiring 116 may have various connections as described in Embodiment 1. It is possible to input various signals, various voltages, or various currents. Here is one example: The signal OUT described in Embodiment 1 is input to wiring 111. As an example, the signal IN1 described in Embodiment 1 is input to 112. As an example, the voltage V1 described in Embodiment 1 is supplied to line 116. And it's not limited to this.

[0129] Next, we will explain an example of the functions of transistors 201-204. 201 controls the timing of supplying signal IN2 to node B, depending on the potential of node C. It has the function of being able to function as a bootstrap transistor or a switch. It is possible. Transistor 202 reacts to the potential (signal OUT) of wiring 111. By controlling the conduction state between 6 and node B, voltage V1 is supplied to node B. It has the function of controlling the ming and can function as a switch. (Transistor) 203 has the function of raising the potential of node C and then putting node C into a floating state, It can function as an iod. Transistor 204 is at the potential of wiring 111 ( In response to the signal (OUT), the electrical current is controlled by the continuity state between wiring 116 and node C. It has the function of controlling the timing of supplying pressure V1 to node C and functions as a switch. This is possible. However, it is not limited to this; transistors 201-204 can also do the following: It is possible to have various functions. Or, these elements or circuits have the functions described above. It is possible not to have it.

[0130] Next, regarding the operation of circuit 104, see Figures 1(B), 9(B), 9(C), and 9(D). This will be explained with reference to Figures 9(E) and 9(F). Figure 9(B) shows the circuit during period T1. This is an example of a schematic diagram of the operation of circuit 104. Figure 9(C) shows the operation of circuit 104 during period T2. This is an example of a schematic diagram. Figure 9(D) is a schematic diagram of the operation of circuit 104 during period T3. This is an example. Figure 9(E) is an example of a schematic diagram of the operation of circuit 104 during period T4. Figure 9(F) is an example of a schematic diagram of the operation of circuit 104 during period T5.

[0131] First, for convenience, we will explain the operation in period T2. During period T2, signal IN2 is H The signal level becomes high, and the signal OUT becomes high. Because the signal OUT becomes high, the transistor The zista 202 and transistor 204 turn on. Then, the wiring 116 and node B A conductive state is established, and wiring 116 and node C become conductive. Therefore, voltage V1 is connected to wiring 1 Since it is supplied from 16 to node B via transistor 202, the potential at node B is V1 It decreases to... Then, voltage V1 is sent from wiring 116 through transistor 204 to node C As it is supplied, the potential of node C decreases. At this time, the potential of node C is the transient This is determined by the operating point of transistor 203 and transistor 204. Here, as an example, The potential of C is the sum of the voltage V1 and the threshold voltage of transistor 201 (Vth201) (V1 It is assumed that the value will be lower than +Vth201). Therefore, transistor 201 is turned off. Therefore, wiring 112 and node B become non-conductive.

[0132] Next, during period T3, signal IN1 becomes low, and signal OUT becomes low. Since OUT becomes low, transistors 202 and 203 turn off. Therefore, wiring 116 and node B become non-conductive, and wiring 116 and node C become non-conductive. The circuit enters a continuous state. Then, since signal IN1 becomes low, transistor 203 turns off. Therefore, node C becomes a floating state and maintains its potential during period T2. Therefore, transistor 201 remains off.

[0133] Next, during period T4, signal IN1 becomes high level, while signal OUT remains low level. Since the signal OUT remains at a low level, transistors 202 and 203 It remains off. Therefore, wiring 116 and node B remain in a non-conductive state, and wiring 1 Node 16 and node C remain in a non-conductive state. At this time, signal IN1 becomes high. As a result, transistor 203 turns on, and wiring 112 and node C become conductive. Therefore, the H-level signal IN1 is transmitted from wiring 112 through transistor 203 to node C. As it is supplied, the potential of node C begins to rise. Subsequently, the potential of node C reaches V1+V When it becomes th201, transistor 201 turns on. Then, wiring 112 and no The circuit B becomes conductive. Therefore, the H-level signal IN1 is transmitted from wiring 112 through the transistor. Since it is supplied to node B via TA201, the potential of node B begins to rise. Subsequently, The potential of node C is the threshold voltage of transistor 203, which is the potential (V2) of the high-level signal IN1. When the value obtained by subtracting the voltage (Vth203) becomes (V2-Vth203), the transistor... 203 turns off. Therefore, wiring 112 and node C become non-conductive. Then, no Since node C is in a floating state, the potential of node C is the same as the gate and second terminal of transistor 201. The capacity of parasitic capacity between offspring, i.e., the bootstrap action, continues to increase further. And if the potential of node C becomes higher than V2 + Vth201, then The potential of point B rises to V2.

[0134] Next, during period T5 or period T1, signal IN1 becomes L level and signal OUT becomes L level. The signal OUT remains at a low level, so transistor 202 and the transistor remain at a low level. Zistor 203 remains off. Therefore, wiring 116 and node B remain non-conductive. As a result, wiring 116 and node C remain in a non-conductive state. And signal IN1 is L It becomes a bell. Then, transistor 203 turns off, so wiring 112 and node C are not connected. The conductive state remains. Therefore, node C is in a floating state, and V2+Vth201 It maintains a higher potential than [the specified value]. As a result, transistor 201 remains on, so [the circuit] The wire 112 and node B remain in a conductive state. Therefore, the L-level signal IN1 is connected to wire 1 Since it is supplied from 12 to node B via transistor 201, the potential at node B is V1 It decreases to this. At this time, node C is in a floating state, so the gate and the first The potential often decreases due to capacitive coupling of parasitic capacitance between terminal 2 and the other terminal. The potential of line C decreases during period T4 by the amount that it increased due to the bootstrap action. This is often the case.

[0135] The circuit 104 in Figure 9(A) has been explained above. The circuit 104 in Figure 9(A) is a bootleg By using the trapping action, the potential of node B can be raised to V2. Therefore, the V of transistors 102 and 103 described in Embodiment 1 The gs can be increased. As a result, transistors 102 and 10 Since the channel width of channel 3 can be reduced, the layout area can be reduced. Alternatively, even if the threshold voltages of transistors 102 and 103 rise, The transistor can be made easier to turn on. Alternatively, transistor 102, and Since the on-resistance of Zistor 103 decreases, the potential of node A and the potential of wiring 111 are set to V1 This makes it easier to maintain.

[0136] Alternatively, in circuit 104 of Figure 9(A), the polarity of all transistors can be set to N-channel or P It is possible to use a channel type. Therefore, the number of processes can be reduced, the yield can be improved, and reliability can be increased. This can improve performance or reduce costs. In particular, if all transistors are N-channel In the case of the L-type transistor, the semiconductor layer can be made of non-single-crystal semiconductors, microcrystalline semiconductors, or organic semiconductors. It becomes possible to use materials or oxide semiconductors. Therefore, the number of processes and yield can be reduced. This can lead to improvements in performance, increased reliability, or reduced costs. However, it is not limited to these. First, circuit 104 in Figure 9(A) uses a P-channel transistor and an N-channel transistor. It is possible to have a CMOS circuit composed of transistors. Alternatively, a transistor As the semiconductor layer, it is possible to use a single-crystal semiconductor or a polycrystalline semiconductor.

[0137] Alternatively, in circuit 104 of Figure 9(A), at least one of period T4 and period T5 And transistors 202-204 turn off. Therefore, the transistors operate for one period. Because it does not remain in an on state continuously, transients such as an increase in threshold voltage or a decrease in mobility occur. The degradation of the characteristics of the node can be suppressed. Alternatively, in period T4 and period T5, C repeatedly experiences an increase in potential and a decrease in potential. Therefore, when a pulse is input to transistor 201... This will result in a decrease in transistor characteristics, such as an increase in threshold voltage or a decrease in mobility. This can suppress deformation. In particular, non-single-crystal semiconductors and microcrystalline semiconductors can be used as semiconductor layers in transistors. When crystalline semiconductors, organic semiconductors, or oxide semiconductors are used, the characteristics of the transistor Degradation is often quite noticeable. However, in the semiconductor device shown in Figure 9(A), the transistor Because it can suppress performance degradation, non-single-crystal semiconductors are used as the semiconductor layer of transistors. This makes it easier to use microcrystalline semiconductors, organic semiconductors, or oxide semiconductors. However, However, the semiconductor layer may be a polycrystalline semiconductor or a single-crystal semiconductor. This is possible.

[0138] For example, the channel width of transistor 203 is equal to the channel width of transistor 204. It is preferable that it be smaller than the width. This is because, during period T2, transistor 203 and This is to lower the potential of node C when transistor 204 is turned on. For example, the channel length of transistor 203 is the same as the channel length of transistor 204. It is preferable that the length be shorter than the channel length. However, it is not limited to this, and the transistor 203 The channel width can be greater than the channel width of transistor 204. The channel length of transistor 203 is smaller than the channel length of transistor 204. This is possible.

[0139] For example, the channel width of transistor 204 is equal to the channel width of transistor 202. It is preferable that it be smaller than the width. This is because the load on node B is larger than the load on node C. This is because it is often the case. For the same reason, the channel width of transistor 203 is It is preferable that it be smaller than the channel width of ZISTA 201. However, it is not limited to this, The channel width of transistor 204 is greater than the channel width of transistor 202. It is possible. Alternatively, the channel width of transistor 203 is the channel width of transistor 201. It is possible to have a width greater than the r width.

[0140] For example, the channel width of transistor 201 and the channel width of transistor 202 It is preferable that they be roughly equal. This is because transistor 201 and transistor 2 The reason for the 02 designation is that both transistors control the potential of node C and have the same polarity. However, this is not limited to the channel width of transistor 201, which is the channel width of transistor 202. It is possible for the channel width to be larger or smaller than the channel width.

[0141] For example, transistor 201, transistor 202, transistor 203, and The channel width of transistor 204 is the same as that of transistor 101 described in Embodiment 1. It is preferable that it be smaller than the channel width of transistor 102 or transistor 103. Furthermore, and not limited to this, the channel width of any one of transistors 201 to 204 is shown in Figure The channel of transistor 101, transistor 102, or transistor 103 of 1(A) It is possible to have a width greater than the r width.

[0142] As an example, similar to transistor 101 described in Embodiment 1, transistor 2 In 01, the parasitic capacitance between the gate and the second terminal is the parasitic capacitance between the gate and the first terminal. It is preferable that it be greater than the raw capacity. This is because, during period T4, the potential of node C is This is because the height tends to increase due to the action of the t-strap. Therefore, as a gate The area where the functional conductive layer and the conductive layer that functions as a source or drain overlap is the second It is preferable that the terminal side is larger than the first terminal side. However, this is not limited to this. stomach.

[0143] Furthermore, it is possible to input a signal with a potential lower than V1 at the L level to terminal 104b. Yes. Thus, a reverse bias is applied to transistors 202 and 204. This allows for the mitigation of characteristic degradation of transistors 202 and 204. This is possible. Alternatively, a signal with a potential lower than V2 at the H level is input to terminal 104b. This is possible. In this way, transistors 202 and 204 turn on. Since Vgs can be made smaller in this case, transistor 202 and transistor The characteristic degradation of 204 can be suppressed. In such cases, the wiring 111 has an L level A signal with a potential lower than V1, a signal with a potential lower than V2 at the H level, or a signal at the L level It is possible to input a signal whose position is lower than V1 and whose high-level potential is lower than V2. Yes, however, it is not limited to this, and terminal 104b may be connected to a different wiring than wiring 111. In this wiring, signals with a low level potential lower than V1 and signals with a high level potential lower than V2 are present. A signal where the L level potential is lower than V1 and the H level potential is lower than V2. It is possible to input this.

[0144] Furthermore, similar to Embodiment 1, it is possible to divide the wiring into multiple wires. The same signal or voltage can be input to these multiple wires, or different signals or It is possible to input voltage. Alternatively, the multiple wires may be the same wire or the same element. They can be connected, and these multiple wires can be connected to separate wires or separate elements. It is possible to do this. In one example in Figure 10(A), wiring 111 is connected to wiring 111A~111B This is divided into multiple wires, and wire 112 is divided into multiple wires 112C~112D When divided, the wiring 116 is divided into multiple wirings 116E to 116F. This shows that the transistor 204's gate is connected to wiring 111A, and the transistor The gate of transistor 202 is connected to wiring 111B. The first terminal of transistor 201 is connected to wiring The first terminal and gate of transistor 203 are connected to wire 112C and wire 112D. The first terminal of transistor 202 is connected to wiring 116E, and the transistor The first terminal of terminal 204 is connected to wiring 116F. However, it is not limited to this, wiring Only one or two of wiring 111, wiring 112, and wiring 116 are divided into multiple wires. It is possible to do so. Alternatively, the gate and the first terminal of transistor 203 are separate It is possible to input a signal or separate voltages. In this case, the gate of transistor 203 The terminal and the first terminal can be connected to separate wiring.

[0145] In Figure 10(A), wiring 111A to 111B are relative to wiring 111 in Figure 9(A). Correspond. Therefore, similar to wiring 111, input signal OUT to wirings 111A~111B. It is possible for wiring 111A to 111B to function as signal lines. Yes. However, it is not limited to this, and wiring 111A to 111B may have voltage V1 or voltage V2 It is possible to supply voltages such as those listed above, and wiring 111A~111B functions as a power line. It is possible to do so. Alternatively, separate signals or separate electrical signals can be connected to wiring 111A~111B. It is possible to input voltage. Alternatively, wiring 111A~111B can also handle various other signals. It is possible to input various voltages or various currents.

[0146] In Figure 10(A), wiring 112C to 112D corresponds to wiring 112 in Figure 9(A). Correspond. Therefore, similar to wiring 112, input signal IN1 to wirings 112C~112D. It is possible to do so, and wiring 112C~112D can function as a signal line. Yes. However, it is not limited to this, and wiring 112C~112D may have voltage V1 or voltage V2 It is possible to supply voltages such as those listed above, and wiring 112C~112D functions as a power line. It is possible to do so. Alternatively, separate signals or separate electrical signals can be connected to wiring 112C~112D. It is possible to input voltage. Alternatively, wiring 112C~112D can also be used for various other signals. It is possible to input various voltages or various currents.

[0147] In Figure 10(A), wiring 116E to 116F corresponds to wiring 116 in Figure 9(A). Corresponds. Therefore, similar to wiring 116, voltage V1 is supplied to wirings 116E to 116F. It is possible for this to happen, and wiring 116E~116F can function as a power line. However, this is not limited to the above; wiring 116E to 116F may have a signal OUT or a signal I By inputting signals such as N1~IN4, wiring 116E~116F becomes a signal line and It is possible for it to function in this way. Alternatively, the wiring 116E~116F has separate voltages, It is possible to supply separate signals. Alternatively, wiring 116E~116F can also It is possible to input various signals, voltages, or currents.

[0148] In Figure 10(A), wiring 116E and wiring 116F are connected during period T2. It is possible to input a signal that will be at an L level. For example, wiring 116E and wiring 1 Signal IN2 can be input to 16F. In this case, wiring 116E and wiring Line 116F can be connected to wiring 113 as described in Embodiment 1. By doing so, a reverse bias is applied to transistors 202 and 204. Therefore, the degradation of the characteristics of transistors 202 and 204 can be mitigated. Yes, it is possible. However, it is not limited to this; the signal can be transmitted to only one of the wires, either wire 116E or wire 116F. It is possible to input IN2. In this case, only one of wires 116E or 116F can be used. It is possible to connect it to wiring 113. Or, wiring 116E, and / or wiring It is possible to input signal IN3 or signal IN4 to 116F. In this case, wiring Wiring 116E and / or wiring 116F is the same as wiring 114 or wiring 11 described in Embodiment 1. It is possible to connect to 5.

[0149] In Figure 10(A), it is possible to input signal IN2 to wiring 112D. In this case, the gate and first terminal of transistor 203 are connected to wiring 113. This is possible. By doing so, during period T3, the potential of node C is at level H. The threshold voltage (Vth203) of transistor 203 is subtracted from the potential (V2) of the signal IN2. The value becomes (V2-Vth203). Subsequently, during period T4, signal IN1 reaches the H level. Therefore, the potential of node C will be V2-Vth203 due to the bootstrap operation. It rises further from there. Therefore, the potential of node C becomes higher, and the V of transistor 201 gs can be increased. As a result, the output signal of circuit 104 (potential at node B) The fall time and rise time can be shortened. Alternatively, the output of circuit 104 The delay of the power signal can be reduced. However, this is not limited to the above; wiring 112D includes, It is possible to supply voltage V2.

[0150] Furthermore, as shown in Figure 10(B), between the gate and the second terminal of transistor 201, It is possible to connect a new capacitive element 221. By doing so, Figure 6(A) Similarly, the potential of node C can be increased. However, this is not limited to Figure 6. Similar to A), the first and second terminals of the capacitive element 221 are connected to node B. A transistor whose gate is connected to node C can be used as a MOS capacitor. ru.

[0151] Furthermore, similar to Figure 10(B), in Figure 10(A) as well, the gate of transistor 201 and It is possible to newly connect a capacitive element 221 between the second terminal and the first terminal. The terminals of the first and second terminals are connected to node B, and the gate of the transistor is connected to node C. It is possible to connect a new device.

[0152] Furthermore, as shown in Figure 10(C), transistor 204 can be omitted. Alternatively, as shown in Figure 10(D), transistor 202 can be omitted. By doing so, the number of transistors can be reduced. Therefore, the layout area This can lead to a reduction in production or an improvement in yield. However, it is not limited to this, It is possible to omit both transistor 202 and transistor 204.

[0153] Furthermore, similar to Figure 10(C) or Figure 10(D), in Figures 10(A) and (B), Transistor 202 and / or transistor 204 can be omitted.

[0154] As shown in Figure 10(E), transistor 202 is connected to one terminal (hereinafter referred to as the positive terminal). One terminal (hereinafter also referred to as the negative terminal) is connected to node B, and the other terminal (hereinafter also referred to as the negative terminal) is connected to wiring 111. It is possible to replace it with diode 202a. Alternatively, transistor 203 One terminal (hereinafter also called the positive terminal) is connected to node C, and the other terminal (hereinafter also called the negative terminal) is connected to node C. It is possible to replace (also known as) with diode 203a connected to wiring 111. In this case, terminal 104b of circuit 104 receives either the inverted signal of signal OUT or the potential of node A. An inverted signal can be input. To achieve this, wiring 111, and Node A inverts the input signal using an inverter circuit, NAND gate, or NOR gate. It can be connected to terminal 104b of circuit 104 via a circuit that has the function of outputting. It is possible. However, it is not limited to this, and one of transistors 202 and 204 It is possible to replace one of them with a diode. Alternatively, diode 202a, and / or It is possible to add diode 203a.

[0155] Furthermore, similar to Figure 10(E), in Figures 10(A) to (D), transistor 202 is also used. Diode 2, one terminal of which is connected to node B and the other terminal of which is connected to wiring 111. It can be replaced with 02a. Alternatively, transistor 203 can be replaced with one terminal of 02a. Diode 203a, which is connected to diode C and whose other terminal is connected to wiring 111, is replaced. It is possible to do so. Alternatively, diode 202a and / or diode 203a It is possible to add new entries.

[0156] Although not shown in the diagram, in Figures 10(A) to (E), the first terminal of transistor 202 The child is connected to wiring 111, and the second terminal of transistor 202 is connected to node B, The gate of transistor 202 is connected to wiring 111 or node B, thereby transforming It is possible to connect transistor 202 in diode mode. Alternatively, transistor 204 The first terminal is connected to wiring 111, and the second terminal of transistor 204 is connected to node C. The gate of transistor 204 is connected to wiring 111 or node C. It is possible to connect transistor 204 in diode mode. However, this is not the only option. However, only one of transistors 202 and 204 is connected in a diode configuration. This is possible.

[0157] As shown in Figure 10(F), transistors 201 to 204 are P-channel type transistors. Transistors can be used. In particular, transistors 101-103 in Figure 1(A) When a P-channel transistor is used, transistors 201-204 It is preferable to use a P-channel transistor. Transistor 201p, Transistor 202p, transistor 203p, and transistor 204p are, respectively, Compatible with transistors 201, 202, 203, and 204. It is a P-channel type.

[0158] Furthermore, similar to Figure 10(F), in Figures 10(A) to (E), transistor 201~ A P-channel transistor can be used as component 204.

[0159] Furthermore, as already mentioned, the circuit 104 of the circuit 100 described in Embodiment 1 is The configuration of circuit 104 described in the embodiment can be used. Figure 11 shows an example. Therefore, an example of the circuit 104 in Figure 9(A) is used in the circuit 104 of the circuit 100 in Figure 7(C). The configuration in the case where it is present is shown. However, it is not limited to this, see Figure 9(A), Figure 10(A), Figure 10 (B), Figure 10(C), Figure 10(D), Figure 10(E), Figure 10(F), or a combination thereof The combined circuit 104 is shown in Figures 1(A), 5(A), 5(B), 6(A), and 6 (B), Figure 6(C), Figure 7(A), Figure 7(B), Figure 8(A), or a combination thereof. It can be used in the circuit 104 of the circuit 100 in this case.

[0160] (Embodiment 3) In this embodiment, a specific example of circuit 105 will be described. Note that circuit 105 is a semiconductor device. It can be referred to as a drive circuit or gate driver. Note that Embodiment 1 and The details described in Embodiment 2 will be omitted. The contents described in State 2 can be freely combined with the contents described in this embodiment.

[0161] First, an example of circuit 105 will be explained with reference to Figure 12(A). Figure 9(A) Example So, circuit 105 is transistor 301 (also called the 8th transistor), transistor Transistor 302 (also known as the 9th transistor), Transistor 303 (the 10th transistor) (also known as), transistor 304 (also known as the 11th transistor), and transistor It has a 305 (also called the 12th transistor). However, it is not limited to these, It is possible to omit any of these transistors. Any of these can be a capacitive element, a resistive element, or a diode or other various elements, or these It is possible to replace it with a circuit that combines any of our elements. Or, Various elements such as diodes, capacitive elements, resistive elements, or diodes, or these It is possible to add a new circuit by combining any of these elements.

[0162] For example, transistors 301-305 are assumed to be N-channel type. In addition, transistors 101 to 103 described in Embodiment 1, and transistors described in Embodiment 2 If transistors 201-204 are N-channel type, then transistors 301-305 are It is preferable that it be an N-channel type. In this way, all transistors have the same polarity. It is possible. However, it is not limited to this, and transistors 301 to 305 are P-channel. It is possible for it to be a type.

[0163] Next, an example of the connection relationship of circuit 105 in Figure 12(A) will be explained. Transistor 30 The first terminal of 1 is connected to wiring 114, and the second terminal of transistor 301 is connected to node The gate of transistor 301 is connected to wire 114, and is connected to A. The first terminal of 302 is connected to wiring 114, and the second terminal of transistor 302 is connected to The gate of transistor 302 is connected to wire A and wire 113. The first terminal of transistor 303 is connected to wiring 116, and the second terminal of transistor 303 is The gate of transistor 303 is connected to wire 115, and is connected to node A. The first terminal of transistor 304 is connected to wiring 116, and the second terminal of transistor 304 is connected to wiring 116. The child is connected to wire 111, and the gate of transistor 304 is connected to wire 115. The first terminal of transistor 305 is connected to wiring 116, and the second terminal of transistor 305 Terminal 2 is connected to wire 111, and the gate of transistor 305 is connected to wire 113. This is the case. However, it is not limited to this, and various other connection configurations are also possible.

[0164] Furthermore, wiring 113, wiring 114, wiring 115, or wiring 116 are connected as described in Embodiment 1. As such, it is possible to input various signals, various voltages, or various currents. For example, the signal IN2 described in Embodiment 1 is input to wiring 113. As an example, the signal IN3 described in Embodiment 1 is input to wiring 114. As an example, the signal IN4 shown in Figure 1(B) or Figure 3(A) is connected to wiring 115. It shall be assumed that the input is provided. For example, voltage V1 shall be supplied to wiring 116. However, this is not the only example.

[0165] Next, we will explain an example of the functions of transistors 301 to 305. 301 is the timing to supply a high-level signal IN2 to node A in response to signal IN3. It can control and function as a diode. Alternatively, transistor 301 is By controlling the conductivity between the wiring 114 and node A according to the potential of node A, Transistor 3 has the function of controlling the timing of supplying signal IN3 to node A. 02 controls the conductivity state between wiring 114 and node A in accordance with signal IN2. It has the function of controlling the timing of supplying signal IN3 to node A, and as a switch It is possible for it to function. Transistor 303, in response to signal IN4, is connected to wiring 116 and It has the function of supplying voltage V1 to node A by controlling the conduction state with node A. It can function as a switch. Transistor 304 responds to signal IN4 Then, by controlling the conductivity state between wiring 116 and wiring 111, the voltage V1 is controlled by wiring 1 It has the function of supplying power to 11 and can function as a switch. Transistor 3 05 controls the continuity state between wiring 116 and wiring 111 in response to signal IN2. It has the function of supplying voltage V1 to wiring 111 and can function as a switch. Yes, but it is not limited to this; transistors 301-305 also have various other functions. It is possible to have them. Or, these elements or circuits do not have the functions described above. It is possible.

[0166] Next, regarding the operation of circuit 105, see Figure 1(B), Figure 12(B), Figure 12(C), Figure 13( A) This will be explained with reference to Figures 13(B) and 13(C). Figure 12(B) shows the period T1 This is an example of a schematic diagram of the operation of circuit 105 in the following case. Figure 12(C) shows the number of cycles in period T2. This is an example of a schematic diagram of the operation of circuit 105. Figure 13(A) shows the operation of circuit 105 during period T3. This is an example of a schematic diagram of operation. Figure 13(B) shows a schematic diagram of the operation of circuit 105 during period T4. This is an example of a diagram. Figure 13(C) is an example of a schematic diagram of the operation of circuit 105 during period T5. be.

[0167] First, during period T1, signal IN2 becomes high level, signal IN3 becomes high level, and signal IN4 becomes low. Signal IN3 becomes high, so transistor 301 turns on. At the same time, the signal IN2 becomes high level, so transistor 302 and the transistor Node 305 turns on. Then, wiring 114 and node A become conductive, so the signal goes in. 3 supplies power to node A via transistors 301 and 302 from wiring 114. It is supplied. Therefore, the potential of node A begins to rise. Similarly, wiring 116 and wiring 111 and Since it becomes conductive, voltage V1 is transmitted from wiring 116 through transistor 305 to wiring 11 It is supplied to 1. Therefore, the potential of wiring 111 becomes V1. At this time, signal IN4 is L Since it's a bell, transistors 303 and 304 are turned off. Therefore, the wiring... Node 116 and node A become non-conductive, and wiring 116 and wiring 111 become non-conductive. Subsequently, the potential of node A is lowered from the potential of wiring 114 (V2) to the threshold voltage of transistor 301. When the value obtained by subtracting the voltage (Vth301) (V2-Vth301) becomes the transistor, 301 turns off. Similarly, the potential of node A transitions from the potential of wiring 113 (V2). The value obtained by subtracting the threshold voltage of ST302 (Vth302) (V2-Vth302) is obtained. Therefore, transistor 302 turns off. Consequently, wiring 114 and node A are not conductive. This is the result. Here, as an example, when the potential of node A becomes V2-Vth301... , transistors 301 and 302 are turned off. Therefore, node A remains in a floating state while maintaining its potential at V2-Vth301.

[0168] Next, during period T2, signal IN3 becomes low, signal IN4 becomes low, and signal IN5 remains at a low level. Signal IN3 becomes low, so transistor 301 It remains off. At the same time, signal IN2 becomes low, so transistor 302 It remains off, and transistor 303 turns off. Therefore, wiring 114 and node A are The circuit remains in a non-conductive state, and wiring 116 and wiring 111 are in a non-conductive state. At this time, Since IN4 remains at the low level, transistors 303 and 304 are turned off. This remains the case. Therefore, wiring 116 and node A remain in a non-conductive state, and wiring 116 The wiring 111 remains in a non-conductive state.

[0169] Next, during period T3, signal IN2 becomes high level, while signal IN3 remains low level. Signal IN4 becomes high level. Signal IN3 remains low level, so transistor 30 1 remains off. And since signal IN2 becomes high level, transistor 302 , and transistor 304 turns on. Then, wiring 114 and node A become conductive. Therefore, the L-level signal IN3 is transmitted from wiring 114 through transistor 302 to node A It is supplied to the same. Similarly, since wiring 116 and wiring 111 become conductive, voltage V1 is supplied The signal IN is supplied from line 116 to wiring 111 via transistor 305. Since 4 becomes high, transistors 303 and 304 turn on. As a result, wiring 116 and node A become conductive, and voltage V1 is transmitted from wiring 116. It is supplied to node A via inverter 303. Similarly, wiring 116 and wiring 111 are Since the state is open, voltage V1 is transmitted from wiring 116 through transistor 304 to wiring 111. It is supplied. Therefore, the potential of node A decreases to V1, and the power of wiring 111 The rank decreases to V1.

[0170] Next, during period T4, signal IN2 becomes low, and signal IN3 remains low. Signal IN4 becomes L level. Since signal IN3 remains L level, transistor 30 1 remains off. And since signal IN2 becomes low level, transistor 302 , and transistor 305 turns off. Therefore, wiring 114 and node A are non-conductive. As a result, wiring 116 and wiring 111 become non-conductive. At the same time, signal IN4 is at the low level. Therefore, transistors 303 and 304 turn off. Thus, the wiring... Node 116 and node A become non-conductive, and wiring 116 and wiring 111 become non-conductive. Thus, during period T4, the circuit 105 sends a signal or electricity to node A or wiring 111. Often, pressure or other similar supplies are not provided.

[0171] Next, during period T5, signal IN2 becomes high level, while signal IN3 remains low level. The signal IN4 remains at a low level. Because the signal IN4 remains at a low level, the transistor Transistor 303 and transistor 304 are turned off. Therefore, wiring 116 and node A are not connected. The circuit becomes conductive, and wiring 116 and wiring 111 become non-conductive. Similarly, signal IN3 Since it remains at an L level, transistor 301 remains off. At this time, signal IN2 Since the voltage becomes high, transistors 302 and 305 turn on. As a result, wiring 114 and node A become conductive, and the L-level signal IN3 is connected to wiring 11 It is supplied from 4 to node A via transistor 302. Therefore, the potential of node A is It is maintained at V1. Similarly, since wiring 116 and wiring 111 become conductive, the voltage V1 This is supplied from wiring 116 to wiring 111 via transistor 305. Therefore, wiring 1 The potential at 11 is maintained at V1.

[0172] The circuit 105 in Figure 12(A) has been explained above. The polarity of each transistor can be set to either N-channel or P-channel. Therefore, it is possible to reduce the number of processes, improve yield, enhance reliability, or reduce costs. Yes, it is possible. In particular, if all transistors are N-channel type, the semiconductor layer of the transistor is Therefore, non-single-crystal semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors can be used. This becomes possible. Therefore, it is possible to reduce the number of processes, improve yield, increase reliability, or reduce costs. This can be achieved. However, it is not limited to this, and the circuit 105 in Figure 12(A) is P-cha CMOS circuit composed of Nell-type transistors and N-channel transistors It is possible to have a single-crystal semiconductor as the semiconductor layer of the transistor, Polycrystalline semiconductors can be used.

[0173] Alternatively, in circuit 105 of Figure 12(A), at least one of period T4 and period T5 In this state, transistors 301-305 are turned off. Therefore, the transistors are in their first operating phase. Since it does not remain in an on state throughout the entire period, transitions such as an increase in threshold voltage or a decrease in mobility occur. This can suppress the degradation of the transistor's characteristics. In particular, as a semiconductor layer of the transistor, non-single-coupled When crystalline semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors are used, The degradation of the characteristics of the zista is often quite noticeable. However, in circuit 105 of Figure 12(A), Because it can suppress the degradation of transistor characteristics, as a semiconductor layer of a transistor, Non-single-crystal semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors can be easily used. This is the case. However, it is not limited to this, and the semiconductor layer may be a polycrystalline semiconductor or a single-crystal semiconductor. It is possible to use one's body.

[0174] For example, the channel width of transistor 305 is equal to the channel width of transistor 302. It is preferable that it be greater than the width. Alternatively, the channel width of transistor 304 is, for example, Therefore, it is preferable that it be larger than the channel width of transistor 303. This is because wiring 11 Since the load at node 1 is often greater than the load at node A, the wiring 111 has a signal or voltage. The driving capability of the transistors that supply signals, voltages, etc. to node A is determined by the transistors that supply signals or voltages, etc. This is because it is often greater than the driving capacity of the transistor. And, transistor 305, and Transistor 304 has the function of supplying a signal or voltage to wiring 111, Transistor 302 and transistor 303 have the function of supplying a signal or voltage to node A. Therefore. However, this is not limited to the channel width of transistor 305. It is possible to have a channel width smaller than that of transistor 302. Or, the channel width of transistor 304 The channel width can be smaller than, for example, the channel width of transistor 303. Yes, because node A has the first terminal of transistor 101 described in Embodiment 1. This is because noise is easily generated due to the parasitic capacitance between the gate and the signal. In some cases, the transistor 101 turns on, causing the potential of the wiring 111 to rise. Because it exists.

[0175] For example, the channel width of transistor 303 is equal to the channel width of transistor 302. It is preferable that it be greater than the width. Alternatively, the channel width of transistor 304 is, for example, Therefore, it is preferable that it be larger than the channel width of transistor 305. By doing this, This reduces the impact of noise on node A and wiring 111. However, However, the channel width of transistor 303 is the channel width of transistor 302. It is possible to have a width smaller than the channel width. Alternatively, the channel width of transistor 304 is It is possible to use a channel width smaller than that of the ZISTA 305.

[0176] Note that when a signal with a potential lower than V1 at L level is input to terminals 105a and 105c, It is possible to apply this force. In this way, a reverse bias is applied to transistors 302-305. This makes it possible to mitigate the characteristic degradation of transistors 302-305. Alternatively, terminals 105a and 105c have a signal with a potential lower than V2 at the H level. It is possible to input a number. In this way, when transistors 302-305 are ON Since Vgs can be reduced, the characteristic degradation of transistors 302-305 is suppressed. This is possible. In such a case, the potential of the wiring 113 and wiring 115 is at L level V A signal lower than 1, a signal with an H level potential lower than V2, or a signal with an L level potential lower than V1 It is possible to input a signal that is lower than and has a high-level potential lower than V2. Furthermore, and not limited to this, if one of terminals 105a and 105c has a potential of L level V A signal lower than 1, a signal with an H level potential lower than V2, or a signal with an L level potential lower than V1 It is possible to input a signal that is lower than and has a high-level potential lower than V2. In this case, one of the wires 113 and 115 has a signal with a potential lower than V1 at the L level, H A signal with a level potential lower than V2, or a signal with an L level potential lower than V1 and an H level It is possible to input a signal where the potential of the bell is lower than V2. Alternatively, terminal 105a It is connected to a different wire from wire 113, and a signal with a potential lower than V1 at the L level is transmitted to that wire. A signal where the H level potential is lower than V2, or the L level potential is lower than V1, It is possible to input a signal with a potential lower than V2 at the H level. Alternatively, terminal 105 c is connected to a different wire from wire 115, and the potential of that wire is lower than V1 at an L level. A signal whose H level potential is lower than V2, or a signal whose L level potential is lower than V1, Furthermore, it is possible to input a signal with a potential lower than V2, which is at the H level.

[0177] Furthermore, terminal 105d will be at an L level during periods T1, T3, and T4. It is possible to input signals. For example, the signal IN2 can be input to terminal 105d. This is possible. In this case, terminal 105d can be connected to wiring 113. By doing so, transistor 303, transistor 304, or transistor Since it becomes possible to apply a reverse bias to transistor 305, transistor 303, This can mitigate the characteristic degradation of the transistor 304 or the transistor 305.

[0178] Furthermore, similar to Embodiment 1 or Embodiment 2, the wiring can be divided into multiple wires. It is possible. And it is possible to input the same signal or voltage to these multiple wires. It is possible to input different signals or voltages. Alternatively, the multiple wires may be the same It is possible to connect the wiring or the same element, and the multiple wires are separate wires or It is possible to connect to separate elements. In one example shown in Figure 14(A), wiring 113 is connected It is divided into multiple wires 113A to 113B, and wire 114 is divided into wires 114A to 114B. The wiring is divided into multiple wires, and wire 115 is divided into multiple wires 115A to 115B. When divided, the wiring 116 is divided into multiple wirings 116G to 116I. This shows that the transistor 302's gate is connected to wiring 113A, and the transistor The gate of transistor 305 is connected to wiring 113B. The first terminal of transistor 302 is connected to wiring Connected to 114A, the first terminal and gate of transistor 301 are connected to wiring 114B. The gate of transistor 303 is connected to wiring 115A, and transistor 304 The gate is connected to wire 115B. The first terminal of transistor 303 is connected to wire 116G. The first terminal of transistor 304 is connected to wiring 116H, and transistor 3 The first terminal of 05 is connected to wiring 116I. However, it is not limited to wiring 113 Only one, two, or three of the wirings 114, 115, and 116 may be multiple. It is possible to divide the wiring into these components.

[0179] Note that in Figure 14(A), wiring 113A to 113B are connected to wiring 113 in Figure 12(A). Corresponds. Therefore, similar to wiring 113, signal IN2 is input to wirings 113A~113B. It is possible to power the wiring, and wires 113A to 113B can function as signal lines. However, this is not limited to the above, and the wiring 113A to 113B may have voltage V1 or voltage V It is possible to supply voltages such as 2, and wiring 113A~113B is used as a power line. It is possible to do so. Alternatively, separate signals or separate It is possible to input voltage. Alternatively, wiring 113A~113B can also be used for various other purposes. It is possible to input signals, various voltages, or various currents.

[0180] Note that in Figure 14(A), wiring 114A to 114B are connected to wiring 114 in Figure 12(A). Corresponds. Therefore, similar to wiring 114, signal IN3 is input to wirings 114A~114B. It is possible to power the wiring, and wires 114A to 114B can function as signal lines. However, this is not limited to the above, and the wiring 114A to 114B may have voltage V1 or voltage V It is possible to supply voltages such as 2, and wiring 114A~114B is used as a power line. It is possible to do so. Alternatively, separate signals or separate It is possible to input voltage. Alternatively, wiring 114A~114B can also be used for various other purposes. It is possible to input signals, various voltages, or various currents.

[0181] Note that in Figure 14(A), wiring 115A to 115B is connected to wiring 115 in Figure 12(A). Corresponds. Therefore, similar to wiring 115, signal IN4 is input to wirings 115A~115B. It is possible to power the wires, and wiring 115A~115B can function as signal lines. However, this is not limited to the above, and the wiring 115A to 115B may have voltage V1 or voltage V It is possible to supply voltages such as 2, and wiring 115A~115B is used as a power line. It is possible to do so. Alternatively, separate signals or separate It is possible to input voltage. Alternatively, wiring 115A~115B can also be used for various other purposes. It is possible to input signals, various voltages, or various currents.

[0182] Note that in Figure 14(A), wiring 116G~116I is connected to wiring 116 in Figure 12(A). Corresponds. Therefore, similar to wiring 116, voltage V1 is supplied to wirings 116G to 116I. It is possible to do so, and wiring 116G~116I can function as a power line. Yes. However, this is not limited to this; wiring 116G~116I may have a signal OUT or a signal By inputting signals such as IN1 to IN4, wiring 116G to 116I becomes a signal line. It can function as such. Alternatively, separate voltages can be used for wiring 116G~116I. Alternatively, it is possible to supply separate signals. Or, wiring 116G~116I may have other It is possible to input various signals, voltages, or currents to it.

[0183] In Figure 14(A), wiring 116G and wiring 116H are connected during period T3. It is possible to input a signal that will be at an L level. For example, wiring 116G and wiring 1 Signal IN2 can be input to 16H. In this case, wiring 116G and wiring The wire 116H can be connected to the wiring 112 described in Embodiment 1 and Embodiment 2. This is possible. By doing this, inverse bucking occurs in transistors 303 and 304. Since it becomes possible to apply IAS, transistors 303 and 304 This can suppress the degradation of the characteristics of wiring 116G and wiring 1 It is possible to input signal IN2 to only one of the 16H terminals. Alternatively, wiring 116G , and / or, it is possible to input signal OUT or signal IN3 to wiring 116H. In this case, wiring 116G and / or wiring 116H are in the form of Embodiment 1 and the embodiment. It is possible to connect to the wiring 111 or wiring 114 described in state 2.

[0184] In Figure 14(A), wiring 116I is connected during periods T1, T3, and T5. Therefore, it is possible to input a signal that will be at an L level. For example, wiring 116I is used for signal It is possible to input IN2. In this case, wiring 116I is used in Embodiment 1 and the implementation. It is possible to connect to the wiring 112 described in form 2. By doing so, Since it becomes possible to apply a reverse bias to transistor 305, This can suppress the degradation of characteristics. However, it is not limited to this.

[0185] Note that, as shown in Figure 14(B), transistors 303 and 304 are omitted. It is possible to do this. In this way, the number of transistors can be reduced. Therefore, This allows for a reduction in the output area or an improvement in yield. However, this is not limited to the above, and only one of transistors 303 and 304 may be omitted. It can be abbreviated.

[0186] Furthermore, similar to Figure 14(B), in Figure 14(A) as well, transistor 303 and / or Therefore, transistor 304 can be omitted.

[0187] Furthermore, as shown in Figure 14(C), transistor 305 can be omitted. Thus, the number of transistors can be reduced. Therefore, the layout area can be reduced, or This can lead to improvements in yield, among other things. However, it is not limited to this.

[0188] Furthermore, similar to Figure 14(C), in Figures 14(A) and (B), transistor 305 is also used. It is possible to omit it.

[0189] Furthermore, as shown in Figure 15(A), transistor 302 can be omitted. Thus, the number of transistors can be reduced. Therefore, the layout area can be reduced, or This can lead to improvements in yield, among other things. However, it is not limited to this.

[0190] Furthermore, similar to Figure 15(A), in Figures 14(A) to (C), transistor 302 is also used. It can be omitted.

[0191] Furthermore, as shown in Figure 15(B), transistor 301 can be omitted. Thus, the number of transistors can be reduced. Therefore, the layout area can be reduced, or This can lead to improvements in yield, among other things. However, it is not limited to this.

[0192] Furthermore, similar to Figure 15(B), in Figures 14(A) to (C), and Figure 15(A), The Rangista 301 can be omitted.

[0193] As shown in Figure 16(A), transistor 303 is connected to one terminal (hereinafter referred to as the positive terminal). One terminal (hereinafter also referred to as the negative terminal) is connected to node A, and the other terminal (hereinafter also referred to as the negative terminal) is connected to wiring 115. It is possible to replace it with diode 303a. Alternatively, transistor 304 One terminal (hereinafter also referred to as the positive terminal) is connected to the wiring 111, and the other terminal (hereinafter referred to as the negative terminal) is connected to the wiring 111. (Also known as) can be replaced with diode 304a connected to wiring 115. However, this is not limited to the above, and one of transistors 303 and 304 may be die-cut. It is possible to replace it with an diode. Or, diode 303a, and / or die It is possible to add Od 304a as a new option.

[0194] Furthermore, similar to Figure 16(A), Figures 14(A)-(C) and 15(A)-(B) show odors. However, transistor 303 has one terminal connected to node A and the other terminal connected to wiring 11 It is possible to replace diode 303a connected to 5. Alternatively, the transistor One terminal of terminal 304 is connected to wiring 111, and the other terminal is connected to wiring 115. It is possible to replace it with diode 304a, or diode 303a, and Alternatively, a diode 304a can be added.

[0195] Although not shown in the illustrations, please refer to Figures 14(A)-(C), 15(A)-(B), and 16(A) In this configuration, the first terminal of transistor 303 is connected to the wiring 115, and transistor 3 The second terminal of 03 is connected to node A, and the gate of transistor 303 is connected to node A. This makes it possible to connect transistor 303 in diode mode. Alternatively, the first terminal of transistor 304 is connected to the wiring 115, and the transistor 304 The second terminal is connected to wiring 111, and the gate of transistor 304 is connected to wiring 111. This makes it possible to connect transistor 304 in diode mode. And, not limited to this, one of transistors 303 and 304 may be a diode It is possible to connect to it.

[0196] As shown in Figure 16(B), transistor 305 is connected to one terminal (hereinafter referred to as the positive terminal). One terminal (hereinafter also referred to as the negative terminal) is connected to wiring 111, and the other terminal (hereinafter also referred to as the negative terminal) is connected to wiring 113. It is possible to replace the diode 305a with this. However, it is not limited to this. It is possible to add a diode 305a.

[0197] Furthermore, similar to Figure 16(B), Figures 14(A)-(C), 15(A)-(B), and Figure 1 In 6(A), the transistor 305 is connected to the wiring, with one terminal (hereinafter also referred to as the positive terminal) connected to the wiring. A diode connected to 111, with the other terminal (hereinafter also referred to as the negative terminal) connected to wiring 113. It can be replaced with diode 305a. Alternatively, a new diode 305a can be added. It is possible to do so.

[0198] Although not shown in the illustrations, please refer to Figures 14(A)-(C), 15(A)-(B), and 16(A) In (B), the first terminal of transistor 305 is connected to wiring 113, The second terminal of transistor 305 is connected to wiring 111, and the gate of transistor 305 is connected to wiring By connecting to 111, transistor 305 can be made into a diode connection. It is Noh. However, it is not limited to this.

[0199] As shown in Figure 17(A), the gate of transistor 301 is connected to wiring 117. It is possible to do this. For this purpose, the circuit 105 may have a new terminal 105g. It is possible. And the wiring 117 is connected to the gate of transistor 301 via terminal 105g. It is connected to the following. Voltage V2 is supplied to wiring 117, and wiring 117 functions as a power line. It is possible to do so. However, it is not limited to this, and the first terminal of transistor 301 is also available. The gate of transistor 301 is connected to wire 117 and can be connected to wire 114. It is possible. Alternatively, a signal that is at an H level during period T2 is input to wiring 117. It is possible for wiring 117 to function as a signal line. It is possible to input signal IN2 to wire 117, and wiring 117 is connected to wiring 113. It is possible to do so. Alternatively, wiring 117 can also carry various other signals, various voltages, or It is possible to input various currents.

[0200] Furthermore, similar to Figure 17(A), Figures 14(A)-(C), 15(A)-(B), and Figure 1 In 6(A)~(B), the gate of transistor 301, or the gate of transistor 301 The first terminal can be connected to wiring 117.

[0201] Furthermore, as shown in Figure 17(B), transistors 306 and 307 are newly... It is possible to add transistor 306 and transistor 30 7 often has the same polarity as transistors 301-305, and is an N-channel type. The first terminal of transistor 306 is connected to wiring 116, and transistor 3 The second terminal of 06 is connected to node A, and the gate of transistor 306 is connected to wiring 118. The first terminal of transistor 307 is connected to wiring 116, and the transistor The second terminal of transistor 307 is connected to wiring 111, and the gate of transistor 307 is connected to wiring It is connected to 118. As an example, signal IN5 is input to wiring 118. Wiring 118 can function as a signal line. Transistor 306 is signal I Depending on the potential of N5 or wiring 115, the conduction state between wiring 116 and node A is controlled. This has the function of controlling the timing at which voltage V1 is supplied to node A, and the switch It can function as a transistor. Transistor 307 is connected to signal IN5, or wiring 11 By controlling the conduction state between wiring 116 and wiring 111 according to the potential of 5, the voltage V1 has the function of controlling the timing at which it is supplied to wiring 111, and functions as a switch. It is possible to do so. Signal IN5, for example, functions as a full reset signal. This is common. However, it is not limited to this, and one of transistors 306 and 307 It is possible to add only this new item.

[0202] Note that, similar to Figure 17(B), Figures 14(A)~(C), Figures 15(A)~(B), and Figure 16( In A)~(B), and also in Figure 17(A), transistor 306 and / or transistor It is possible to add transistor 307. The first terminal of transistor 306 is The second terminal of transistor 306 is connected to node A, and the wiring 116 is connected to the second terminal of transistor 306. The gate of transistor 306 is connected to wiring 118. The first terminal of transistor 307 The second terminal of transistor 307 is connected to wiring 116, and the second terminal of transistor 307 is connected to wiring 111. The gate of transistor 307 is connected to wiring 118.

[0203] As shown in Figure 17(C), transistors 301 to 305 are P-channel type transistors. A transistor can be used. In particular, transistor 101 described in Embodiment 1 ~103 and the transistors 201~204 described in Embodiment 2 are P-channel type When transistors are used, they are designated as transistors 301-305 and are P-channel type. It is preferable to use transistors. Transistor 301p, transistor 302p, Transistors 303p, 304p, and 305p are, respectively, Transistor 301, Transistor 302, Transistor 303, Transistor 304, Compatible with Rangista 305.

[0204] Note that, similar to Figure 17(C), Figures 14(A)-(C), 15(A)-(B), and 16( In A) and (B), and in Figure 17(A) and (B), transistors 301 and 305 are used. Therefore, it is possible to use a P-channel transistor.

[0205] Furthermore, as already mentioned, the circuit 105 of the circuit 100 described in Embodiment 1 is It is possible to use the configuration of circuit 105 described in the embodiment. Figure 18(A) shows one For example, the circuit 105 of the circuit 100 in Figure 1(A) is connected to the circuit 105 of the circuit 105 in Figure 12(A). The configuration using one example is shown. And, as an example, Figure 18(B) is shown. An example of the circuit 105 in Figure 12(A) is used for the circuit 105 of circuit 100, and further, Figure 1 When using an example of the circuit 104 in Figure 9(A) for the circuit 104 of the circuit 100 in (A) The configuration is shown below. However, it is not limited to this, see Figures 12(A), 14(A), and 14(B). Figures 14(C), 15(A), 15(B), 16(A), 16(B), 17( A), Figure 17(B), Figure 17(C), or a circuit 105 obtained by combining these, is shown in Figure 1(A), Figure 5(A), Figure 5(B), Figure 6(A), Figure 6(B), Figure 6(C), Figure 7(A) , Figure 7(B), Figure 8(A), or a combination thereof, the circuit 100 has It can be used with 05.

[0206] (Embodiment 4) This embodiment describes an example of a shift register. The shift register of this embodiment The stator can have semiconductor devices according to Embodiments 1 to 3. The foot register can represent a semiconductor device or a gate driver. The contents described in Embodiments 1 to 3 will not be explained further. The contents described in the third embodiment can be freely combined with the contents described in this embodiment. ru.

[0207] First, an example of a shift register will be explained with reference to Figure 19. Shift register 40 0 is a flip-flop called 401_1~401_N (where N is a natural number) Rope.

[0208] Note that flip-flops 401_1 to 401_N correspond to Embodiments 1 to 3, respectively. This corresponds to the semiconductor device described below. An example in Figure 19 is flip-flops 401_1 to 40 Let's consider the case where 1_N is the semiconductor device shown in Figure 1(A). However, we are not limited to this case. Not done, and as flip-flops 401_1~401_N, the semiconductor device in Figure 1(A) In addition, the semiconductor devices described in Embodiments 1 to 3, or various other semiconductor devices, It is possible to use a circuit.

[0209] Next, we will explain the connection of the shift registers. Shift register 400 is connected to wiring 41 1_1~411_N is connected to wiring 412, wiring 413, wiring 414, and wiring 415. And, in the flip-flop 401_i (where i is one of 1 to N), wiring 1 Wire 11 is connected to wire 411_i, and wire 112 is connected to either wire 412 or wire 413. Wiring 113 is connected to the other side of wiring 412 and wiring 413, and wiring 114 is connected to wiring 41 Wiring 115 is connected to 1_i-1, and wiring 411_i+1 is connected to wiring 116. It is connected to 416. Here, odd-numbered flip-flops and even-numbered flip-flops In many cases, the connections of wires 112 and 113 are reversed. For example, odd numbers In the flip-flop stage, wire 112 is connected to wire 412, and wire 113 is connected to wire When connected to 413, in even-numbered flip-flops, wiring 112 is connected to wiring 41 It is connected to 3, and in many cases wiring 113 is connected to wiring 412. On the other hand, odd-numbered stages In the flop, wire 112 is connected to wire 413, and wire 113 is connected to wire 412. If continued, in an even-numbered flip-flop, wiring 112 is connected to wiring 412. In many cases, wiring 113 is connected to wiring 413. However, this is not limited to other cases. It is also possible to create various connection configurations.

[0210] Note that in flip-flop 401_1, wiring 114 is connected to wiring 414. There are many. And in flip-flop 401_N, wire 115 is connected to wire 415. In many cases, this is the case.

[0211] Note that wiring 411_1 to 411_N are the wirings described in Embodiments 1 to 3, respectively. Corresponds to 111. Wiring 412 is the same as wiring 112 described in Embodiments 1 to 3 or It corresponds to wiring 113. Wiring 413 corresponds to wiring 112 described in Embodiments 1 to 3. Alternatively, it corresponds to wiring 113. Wiring 414 corresponds to wiring 1 described in Embodiments 1 to 3. Corresponds to 14. Wiring 415 corresponds to wiring 115 described in Embodiments 1 to 3. Wiring 416 corresponds to wiring 116 described in Embodiments 1 to 3.

[0212] Next, wiring 411_1~411_N, wiring 412, wiring 413, wiring 414, wiring 415 Next, an example of a signal or voltage input to or output to wiring 416 will be described. Wiring 411_ From 1 to 411_N, for example, signals GOUT_1 to GOUT_N are output respectively. It shall be assumed that signals GOUT_1 to GOUT_N are each connected to flip-flop 401_1. This is the output signal of ~401_N. And signals GOUT_1~GOUT_N are in their actual form. Corresponding to the signal OUT described in Embodiments 1 to 3, the output signal, selection signal, transfer signal, and station It can function as a gate signal, reset signal, gate signal, or scan signal. As an example, the signal GCK is input to wiring 412. The signal GCK is implemented Corresponding to signal IN1 or signal IN2 described in Embodiments 1 to 3, and used as a clock signal. It is possible for it to function. For example, the signal GCKB is input to wiring 413. The signal GCKB is the signal IN1 or signal described in Embodiments 1 to 3. It is compatible with IN2 and can function as an inverting clock signal. Wiring 414 is: As an example, let's assume that a signal GSP is input. The signal GSP is as follows: Corresponding to signal IN3 as described in Form 3, it functions as a start signal or a vertical synchronization signal. This is possible. For example, the signal GRE is input to wiring 415. Signal GRE corresponds to signal IN4 as described in Embodiments 1 to 3, and is a reset signal. It is possible to function in this way. For example, the voltage V1 is input to wiring 416. This shall apply. However, it is not limited to wiring 411_1~411_N, wiring 412, wiring Wires 413, 414, 415, and / or 416 also carry various other signals. It is possible to input various currents or voltages. For example, wiring 412, wiring 41 3. A voltage such as voltage V1 or voltage V2 is supplied to wiring 414 and / or wiring 415. It is possible to connect signals GOUT_1 to GOUT_N to wiring 416. Signals such as GCK, GCKB, GSP, or GRE can be input. That is. Or, wiring 411_1~411_N, wiring 412, wiring 413, wiring 414, Without inputting a signal or voltage to wiring 415 and / or wiring 416, these wiring It is possible to make it float.

[0213] Note that wiring 411_1 to 411_N are signal lines, gate lines, scan lines, or output signal lines. It is possible for it to function. Wiring 412 can function as a signal line or a clock signal line. It is possible that wiring 413 can function as a signal line or a clock signal line. Yes, it is possible. Wiring 414 can function as a signal line. Wiring 415 is a signal line. It can function as a power line. Wiring 416 can function as a power line or ground line. It is possible to do so. However, it is not limited to this, and wiring 411_1~411_N, wiring Wire 412, wiring 413, wiring 414, wiring 415, and / or wiring 416 are also... It can function as various types of wiring. For example, wiring 412, wiring 413, wiring 41 4. And / or, if voltage is supplied to wiring 415, these wirings are power lines. It is possible for it to function. Or, if a signal is input to wiring 416, wiring 416 It can function as a signal line.

[0214] As already mentioned, the shift register can handle multiphase clock signals or unbalanced clock signals. It is possible to input a lock signal.

[0215] Note that wiring 412, wiring 413, wiring 414, wiring 415, and wiring 416 are connected to circuit 4 A signal or voltage is input from 20. Circuit 420 is a shift register 40 This function controls the shift register 400 by supplying a signal or voltage to 0. It has the capability to function as a control circuit or controller, etc. (Embodiment) For example, circuit 420 has wiring 412, wiring 413, wiring 414, wiring 415, And to wiring 416, signals GCK, GCKB, GSP, GRE, and voltage V are respectively connected. It shall supply 1. However, it shall not be limited to this, and the circuit 420 shall supply shift register 4 Not only 00, but also various other circuits (for example, signal line drive circuits, scan line drive circuits, and / Alternatively, it is possible to supply signals or voltages to pixels (or other elements) and control these circuits. .

[0216] For example, circuit 420 may include circuits 421 and 422. Circuit 421 generates power supply voltages such as positive power supply voltage, negative power supply voltage, ground voltage, and reference voltage. It has the function of being able to function as a power supply circuit or a regulator. Circuit 42 2 is the clock signal, inverted clock signal, start signal, reset signal, and / or, It has the function of generating various signals, such as audio signals, and functions as a timing generator. It is possible to do so. However, it is not limited to this, and circuit 420 can be used with circuit 421 and circuit 4 In addition to 22, it is possible to have various other circuits or elements. For example, circuit 42 0 is an oscillator, level shift circuit, inverter circuit, buffer circuit, DA conversion circuit, AD conversion circuit, operational amplifier, shift register, lookup table, coil, transistor It may include elements such as capacitors, capacitive elements, resistive elements, and / or frequency dividers.

[0217] Next, regarding the operation of the shift register in Figure 19, please refer to the timing chart in Figure 20. Let me explain. Figure 20 is an example of a timing chart to illustrate the operation of a shift register. Figure 20 shows signals GSP, GRE, GCK, GCKB, and GOU. T_1, signal GOUT_i-1, signal GOUT_i, signal GOUT_i+1, and signal G An example of OUT_N is shown. Note that this is common to the operation of the semiconductor device in Embodiments 1 to 3. Where necessary, the explanation will be omitted.

[0218] Let's explain the operation of flip-flop 401_i. First, when the signal GOUT_i-1 is high... It reaches a certain level. Then, the flip-flop 401_i begins its operation during period T1. Then, the signal GOUT_i becomes low. Subsequently, the signals GCK and GCKB invert. Then, flip-flop 401_i starts operating during period T2, and the signal GOU T_i becomes high level. The signal GOUT_i is reset to flip-flop 401_i-1. It is input as a start signal and also input to flip-flop 401_i+1 as a start signal. Therefore, flip-flop 401_i-1 starts operating during period T3. Then, the flip-flop 401_i+1 begins operation during period T1. Subsequently, the signal The GCK and GCKB signals are inverted again. Then the flip-flop 401_i+1 Operation in period T2 begins, and signal GOUT_i+1 becomes high. Signal GOUT _i+1 is input to flip-flop 401_i as a reset signal. Therefore Since flip-flop 401_i starts operating during period T3, the signal GOUT_ i becomes low. After that, until the signal GOUT_i-1 becomes high again, it will remain frozen. The flop 401_i is activated during period T4 whenever the signals GCK and GCKB are inverted. The operation in [location] and the operation in period T5 are repeated.

[0219] Note that flip-flop 401_1 replaces the output signal of the previous flip-flop. The signal GSP is input from circuit 420 via wiring 414. Therefore, the signal GSP is When it reaches the H level, flip-flop 401_1 begins its operation for period T1.

[0220] Note that in flip-flop 401_N, instead of the output signal of the next stage flip-flop... The signal GRE is input from circuit 420 via wiring 415. Therefore, the signal GRE is When it reaches the H level, the flip-flop 401_N begins its operation during period T3.

[0221] The operation of the shift register of this embodiment has been described above. ZISTA uses the semiconductor devices of Embodiments 1 to 3, It is possible to obtain the same benefits as the device.

[0222] Furthermore, as described in Embodiments 1 to 3, the relationship between signals GCK and GCKB It is possible to make it non-equilibrium. For example, as shown in the timing chart in Figure 21(A) In the case of signals GCK and GCKB, the period during which they are at an H level is the period during which they are at an L level. It is possible to make it shorter than this. By doing so, the signal GOUT_1~GOUT Even if delays or distortions occur in _N, this prevents these signals from remaining at a high level for extended periods. Therefore, when the shift register of this embodiment is used in a display device... This prevents multiple rows from being selected simultaneously. However, this is not limited to this, In signal GCK and / or signal GCKB, the period during which it is at an H level is the period during which it is at an L level. It is possible to have a duration longer than the interval.

[0223] Furthermore, as described in Embodiments 1 to 3, using a multiphase clock signal is possible. It is possible. For example, as shown in the timing chart in Figure 21(B), M(where M is a natural number) It is possible to use a clock signal of phase ). In this case, the signals GOUT_1~GOUT In _N, the period during which a certain stage is at level H is the same as the period during which the stages before and after it are at level H. This makes it possible for the period to overlap. Therefore, if this embodiment is used in a display device In this case, multiple rows will be selected simultaneously. This will result in video signals to pixels in other rows. This makes it possible to use the number as a precharge voltage.

[0224] In Figure 21(B), it is preferable that M ≤ 8. More preferably, M ≤ 6. It is preferable that there be a condition. More preferably, it is preferable that M ≤ 4. This is because Shift When a tracer is used in the scan line driving circuit of a display device, if M is too large, multiple pixels will be affected. This is because several types of video signals are written to the pixel. This is because the period during which data is entered becomes longer, which may lead to a decrease in display quality.

[0225] Furthermore, similar to Figure 21(B), the timing chart in Figure 21(A) also shows multiphase It is possible to use a lock signal.

[0226] Note that wiring 415 can be shared with other wiring or omitted. For example, wiring Wire 415 may be shared with wire 412, wire 413, wire 414, or wire 416. It is possible. In this case, wiring 415 is omitted, and in the flip-flop 401_N, Wire 115 is connected to wiring 412, wiring 413, wiring 414, or wiring 416. It is possible. As another example, wiring 415 can be omitted. In this case, In the flop 401_N, similar to Figure 14(B), the transistors of circuit 105 The transistors 303 and 304 can be omitted.

[0227] Depending on the configuration of flip-flops 401_1 to 401_N, additional wiring may be required. It is possible to do so. For example, as shown in Figure 17(A) or Figure 17(B), the voltage V2, or If a signal that can function as a full reset signal is required, new wiring may be needed. It is possible to add this. And the newly added wiring will receive signals from circuit 420 or It is possible to supply voltage and other signals.

[0228] As shown in Figure 22, flip-flops 401_1 to 401_N are each equipped with transistors. It is possible to add transistor 431. The polarity of transistor 431 is... It is preferable that it has the same polarity as 101, and is often of the N-channel type. However, Transistor 431 is not limited to this, and can also be a P-channel type. In rop 401_i, the first terminal of transistor 431 is connected to wiring 112. The second terminal of transistor 431 is connected to wiring 417_i, and transistor 431 The gate is connected to node A. Then, in flip-flop 401_i, Wire 111 is connected to wire 411_i, and wire 112 is connected to either wire 412 or wire 413. Wiring 113 is connected to the other side of wiring 412 and wiring 413, and wiring 114 is Wiring 115 is connected to wire 417_i-1 and wire 411_i+1. 6 is connected to wiring 416. By doing this, wirings 411_1 to 411_N are connected. Even when a load such as a pixel or gate line is connected, the next stage flip-flop is driven. Therefore, the transfer signal for the shift register does not become distorted or delayed. The effects of delay can be reduced. However, this is not limited to wiring 114, wiring 4 It is possible to connect to 11_i-1. Alternatively, wiring 115 can be connected to wiring 417_i+ It is possible to connect to 1. Alternatively, the potential of wiring 417_1~417_N can be set to V1. It is possible to add new transistors to maintain the current.

[0229] In Figure 22, as in Figure 21(A), the signals GCK and GCKB are unbalanced. This is possible. Alternatively, as in Figure 21(B), a multiphase clock signal can be used. It is possible.

[0230] (Embodiment 5) This embodiment describes an example of a display device.

[0231] First, with reference to Figure 23(A), an example of a liquid crystal display system block will be explained. The liquid crystal display device consists of circuits 5361, 5362, 5363_1, and 5363_ 2. It has a pixel section 5364, a circuit 5365, and an illumination device 5366. In this configuration, multiple wires 5371 extend from circuit 5362 and are arranged, and multiple wires 5372 are arranged It is arranged as an extension from path 5363_1 and circuit 5363_2. And multiple Each of the intersection regions of line 5371 and multiple wirings 5372 contains a display element such as a liquid crystal element. The 5367 pixels are arranged in a matrix.

[0232] Circuit 5361, in response to the video signal 5360, controls circuits 5362, 5363_1, and 5 363_2 and circuit 5365 have the function of supplying signals, voltage, or current, etc. Controllers, control circuits, timing generators, power supply circuits, or regulators, etc. It is possible for it to function. In this embodiment, as an example, circuit 5361 is circuit 5 362, start signal for signal line drive circuit (SSP), clock signal for signal line drive circuit ( SCK), inverting clock signal for signal line drive circuit (SCKB), data for video signal (DA) TA) and a latch signal (LAT) shall be supplied. Alternatively, circuit 5361 is an example and Then, the start signal (G) for the scan line drive circuit is sent to circuits 5363_1 and 5363_2. SP), clock signal for scan line drive circuit (GCK), and clock for inverted scan line drive circuit The signal (GCKB) shall be supplied. Alternatively, circuit 5361 shall supply the signal to circuit 5365. The circuit shall supply a light control signal (BLC). However, it shall not be limited to this, and the circuit 5361 also handles various signals, voltages, or currents, etc., in circuit 5362, It is possible to supply power to path 5363_1, circuit 5363_2, and circuit 5365.

[0233] Circuit 5362 receives signals supplied from circuit 5361 (e.g., SSP, SCK, SCKB). It has the function of outputting video signals to multiple wires 5371 according to DATA and LAT. It can function as a signal line driving circuit. Circuit 5363_1 and Circuit 536 3_2 operates according to the signals (GSP, GCK, GCKB) supplied from circuit 5361. It has the function of outputting scan signals to multiple wires 5372 and functions as a scan line drive circuit. This is possible. Circuit 5365 responds to the signal (BLC) supplied from circuit 5361. By controlling the amount of power or the time supplied to the lighting device 5366, the lighting device It has the function of controlling the brightness (or average brightness) of 5366 and can function as a power supply circuit. It is possible.

[0234] Furthermore, if video signals are input to multiple wires 5371, the multiple wires 5371 will receive the signal. It can function as a wire, video signal wire, or source wire, etc. Multiple wires 53 When a scan signal is input to 72, multiple wires 5372 are signal lines, scan lines, or gate lines. It can function as a line or similar element, but is not limited to this.

[0235] Furthermore, the same signal is input to circuits 5363_1 and 5363_2 from circuit 5361. In this case, the scanning signal that circuit 5363_1 outputs to multiple wires 5372, and circuit 5363 The scanning signals that _2 outputs to multiple wires 5372 will be at roughly the same timing. There are many cases. Therefore, the load driven by circuits 5363_1 and 5363_2 is reduced. It can be made larger. Therefore, the display device can be made larger. Alternatively, the display device can be made larger. High resolution can be achieved. Or, circuits 5363_1 and 5363_2 have Since the channel width of the transistor can be reduced, a narrow-bezel display device can be obtained. This is possible. However, it is not limited to this, and circuit 5361 can be used with circuit 5363_1 and circuit 536 It is possible to supply separate signals to 3_2 and 3_2.

[0236] Note that either circuit 5363_1 or circuit 5363_2 can be omitted.

[0237] Furthermore, new wiring such as capacitance lines, power lines, and scanning lines can be added to the pixel section 5364. It is possible. And circuit 5361 outputs signals or voltages to these wires. This is possible. Alternatively, a new circuit similar to circuit 5363_1 or circuit 5363_2 can be added. In addition, this newly added circuit outputs signals such as scanning signals to the newly added wiring. It is possible.

[0238] Furthermore, pixel 5367 can have a light-emitting element such as an EL element as a display element. In this case, as shown in Figure 23(B), the display element can emit light, so circuit 5 365 and the lighting device 5366 can be omitted. And power to the display element To supply power, multiple wires 5373 capable of functioning as power lines are provided in the pixel section 53 It can be arranged in 64. Circuit 5361 distributes a power supply voltage called voltage (ANO). It is possible to supply power to line 5373. This wiring 5373 is connected according to the color element of the pixel. It is possible to connect to all pixels, and it is also possible to connect to all pixels in common.

[0239] Note that in Figure 23(B), as an example, circuit 5361 is connected to circuit 5363_1 and circuit 536 An example of supplying separate signals to 3_2 is shown. Circuit 5361 is for the scan line drive circuit. Start signal (GSP1), clock signal for scan line drive circuit (GCK1), and inverted scan The clock signal (GCKB1) for the line drive circuit and other signals are supplied to circuit 5363_1. Circuit 5361 then provides a start signal (GSP2) for the scan line drive circuit, and for the scan line drive circuit Clock signal (GCK2), and clock signal for inverted scan line drive circuit (GCKB2), etc. The signal is supplied to circuit 5363_2. In this case, circuit 5363_1 has multiple wires 53 Scanning only the odd-numbered rows of wiring 72, circuit 5363_2 is a multiple wiring 5372 This makes it possible to scan only the wiring in even-numbered rows. Therefore, circuit 5363_1, and Since the driving frequency of track 5363_2 can be reduced, power consumption can be reduced. Alternatively, increase the area available for laying out one stage of flip-flops. This is possible. Therefore, the display device can be made high-resolution. Alternatively, the display device can be made larger. This is possible. However, it is not limited to this, and, similar to Figure 23(A), circuit 5361 is, It is possible to output the same signal to both circuit 5363_1 and circuit 5363_2.

[0240] Note that, similar to Figure 23(B), in Figure 23(A), circuit 5361 is also circuit 5363 It is possible to supply separate signals to _1 and circuit 5363_2.

[0241] The above describes an example of a system block for a display device.

[0242] Next, an example of the display device configuration is shown in Figures 24(A), (B), (C), (D), and ( See E) for further explanation.

[0243] Figure 24(A) shows a circuit that has the function of outputting a signal to the pixel unit 5364 (for example, circuit 5 Circuits 362, 5363_1, and 5363_2, etc., are on the same substrate as the pixel unit 5364. It is formed at 5380. The circuit 5361 is formed on a separate substrate from the pixel section 5364. This reduces the number of external parts, thus lowering costs. Alternatively, Since the number of signals or voltages input to board 5380 decreases, the relationship between board 5380 and external components The number of connections can be reduced. Therefore, it is possible to improve reliability or yield. can.

[0244] Furthermore, if the circuit is formed on a substrate separate from the pixel section 5364, the substrate is TAB(Ta FPC (Flexible Printed Circuit) is a method of Automated Bonding. It can be mounted on a Printed Circuit. Alternatively, the board can be , COG (Chip on Glass) method, the same substrate 538 as the pixel unit 5364 It is possible to implement this in 0.

[0245] Furthermore, if the circuit is formed on a substrate separate from the pixel section 5364, the substrate may contain a single-crystal semiconductor. It is possible to form a transistor using the substrate. Therefore, the substrate is formed The circuit offers advantages such as improved drive frequency, improved drive voltage, and reduced output signal variation. You can obtain [something].

[0246] Furthermore, signals, voltages, or currents are input from external circuits via input terminal 5381. In many cases, this is the case.

[0247] In Figure 24(B), circuits with low drive frequencies (for example, circuit 5363_1, circuit 5363_ 2) is formed on the same substrate 5380 as the pixel section 5364. And the circuit 5361, Circuit 5362 is formed on a separate substrate from the pixel section 5364. This way, the mobility is small. The transistors make it possible to construct the circuit formed on the substrate 5380. So, as semiconductor layers in transistors, there are non-single-crystal semiconductors, amorphous semiconductors, and microcrystalline semiconductors. It becomes possible to use organic semiconductors or oxide semiconductors. Therefore, the display device This allows for larger size, reduction of the number of processes, cost reduction, and improvement of yield.

[0248] Furthermore, as shown in Figure 24(C), a part of circuit 5362 (circuit 5362a) is the pixel section 53 It is formed on the same substrate 5380 as 64, and the remaining circuit 5362 (circuit 5362b) is the pixel section 5 It is possible to form it on a different substrate than 364. Circuit 5362a has low mobility Circuits that can be constructed using transistors (e.g., shift registers, selectors, etc.) It often has switches, etc. And circuit 5362b has high mobility and characteristic variation A circuit that is preferably constructed using transistors with low shift resistance (for example, a shift resistance transistor) They often have latch circuits, buffer circuits, DA conversion circuits, AD conversion circuits, etc. By doing so, as in Figure 24(B), the semiconductor layer of the transistor is non-single Using crystalline semiconductors, amorphous semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors, etc. This makes it possible to further reduce the number of external parts.

[0249] Figure 24(D) shows a circuit that has the function of outputting a signal to the pixel unit 5364 (for example, circuit 5 Circuits 362, 5363_1, and 5363_2, etc., and the control of these circuits The functional circuit (for example, circuit 5361) is formed on a separate substrate from the pixel section 5364. This makes it possible to form the pixel section and its peripheral circuits on separate substrates. This can lead to an improvement in yield.

[0250] Furthermore, similar to Figure 24(D), in Figures 24(A) to (C), circuit 5363_1, and The circuit 5363_2 can be formed on a separate substrate from the pixel section 5364.

[0251] In Figure 24(E), a portion of circuit 5361 (circuit 5361a) is on the same substrate as the pixel unit 5364. 5380 is formed, and the remaining circuit 5361 (circuit 5361b) is separate from the pixel section 5364. It is formed on the substrate. Circuit 5361a is composed of transistors with low mobility. If the circuit has the capability to do so (for example, a switch, selector, level shift circuit, etc.) There are many. And circuit 5361b uses transistors with high mobility and low variability. A circuit that is preferably configured in this way (for example, a shift register, a timing generator, etc.) They often have a syrator, regulator, or analog buffer.

[0252] In addition, in Figures 24(A) to (D), circuit 5361a is on the same substrate as the pixel unit 5364. It is possible to form the circuit 5361b on a separate substrate from the pixel section 5364.

[0253] The display device of this embodiment has been described above. Circuits 5363_1 and 5363_2 and Thus, it is possible to use the semiconductor device or shift register of Embodiments 1 to 4. In this case, circuits 5363_1 and 5363_2 and the pixel section are mounted on the same substrate. By doing so, the polarity of all transistors formed on the substrate is changed to an N-channel type Alternatively, a P-channel type can be used. Therefore, the number of processes can be reduced and the yield can be improved. This can improve reliability or reduce costs. In particular, all transistor poles If the transistor is an N-channel type, the semiconductor layer of the transistor can be a non-single-crystal semiconductor, microcrystalline semiconductor. It becomes possible to use crystalline semiconductors, organic semiconductors, or oxide semiconductors. Therefore, the table This allows for larger display devices, reduced costs, and improved yield.

[0254] Furthermore, non-single-crystal semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors are used as semiconductor layers. Transistors used in this way may exhibit characteristic degradation such as an increase in threshold voltage or a decrease in mobility. In many cases, however, the semiconductor device or shift register of Embodiments 1 to 4 is This can suppress the degradation of transistor characteristics, thus extending the lifespan of the display device. can.

[0255] Furthermore, as part of circuit 5362, the semiconductor device of Embodiments 1 to 4, or the Shift A tracer can be used. For example, circuit 5362a is implemented in Embodiment 1. It is possible to have a semiconductor device of form 4, or a shift register.

[0256] (Embodiment 6) In this embodiment, an example of a signal line driving circuit will be described. Note that the signal line driving circuit will be half It can be described as a conductor device or a signal generating circuit.

[0257] An example of a signal line driving circuit will be explained with reference to Figure 25(A). The signal line driving circuit is: Multiple circuits named Circuit 502_1 to 502_N (where N is a natural number), Circuit 500, and Circuit 5 It has 01. And circuits 502_1 to 502_N each have transistor 503_ It has multiple transistors numbered 1 to 503_k (where k is a natural number). Transistor 503 _1~503_k are assumed to be N-channel type. However, they are not limited to this, The transistors 503_1 to 503_k can be P-channel type, and CMOS It can be used as a type of switch.

[0258] The connection relationships of the signal line drive circuit will be explained using circuit 502_1 as an example. Transistor The first terminals of 503_1 to 503_k are connected to wiring 505_1. Transistor 5 The second terminals of 03_1~503_k are connected to wiring S1~Sk, respectively. Transis The gates of terminals 503_1 to 503_k are connected to wirings 504_1 to 504_k, respectively. For example, the first terminal of transistor 503_1 is connected to wiring 505_1, and The second terminal of transistor 503_1 is connected to wiring S1, and the gateway of transistor 503_1 This is connected to wiring 504_1.

[0259] Circuit 500 transmits signals to circuits 502_1~502_ via wiring 504_1~504_k. It has the function of supplying N and can function as a shift register or decoder, etc. This signal is often a digital signal and can function as a selection signal. It is possible. And wiring 504_1~504_k can function as signal lines. be.

[0260] Circuit 501 has the function of outputting signals to circuits 502_1 to 502_N, and the video signal is generated It can function as a circuit, etc. For example, circuit 501 has wiring 505_1 The signal is supplied to circuit 502_1 via wiring 505_2. At the same time, the signal is supplied to circuit 5 It is supplied to 02_2. This signal is often an analog signal and is used as a video signal. It is possible to do so. And wiring 505_1~505_N functions as signal lines. It is possible to do so.

[0261] Circuits 502_1 to 502_N select which wire to output the output signal of circuit 501 to. It has a selection function and can function as a selector circuit. For example, circuit 502 _1 specifies which of the wirings S1 to Sk outputs the signal that circuit 501 outputs to wiring 505_1. It has a function to select whether to output to a specific location.

[0262] Transistors 503_1 to 503_k are connected to wiring 5, respectively, according to the output signal of circuit 500. It has the function of controlling the conductivity state between 05_1 and wiring S1~Sk, and functions as a switch. ru.

[0263] Next, regarding the operation of the signal line drive circuit in Figure 25(A), see the timing chart in Figure 25(B). Refer to Figure 25(B) for explanation. The signal 514_1 input to wiring 504_1 is shown in Figure 25(B). , Signal 514_2 input to wiring 504_2, Signal 514 input to wiring 504_k _k, signal 515_1 input to wiring 505_1, and signal input to wiring 505_2 An example of item 515_2 is shown.

[0264] Furthermore, one operating period of the signal line drive circuit corresponds to one gate selection period in the display device. The gate selection period is when a pixel belonging to a certain row is selected and a video signal is written to that pixel. This refers to the period during which it is possible to do something.

[0265] The gate selection period is divided into periods T0, T1, and so on, up to Tk. This is the period for simultaneously applying a pre-charge voltage to the pixels belonging to the selected row. It can function as a pre-charge period. Periods T1 to Tk can each be selected. This is the period for writing a video signal to the pixels belonging to the row, and is defined as the writing period. It is possible to do so.

[0266] For convenience, the operation of the signal line drive circuit will be explained using the operation of circuit 502_1 as an example.

[0267] First, during period T0, circuit 500 receives a high-level signal from wiring 504_1 to 504_k. This outputs the following: Transistors 503_1~503_k turn on, so wire 505 _1 and wiring S1~Sk become conductive. At this time, circuit 501 is connected to wiring 505_1 Since a precharge voltage Vp is supplied to it, the precharge voltage Vp is, Outputs are sent to wiring S1 to Sk via 03_1 to 503_k. Then, the preset The charge voltage Vp is written to the pixels belonging to the selected row, so the pixels belonging to the selected row The pixels are pre-charged.

[0268] Next, during period T1, circuit 500 outputs a high-level signal to wiring 504_1. Then, transistor 503_1 turns on, and wiring 505_1 and wiring S1 become conductive. This state occurs. Then, wiring 505_1 and wiring S2~Sk become non-conductive. At this time, If circuit 501 outputs signal Data(S1) to wiring 505_1, then signal D ata(S1) is output to wiring S1 via transistor 503_1. The signal Data(S1) is the pixel belonging to the selected row among the pixels connected to wiring S1. It will be written directly.

[0269] Next, during period T2, circuit 500 outputs a high-level signal to wiring 504_2. Then, transistor 503_2 turns on, and wiring 505_2 and wiring S2 become conductive. This is the state in which the wiring 505_1 and wiring S1 become non-conductive, and the wiring 505_1 and Wiring S3 to Sk remains in a non-conductive state. At this time, circuit 501 receives the signal Data( If S2) is output to wiring 505_1, then the signal Data(S2) is the transistor The signal Data(S2) is output to wiring S2 via TA503_2. The data is written to the pixels belonging to the selected row among the pixels connected to line S2.

[0270] Subsequently, until period Tk, circuit 500 sends a high-level signal to wiring 504_1~504_k. Since the output is generated sequentially, the same applies to periods T1 and T2, and also from period T3 to period Tk, circuit 5 00 outputs high-level signals sequentially to wiring 504_3~504_k. Therefore, the transistor Since transistors 503_3 to 503_k are turned on in order, transistors 503_1 to 503_ k is turned on in order. Therefore, the signals output from circuit 501 are in order of wiring S1 to Sk. The output is displayed. In this way, it is possible to sequentially write the signal to the pixels belonging to the selected row. It will become.

[0271] The above describes an example of a signal line drive circuit. The signal line drive circuit of this embodiment is a selector Because it has a circuit that functions as a connector, the number of signals or wires can be reduced. Alternatively, a voltage for pre-charging before writing the video signal to the pixel (period T0) Since it is written to the pixels, the video signal writing time can be shortened. Therefore This allows for larger and higher-resolution display devices. However, it is not limited to this. Furthermore, it is possible to omit the period T0 and not precharge the pixels.

[0272] Furthermore, if k is too large, the writing time to the pixels will be shortened, so the video signal to the pixels The writing process may not complete within the allotted time. Therefore, it is preferable that k ≤ 6. It is more preferable that k ≤ 3. Even more preferable that k = 2. It's nice.

[0273] In particular, when the color elements of a pixel are divided into n (where n is a natural number) parts, it is possible to set k=n. Yes, for example, when the color elements of a pixel are divided into three parts: red (R), green (G), and blue (B). It is possible that k=3. In this case, the 1-gate selection period is period T0, period T1 It is then divided into period T2 and period T3. And in period T1, period T2, and period T3, It is possible to write video signals to the red (R) pixels, green (G) pixels, and blue (B) pixels. However, this is not the only option, and the order of periods T1, T2, and T3 can be set arbitrarily. It is possible to do so.

[0274] In particular, a pixel has n (where n is a natural number) subpixels (hereinafter also called subpixels or secondary pixels). When a pixel is divided into subpixels, it is possible to set k=n. For example, if a pixel is divided into two subpixels If divided, k=2 is possible. In this case, the 1-gate selection period is period T. It is divided into periods 0, T1, and T2. Then, in period T1, one of the two subpixels The video signal is written, and during period T2, the video signal is written to the other of the two subpixels. This is possible.

[0275] Note that the drive frequencies of circuits 500 and 502_1~502_N are often low. Circuits 500 and 502_1 to 502_N are formed on the same substrate as the pixel section. It is possible. In this way, the number of connections between the substrate on which the pixel is formed and the external circuit can be reduced. This allows for improvements in yield and reliability. Furthermore, Figure 2 As shown in 4(C), the scan line driving circuit is also formed on the same substrate as the pixel section, further This reduces the number of connections to external circuits.

[0276] The circuit 500 is a semiconductor device or shift register of Embodiments 1 to 4. It is possible to use this. In this case, the polarity of all transistors in circuit 500 is It can be an N-channel type or a P-channel type. Therefore, the number of processes can be reduced. This can lead to improved yield or reduced costs.

[0277] Furthermore, this applies not only to circuit 500, but also to all transistors in circuits 502_1 to 502_N. The polarity can also be N-channel or P-channel. Therefore, circuit 5 When circuits 00 and 502_1 to 502_N are formed on the same substrate as the pixel section, the number of steps This can lead to reductions in transients, improved yield, or cost reductions. In particular, all transients By making the polarity of the transistor an N-channel type, the semiconductor layer of the transistor is non-single-connected. By using crystalline semiconductors, amorphous semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors, etc. This is possible because the drive frequencies of circuits 500 and 502_1~502_N are Because it is often low.

[0278] (Embodiment 7) In this embodiment, the pixel configuration and pixel operation applicable to the liquid crystal display device are described below. explain.

[0279] Figure 26(A) shows an example of a pixel. Pixel 5420 is composed of transistor 5421 and liquid crystal element. It has 5422 and a capacitive element 5423. And the first terminal of transistor 5421 It is connected to wiring 5431, and the second terminal of transistor 5421 is connected to liquid crystal element 5422 One electrode of the transistor 5421 is connected to one electrode of the capacitor element 5423, and the transistor 5421 is connected to one electrode of the capacitor element 5423. The wire is connected to wiring 5432. The other electrode of liquid crystal element 5422 is connected to electrode 5434. The other electrode of the capacitive element 5423 is connected to the wiring 5433.

[0280] For example, a video signal can be input to wiring 5431. Wiring 543 For example, a scan signal, selection signal, or gate signal can be input to 2. For example, a constant voltage can be supplied to wiring 5433. Electrode 5 For example, a constant voltage can be supplied to the 434. However, this is not limited to this. The video signal is not specified, and a precharge voltage is supplied to wiring 5431. It is possible to shorten the writing time. Alternatively, a signal is input to wiring 5433. This makes it possible to control the voltage applied to the liquid crystal element 5422. By inputting a signal to electrode 5434, frame inversion drive can be achieved. It is Noh.

[0281] Wiring 5431 can function as a signal line, video signal line, or source line. Wiring 5432 can function as a signal line, scan line, or gate line. The wiring 5433 can function as a power line or a capacitance line. Electrode 543 4 can function as a common electrode or a counter electrode. However, it is not limited to this. If voltage is supplied to wiring 5431 and wiring 5432, these wirings are power lines. It can function as follows: Alternatively, if a signal is input to wiring 5433, wiring 5433 can function as a signal line.

[0282] Transistor 5421 determines the conductivity between wiring 5431 and one electrode of liquid crystal element 5422. By controlling it, it has the function of controlling the timing of writing the video signal to the pixel. It can function as a switch. Capacitive element 5423 is one of the liquid crystal elements 5422. The potential difference between the electrode and the wiring 5433 is maintained, and the voltage applied to the liquid crystal element 5422 is maintained. It has the function of maintaining a constant value and functions as a holding capacity. However, it is not limited to this.

[0283] Figure 26(B) shows one of the timing charts used to explain the operation of the pixels in Figure 26(A). An example is shown. Figure 26(B) shows the signal 5442_j (where j is a natural number) and the signal 5442_j+1 This shows signal 5441_i (where i is a natural number), signal 5441_i+1, and voltage 5442. Figure 26(B) shows the k-th (where k is a natural number) frame and the k+1 frame. Note that signals 5442_j, ​​5442_j+1, 5441_i, and 5441_i +1 and voltage 5442 are signals input to wiring 5432 on line j, respectively, line j+1 The signal input to wiring 5432, the signal input to wiring 5431 in the i-th column, i+1th column This is an example of the signal input to wiring 5431 and the voltage supplied to wiring 5432.

[0284] The operation of pixel 5420, located at row j and column i, is described below. The signal 5442_j is at the H level. When this happens, transistor 5421 turns on. Therefore, the i-th row wiring 5431 and the liquid crystal element Since one electrode of 5422 becomes conductive, the signal 5441_j is transmitted to transistor 542 It is input to one electrode of the liquid crystal element 5422 via 1. Then, the capacitive element 5423, At this time, maintain the potential difference between the potential of one electrode of the liquid crystal element 5422 and the potential of the wiring 5433. Therefore, until the signal 5442_j reaches a high level again, the liquid crystal element 542 The voltage applied to 2 remains constant. Then, the liquid crystal element 5422 responds to the applied voltage. It expresses gradations of tone.

[0285] Note that in Figure 26(B), positive and negative polarity signals are alternately distributed for each row selection period. An example of what happens when input to line 5431 is shown. A positive polarity signal is one in which the potential is equal to the reference value (for example). A signal higher than the potential of electrode 5434 is a negative polarity signal, where the potential is higher than the reference value. This refers to a signal lower than (for example, the potential of electrode 5434). However, it is not limited to this. The signal input to wiring 5431 can have the same polarity for the duration of one frame. ru.

[0286] Note that Figure 26(B) shows the polarity of signal 5441_i and the polarity of signal 5441_i+1. An example of a case where they are different is shown. However, it is not limited to this, and the polarity of signal 5441_i and The polarity of signal 5441_i+1 can be the same.

[0287] Figure 26(B) shows the period during which signal 5442_j is at the H level, and the signal 5442_j This example shows a case where the period when +1 is at the H level does not overlap. However, this is not the only example. Furthermore, as shown in Figure 26(C), there is a period during which signal 5442_j is at an H level, and signal 54 The period during which 42_j+1 is at the H level can overlap. In this case, wiring 543 It is preferable that the same polarity signal is supplied to 1 for the duration of one frame. The signal 5441_j, which is written to the j-th row pixel, is used to write the j+1-th row pixel. It can be pre-charged. This shortens the time it takes to write the video signal to the pixels. This is possible. Therefore, the display device can be made high-resolution. Or, the display device's display The display area can be enlarged. Alternatively, the same wiring 5431 can be used for one frame period. Since a polarity signal is input, power consumption can be reduced.

[0288] Furthermore, the pixel configuration in Figure 27(A) and the timing chart in Figure 26(C) are combined. This enables dot inversion driving. In the pixel configuration shown in Figure 27(A), Pixel 5420(i, j) is connected to wiring 5431_i. On the other hand, pixel 5420(i, j+1) is connected to wiring 5431_i+1. In other words, the pixels belonging to the i-th column are in row 1. The wires are connected alternately, one at a time, to wire 5431_i and the other to wire 5431_i+1. In this way, the i-th row The pixels belonging to the eye are written with alternating positive and negative polarity signals, one row at a time. This enables dot inversion driving. However, it is not limited to this, and also applies to the i-th column. The pixels are arranged alternately in multiple rows (for example, 2 or 3 rows) with wiring 5431_i and wiring 5431 It is possible to connect it to _i+1.

[0289] Furthermore, a subpixel structure can be used as the pixel configuration. Figure 27(B) Figure (C) shows the configuration when a pixel is divided into two subpixels. And Figure 27( Figure B) shows a subpixel structure called 1S+2G, and Figure 27(C) shows 2S+1 It shows a subpixel structure called G. Subpixels 5420A and 5420B are It corresponds to pixel 5420. Transistors 5421A and 5421B are transistors It corresponds to the 5421. Liquid crystal elements 5422A and 5422B are liquid crystal elements Corresponds to 5422. Capacitive elements 5423A and 5423B are the same as capacitive element 5423 Corresponds to. Wiring 5431A and Wiring 5431B correspond to Wiring 5431. Wiring 54 Wiring 32A and 5432B correspond to wiring 5432.

[0290] The pixel configuration and pixel driving method of this embodiment have been described above. Pixels and semiconductor devices, shift registers, display devices, or signals of Embodiments 1 to 6 By combining it with a linear drive circuit, various advantages can be obtained. For example If a subpixel structure is used as the pixel, the signal required to drive the display device The number of these increases. As a result, the number of gate lines or source lines increases. As a result, the number of connections between the substrate on which the pixel area is formed and the external circuitry can increase significantly. However, even if the number of gate lines increases, as shown in Embodiment 5, the scanning line driving circuit can be moved to the pixels It is possible to form the pixel portion on the same substrate as the outer portion. Therefore, the substrate on which the pixel portion is formed and the outer portion It is possible to use pixels with a subpixel structure without significantly increasing the number of connections to the subcircuit. Alternatively, even if the number of source lines increases, the signal line driving circuit of Embodiment 6 can be based on the same base as the pixel section. It is possible to form it on a plate. Therefore, the substrate on which the pixel portion is formed and the external circuit It is possible to use pixels with a subpixel structure without significantly increasing the number of connections.

[0291] Alternatively, when inputting a signal to a capacitance line, the number of connections between the substrate on which the pixel is formed and the external circuit In some cases, the capacitance can increase significantly. Therefore, the capacitance line is half of the capacitance lines of Embodiments 1 to 4. It is possible to supply signals using a conductor device or a shift register. The semiconductor device or shift register of Embodiments 1 to 4 is formed on the same substrate as the pixel portion. Therefore, it is possible to significantly reduce the number of connections between the substrate on which the pixel portion is formed and the external circuit. The signal can be input to the capacitance line without increasing the capacitance.

[0292] Alternatively, if AC drive is used, the time required to write the video signal to the pixels becomes shorter. As a result, there may be insufficient time to write the video signal to the pixels. Similarly, when using pixels with a subpixel structure, the time required to write the video signal to the pixels is short. This can result in insufficient time to write the video signal to the pixels. Therefore, using the signal line driving circuit of Embodiment 6, it is possible to write a video signal to the pixels. It is possible. In this case, before writing the video signal to the pixel, a pre-charge voltage is applied to the pixel. Since it writes the signal, the video signal can be written to the pixels in a short amount of time. Or, see Figure 21. As shown in (B), the period during which one row is selected and the period during which another row is selected overlap. This makes it possible to use the video signal from another line as the voltage for precharging. .

[0293] (Embodiment 8) In this embodiment, an example of the cross-sectional structure of the display device is shown in Figures 29(A), (B), and ( Refer to C) for further explanation.

[0294] Figure 29(A) is an example of a top view of a display device. A drive circuit 5392 and A pixel section 5393 is formed. An example of a drive circuit 5392 is a scan line drive circuit , or signal line drive circuits, etc.

[0295] Figure 29(B) shows an example of the AB section of Figure 29(A). And in Figure 29(B) , a substrate 5400, a conductive layer 5401 formed on the substrate 5400, and the conductive layer 5401 An insulating layer 5402 is formed to cover the conductive layer 5401 and the insulating layer 5402. A semiconductor layer 5403a is formed, and a semiconductor layer 5403b is formed on top of the semiconductor layer 5403a. Furthermore, a conductive layer 5404 is formed on the semiconductor layer 5403b and the insulating layer 5402, and An insulating layer 5405 having an opening is formed on the edge layer 5402 and the conductive layer 5404. , a conductive layer 5406 formed on the insulating layer 5405 and in the openings of the insulating layer 5405, and insulation An insulating layer 5408 is placed on top of layer 5405 and on top of the conductive layer 5406, and insulating layer 5405 A liquid crystal layer 5407 formed on top of the liquid crystal layer 5407 and an insulating layer 5408 formed on top of the liquid crystal layer 5407 The conductive layer 5409 and the substrate 5410 formed on the conductive layer 5409 are shown.

[0296] The conductive layer 5401 can function as a gate electrode. The insulating layer 5402 is a gate electrode. It can function as a conductive insulating film. The conductive layer 5404 is used for wiring and transistors. It can function as an electrode, or an electrode of a capacitive element. The insulating layer 5405 is a layer It can function as an interlayer or planarization layer. The conductive layer 5406 is used for wiring, pixel electricity It can function as a pole or a reflector electrode. The insulating layer 5408 is a sealing material. It is possible for it to function. The conductive layer 5409 can function as a counter electrode or a common electrode. It is possible.

[0297] In this case, parasitic capacitance may occur between the drive circuit 5392 and the conductive layer 5409. As a result, the output signal of the drive circuit 5392 or the potential of each node may have a smudge or delay. This can happen. Or, power consumption will increase. However, as shown in Figure 29(B)... Furthermore, an insulating layer 5408 capable of functioning as a sealant is placed on top of the drive circuit 5392. By forming this, the parasitic capacitance that occurs between the drive circuit 5392 and the conductive layer 5409 is eliminated. This can be reduced because the dielectric constant of the sealing material is lower than that of the liquid crystal layer. This is because there are many of them. Therefore, the output signal of the drive circuit 5392 or the raw potential of each node This can reduce the delay or power consumption of the drive circuit 5392. It is possible.

[0298] Furthermore, as shown in Figure 29(C), a portion of the drive circuit 5392 is placed on top of it, functioning as a sealing material. It is possible to form an insulating layer 5408 that allows for this. This makes it possible to reduce the parasitic capacitance that occurs between the drive circuit 5392 and the conductive layer 5409. Therefore, the output signal of the drive circuit 5392 or the potential of each node can be reduced. Yes, it is possible. However, it is not limited to this, and on the drive circuit 5392, a material that functions as a sealant can be used. It is possible that an insulating layer 5408 is not formed.

[0299] Furthermore, the display element is not limited to liquid crystal elements, but can include various other elements such as EL elements or electrophoretic elements. It is possible to use indicative elements.

[0300] In this embodiment, an example of the cross-sectional structure of the display device has been described. This involves combining the semiconductor device or shift register of Embodiments 1 to 4. This is possible. For example, non-single-crystal semiconductors and amorphous semiconductors can be used as semiconductor layers in transistors. When using microcrystalline semiconductors, organic semiconductors, or oxide semiconductors, the transistor's chat The panel width is often large. However, as in this embodiment, the parasitic capacitance of the drive circuit is If it can be made smaller, the channel width of the transistor can be reduced. Therefore, Layer Since the footprint can be reduced, the display device can have a narrow bezel. This allows for high-definition display devices.

[0301] (Embodiment 9) In this embodiment, an example of the transistor structure is shown in Figures 30(A), (B), and (C). (See the references below for further explanation.)

[0302] Figure 30(A) shows an example of the configuration of a top-gate type transistor. Figure 30(B) shows... This is an example of the configuration of a bottom-gate type transistor. Figure 30(C) shows a semiconductor substrate. This is an example of the structure of a transistor that is manufactured using this method.

[0303] Figure 30(A) shows a substrate 5260 and an insulating layer 5261 formed on the substrate 5260, Formed on the insulating layer 5261, region 5262a, region 5262b, region 5262c, A semiconductor layer 5262 having regions 5262d and 5262e, and a covering for the semiconductor layer 5262 An insulating layer 5263 is formed in such a manner, and a semiconductor layer 5262 and an insulating layer 5263 are formed on top of the insulating layer 5263. A conductive layer 5264 and an insulating layer 5263 and a conductive layer 5264 are formed on top of the conductive layer 5264 and have openings. An insulating layer 5265 and conductive material formed on the insulating layer 5265 and in the openings of the insulating layer 5265. A layer 5266 and a conductive layer 5266 and an insulating layer 5265 formed on top of the conductive layer 5266 and having an opening An insulating layer 5267 and a conductive layer formed on the insulating layer 5267 and in the openings of the insulating layer 5267. 5268 and an insulating layer 5267 and a conductive layer 5268 formed on top of the conductive layer 5268, having an opening Edge layer 5269 and light-emitting layer 5 formed on top of the insulating layer 5269 and in the opening of the insulating layer 5269 270 and the conductive layer 5271 formed on the insulating layer 5269 and the light-emitting layer 5270 show.

[0304] Figure 30(B) shows a substrate 5300 and a conductive layer 5301 formed on the substrate 5300. An insulating layer 5302 is formed to cover the conductive layer 5301, and the conductive layer 5301 and the insulating layer 5 A semiconductor layer 5303a formed on 302, and a semiconductor layer formed on semiconductor layer 5303a Conductive layer 5303b and conductive layer formed on semiconductor layer 5303b and insulating layer 5302 Layer 5304 and an insulating layer 5302 and an insulating layer 5304 formed on top of the conductive layer 5304, having an opening Edge layer 5305 and conductive layer 5 formed on the insulating layer 5305 and in the openings of the insulating layer 5305 306, and a liquid crystal layer 5307 disposed on the insulating layer 5305 and the conductive layer 5306, This shows a conductive layer 5308 formed on top of the liquid crystal layer 5307.

[0305] Figure 30(C) shows a semiconductor substrate 5352 having regions 5353 and 5355, and a semiconductor An insulating layer 5356 formed on the substrate 5352, and a semiconductor substrate 5352 formed on the semiconductor substrate 5352 An insulating layer 5354, a conductive layer 5357 formed on the insulating layer 5356, and an insulating layer 535 4. An insulating layer 535 having an opening, formed on the insulating layer 5356 and the conductive layer 5357. 8 and the conductive layer 5359 formed on the insulating layer 5358 and in the opening of the insulating layer 5358 This is shown. In this way, transistors are fabricated in region 5350 and region 5351, respectively.

[0306] The insulating layer 5261 can function as an undercoat. The insulating layer 5354 is between elements. It functions as a separation layer (e.g., a field oxide film). Insulating layer 5263, insulating layer 5302, The insulating layer 5356 can function as a gate insulating film. The conductive layer 5264, The electrode layer 5301 and the conductive layer 5357 can function as gate electrodes. Insulating layer 5265, insulating layer 5267, insulating layer 5305, and insulating layer 5358 are interlayer films or flat It can function as a film. Conductive layer 5266, conductive layer 5304, and conductive layer 5 359 can function as wiring, a transistor electrode, or a capacitive element electrode, etc. It is possible. The conductive layer 5268 and the conductive layer 5306 are used as pixel electrodes or reflective electrodes, etc. It is possible for it to function. The insulating layer 5269 can function as a dam. The conductive layer 5271 and the conductive layer 5308 function as counter electrodes or common electrodes, etc. This is possible.

[0307] Examples of substrates 5260 and 5300 include glass substrates, quartz substrates, and silicon substrates. (or single crystal substrate), SOI substrate, plastic substrate, metal substrate, stainless steel substrate, ste Substrates having stainless steel foil, tungsten substrates, and tungsten foil Examples include rigid substrates or flexible substrates. An example of a glass substrate is barium borosilicate glass. Examples include glass and aluminoborosilicate glass. An example of a flexible substrate is polyethylene. Reflatate (PET), polyethylene naphthalate (PEN), polyethersulfate Plastics such as PES, or flexible synthetic resins such as acrylic, etc. There are also laminated films (polypropylene, polyester, vinyl, polyf Paper containing fibrous materials (such as polyvinyl chloride, polyvinyl chloride, etc.), base film (polyester, Examples include polyamides, inorganic vapor-deposited films, and paper products.

[0308] As an example of the semiconductor substrate 5352, a single crystal Si group having n-type or p-type conductivity A board can be used. However, it is not limited to this, and a board similar to the circuit board 5260 can be used. It can be used. Region 5353 is, for example, a semiconductor substrate 5352 with impurities. This is an added region that functions as a well. For example, if the semiconductor substrate 5352 is p-type If it has an electrical type, region 5353 has an n-type conductivity and functions as an n-well. On the other hand, if the semiconductor substrate 5352 has an n-type conductivity, then region 5353 has a p-type conductivity. It has and functions as a p-well. Region 5355 is, for example, a semiconductor substrate 5 This is a region added to 352 and functions as either a source region or a drain region. It is possible to form an LDD region on the conductive substrate 5352.

[0309] Examples of insulating layer 5261 include silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxide. Acids such as silicon dioxide (SiOxNy) (x>y) and silicon nitride (SiNxOy) (x>y) This includes films containing elemental or nitrogen, or laminated structures thereof. The insulating layer 5261 has a two-layer structure. One example of a structure that can be provided is a silicon nitride film as the first insulating layer, and the second layer A silicon oxide film can be provided as an insulating film. The insulating layer 5261 is provided in a three-layer structure. One example of this is when a silicon oxide film is provided as the first insulating layer, and the second insulating layer is It is possible to provide a silicon nitride film and a silicon oxide film as a third insulating layer.

[0310] Examples of semiconductor layers 5262, 5303a, and 5303b include non-single Crystalline semiconductors (amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.) , single crystal semiconductors, compound semiconductors or oxide semiconductors (ZnO, InGaZnO, SiG e, GaAs, IZO, ITO, SnO, TiO, AlZnSnO(AZTO)), organic Examples include semiconductors and carbon nanotubes.

[0311] For example, region 5262a is an intrinsic region where no impurities are added to the semiconductor layer 5262. This state functions as a channel region. However, if a trace amount of impurity is added to region 5262a... It is possible to add impurities to region 5262a, region 5262b, region Lower than the concentration of impurities added to region 5262c, region 5262d, or region 5262e This is preferable. Regions 5262b and 5262d are areas to which impurities are added at low concentrations. This is a domain, and as an LDD (Lightly Doped Drain) domain, it is a machine It is possible. However, areas 5262b and 5262d can be omitted. Regions 5262c and 5262e are areas where impurities are added to the semiconductor layer 5262 at high concentrations. It is a region that functions as either a source region or a drain region.

[0312] Furthermore, semiconductor layer 5303b is a semiconductor layer to which phosphorus and other impurity elements are added. It has an n-type conductivity.

[0313] Furthermore, when an oxide semiconductor or a compound semiconductor is used as the semiconductor layer 5303a, The semiconductor layer 5303b can be omitted.

[0314] Examples of insulating layers 5263, 5302, and 5356 include silicon dioxide (Si Silicon nitride (Ox), silicon nitride (SiNx), silicon oxide nitride (SiOxNy) (x>y), silicon nitride oxide A film containing oxygen or nitrogen, such as (SiNxOy)(x>y), or a laminated structure thereof. There are structures, etc.

[0315] Conductive layer 5264, conductive layer 5266, conductive layer 5268, conductive layer 5271, conductive layer 5301, Conductive layer 5304, conductive layer 5306, conductive layer 5308, conductive layer 5357, and conductive layer 535 Examples of 9 include single-layer conductive films, or multilayer structures thereof. Examples include aluminum (Al), tantalum (Ta), titanium (Ti), and molybdenum. (Mo), Tungsten (W), Neodymium (Nd), Chromium (Cr), Nickel (Ni) Platinum (Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt ( Co), niobium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon ( C), scandium (Sc), zinc (Zn), phosphorus (P), boron (B), arsenic (As) Gallium (Ga), indium (In), tin (Sn), oxygen (O), zirconium (Z) r) A single element film selected from the group composed of cerium (Ce), or Examples of such compounds include those containing one or more elements selected from the aforementioned group. Therefore, an alloy containing one or more elements selected from the above group (indium tin oxide (I TO), indium zinc oxide (IZO), silicon oxide-containing indium tin oxide (ITS) O), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminum Odymium (Al-Nd), aluminum tungsten (Al-Ta), aluminum zirconium (Al -Zr), aluminum titanium (Al-Ti), aluminum cerium (Al-Ce), magnesium Silver (Mg-Ag), Molybdenum niobium (Mo-Nb), Molybdenum tungsten (Mo- W), alloy materials such as molybdenum tantalum (Mo-Ta), one selected from the above group or compounds of multiple elements with nitrogen (such as titanium nitride, tantalum nitride, molybdenum nitride, etc.) Nitride film), or a compound of silicon with one or more elements selected from the group (nitride film) Sten silicide, titanium silicide, nickel silicide, aluminum silicon, molybdenum Examples include silicide films such as butene silicon. Other examples include carbon nanotubes and organic There are nanotube materials such as nanotubes, inorganic nanotubes, or metallic nanotubes. .

[0316] Furthermore, silicon (Si) contains n-type impurities (such as phosphorus) or p-type impurities (such as boron). It is possible to include it.

[0317] Furthermore, when copper is used as a conductive layer, a laminated structure is used to improve adhesion. It is preferable.

[0318] Furthermore, molybdenum or titanium may be used as the conductive layer in contact with the oxide semiconductor or silicon. It is preferable to use it.

[0319] Furthermore, by using an alloy material of neodymium and aluminum as the conductive layer, aluminum This makes it less likely for nium to cause hillocks.

[0320] Furthermore, when using semiconductor materials such as silicon as the conductive layer, the semiconductor material such as silicon It is possible to form the material simultaneously with the semiconductor layer of the transistor.

[0321] Note that ITO, IZO, ITSO, ZnO, Si, SnO, CTO, or carbon nanochips are also used. Tubes and similar materials are translucent, so these materials can be used as pixel electrodes, counter electrodes, or common electrodes. It can be used in light-transmitting parts such as electrodes.

[0322] Furthermore, by using low-resistance materials (such as aluminum) to create a laminated structure, The resistance of the wire can be reduced.

[0323] Furthermore, low heat-resistant materials (e.g., aluminum) are used with high heat-resistant materials (e.g., molybdenum By creating a laminated structure sandwiched between materials (such as titanium and neodymium), low heat-resistant materials can be produced. While taking advantage of its benefits, it is possible to increase the heat resistance of wiring, electrodes, etc.

[0324] Furthermore, materials that react with other materials and change their properties are referred to as materials that do not react easily with those other materials. It is possible to sandwich or cover them depending on the material. For example, ITO and aluminum When connecting ITO and aluminum, neodymium alloy, titanium, molybdenum It is possible to insert things like [this]. For example, when connecting silicon and aluminum, Neodymium alloy, titanium, and molybdenum can be sandwiched between silicon and aluminum. It is Noh. These materials are also used in wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, etc. It is possible to do so.

[0325] Insulating layer 5265, insulating layer 5267, insulating layer 5269, insulating layer 5305, and insulating layer 535 Examples of 8 include single-layer insulating films, or multilayer structures thereof. For example, silicon dioxide (SiOx), silicon nitride (SiNx), or silicon oxide nitride ( Oxygen or silicon dioxide (SiNxOy) (x>y), silicon nitride (SiNxOy) (x>y), etc. Nitrogen-containing membranes, carbon-containing membranes such as DLC (diamond-like carbon), or siloxane Sun resin, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclob Examples include resin or organic materials such as acrylic.

[0326] Examples of the light-emitting layer 5270 include organic EL elements and inorganic EL elements. Examples of elements include a hole injection layer made of a hole injection material and a hole transport layer made of a hole transport material. A layer consisting of a light-emitting layer made of a light-emitting material, an electron transport layer made of an electron transport material, and an electron injection material An electron injection layer, or a single-layer structure of a layer made by mixing multiple of these materials, or These include layered structures.

[0327] Furthermore, an insulating layer that functions as an alignment film is placed on top of the insulating layer 5305 and on top of the conductive layer 5306. It is possible to form insulating layers and other structures that function as protrusions.

[0328] Furthermore, on top of the conductive layer 5308, there are color filters, black matrices, or protrusions. It is possible to form insulating layers and the like that which function as conductive layers. Below the conductive layer 5308, there is an alignment film and It is possible to form an insulating layer that functions in this way.

[0329] In the cross-sectional structure shown in Figure 30(A), the insulating layer 5269, the light-emitting layer 5270, and the conductive layer Omitting 5271, the liquid crystal layer 5307 and conductive layer 5308 shown in Figure 30(B) are replaced with the insulating layer 526 It is possible to form it on 7 and on the conductive layer 5268.

[0330] Note that in the cross-sectional structure of Figure 30(B), the liquid crystal layer 5307 and the conductive layer 5308 are omitted, and the figure The insulating layer 5269, the light-emitting layer 5270, and the conductive layer 5271 shown in 30(A) are insulated with insulating layer 530 It is possible to form it on 5 and on the conductive layer 5306.

[0331] Furthermore, in the cross-sectional structure of Figure 30(C), on top of the insulating layer 5358 and the conductive layer 5359, Form the insulating layer 5269, the light-emitting layer 5270, and the conductive layer 5271 shown in 30(A). This is possible. Alternatively, the liquid crystal layer 5307 and conductive layer 5308 shown in Figure 30(B) can be used as an insulating layer. It is possible to form it on 5267 and on the conductive layer 5268.

[0332] In this embodiment, an example of transistor structure has been described. The transistor can be applied to embodiments 1 to 8. In particular, Figure 3 In 0(B), the semiconductor layer is a non-single-crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, or When using oxide semiconductors, the transistor may degrade. However, in practice In the semiconductor device, shift register, or display device of Embodiments 1 to 8, the transition This is advantageous because it can suppress the deterioration of the stamina.

[0333] (Embodiment 10) In this embodiment, the layout diagram of the shift register (hereinafter also referred to as the top view) will be described. To clarify, in this embodiment, as an example, the shift register layer described in Embodiment 4 The diagram will now be explained. Note that the contents described in this embodiment are described in Embodiment 4. In addition to the shift register described, the semiconductor devices and shift registers of Embodiments 1 to 9 are also mentioned. It can be applied to a station or display device. The layout diagram of this embodiment is This is just one example, and not an exhaustive list.

[0334] The layout diagram of this embodiment will be described with reference to Figures 31 and 32. Figure 31 Figure 32 shows an example of a layout diagram of a shift register, and as an example, The layout diagram for the lipflop 401_i is shown.

[0335] The transistors or wiring shown in Figures 31 and 32 consist of a conductive layer 601 and a semiconductor layer 60 2. It is composed of a conductive layer 603, a conductive layer 604, and a contact hole 605. Furthermore, this is not limited to the formation of a new conductive layer, insulating film, or contact hole. It is possible to do so. For example, a contactor for connecting conductive layer 601 and conductive layer 603 It is possible to add new Kutohall.

[0336] The conductive layer 601 may include portions that function as gate electrodes or wiring. The conductive layer 602 may include a portion that functions as a semiconductor layer of the transistor. The conductive layer 603 may include portions that function as wiring, sources, or drains. The conductive layer 604 may include portions that function as transparent electrodes, pixel electrodes, or wiring. It is possible. The contact hole 605 has the function of connecting the conductive layer 601 and the conductive layer 604. Alternatively, it has the function of connecting conductive layer 603 and conductive layer 604.

[0337] In the example shown in Figure 31, wiring 412 has an opening 611, and wiring 413 has an opening 612 It has. In this way, the wiring 412 and wiring 413 have openings, parasitic The capacitance can be reduced. Alternatively, the destruction of transistors caused by electrostatic discharge can be prevented. It can be suppressed. However, it is not limited to this, and the same applies to the opening 611 as to the wiring 416. Alternatively, the opening 612 can be omitted. Or, the wiring 416 can be connected to the wiring 412 or Similar to wiring 413, it is possible to provide an opening for this.

[0338] In the example shown in Figure 31, there is an opening in part of the intersection of wiring 412 or wiring 413 with another wiring. By providing this, the crossover capacitance of the wiring can be reduced. Therefore, noise This can reduce signal delay or distortion.

[0339] In the example shown in Figure 31, a conductive layer 604 is formed on a portion of the conductive layer 603 of the wiring 416. This is achieved. And the conductive layer 604 is connected to the conductive layer 6 through the contact hole 605. It is connected to 03. In this way, the wiring resistance can be reduced, thus reducing the voltage drop. or it may be possible to reduce signal delay or distortion. However, this is not limited to the above. The conductive layer 604 and the contact hole 605 can be omitted. Similarly to wiring 416, in wiring 412 or wiring 413, a portion of the conductive layer 603 A conductive layer 604 is formed on top, and the conductive layer 604 is connected to the conductive layer 603. It is possible.

[0340] Here, in the example shown in Figure 31, the wiring width of wiring 412, the wiring width of wiring 413, and wiring 4 The 16 wiring widths are indicated as wiring width 621, wiring width 622, and width 623, respectively. And the opening The width of 611, the length of opening 611, the width of opening 612, and the length of opening 612, respectively It is indicated as having a width of 624, a length of 625, a width of 626, and a length of 627.

[0341] The signals input to wiring 412 and wiring 413 are often inverted signals of each other. Therefore, the wiring resistance or parasitic capacitance of wiring 412 is equal to the wiring resistance or parasitic capacitance of wiring 413. It is preferable to set it to be approximately equal to the above. Therefore, the wiring 412 is It is preferable to include a portion that is approximately equal to the line width 622. Alternatively, the opening 611 is an opening The portion may include a portion that is approximately equal to the width 626 of part 612, or the length 627 of the opening 612. Preferred. However, it is not limited to the wiring width 621, wiring width 622, and the width of the opening 611. 624, width of opening 611 624, length of opening 611 625, or length of opening 612 627 can be set to various values. For example, the intersection of wire 412 and other wires. Assume that the difference capacitance is greater than the crossover capacitance between wiring 413 and other wiring. In this case, wiring 41 By reducing the resistance of wiring 2, the signals input to wiring 412 and wiring 413 are reduced. It is possible to set the delay or saturation to be roughly equal. For this purpose, The wiring 412 may include portions larger than the wiring width 622, or openings. 611 may include a portion smaller than the width 626 of the opening 612. Or, The opening 611 may include a portion shorter than the length 627 of the opening 612. On the other hand, the crossover capacitance between wiring 412 and other wiring is smaller than the crossover capacitance between wiring 413 and other wiring. In that case, wiring 412 may include portions smaller than the wiring width 622. Alternatively, the opening 611 may include a portion larger than the width 626 of the opening 612. Alternatively, the opening 611 may include a portion longer than the length 627 of the opening 612. It is Noh.

[0342] If the wiring 416 does not have an opening, the wiring 416 has a wiring width of 621 or a wiring width of 62 It is preferable to include a portion smaller than 2, because the wiring 416 does not have an opening. Therefore, the wiring resistance of wiring 416 is small. However, this is not limited to wiring 4 16 may include portions larger than the wiring width 621 or 622.

[0343] In the example shown in Figure 32, transistors 101, 102, 103, Transistor 201, Transistor 202, Transistor 203, Transistor 204, Transistor 301, transistor 302, transistor 303, transistor 304, and or, in transistor 305, the conductive layer 601 and conductive layer 603 of the second terminal The overlapping area is smaller than the overlapping area of ​​the conductive layer 601 and conductive layer 603 of the first terminal. This is preferable. By doing so, the gate of transistor 101, or wiring 401_ This can reduce the noise at i. Alternatively, it can suppress the concentration of the electric field at the second terminal. This allows for the suppression of transistor degradation or even transistor destruction. .

[0344] The above describes an example of a shift register layout diagram. However, as already mentioned, The layout diagram of this embodiment is an example and is not limited thereto.

[0345] Furthermore, a semiconductor layer 602 is formed in the portion where the conductive layer 601 and the conductive layer 603 overlap. This is possible. By doing so, the parasitic capacitance between the conductive layer 601 and the conductive layer 603 can be reduced. Because it can be made smaller, noise can be reduced. For the same reason, conductive layer A semiconductor layer 602 or a conductive layer 603 is formed in the portion where 601 and the conductive layer 604 overlap. It is possible.

[0346] Furthermore, a conductive layer 604 is formed on a part of the conductive layer 601, and the conductive layer 601 is contact It is possible to connect to the conductive layer 604 via the tohole 605. This can reduce the wiring resistance. Alternatively, a conductive layer 603 can be placed on top of a portion of the conductive layer 601. , and a conductive layer 604 is formed, and the conductive layer 601 is contacted via the contact hole 605 The conductive layer 603 is connected to the conductive layer 604, and the conductive layer 603 is connected via another contact hole 605. It is possible to connect to the conductive layer 604. By doing so, the wiring resistance is reduced. It can be lowered further.

[0347] Furthermore, a conductive layer 604 is formed on a part of the conductive layer 603, and the conductive layer 603 is contact It is possible to connect to the conductive layer 604 via the tohole 605. This can reduce wiring resistance.

[0348] Furthermore, a conductive layer 601 or a conductive layer 603 is formed beneath a portion of the conductive layer 604, and the conductive layer 604, through the contact hole 605, connects to the conductive layer 601 or the conductive layer 603 It is possible to connect them in this way. By doing so, the wiring resistance can be reduced. .

[0349] As described in Embodiment 1, between the gate and the first terminal of transistor 101 The parasitic capacitance between the gate and the second terminal of transistor 101 is made larger than the parasitic capacitance. It is possible to do so. As shown in Figure 32, it functions as the first electrode of transistor 101. The width of the conductive layer 603, which allows for this, is shown as width 631, and the second electrode of the transistor 101 The width of the conductive layer 603 capable of functioning as such is indicated as width 632. And the width 631 is, It is possible to have a width greater than 632. By doing so, as described in Embodiment 1... Thus, the parasitic capacitance between the gate and the first terminal of transistor 101 is greater than the transistor It is possible to increase the parasitic capacitance between the gate of TA101 and the second terminal. However, This is not limited to this.

[0350] (Embodiment 11) In this embodiment, an example of an electronic device will be described.

[0351] Figures 33(A) to 33(H) and 34(A) to 34(D) are diagrams showing electronic devices. Yes, these electronic devices consist of a casing 5000, a display unit 5001, a speaker 5003, and an LED. Lamp 5004, operation key 5005 (including operation switch or power switch), connection terminal Child 5006, Sensor 5007 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power, radiation, (Including functions for measuring flow rate, humidity, gradient, vibration, odor, or infrared radiation), Microphone It can have n5008, etc.

[0352] Figure 33(A) shows a mobile computer, and in addition to the above, it includes switch 5009, It may have an infrared port 5010, etc. Figure 33(B) shows a portable device equipped with a recording medium. This is a type of image playback device (for example, a DVD player), and in addition to the above, a second display It may have a section 5002, a recording medium reading section 5011, etc. Figure 33(C) is a goggle. It is a type display, and in addition to the above, it has a second display unit 5002, a support unit 5012, It may have earphones 5013, etc. Figure 33(D) is a portable gaming machine, as described above. In addition to the above, it may also have a recording medium reading unit 5011, etc. Figure 33(E) It is a projector and, in addition to the above-mentioned components, includes a light source 5033, a projection lens 5034, etc. This is possible. Figure 33(F) is a portable gaming machine, and in addition to the above, a second display unit It may have 5002, a recording medium reading unit 5011, etc. Figure 33(G) is a television receiver. It is an image device, and in addition to the above-mentioned components, it may also have a tuner, an image processing unit, etc. (Figure) 33(H) is a portable television receiver, and in addition to the above, it is capable of transmitting and receiving signals. It may have a charger 5017, etc. Figure 34(A) is a display, and the above In addition to the above, it may have a support base 5018, etc. Figure 34(B) is a camera. In addition to the above, there is an external connection port 5019, a shutter button 5015, and an image receiving unit. 5016, etc. may be included. Figure 34(C) is a computer, as described above. In addition, there is a pointing device 5020, an external connection port 5019, and a reader / writer 5 021, etc. may be included. Figure 34(D) is a mobile phone, and in addition to the above, Antenna 5014, for 1-segment partial reception service for mobile phones and mobile terminals. It may have, etc.

[0353] The electronic devices shown in Figures 33(A) to 33(H) and Figures 34(A) to 34(D) are various It can have various functions. For example, various types of information (still images, videos, text images, etc.) Functions that display information on the display unit, touch panel function, calendar, date or time display, etc. Functions, functions that control processing through various software (programs), wireless communication functions, The ability to connect to various computer networks using wireless communication functions, and wireless communication functions Functions that use to transmit or receive various data, programs recorded on recording media, or It can have functions such as reading data and displaying it on the display unit. Furthermore, multiple In electronic devices having a display unit, one display unit is primarily used to display image information, and another... A function that primarily displays text information on one display unit, or a function that takes parallax into account on multiple display units. It can have functions such as displaying three-dimensional images by displaying images. Furthermore, Electronic devices having an image receiving unit include functions for taking still images, functions for taking videos, and shooting Functions to automatically or manually correct the captured image, and the recording medium (external or camera) on which the captured image is stored. It can have functions such as saving images internally and displaying captured images on the display unit. Furthermore, the electronic devices shown in Figures 33(A) to 33(H) and Figures 34(A) to 34(D) The functions it can possess are not limited to these, and it can have a variety of functions.

[0354] The electronic device described in this embodiment has a display unit for displaying some kind of information. This embodiment is characterized by the electronic device of this embodiment and the semiconductor device of Embodiments 1 to 9. By combining it with a shift register or display device, reliability and yield can be improved. This allows for improvements in performance, cost reduction, larger display area, and higher resolution display area. .

[0355] Next, we will explain some application examples of semiconductor devices.

[0356] Figure 34(E) shows an example of a semiconductor device being installed as an integral part of a building. ) consists of a housing 5022, a display unit 5023, a remote control device 5024 which is the operating unit, and a speaker 5 Includes 025, etc. The semiconductor equipment is wall-mounted and integrated with the building, and the installation space It can be installed without requiring a large space.

[0357] Figure 34(F) shows another example in which semiconductor equipment is installed within a building and integrated with the building itself. The display panel 5026 is installed together with the unit bath 5027, and the bather This allows viewing of the display panel 5026.

[0358] In this embodiment, walls and a unit bathroom were used as examples of buildings, but the actual form The configuration is not limited to this, and semiconductor devices can be installed in various types of buildings.

[0359] Next, we will show an example in which a semiconductor device is integrated with a mobile device.

[0360] Figure 34(G) shows an example of a semiconductor device installed in an automobile. (Display panel) 5028 is attached to the vehicle body 5029 and is controlled by the movement of the vehicle body or from inside or outside the vehicle body The system can display the entered information on demand. It also includes a navigation function. It's okay to do so.

[0361] Figure 34(H) shows an example of a semiconductor device being integrated with a passenger aircraft. Yes. Figure 34(H) shows a display panel 5031 on the ceiling 5030 above the seats of a passenger airplane. This diagram shows the shape of the unit when installed and in use. The display panel 5031 is located on the ceiling 50 30 is attached integrally with the hinge portion 5032, and the extension and retraction of the hinge portion 5032 Passengers will be able to view the display panel 5031. The display panel 5031 can be operated by passengers. It has the function of displaying information by doing so.

[0362] In this embodiment, examples of mobile bodies include automobile bodies and aircraft bodies. However, this is not limited to motorcycles, four-wheeled vehicles (including automobiles, buses, etc.), and trains (monorails). It can be installed on various things, including railroads, railways, ships, etc. [Explanation of Symbols]

[0363] 100 circuits 101 Transistors 102 transistors 103 Transistors 104 circuits 105 circuits 106 circuits 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 116 Wiring 117 Wiring 118 Wiring 121 Capacitive elements 122 transistors 201 Transistors 202 transistors 203 Transistors 204 transistors 221 Capacitive element 301 Transistors 302 Transistors 303 Transistors 304 transistors 305 Transistors 306 transistors 307 transistors 400 Shift Registers 401 Flip-Flops 411 Wiring 412 Wiring 413 Wiring 414 Wiring 415 Wiring 416 Wiring 417 Wiring 420 circuits 421 Circuits 422 circuits 431 transistors 500 circuits 501 Circuit 502 Circuit 503 Transistors 504 Wiring 505 Wiring 514 signal 515 Signal 540 pixels 601 Conductive layer 602 Semiconductor layer 603 Conductive layer 604 Conductive layer 605 Contact Hole 611 Opening 612 Opening 621 Wiring width 622 Wiring width 623 width 624 width 626 width 631 width 632 width 101pF transistor 102a diode 102pF transistor 103a diode 103pF transistor 104a terminal 104b terminal 104c terminal 104d terminal 105a terminal 105b terminal 105c terminal 105d terminal 105e terminal 105f terminal 105g terminal 111A Wiring 112A wiring 112B Wiring 112C wiring 112D Wiring 113A Wiring 113B Wiring 114A Wiring 114B Wiring 115A wiring 115B Wiring 116A Wiring 116B Wiring 116C Wiring 116D Wiring 116E Wiring 116F Wiring 116G wiring 116H Wiring 116I Wiring 201pF transistor 202a diode 202pF transistor 203a diode 203pF transistor 204pF transistor 301pF transistor 302pF transistor 3030 transistor 303a diode 303pF transistor 304a diode 304pF transistor 305a diode 305pF transistor 5000 cabinets 5001 Display section 5002 Display section 5003 Speaker 5004 LED Lamp 5005 Operation Keys 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared Port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 Pointing Device 5021 Leader / Writer 5022 enclosure 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit Bathroom 5028 Display Panel 5029 Car body 5030 Ceiling 5031 Display Panel 5032 Hinge section 5033 Light source 5034 Projection Lens 5260 circuit board 5261 Insulating layer 5262 Semiconductor layer 5263 Insulating layer 5264 Conductive layer 5265 Insulating layer 5265 Insulating film 5266 Conductive layer 5267 Insulating layer 5268 Conductive layer 5269 Insulating layer 5269 Insulating film 5270 Emitting layer 5271 Conductive layer 5273 Insulating layer 5300 circuit boards 5301 Conductive layer 5302 Insulating layer 5304 Conductive layer 5305 Insulating layer 5306 Conductive layer 5307 Liquid crystal layer 5308 Conductive layer 5321 Transistor 5350 area 5351 area 5352 Semiconductor substrate 5353 area 5354 Insulating layer 5355 area 5356 Insulating layer 5357 Conductive layer 5358 Insulating layer 5359 Conductive layer 5360 Video signal 5361 Circuit 5362 Circuit 5362 Wiring 5363 Circuit 5364 pixel section 5365 Circuit 5366 Lighting device 5367 pixels 5371 Wiring 5372 Wiring 5373 Wiring 5380 circuit board 5381 Input terminal 5391 circuit board 5392 Drive Circuit 5393 pixel section 5400 circuit boards 5401 Conductive layer 5402 Insulating layer 5404 Conductive layer 5405 Insulating layer 5406 Conductive layer 5408 Insulating layer 5409 Conductive layer 5410 circuit board 5420 pixels 5421 Transistor 5421 Wiring 5422 liquid crystal element 5423 Capacitive element 5431 Wiring 5432 Wiring 5433 Wiring 5434 Electrode 5441 Signal 5442 signal 5262a area 5262b area 5262c area 5262d area 5262e area 5303a Semiconductor layer 5303b Semiconductor layer 5361a Circuit 5361b circuit 5362a Circuit 5362b circuit 5403a Semiconductor layer 5403b Semiconductor layer 5420A subpixel 5420B subpixels 5421A Transistor 5421B Transistor 5422A Liquid Crystal Element 5422B Liquid Crystal Element 5423A Capacitive element 5423B Capacitive element 5431A Wiring 5431B Wiring 5432A Wiring 5432B Wiring

Claims

1. It has a first clock signal line and a second clock signal line, The first clock signal line has at least a first conductive layer, a second conductive layer, and a third conductive layer. The second clock signal line has at least a fourth conductive layer and a fifth conductive layer. The first conductive layer has a first opening, The fourth conductive layer has a second opening, Each of the first conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer has a region extending along the first direction, The second conductive layer has a region that extends along a second direction intersecting the first direction, The second conductive layer has a region in contact with the first conductive layer, The second conductive layer has a region that overlaps with the second opening, The third conductive layer has a region in contact with the first conductive layer, The fifth conductive layer has a region in contact with the fourth conductive layer, The width of the third conductive layer along the first direction is smaller than the width of the first conductive layer along the first direction. The width of the third conductive layer along the second direction is smaller than the width of the first conductive layer along the second direction. The width of the fifth conductive layer along the first direction is smaller than the width of the fourth conductive layer along the first direction. A semiconductor device in which the width of the fifth conductive layer along the second direction is smaller than the width of the fourth conductive layer along the second direction, It has first to seventh transistors, Either the source or the drain of the first transistor is always in contact with the gate wire. The source or drain of the first transistor is always in conductivity with either the first clock signal line or the second clock signal line. Either the source or the drain of the second transistor is always in contact with the gate wire. The source or drain of the second transistor, the other of which is always in contact with the power line, Either the source or the drain of the third transistor is always in electrical contact with the power line. The gate of the third transistor is always in electrical contact with the gate of the second transistor. Either the source or the drain of the fourth transistor is always in contact with the gate of the second transistor. The source or drain of the fourth transistor, the other of which is always in contact with the first signal line, Either the source or drain of the fifth transistor is always in contact with the gate of the fourth transistor. The source or drain of the fifth transistor, the other of which is always in conductivity with the first signal line, The gate of the fifth transistor is always in conductivity with the first signal line. Either the source or the drain of the sixth transistor is always in contact with the second signal line. The gate of the sixth transistor is always in conductivity with the second signal line. Either the source or the drain of the seventh transistor is always in electrical contact with the power line. The gate of the seventh transistor is always in contact with the third signal line. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the third transistor, the third transistor is on. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the seventh transistor, the seventh transistor is on. When the second signal line is in conduction with the gate of the first transistor, at least through the channel formation region of the sixth transistor, the sixth transistor is on. At least one of the first to seventh transistors is a semiconductor device having an oxide semiconductor in its channel formation region.

2. It has a first clock signal line and a second clock signal line, The first clock signal line has at least a first conductive layer, a second conductive layer, and a third conductive layer. The second clock signal line has at least a fourth conductive layer and a fifth conductive layer. The first conductive layer has a first opening, The fourth conductive layer has a second opening, Each of the first conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer has a region extending along the first direction, The second conductive layer has a region that extends along a second direction intersecting the first direction, The second conductive layer has a region in contact with the first conductive layer, The second conductive layer has a region that overlaps with the second opening, The third conductive layer has a region in contact with the first conductive layer, The fifth conductive layer has a region in contact with the fourth conductive layer, The width of the third conductive layer along the first direction is smaller than the width of the first conductive layer along the first direction. The width of the third conductive layer along the second direction is smaller than the width of the first conductive layer along the second direction. The width of the fifth conductive layer along the first direction is smaller than the width of the fourth conductive layer along the first direction. A semiconductor device in which the width of the fifth conductive layer along the second direction is smaller than the width of the fourth conductive layer along the second direction, It has first to seventh transistors, Either the source or the drain of the first transistor is always in contact with the gate wire. The source or drain of the first transistor is always in conductivity with either the first clock signal line or the second clock signal line. Either the source or the drain of the second transistor is always in contact with the gate wire. The source or drain of the second transistor, the other of which is always in contact with the power line, Either the source or the drain of the third transistor is always in electrical contact with the power line. The gate of the third transistor is always in electrical contact with the gate of the second transistor. Either the source or the drain of the fourth transistor is always in contact with the gate of the second transistor. The source or drain of the fourth transistor, the other of which is always in contact with the first signal line, Either the source or drain of the fifth transistor is always in contact with the gate of the fourth transistor. The source or drain of the fifth transistor, the other of which is always in conductivity with the first signal line, The gate of the fifth transistor is always in conductivity with the first signal line. Either the source or drain of the sixth transistor is always in contact with the gate of the first transistor. The gate of the sixth transistor is always in contact with the second signal line. Either the source or the drain of the seventh transistor is always in electrical contact with the power line. The gate of the seventh transistor is always in contact with the third signal line. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the third transistor, the third transistor is on. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the seventh transistor, the seventh transistor is on. When the second signal line is in conduction with the gate of the first transistor, at least through the channel formation region of the sixth transistor, the sixth transistor is on. At least one of the first to seventh transistors is a semiconductor device having an oxide semiconductor in its channel formation region.

3. It has a first clock signal line and a second clock signal line, The first clock signal line has at least a first conductive layer, a second conductive layer, and a third conductive layer. The second clock signal line has at least a fourth conductive layer and a fifth conductive layer. The first conductive layer has a first opening, The fourth conductive layer has a second opening, Each of the first conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer has a region extending along the first direction, The second conductive layer has a region that extends along a second direction intersecting the first direction, The second conductive layer has a region in contact with the first conductive layer, The second conductive layer has a region that overlaps with the second opening, The third conductive layer has a region in contact with the first conductive layer, The fifth conductive layer has a region in contact with the fourth conductive layer, The width of the third conductive layer along the first direction is smaller than the width of the first conductive layer along the first direction. The width of the third conductive layer along the second direction is smaller than the width of the first conductive layer along the second direction. The width of the fifth conductive layer along the first direction is smaller than the width of the fourth conductive layer along the first direction. A semiconductor device in which the width of the fifth conductive layer along the second direction is smaller than the width of the fourth conductive layer along the second direction, It has first to seventh transistors, Either the source or the drain of the first transistor is always in contact with the gate wire. The source or drain of the first transistor is always in conductivity with either the first clock signal line or the second clock signal line. Either the source or the drain of the second transistor is always in contact with the gate wire. The source or drain of the second transistor, the other of which is always in contact with the power line, Either the source or the drain of the third transistor is always in electrical contact with the power line. The gate of the third transistor is always in electrical contact with the gate of the second transistor. Either the source or the drain of the fourth transistor is always in contact with the gate of the second transistor. The source or drain of the fourth transistor, the other of which is always in contact with the first signal line, Either the source or drain of the fifth transistor is always in contact with the gate of the fourth transistor. The source or drain of the fifth transistor, the other of which is always in conductivity with the first signal line, The gate of the fifth transistor is always in conductivity with the first signal line. Either the source or the drain of the sixth transistor is always in contact with the second signal line. The gate of the sixth transistor is always in conductivity with the second signal line. Either the source or drain of the seventh transistor is always in contact with the gate of the first transistor. The gate of the seventh transistor is always in contact with the third signal line. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the third transistor, the third transistor is on. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the seventh transistor, the seventh transistor is on. When the second signal line is in conduction with the gate of the first transistor, at least through the channel formation region of the sixth transistor, the sixth transistor is on. At least one of the first to seventh transistors is a semiconductor device having an oxide semiconductor in its channel formation region.

4. It has a first clock signal line and a second clock signal line, The first clock signal line has at least a first conductive layer, a second conductive layer, and a third conductive layer. The second clock signal line has at least a fourth conductive layer and a fifth conductive layer. The first conductive layer has a first opening, The fourth conductive layer has a second opening, Each of the first conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer has a region extending along the first direction, The second conductive layer has a region that extends along a second direction intersecting the first direction, The second conductive layer has a region in contact with the first conductive layer, The second conductive layer has a region that overlaps with the second opening, The third conductive layer has a region in contact with the first conductive layer, The fifth conductive layer has a region in contact with the fourth conductive layer, The width of the third conductive layer along the first direction is smaller than the width of the first conductive layer along the first direction. The width of the third conductive layer along the second direction is smaller than the width of the first conductive layer along the second direction. The width of the fifth conductive layer along the first direction is smaller than the width of the fourth conductive layer along the first direction. A semiconductor device in which the width of the fifth conductive layer along the second direction is smaller than the width of the fourth conductive layer along the second direction, It has first to seventh transistors, Either the source or the drain of the first transistor is always in contact with the gate wire. The source or drain of the first transistor is always in conductivity with either the first clock signal line or the second clock signal line. Either the source or the drain of the second transistor is always in contact with the gate wire. The source or drain of the second transistor, the other of which is always in contact with the power line, Either the source or the drain of the third transistor is always in electrical contact with the power line. The gate of the third transistor is always in electrical contact with the gate of the second transistor. Either the source or the drain of the fourth transistor is always in contact with the gate of the second transistor. The source or drain of the fourth transistor, the other of which is always in contact with the first signal line, Either the source or drain of the fifth transistor is always in contact with the gate of the fourth transistor. The source or drain of the fifth transistor, the other of which is always in conductivity with the first signal line, The gate of the fifth transistor is always in conductivity with the first signal line. Either the source or drain of the sixth transistor is always in contact with the gate of the first transistor. The gate of the sixth transistor is always in contact with the second signal line. Either the source or drain of the seventh transistor is always in contact with the gate of the first transistor. The gate of the seventh transistor is always in contact with the third signal line. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the third transistor, the third transistor is on. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the seventh transistor, the seventh transistor is on. When the second signal line is in conduction with the gate of the first transistor, at least through the channel formation region of the sixth transistor, the sixth transistor is on. At least one of the first to seventh transistors is a semiconductor device having an oxide semiconductor in its channel formation region.

5. It has a first clock signal line and a second clock signal line, The first clock signal line has at least a first conductive layer, a second conductive layer, and a third conductive layer. The second clock signal line has at least a fourth conductive layer and a fifth conductive layer. The first conductive layer has a first opening, The fourth conductive layer has a second opening, Each of the first conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer has a region extending along the first direction, The second conductive layer has a region that extends along a second direction intersecting the first direction, The second conductive layer has a region in contact with the first conductive layer, The second conductive layer has a region that overlaps with the second opening, The third conductive layer has a region in contact with the first conductive layer, The fifth conductive layer has a region in contact with the fourth conductive layer, The width of the third conductive layer along the first direction is smaller than the width of the first conductive layer along the first direction. The width of the third conductive layer along the second direction is smaller than the width of the first conductive layer along the second direction. The width of the fifth conductive layer along the first direction is smaller than the width of the fourth conductive layer along the first direction. A semiconductor device in which the width of the fifth conductive layer along the second direction is smaller than the width of the fourth conductive layer along the second direction, It has first to seventh transistors, Either the source or the drain of the first transistor is always in contact with the gate wire. The source or drain of the first transistor is always in conductivity with either the first clock signal line or the second clock signal line. Either the source or the drain of the second transistor is always in contact with the gate wire. The source or drain of the second transistor, the other of which is always in contact with the power line, Either the source or drain of the third transistor is always in contact with the gate of the first transistor. The gate of the third transistor is always in electrical contact with the gate of the second transistor. Either the source or the drain of the fourth transistor is always in contact with the gate of the second transistor. The source or drain of the fourth transistor, the other of which is always in contact with the first signal line, Either the source or drain of the fifth transistor is always in contact with the gate of the fourth transistor. The source or drain of the fifth transistor, the other of which is always in conductivity with the first signal line, The gate of the fifth transistor is always in conductivity with the first signal line. Either the source or the drain of the sixth transistor is always in contact with the second signal line. The gate of the sixth transistor is always in conductivity with the second signal line. Either the source or the drain of the seventh transistor is always in electrical contact with the power line. The gate of the seventh transistor is always in contact with the third signal line. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the third transistor, the third transistor is on. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the seventh transistor, the seventh transistor is on. When the second signal line is in conduction with the gate of the first transistor, at least through the channel formation region of the sixth transistor, the sixth transistor is on. At least one of the first to seventh transistors is a semiconductor device having an oxide semiconductor in its channel formation region.

6. It has a first clock signal line and a second clock signal line, The first clock signal line has at least a first conductive layer, a second conductive layer, and a third conductive layer. The second clock signal line has at least a fourth conductive layer and a fifth conductive layer. The first conductive layer has a first opening, The fourth conductive layer has a second opening, Each of the first conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer has a region extending along the first direction, The second conductive layer has a region that extends along a second direction intersecting the first direction, The second conductive layer has a region in contact with the first conductive layer, The second conductive layer has a region that overlaps with the second opening, The third conductive layer has a region in contact with the first conductive layer, The fifth conductive layer has a region in contact with the fourth conductive layer, The width of the third conductive layer along the first direction is smaller than the width of the first conductive layer along the first direction. The width of the third conductive layer along the second direction is smaller than the width of the first conductive layer along the second direction. The width of the fifth conductive layer along the first direction is smaller than the width of the fourth conductive layer along the first direction. A semiconductor device in which the width of the fifth conductive layer along the second direction is smaller than the width of the fourth conductive layer along the second direction, It has first to seventh transistors, Either the source or the drain of the first transistor is always in contact with the gate wire. The source or drain of the first transistor is always in conductivity with either the first clock signal line or the second clock signal line. Either the source or the drain of the second transistor is always in contact with the gate wire. The source or drain of the second transistor, the other of which is always in contact with the power line, Either the source or drain of the third transistor is always in contact with the gate of the first transistor. The gate of the third transistor is always in electrical contact with the gate of the second transistor. Either the source or the drain of the fourth transistor is always in contact with the gate of the second transistor. The source or drain of the fourth transistor, the other of which is always in contact with the first signal line, Either the source or drain of the fifth transistor is always in contact with the gate of the fourth transistor. The source or drain of the fifth transistor, the other of which is always in conductivity with the first signal line, The gate of the fifth transistor is always in conductivity with the first signal line. Either the source or drain of the sixth transistor is always in contact with the gate of the first transistor. The gate of the sixth transistor is always in contact with the second signal line. Either the source or the drain of the seventh transistor is always in electrical contact with the power line. The gate of the seventh transistor is always in contact with the third signal line. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the third transistor, the third transistor is on. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the seventh transistor, the seventh transistor is on. When the second signal line is in conduction with the gate of the first transistor, at least through the channel formation region of the sixth transistor, the sixth transistor is on. At least one of the first to seventh transistors is a semiconductor device having an oxide semiconductor in its channel formation region.

7. It has a first clock signal line and a second clock signal line, The first clock signal line has at least a first conductive layer, a second conductive layer, and a third conductive layer. The second clock signal line has at least a fourth conductive layer and a fifth conductive layer. The first conductive layer has a first opening, The fourth conductive layer has a second opening, Each of the first conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer has a region extending along the first direction, The second conductive layer has a region that extends along a second direction intersecting the first direction, The second conductive layer has a region in contact with the first conductive layer, The second conductive layer has a region that overlaps with the second opening, The third conductive layer has a region in contact with the first conductive layer, The fifth conductive layer has a region in contact with the fourth conductive layer, The width of the third conductive layer along the first direction is smaller than the width of the first conductive layer along the first direction. The width of the third conductive layer along the second direction is smaller than the width of the first conductive layer along the second direction. The width of the fifth conductive layer along the first direction is smaller than the width of the fourth conductive layer along the first direction. A semiconductor device in which the width of the fifth conductive layer along the second direction is smaller than the width of the fourth conductive layer along the second direction, It has first to seventh transistors, Either the source or the drain of the first transistor is always in contact with the gate wire. The source or drain of the first transistor is always in conductivity with either the first clock signal line or the second clock signal line. Either the source or the drain of the second transistor is always in contact with the gate wire. The source or drain of the second transistor, the other of which is always in contact with the power line, Either the source or drain of the third transistor is always in contact with the gate of the first transistor. The gate of the third transistor is always in electrical contact with the gate of the second transistor. Either the source or the drain of the fourth transistor is always in contact with the gate of the second transistor. The source or drain of the fourth transistor, the other of which is always in contact with the first signal line, Either the source or drain of the fifth transistor is always in contact with the gate of the fourth transistor. The source or drain of the fifth transistor, the other of which is always in conductivity with the first signal line, The gate of the fifth transistor is always in conductivity with the first signal line. Either the source or the drain of the sixth transistor is always in contact with the second signal line. The gate of the sixth transistor is always in conductivity with the second signal line. Either the source or drain of the seventh transistor is always in contact with the gate of the first transistor. The gate of the seventh transistor is always in contact with the third signal line. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the third transistor, the third transistor is on. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the seventh transistor, the seventh transistor is on. When the second signal line is in conduction with the gate of the first transistor, at least through the channel formation region of the sixth transistor, the sixth transistor is on. At least one of the first to seventh transistors is a semiconductor device having an oxide semiconductor in its channel formation region.

8. It has a first clock signal line and a second clock signal line, The first clock signal line has at least a first conductive layer, a second conductive layer, and a third conductive layer. The second clock signal line has at least a fourth conductive layer and a fifth conductive layer. The first conductive layer has a first opening, The fourth conductive layer has a second opening, Each of the first conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer has a region extending along the first direction, The second conductive layer has a region that extends along a second direction intersecting the first direction, The second conductive layer has a region in contact with the first conductive layer, The second conductive layer has a region that overlaps with the second opening, The third conductive layer has a region in contact with the first conductive layer, The fifth conductive layer has a region in contact with the fourth conductive layer, The width of the third conductive layer along the first direction is smaller than the width of the first conductive layer along the first direction. The width of the third conductive layer along the second direction is smaller than the width of the first conductive layer along the second direction. The width of the fifth conductive layer along the first direction is smaller than the width of the fourth conductive layer along the first direction. A semiconductor device in which the width of the fifth conductive layer along the second direction is smaller than the width of the fourth conductive layer along the second direction, It has first to seventh transistors, Either the source or the drain of the first transistor is always in contact with the gate wire. The source or drain of the first transistor is always in conductivity with either the first clock signal line or the second clock signal line. Either the source or the drain of the second transistor is always in contact with the gate wire. The source or drain of the second transistor, the other of which is always in contact with the power line, Either the source or drain of the third transistor is always in contact with the gate of the first transistor. The gate of the third transistor is always in electrical contact with the gate of the second transistor. Either the source or the drain of the fourth transistor is always in contact with the gate of the second transistor. The source or drain of the fourth transistor, the other of which is always in contact with the first signal line, Either the source or drain of the fifth transistor is always in contact with the gate of the fourth transistor. The source or drain of the fifth transistor, the other of which is always in conductivity with the first signal line, The gate of the fifth transistor is always in conductivity with the first signal line. Either the source or drain of the sixth transistor is always in contact with the gate of the first transistor. The gate of the sixth transistor is always in contact with the second signal line. Either the source or drain of the seventh transistor is always in contact with the gate of the first transistor. The gate of the seventh transistor is always in contact with the third signal line. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the third transistor, the third transistor is on. When the power line is in conduction with the gate of the first transistor, at least through the channel formation region of the seventh transistor, the seventh transistor is on. When the second signal line is in conduction with the gate of the first transistor, at least through the channel formation region of the sixth transistor, the sixth transistor is on. At least one of the first to seventh transistors is a semiconductor device having an oxide semiconductor in its channel formation region.

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