Memory device and method for manufacturing the same

Abstract

To provide a memory device in which the structural stability of a stacked body can be ensured.SOLUTION: A memory device 100 according to an embodiment of the present invention may include: a cell region CR; a contact region CTR extending from the cell region CR in a first direction X, and including a stepped structure arranged along a second direction Y that intersects the first direction X; and a support pattern SP separating the contact region CTR into a first contact region GCTR coupled to the cell region CR and a second contact region PCTR separated from the cell region CR. The support pattern SP may include sub-support patterns SSP1-SSP4 extending in the first direction X and contacting both sides of the second contact region PCTR. At least one of the sub-support patterns SSP1-SSP4 may be formed to overlap with at least a portion of the stepped structure, and the second contact region PCTR may be formed not to overlap with the stepped structure.SELECTED DRAWING: Figure 4b

Description

Technical Field

[0001] The present invention relates to a memory device and a method for manufacturing the same, and more specifically, to a memory device including a memory block having a three-dimensional structure and a method for manufacturing the same.

Background Art

[0002] The memory device can include a non-volatile memory device in which data stored even when the power supply is cut off is retained as it is. The non-volatile memory device is classified into a two-dimensional structure or a three-dimensional structure according to the array structure of memory cells. The memory cells of the non-volatile memory device having a two-dimensional structure can be arranged in a single layer on a substrate, and the memory cells of the non-volatile memory device having a three-dimensional structure can be stacked vertically on the substrate. In recent years, electronic devices using non-volatile memory devices having a three-dimensional structure have increased because the integration degree of non-volatile memory devices having a three-dimensional structure is higher than that of non-volatile memory devices having a two-dimensional structure.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present invention provide a memory device and a method for manufacturing the same that can ensure the structural stability of a laminate.

Means for Solving the Problems

[0004] A memory device according to an embodiment of the present invention can include a cell region, a contact region including a staircase structure that extends from the cell region in a first direction and is arranged along a second direction intersecting the first direction, and a support pattern that separates the contact region into a first contact region connected to the cell region and a second contact region separated from the cell region. The support patterns can each include sub-support patterns that extend in the first direction and contact both sides of the second contact region. Any one of the sub-support patterns can overlap at least a part of the staircase structure, and the second contact region can not overlap the staircase structure.

[0005] A method for manufacturing a memory device according to an embodiment of the present invention may include the steps of: forming a pre-laminate containing first and second material films; forming cell plugs in the cell regions of the pre-laminate; forming a staircase structure in a contact region extending from the cell region in a first direction, arranged along a second direction intersecting the first direction; and forming a support pattern that penetrates the contact region and includes sub-support patterns extending in the first direction, thereby separating the contact region into a first contact region and a second contact region surrounded by the support pattern. In the step of forming the support pattern, any one of the sub-support patterns may be superimposed on at least a part of the staircase structure, while the second contact region may be formed so as not to superimpose on the staircase structure. [Effects of the Invention]

[0006] This technology ensures the stability of the laminate by adjusting the position of the stepped structure and support pattern in the contact area of ​​the laminate. [Brief explanation of the drawing]

[0007] [Figure 1] This is a diagram illustrating a memory device according to an embodiment of the present invention. [Figure 2] This is a diagram illustrating a memory device according to an embodiment of the present invention. [Figure 3a] This figure illustrates the cell region and contact region according to an embodiment of the present invention. [Figure 3b] This figure illustrates the cell region and contact region according to an embodiment of the present invention. [Figure 3c] This figure illustrates the cell region and contact region according to an embodiment of the present invention. [Figure 4a] This figure illustrates a support pattern superimposed on a staircase structure according to the first embodiment of the present invention. [Figure 4b]This figure illustrates a support pattern superimposed on a staircase structure according to the first embodiment of the present invention. [Figure 5a] This figure illustrates a support pattern superimposed on a staircase structure according to a second embodiment of the present invention. [Figure 5b] This figure illustrates a support pattern superimposed on a staircase structure according to a second embodiment of the present invention. [Figure 6a] This is a diagram illustrating a method for manufacturing a memory device according to an embodiment of the present invention. [Figure 6b] This is a diagram illustrating a method for manufacturing a memory device according to an embodiment of the present invention. [Figure 6c] This is a diagram illustrating a method for manufacturing a memory device according to an embodiment of the present invention. [Figure 6d] This is a diagram illustrating a method for manufacturing a memory device according to an embodiment of the present invention. [Figure 6e] This is a diagram illustrating a method for manufacturing a memory device according to an embodiment of the present invention. [Figure 7] This is a diagram illustrating a memory card system to which the memory device of the present invention is applied. [Figure 8] This is a diagram illustrating an SSD (Solid State Drive) system to which the memory device of the present invention is applied. [Modes for carrying out the invention]

[0008] The specific structural or functional descriptions of embodiments of the concept of the present invention disclosed herein or in the application are illustrative only for the purpose of illustrating embodiments of the concept of the present invention, and embodiments of the concept of the present invention may be carried out in various forms and should not be construed as being limited to the embodiments described herein or in the application.

[0009] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings in order to explain in sufficient detail that a person with ordinary skill in the art to which the present invention pertains can implement the technical idea of ​​the present invention.

[0010] FIG. 1 is a diagram for explaining a memory device according to an embodiment of the present invention.

[0011] Referring to FIG. 1, a memory device 100 may include a memory cell array 110, a peripheral circuit 170, and a control circuit 180.

[0012] The memory cell array 110 may include first to ith memory blocks BLK1 to BLKi. Each of the first to ith memory blocks BLK1 to BLKi may include memory cells capable of storing data. A drain selection line DSL, a word line WL, a source selection line SSL, and a source line SL may be connected to each of the first to ith memory blocks BLK1 to BLKi, and a bit line BL may be commonly connected to the first to ith memory blocks BLK1 to BLKi.

[0013] The first to ith memory blocks BLK1 to BLKi may be formed in a three-dimensional structure. A memory block having a three-dimensional structure may include memory cells stacked in a direction perpendicular to a substrate.

[0014] A memory cell can store 1-bit or 2-bit or more data according to a programming method. For example, a method in which 1-bit data is stored in one memory cell is called a single level cell method, and a method in which 2-bit data is stored is called a multi level cell method. A method in which 3-bit data is stored in one memory cell is called a triple level cell method, and a method in which 4-bit data is stored is called a quad level cell method. In addition, 5-bit or more data can be stored in one memory cell.

[0015] The peripheral circuit 170 can be configured to perform a program operation for storing data in the memory cell array 110, a read operation for outputting the data stored in the memory cell array 110, and an erase operation for erasing the data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0016] The voltage generator 120 can generate various operation voltages Vop used for a program operation, a read operation, or an erase operation in response to an operation code OPCD. For example, the voltage generator 120 can be configured to generate program voltages, turn on voltages, turn off voltages, negative voltages, precharge voltage, verify voltages, read voltages, pass voltages, or erase voltages in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 can be applied to the drain select line DSL, word line WL, source select line SSL, and source line SL of the memory block selected via the row decoder 130.

[0017] The program voltage is a voltage applied to the word line selected from the word line WL during a program operation and can be used to raise the threshold voltage of the memory cell connected to the selected word line. The turn-on voltage can be applied to the drain selection line DSL or source selection line SSL and can be used to turn on the drain selection transistor or source selection transistor. The turn-off voltage can be applied to the drain selection line DSL or source selection line SSL and can be used to turn off the drain selection transistor or source selection transistor. For example, the turn-off voltage can be set to 0V. The precharge voltage is a voltage higher than 0V and can be applied to the bit line during a read operation. The verification voltage can be used during a verification operation to determine whether the threshold voltage of the selected memory cell has risen to a target level. The verification voltage can be set to various levels depending on the target level and can be applied to the selected word line.

[0018] The read voltage can be applied to the selected word line during a read operation of the selected memory cell. For example, the read voltage may be set to various levels depending on the programming scheme of the selected memory cell. The pass voltage is a voltage applied to the unselected word line WL during a program or read operation and can be used to turn on memory cells connected to the unselected word line. The erase voltage can be used during an erase operation to erase memory cells contained in the selected memory block and can be applied to the source line SL.

[0019] The row decoder 130 can be configured to transmit an operating voltage Vop to a drain selection line DSL, a word line WL, a source selection line SSL, and a source line SL connected to a memory block selected according to the row address RADD. For example, the row decoder 130 may be connected to a voltage generator 120 via global lines, or it may be connected to the first to i-th memory blocks BLK1 to BLKi via the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL.

[0020] The page buffer group 140 may include page buffers (not shown) connected to the first to i-th memory blocks BLK1 to BLKi, respectively. Each of the page buffers (not shown) may be connected to the first to i-th memory blocks BLK1 to BLKi via a bit line BL. During a read operation, the page buffer (not shown) can respond to the page buffer control signal PBSIG by sensing the current or voltage of a bit line that varies according to the threshold voltage of the selected memory cell, and temporarily store the sensed data.

[0021] The column decoder 150 can be configured to transmit data between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 can be connected to the page buffer group 140 via column lines CL and transmit an enable signal via column lines CL. The page buffer (not shown) included in the page buffer group 140 can receive or output data via data lines DL in response to the enable signal.

[0022] The input / output circuit 160 can be configured to receive or output commands CMD, addresses ADD, or data via input / output line I / O. For example, the input / output circuit 160 can transmit commands CMD and addresses ADD received from an external controller via input / output line I / O to the control circuit 180, and can transmit data received from an external controller via input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 can output data transmitted from the page buffer group 140 to an external controller via input / output line I / O.

[0023] The control circuit 180 can output at least one of the following in response to a command CMD and an address ADD: an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, or a column address CADD. For example, if the command CMD input to the control circuit 180 corresponds to a program operation, the control circuit 180 can control the peripheral circuit 170 to execute the program operation of the memory block selected by address ADD. If the command CMD input to the control circuit 180 corresponds to a read operation, the control circuit 180 can control the peripheral circuit 170 to execute a read operation of the memory block selected by address and output the read data. If the command CMD input to the control circuit 180 corresponds to an erase operation, the control circuit 180 can control the peripheral circuit 170 to execute an erase operation of the selected memory block.

[0024] Figure 2 is a diagram illustrating a memory device according to an embodiment of the present invention.

[0025] Referring to Figure 2, the memory device 100 may include a peripheral circuit structure PC and memory blocks BLK1 to BLKi arranged on a substrate SUB. The memory blocks BLK1 to BLKi can be superimposed on the peripheral circuit structure PC.

[0026] The substrate SUB may be a single-crystal semiconductor film. For example, the substrate SUB may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by selective epitaxial growth.

[0027] The peripheral circuit structure PC may include a row decoder 130, a column decoder 150, a page buffer group 140, and a control circuit 180, which constitute a circuit for controlling the operation of memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC may include NMOS transistors, PMOS transistors, resistors, and capacitors that are electrically connected to memory blocks BLK1 to BLKi. The peripheral circuit structure PC can be placed between the substrate SUB and the memory blocks BLK1 to BLKi.

[0028] Each of the memory blocks BLK1 to BLKi may include a source structure, a bit line, a cell string electrically connected to the source structure and bit line, a word line electrically connected to the cell string, and a selection line electrically connected to the cell string. Each cell string may include a memory cell and a selection transistor connected in series by a cell plug. Each selection line can be used as the gate electrode of its corresponding selection transistor, and each word line can be used as the gate electrode of its corresponding memory cell.

[0029] In another embodiment, the substrate SUB, peripheral circuit structure PC, and memory blocks BLK1 to BLKi may be stacked in the reverse order of the sequence shown in Figure 2. For example, the peripheral circuit structure PC may be placed on top of the memory blocks BLK1 to BLKi.

[0030] In another embodiment, unlike that shown in Figure 2, the peripheral circuit structure PC may be arranged on a portion of the substrate SUB that does not overlap the memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC and the memory blocks BLK1 to BLKi can be arranged on separate, non-overlapping regions of the substrate SUB.

[0031] Figures 3a to 3c are diagrams illustrating the cell region and contact region according to embodiments of the present invention. Figure 3a is a diagram illustrating the layout of a memory device according to embodiments of the present invention. Figure 3b is a cross-sectional view showing the cross-section AA' of Figure 3a. Figure 3c is a cross-sectional view showing the cross-section BB' of Figure 3a.

[0032] Referring to Figure 3a, the memory device 100 may include slit SLIs. Each slit SLI may extend in the X direction. The slit SLIs may be spaced apart from each other in the Y direction. The slit SLIs can isolate memory blocks (for example, memory blocks BLK1 to BLKi in Figure 2) from each other. For example, the first memory block BLK1 and the second memory block BLK2 can be separated with respect to any one of the slit SLIs.

[0033] The memory device 100 may include a cell area CR and a contact area CTR. The contact area CTR may be located in the X direction of the cell area CR. The contact area CTR may extend from the cell area CR in the X direction. A cell plug CPL may be located in the cell area CR.

[0034] A support pattern SP can be placed in the contact region CTR. The support pattern SP can separate the contact region CTR into a first contact region GCTR and a second contact region PCTR. The support pattern SP can surround at least three faces of the second contact region PCTR (e.g., the face in the Y direction, the face opposite the Y direction, and the face opposite the X direction). For example, the support pattern SP may include sub-support patterns SSP extending in the X direction. The sub-support patterns SSP can be in contact with both Y-direction faces of the second contact region PCTR. The first contact region GCTR can be positioned in the Y direction and the face opposite the Y direction of the second contact region PCTR, with the support pattern SP in between. That is, the support pattern SP can be placed between the second contact region PCTR and the first contact region GCTR. Alternatively, the support pattern SP can be placed between the second contact region PCTR and the cell region CR.

[0035] The first contact region GCTR can be connected to the cell region CR. The first contact region GCTR can extend from the cell region CR. The first contact region GCTR can be electrically connected to the cell region CR. The first contact GCT can be located in the first contact region GCTR. The first contact GCT can be connected to gate lines (e.g., the drain selection line DSL, the word line WL, and the source selection line SSL in Figure 1).

[0036] The second contact region PCTR can be separated from the cell region CR. The second contact region PCTR can be isolated from the cell region CR and the first contact region GCTR by a support pattern SP. The second contact PCT can be located in the second contact region PCTR. The second contact PCT can be connected to a peripheral circuit structure (e.g., peripheral circuit structure PC in Figure 2).

[0037] Referring to Figure 3b, the memory device 100 may include a gate stack GST and a dummy stack DST. The cell region CR of the memory device 100 may include the gate stack GST, and the second contact region PCTR may include the dummy stack DST. The gate stack GST may be located in the cell region CR, and the dummy stack DST may be located in the second contact region PCTR. The gate stack GST may be separated from the dummy stack DST by a support pattern SP. An upper insulating film UIL may be placed on the gate stack GST and the dummy stack DST. The upper insulating film UIL may cover the gate stack GST and the dummy stack DST.

[0038] The gate stack (GST) may include a conductive film CD and an interlayer insulating film IIL. The conductive film CD and the interlayer insulating film IIL can be stacked alternately along the Z direction. The conductive film CD may consist of at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polysilicon (poly-Si). The interlayer insulating film IIL may consist of an oxide film (e.g., silicon oxide). The conductive film CD may correspond to gate lines (e.g., drain selection line DSL, word line WL, source selection line SSL in Figure 1).

[0039] The dummy laminate DST may include a sacrificial film SF and an interlayer insulating film IIL. The sacrificial film SF and the interlayer insulating film IIL may be stacked alternately along the Z direction. The sacrificial film SF may include an insulator having an etching selectivity ratio with respect to the interlayer insulating film IIL. For example, the interlayer insulating film IIL may include an oxide film (e.g., silicon oxide film), and the sacrificial film SF may include a nitride film. The sacrificial film SF of the dummy laminate DST may be located at the same level as the conductive film CD of the gate laminate GST. The sacrificial film SF may be separated from the conductive film CD by a support pattern SP. The interlayer insulating film IIL of the dummy laminate DST may be located at the same level as the interlayer insulating film IIL of the gate laminate GST and may include the same material.

[0040] A source structure SC can be placed below the gate stack GST and dummy stack DST. The source structure SC can include an upper source structure USC, an interlayer source structure FSC, and a lower source structure LSC. An interlayer source structure FSC can be placed on the lower source structure LSC, and an upper source structure USC can be placed on the interlayer source structure FSC. Each of the upper source structure USC, interlayer source structure FSC, and lower source structure LSC can include a semiconductor material (e.g., silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof). Each of the upper source structure USC, interlayer source structure FSC, and lower source structure LSC can include at least one of n-type impurities and p-type impurities. For example, at least one of the upper source structure USC, interlayer source structure FSC, or lower source structure LSC may include a polysilicon film doped with n-type impurities.

[0041] An insulating pattern IP can be placed below the dummy laminate DST. The insulating pattern IP can be superimposed on at least a portion of the dummy laminate DST. The insulating pattern IP can penetrate the source structure SC. The insulating pattern IP can be located at the same level as the source structure SC. The upper surface of the insulating pattern IP can be located at the same level as the upper surface of the upper source structure USC, and the lower surface of the insulating pattern IP can be located at the same level as the lower surface of the lower source structure LSC. The insulating pattern IP may contain an insulator (e.g., oxide, nitride).

[0042] A peripheral circuit structure PC and a substrate SUB can be located below the source structure SC and insulating pattern IP. The peripheral circuit structure PC can be located on the substrate SUB. The peripheral circuit structure PC may include a transistor TR, a peripheral contact plug PPL, and a peripheral line PLN. The transistor TR, peripheral contact plug PPL, and peripheral line PLN can have various patterns depending on the configuration of the peripheral circuit. For example, the number or position of the transistor TR, peripheral contact plug PPL, and peripheral line PLN may vary considerably. A lower insulating film LIL can be located between the transistor TR, peripheral contact plug PPL, and peripheral line PLN. For example, the transistor TR, peripheral contact plug PPL, and peripheral line PLN can be formed inside the lower insulating film LIL.

[0043] Cell plugs (CPLs) can be formed in the cell region (CR). Cell plugs (CPLs) can penetrate the gate stack (GST). Cell plugs (CPLs) can extend in the Z direction. Memory cells and selection transistors can be formed at the points where the cell plugs (CPLs) and the conductive film (CD) intersect, respectively.

[0044] The cell plug CPL may include a memory film ML, a channel film CH, a core pillar CO, and a capping film CAP. The memory film ML may be cylindrical. The memory film ML may be in contact with the gate stack GST. Although not shown, the memory film ML may include a blocking film, a charge trapping film, and a tunnel insulating film. The channel film CH may be formed along the inner wall of the memory film ML. The core pillar CO may be cylindrical and surrounded by the channel film CH. The capping film CAP may be connected to the channel film CH on the core pillar CO.

[0045] The blocking film and tunnel insulating film included in the memory film ML may consist of an oxide film (e.g., silicon oxide film) or an oxidnitride film (e.g., silicon oxidnitride film), or a combination thereof. The charge trap film included in the memory film ML may include a nitride film or a variable resistor material. The channel film CH and capping film CAP may consist of an undoped silicon film or a doped silicon film. Since the capping film CAP and the channel film CH are formed of the same material or of the same type, their interface may not be clearly observed. The core pillar CO may consist of an insulating film or a conductive film.

[0046] The cell plug CPL can be in contact with the source structure SC. The cell plug CPL can penetrate the gate stack GST and extend into the interior of the source structure SC. The cell plug CPL can penetrate the upper source structure USC and the interlayer source structure FSC and extend into the interior of the lower source structure LSC. The memory film ML can be placed between the channel film CH and the upper source structure USC, and between the channel film CH and the lower source structure LSC. The memory film ML does not have to be placed between the channel film CH and the interlayer source structure FSC. Therefore, the channel film CH can be in direct contact with the interlayer source structure FSC.

[0047] A second contact PCT can be formed in a second contact region PCTR. The second contact PCT can penetrate a dummy laminate DST. The second contact PCT can penetrate the sacrificial film SF and interlayer insulating film IIL of the dummy laminate DST. The second contact PCT can penetrate the insulating pattern IP. The second contact PCT can be connected to a peripheral circuit structure PC. For example, the second contact PCT can be in direct contact with the peripheral line PLN of the peripheral circuit structure PC. The second contact PCT can be understood as a peripheral circuit connection contact. The second contact PCT may contain a conductor.

[0048] In Figure 3c, the explanation of the configuration described in relation to Figures 3a and 3b can be omitted or simplified.

[0049] The gate stack GST can extend from the cell region CR to the first contact region GCTR. The first contact region GCTR can contain the gate stack GST. The gate stack GST can contain a stepped structure arranged along the X direction in the first contact region GCTR. For example, the conductive films CD contained in the gate stack GST may have different lengths in the X direction. In Figure 3c, the conductive films CD contained in the gate stack GST can be called the first conductive film CD1, the second conductive film CD2, and the third conductive film CD3, starting from the uppermost conductive film CD1. The first conductive film CD1 may have a shorter length in the X direction than the second conductive film CD2, and the second conductive film CD2 may have a shorter length in the X direction than the third conductive film CD3. The second conductive film CD2 may protrude further in the X direction than the first conductive film CD1. The third conductive film CD3 may protrude further in the X direction than the second conductive film CD2. Each end of the conductive film CD can be exposed on the gate stack GST. For example, the edges of the first conductive film CD1, the edges of the second conductive film CD2, and the edges of the third conductive film CD3 can be in contact with the upper insulating film UIL. Although not shown, the conductive film CD located beneath the third conductive film CD3 may also include a stepped structure arranged along the X direction. In this disclosure, when describing the stepped structure, the description focuses on the conductive film CD (or sacrificial film SF), but as shown in Figure 3c, each step may include the conductive film CD (or sacrificial film SF) and the interlayer insulating film IIL. That is, even if the mention that each step included in the stepped structure includes the interlayer insulating film IIL is omitted, it can be understood that each step includes the interlayer insulating film IIL.

[0050] The first contact GCT can be formed in the first contact region GCTR. The first contact GCT can be connected to the conductive film CD of the gate stack GST, respectively. The first contact GCT can be in contact with the edges of the conductive film CD, respectively. For example, the first contacts GCT1, GCT2, and GCT3 can be in direct contact with the first to third conductive films CD1, CD2, and CD3, respectively. The first contact GCT can be understood as a gate line connection contact. The first contact GCT may contain a conductor.

[0051] Figures 4a and 4b are diagrams illustrating the support pattern superimposed on the staircase structure according to the first embodiment of the present invention. Figure 4a is a cross-sectional view showing the cross-section of CC' in Figure 3a. Figure 4b is a cross-sectional view showing the cross-section of DD' in Figure 3a. Of the configurations shown in Figures 4a and 4b, the configurations described in relation to Figures 3a to 3c can be omitted or simplified in their description.

[0052] Referring to Figures 4a and 4b, each contact area CTR can be divided into a first contact area GCTR and a second contact area PCTR by support patterns SP (e.g., sub-support patterns SSP1 to SSP4). Support patterns SP (e.g., sub-support patterns SSP1 to SSP4) can be placed between the first contact area GCTR and the second contact area PCTR. The first contact area GCTR and the second contact area PCTR can be separated from each other by support patterns SP. The first contact area GCTR can be placed adjacent to the second contact area PCTR with support patterns SP in between. The first contact area GCTR can be located on both sides of the second contact area PCTR. For example, the first contact area GCTR may be located in the Y direction and the opposite direction of the Y direction of the second contact area PCTR.

[0053] Contact regions CTR1 and CTR2, respectively, contained within different memory blocks (e.g., the first and second memory blocks BLK1 and BLK2 in Figure 3a), can be separated from each other by a slit SLI. Contact regions CTR1 and CTR2 can be insulated from each other by a slit SLI. The slit SLI can penetrate the upper insulating film UIL and the gate stack GST and extend into the interior of the source structure SC. The slit SLI can consist of a single film (e.g., a silicon film, an insulating film) or a multilayer film (e.g., a conductive film surrounded by an insulating film, a silicon film surrounded by an insulating film).

[0054] Comparing Figure 4a and Figure 4b, the contact region CTR can include a stepped structure aligned along the X direction. As illustrated in Figure 3c, the third conductive film CD3 protrudes further in the X direction than the second conductive film CD2, so the second conductive film CD2 shown in Figure 4a may not be shown in Figure 4b. Similarly, the third sacrificial film SF3 protrudes further in the X direction than the second sacrificial film SF2, so the second sacrificial film SF2 shown in Figure 4a may not be shown in Figure 4b. When describing the stepped structure of this disclosure, conductive films and sacrificial films arranged at the same level (e.g., the second conductive film CD2 and the second sacrificial film SF2) can be referred to as a multilayer film (e.g., the second multilayer film CD2, SF2). For example, the length of the third multilayer film CD3, SF3 in the X direction may be longer than the length of the second multilayer film CD2, SF2 in the X direction.

[0055] Referring to Figures 4a and 4b, the contact region CTR can include a stepped structure arranged not only along the X direction but also along the Y direction. At least some of the multilayer films CD and SF included in the contact region CTR can include a stepped structure arranged along the Y direction. For example, at least some of the multilayer films CD and SF can have different lengths in the Y direction from each other. In the contact region CTR1 on the right side of Figure 4a, the third multilayer films CD3 and SF3 can protrude further in the Y direction from the second multilayer films CD2 and SF2, the fourth multilayer films CD4 and SF4 can protrude further in the Y direction from the third multilayer films CD3 and SF3, and the fifth multilayer films CD5 and SF5 can protrude further in the Y direction from the fourth multilayer films CD4 and SF4. In the contact region CTR1 on the right side of Figure 4a, the second multilayer film CD2, SF2 may have a shorter length in the Y direction than the third multilayer film CD3, SF3, the third multilayer film CD3, SF3 may have a shorter length in the Y direction than the fourth multilayer film CD4, SF4, and the fourth multilayer film CD4, SF4 may have a shorter length in the Y direction than the fifth multilayer film CD5, SF5. In this disclosure, the number of multilayer films CD, SF including a stepped structure arranged along the X or Y direction is not limited by the illustrations in Figures 4a and 4b. For example, Figure 4a shows a four-layer multilayer film having a stepped structure in the Y direction, but a multilayer film with five or more layers may also have a stepped structure in the Y direction.

[0056] The Y-direction step structure formed in the contact region CTR can have a symmetrical shape with respect to the slit SLI. For example, in the left contact region CTR2 of Figure 4a, the third multilayer film CD3, SF3 can project further in the opposite direction of the Y direction from the second multilayer film CD2, SF2, the fourth multilayer film CD4, SF4 can project further in the opposite direction of the Y direction from the third multilayer film CD3, SF3, and the fifth multilayer film CD5, SF5 can project further in the opposite direction of the Y direction from the fourth multilayer film CD4, SF4. In this disclosure, the specific shape of the step structure arranged along the X or Y direction is not limited by the illustrations in Figures 4a and 4b. For example, although Figure 4a shows the Y-direction step structure having a symmetrical shape with respect to the slit SLI, the Y-direction step structure may have an asymmetrical shape with respect to the slit SLI, or it may be formed in only one of the contact regions CTR1 or CTR2 with respect to the slit SLI.

[0057] The upper insulating film UIL can cover the gate stack GST and dummy stack DST. The ends of the stacked films CD and SF can be in contact with the upper insulating film UIL. For example, the upper insulating film UIL can be in contact with the upper and side surfaces of the respective ends of the stacked films CD and SF that constitute the stepped structure.

[0058] Referring to Figures 4a and 4b, at least a portion of the support pattern SP can be superimposed on at least a portion of the staircase structure arranged along the Y direction. Either one of the sub-support patterns SSP1 and SSP2 included in the contact region CTR1 on the right side of Figure 4a can be superimposed on at least a portion of the staircase structure in the Y direction. Also, either one of the sub-support patterns SSP3 and SSP4 included in the contact region CTR2 on the left side of Figure 4a can be superimposed on at least a portion of the staircase structure in the Y direction. For example, the second sub-support pattern SSP2 and the third sub-support pattern SSP3 can be superimposed on at least a portion of the staircase structure in the Y direction.

[0059] Furthermore, referring to Figures 4a and 4b, the second contact region PCTR does not need to overlap with the stepped structure arranged along the Y direction. In the right contact region CTR1 of Figure 4a, the second contact region PCTR does not need to overlap with the stepped structure in the Y direction. Also, in the left contact region CTR2 of Figure 4a, the second contact region PCTR does not need to overlap with the stepped structure in the Y direction.

[0060] Using the contact region CTR1 on the right side of Figure 4a as a reference, in order for the stepped structure arranged along the Y direction to superimpose on the second sub-support pattern SSP2 and not on the second contact region PCTR, the second sub-support pattern SSP2 can be positioned so that it superimposes on the point where the stepped structure arranged along the Y direction begins. The point where the stepped structure arranged along the Y direction begins may be the point where the end of the laminated film located at the uppermost end in a particular cross-section (for example, the second laminated films CD2 and SF2 in Figure 4a) is located. Therefore, in Figure 4a, the second sub-support pattern SSP2 can be superimposed on the ends of the second laminated films CD2 and SF2. Also, in Figure 4b, the second sub-support pattern SSP2 can be superimposed on the ends of the third laminated films CD3 and SF3.

[0061] Furthermore, referring to Figures 4a and 4b, the first contact region GCTR can be superimposed on other parts of the stepped structure arranged along the Y direction. Any one of the first contact region GCTRs included in the contact region CTR1 on the right side of Figure 4a can be superimposed on at least a part of the stepped structure in the Y direction. Also, any one of the first contact region GCTRs included in the contact region CTR2 on the left side of Figure 4a can be superimposed on at least a part of the stepped structure in the Y direction. For example, the first contact region GCTR located adjacent to the slit SLI shown in Figure 4a can be superimposed on at least a part of the stepped structure in the Y direction.

[0062] At least some of the conductive films CD included in the first contact region GCTR can have different lengths in the Y direction. For example, referring to Figure 4a, in the first contact region GCTR adjacent to the slit SLI, the second to fifth conductive films CD2 to CD5 can have different lengths in the Y direction. Also, referring to Figure 4b, in the first contact region GCTR adjacent to the slit SLI, the third to sixth conductive films CD3 to CD6 can have different lengths in the Y direction.

[0063] The sacrificial films SF included in the second contact region PCTR can have the same length in the Y direction. For example, referring to Figure 4a, the sacrificial films SF2 to SF5 (second to fifth sacrificial films) and the sacrificial film SF located below the fifth sacrificial film SF5 can have the same length in the Y direction. Similarly, referring to Figure 4b, the sacrificial films SF3 to SF6 (third to sixth sacrificial films) and the sacrificial film SF6 located below the sixth sacrificial film SF6 can have the same length in the Y direction.

[0064] Figures 5a and 5b are diagrams illustrating a support pattern superimposed on a staircase structure according to a second embodiment of the present invention. Figure 5a is a cross-sectional view showing the cross-section of CC' in Figure 3a. Figure 5b is a cross-sectional view showing the cross-section of DD' in Figure 3a. Among the configurations shown in Figures 5a and 5b, the configurations described in relation to Figures 3a, 3b, 3c, 4a, and 4b may be omitted or simplified in their description.

[0065] Comparing Figure 5a and Figure 5b, the contact region CTR can include a stepped structure aligned along the X direction. As explained in Figure 3c, the third conductive film CD3 protrudes further in the X direction than the second conductive film CD2, so the second conductive film CD2 shown in Figure 5a may not be shown in Figure 5b.

[0066] Referring to Figures 5a and 5b, the contact region CTR may include a stepped structure arranged along the Y direction. At least a portion of the conductive film CD included in the contact region CTR may include a stepped structure arranged along the Y direction. For example, at least a portion of the conductive film CDs may have different lengths in the Y direction from each other. In the contact region CTR1 on the right side of Figure 5a, the third conductive film CD3 may protrude further in the Y direction from the second conductive film CD2, the fourth conductive film CD4 may protrude further in the Y direction from the third conductive film CD3, and the fifth conductive film CD5 may protrude further in the Y direction from the fourth conductive film CD4. In the contact region CTR1 on the right side of Figure 5a, the second conductive film CD2 may have a shorter Y-direction length than the third conductive film CD3, the third conductive film CD3 may have a shorter Y-direction length than the fourth conductive film CD4, and the fourth conductive film CD4 may have a shorter Y-direction length than the fifth conductive film CD5.

[0067] The Y-direction step structure formed in the contact region CTR can have a symmetrical shape with respect to the slit SLI. For example, in the left contact region CTR2 of Figure 5a, the third conductive film CD3 can protrude further in the opposite direction of the Y direction from the second conductive film CD2, the fourth conductive film CD4 can protrude further in the opposite direction of the Y direction from the third conductive film CD3, and the fifth conductive film CD5 can protrude further in the opposite direction of the Y direction from the fourth conductive film CD4.

[0068] The upper insulating film UIL can cover the gate stack GST and dummy stack DST. The edges of the stacked films CD and SF can be in contact with the upper insulating film UIL. For example, the upper insulating film UIL can be in contact with the upper and side surfaces of each end of the conductive film CD that constitutes the stepped structure.

[0069] Referring to Figures 5a and 5b, at least a portion of the support pattern SP can be superimposed on at least a portion of the staircase structure arranged along the Y direction. Either one of the sub-support patterns SSP1 and SSP2 included in the contact region CTR1 on the right side of Figure 5a can be superimposed on at least a portion of the staircase structure in the Y direction. Also, either one of the sub-support patterns SSP3 and SSP4 included in the contact region CTR2 on the left side of Figure 5a can be superimposed on at least a portion of the staircase structure in the Y direction. For example, the first sub-support pattern SSP1 and the fourth sub-support pattern SSP4 can be superimposed on at least a portion of the staircase structure in the Y direction.

[0070] Furthermore, referring to Figures 5a and 5b, the second contact region PCTR does not need to overlap with the stepped structure arranged along the Y direction. In the right-hand contact region CTR1 of Figure 5a, the second contact region PCTR does not need to overlap with the stepped structure in the Y direction. Similarly, in the left-hand contact region CTR2 of Figure 5a, the second contact region PCTR does not need to overlap with the stepped structure in the Y direction.

[0071] Using the contact region CTR1 on the right side of Figure 5a as a reference, in order for the stepped structure arranged along the Y direction to superimpose on the first sub-support pattern SSP1 and not on the second contact region PCTR, the first sub-support pattern SSP1 can be positioned so that it superimposes on the point where the stepped structure arranged along the Y direction ends. Therefore, in Figure 5a, the first sub-support pattern SSP1 can be superimposed on the edge of the fifth conductive film CD5. Also, in Figure 5b, the first sub-support pattern SSP1 can be superimposed on the edge of the sixth conductive film CD6.

[0072] Furthermore, referring to Figures 5a and 5b, the first contact region GCTR can be superimposed on other parts of the stepped structure arranged along the Y direction. Any one of the first contact region GCTRs included in the contact region CTR1 on the right side of Figure 5a can be superimposed on at least a part of the stepped structure in the Y direction. Also, any one of the first contact region GCTRs included in the contact region CTR2 on the left side of Figure 5a can be superimposed on at least a part of the stepped structure in the Y direction. For example, a first contact region GCTR located further away from the slit SLI shown in Figure 5a can be superimposed on at least a part of the stepped structure in the Y direction.

[0073] At least some of the conductive films CD included in the first contact region GCTR can have different lengths in the Y direction. For example, referring to Figure 5a, in the first contact region GCTR located further away from the slit SLI, the second to fifth conductive films CD2 to CD5 can have different lengths in the Y direction. Also, referring to Figure 5b, in the first contact region GCTR located further away from the slit SLI, the third to sixth conductive films CD3 to CD6 can have different lengths in the Y direction.

[0074] The sacrificial films SF included in the second contact region PCTR can have the same length in the Y direction. For example, referring to Figure 5a, the 6th to 8th sacrificial films SF6 to SF8 can have the same length in the Y direction. Also, referring to Figure 5b, the 7th and 8th sacrificial films SF7 and SF8 can have the same length in the Y direction.

[0075] According to this disclosure, the stability of the laminate can be ensured by adjusting the relative positions of the support pattern SP and the stepped structure of the laminate (e.g., gate laminate GST, dummy laminate DST) within the contact region CTR. The structural stability of the second contact region PCTR can be ensured by arranging the second contact region PCTR so that a portion of the sub-support pattern SSP overlaps the stepped structure arranged along the Y direction within the contact region CTR, while the second contact region PCTR does not overlap. For example, unlike in this disclosure, if a slope occurs between the dummy laminate DST and the upper insulating film UIL inside the second contact region PCTR, defects such as bending of the second contact region PCTR may occur due to differences in material properties between different materials (e.g., oxides and nitrides). However, as in this disclosure, by eliminating the slope between the dummy laminate DST and the upper insulating film UIL inside the second contact region PCTR, the phenomenon of bending of the second contact region PCTR in the Y direction can be prevented.

[0076] Figures 6a to 6e are diagrams illustrating a method for manufacturing a memory device according to an embodiment of the present invention. Figures 6a to 6e are cross-sectional views showing the cross-section of CC' in Figure 3a. Figures 6a to 6e are explained based on the second embodiment of the first embodiment in Figure 4a and the second embodiment in Figure 5a, but the contents described below can also be applied to the first embodiment, except for the relative positions of the staircase structure and the sub-support pattern SSP.

[0077] Referring to Figure 6a, a preliminary source structure pSC can be formed by sequentially stacking a lower source structure LSC, a source sacrificial film SSF, and an upper source structure USC on a substrate (e.g., the substrate SUB in Figures 3b and 3c) or a sacrificial substrate (not shown) that includes peripheral circuits (e.g., the peripheral circuit structure PC in Figures 3b and 3c). The preliminary source structure pSC may further include at least one of a lower protective film LPL between the lower source structure LSC and the source sacrificial film SSF, and an upper protective film UPL disposed between the source sacrificial film SSF and the upper source structure USC. The preliminary source structure pSC may include upper surfaces extending in the X and Y directions that intersect each other.

[0078] Next, an insulating pattern IP can be formed that penetrates the preliminary source structure pSC. The insulating pattern IP can extend along the X direction. For example, the insulating pattern IP may be formed in a position that overlaps at least a portion of the second contact region PCTR shown in Figure 3a.

[0079] Next, a preliminary laminate STK can be formed on the preliminary source structure pSC and the insulating pattern IP. The preliminary laminate STK may include sacrificial films SF and interlayer insulating films IIL alternately stacked along the Z direction. For example, after stacking the interlayer insulating film IIL on the insulating pattern IP and the preliminary source structure pSC, the sacrificial film SF can be stacked on the interlayer insulating film IIL. The sacrificial film SF may have an etching selectivity ratio with respect to the interlayer insulating film IIL. In one embodiment, the interlayer insulating film IIL may contain an oxide such as a silicon oxide film, and the sacrificial film SF may contain a nitride such as a silicon nitride film.

[0080] Next, although not shown, cell plugs (e.g., cell plugs CPL in Figures 3a-3c) can be formed that penetrate the pre-laminated STK. For example, cell plugs can be formed in the cell region of the pre-laminated STK (e.g., cell region CR in Figure 3a). The cell plugs can penetrate the pre-laminated STK and extend into the interior of the pre-source structure pSC. For example, the cell plugs can penetrate the upper source structure USC and the source sacrificial film SSF.

[0081] Referring to Figure 6b, a staircase structure can be formed in the contact region of the pre-laminate STK (for example, the contact region CTR in Figure 3a) along the X and Y directions. A staircase structure can be formed by etching a portion of the pre-laminate STK. In one embodiment, the above staircase structure can be formed such that adjacent interlayer insulating film IIL and sacrificial film SF form a single staircase. For example, in Figure 6b, either one sacrificial film SF and the interlayer insulating film IIL in contact with the lower surface of the sacrificial film SF can correspond to either one staircase. Although Figure 6b shows only the staircase structure arranged along the Y direction among the staircase structures included in the pre-laminate STK, the pre-laminate STK can also include a staircase structure arranged along the X direction, as described in Figures 3c, 4a, 4b, 5a, and 5b.

[0082] Next, an upper insulating film UIL can be formed to cover the pre-laminate STK. The upper insulating film UIL can cover the stepped structure of the pre-laminate STK. For example, the upper insulating film UIL can cover the stepped structures in the X and Y directions included in the pre-laminate STK. Thus, the upper insulating film UIL can be in direct contact with the ends of each step included in the pre-laminate STK (e.g., the ends of the sacrificial film SF).

[0083] Referring to Figure 6c, a support pattern SP can be formed that penetrates the contact region of the pre-laminate STK (e.g., the contact region CTR in Figure 3a). Each support pattern SP may include sub-support patterns SSP1 to SSP4 extending in the X direction. At least one of the sub-support patterns SSP1 to SSP4 can be superimposed on at least a portion of a stepped structure along the Y direction. For example, the first sub-support pattern SSP1 and the fourth sub-support pattern SSP4 can be superimposed on the Y-direction ends of the sacrificial film SF. Furthermore, the sub-support patterns SSP1 to SSP4 can be formed such that no stepped structure along the Y direction is located between sub-support patterns SSP1 and SSP2, or SSP3 and SSP4, which are included in a single support pattern SP. For example, the Y-direction ends of the sacrificial film SF may not be located between the first sub-support pattern SSP1 and the second sub-support pattern SSP2. Also, the Y-direction ends of the sacrificial film SF may not be located between the third sub-support pattern SSP3 and the fourth sub-support pattern SSP4. However, a staircase structure along the X direction can also be located between sub-support patterns SSP1 and SSP2, or SSP3 and SSP4, which are included in a single support pattern SP.

[0084] By forming a support pattern SP in one region of the pre-laminate STK, the contact region of the pre-laminate STK (e.g., contact region CTR in Figure 3a) can be separated into a first contact region (e.g., first contact region GCTR in Figure 3a) and a second contact region (e.g., second contact region PCTR in Figure 3a). For example, the region between the first and second sub-support patterns SSP1 and SSP2 and the region between the third and fourth sub-support patterns SSP3 and SSP4 can become the second contact region (e.g., second contact region PCTR in Figure 3a). Furthermore, the region other than the second contact region (e.g., second contact region PCTR in Figure 3a) can become the first contact region (e.g., first contact region GCTR in Figure 3a). The second contact region (e.g., second contact region PCTR in Figure 3a) can be formed so as to be surrounded by the support pattern SP.

[0085] Referring to Figure 6d, an opening OP can be formed through the pre-laminate STK. The side surface of the source sacrificial film SSF can be exposed through the opening OP. The source sacrificial film SSF can be removed through the opening OP. Although not shown, a portion of the memory film (e.g., memory film ML in Figure 3b) of the cell plug (e.g., cell plug CPL in Figure 3b) can be removed through the opening OP. While a portion of the memory film ML is being removed through the opening OP, the upper protective film UPL and the lower protective film LPL can be removed. Next, an interlayer source structure FSC can be filled between the upper source structure USC and the lower source structure LSC through the opening OP. By filling with the interlayer source structure FSC, a source structure SC can be formed, which includes the upper source structure USC, the interlayer source structure FSC, and the lower source structure LSC.

[0086] Furthermore, a portion of the sacrificial film SF can be exposed through the opening OP. The sacrificial film SF exposed through the opening OP can be removed. For example, the sacrificial film SF located in the cell region CR and the first contact region GCTR in Figure 3a can be removed. The conductive film CD can then be filled into the space where the sacrificial film SF was removed through the opening OP.

[0087] While a portion of the sacrificial film SF is removed, other portions of the sacrificial film SF that are not exposed through the opening OP can remain. For example, the sacrificial film SF located in the second contact region PCTR in Figure 3a can not be removed because it is surrounded by the support pattern SP. The sacrificial film located between the first sub-support pattern SSP1 and the second sub-support pattern SSP2 can not be removed. Also, the sacrificial film located between the third sub-support pattern SSP3 and the fourth sub-support pattern SSP4 can not be removed.

[0088] Therefore, a portion of the pre-laminated stack STK can become a gate stack GST containing a conductive film CD and an interlayer insulating film IIL, while the other portion of the pre-laminated stack STK can become a dummy stack DST containing a sacrificial film SF and an interlayer insulating film IIL. Referring to Figure 6d, the dummy stack DST does not include a stepped structure aligned along the Y direction, while the gate stack GST may include a stepped structure aligned along the Y direction. For example, the dummy stack DST may not include a stepped structure aligned along the Y direction because the support patterns SP are formed so that the regions enclosed by each support pattern SP (e.g., the second contact region PCTR in Figure 3a) do not overlap with a stepped structure aligned along the Y direction. Also, the gate stack GST may include a stepped structure aligned along the Y direction because the support patterns SP are formed so that the regions not enclosed by each support pattern SP (e.g., the first contact region GCTR in Figure 3a) overlap with a stepped structure aligned along the Y direction. Although not shown, both the gate stack GST and the dummy stack DST may include a stepped structure aligned along the X direction.

[0089] After a portion of the sacrificial film SF is replaced by the conductive film CD through the opening OP, a slit SLI can be formed inside the opening OP. The slit SLI may contain at least one material filled inside the opening OP.

[0090] Referring to Figure 6e, a second contact PCT can be formed that penetrates the dummy laminate DST. The second contact PCT can penetrate the upper insulating film UIL, the dummy laminate DST, and the insulating pattern IP. The second contact PCT can be in direct contact with a peripheral circuit structure located below the insulating pattern IP (e.g., the peripheral circuit structure PC in Figures 3b and 3c).

[0091] Figure 7 is a diagram illustrating a memory card system to which the memory device of the present invention is applied.

[0092] Referring to Figure 7, the memory card system 3000 includes a controller 3100, a memory device 3200, and a connector 3300.

[0093] The controller 3100 can be connected to the memory device 3200. The controller 3100 can be configured to access the memory device 3200. For example, the controller 3100 can be configured to control the program, read, or erase operations of the memory device 3200, or to control background operations. The controller 3100 can be configured to provide an interface between the memory device 3200 and the host. The controller 3100 can be configured to drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0094] The controller 3100 can communicate with an external device via the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller 3100 is configured to communicate with an external device via at least one of various communication standards such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, or NVMe. For example, the connector 3300 can be defined by at least one of the various communication standards mentioned above.

[0095] The memory device 3200 can include multiple memory cells and can be configured similarly to the memory device 100 shown in Figure 1.

[0096] The controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to constitute a memory card. For example, the controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to constitute a memory card such as a PC card (PCMCIA, personal computer memory card international association), CompactFlash® card (CF), SmartMedia card (SM, SMC), Memory Stick, Multimedia card (MMC, RS-MMC, MMCmicro, eMMC), SD card (SD, miniSD, microSD, SDHC), or general-purpose flash memory (UFS).

[0097] Figure 8 is a diagram illustrating an SSD (Solid State Drive) system to which the memory device of the present invention is applied.

[0098] Referring to Figure 8, the SSD system 4000 can include a host 4100 and an SSD 4200. The SSD 4200 can send and receive signals with the host 4100 via a signal connector 4001 and can receive power input via a power connector 4002. The SSD 4200 can include a controller 4210, a plurality of memory devices 4221-422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0099] The controller 4210 can control multiple memory devices 4221-422n in response to signals received from the host 4100. For example, the signals may be based on the interface between the host 4100 and the SSD 4200. For example, the signals may be defined by at least one of the following interfaces: USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, or NVMe.

[0100] Multiple memory devices 4221-422n can include multiple memory cells configured to store data. Each of the multiple memory devices 4221-422n can be configured similarly to memory device 100 shown in Figure 1. Multiple memory devices 4221-422n can communicate with controller 4210 via channels CH1-CHn.

[0101] The auxiliary power supply unit 4230 can be connected to the host 4100 via the power connector 4002. The auxiliary power supply unit 4230 can be charged by receiving a power supply voltage input from the host 4100. If the power supply from the host 4100 is not smooth, the auxiliary power supply unit 4230 can provide power to the SSD 4200. For example, the auxiliary power supply unit 4230 may be located inside the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply unit 4230 can be located on the main board and provide auxiliary power to the SSD 4200.

[0102] The buffer memory 4240 can operate as a buffer memory for the SSD 4200. For example, the buffer memory 4240 can temporarily store data received from the host 4100 or data received from multiple memory devices 4221-422n, or it can temporarily store metadata (e.g., mapping tables) of the memory devices 4221-422n. The buffer memory 4240 may contain volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, or non-volatile memory such as FRAM®, ReRAM, STT-MRAM, or PRAM. [Explanation of Symbols]

[0103] GST gate stack CD conductive film IIL Interlayer Insulation Film DST Dummy Laminate SF sacrificial membrane GCTR 1st Contact Area PCTR Second Contact Area SLI Slit SP support pattern SSP Sub-support Pattern SC Source Structure USC Upper Source Structure FSC interlayer source structure LSC Lower Source Structure IP isolation pattern

Claims

1. A laminated structure that extends in a first direction from a cell region to a contact region and includes a laminated layer, and includes a stepped structure that includes the end of the laminated layer and is arranged along a second direction intersecting the first direction, The laminated structure includes a support pattern that penetrates the above-mentioned layered structure and separates the contact region into a first contact region connected to the cell region and a second contact region separated from the cell region, Each of the above support patterns extends in the first direction and includes sub-support patterns that are in contact with both sides of the second contact region. Any one of the above sub-support patterns is superimposed on at least one of the above ends of the laminated layer. The above-mentioned staircase structure is not positioned between the above-mentioned sub-support patterns, and is a memory device.

2. The memory device according to claim 1, wherein the above-mentioned staircase structure is arranged along the first direction and the second direction.

3. The laminated structure includes gate laminates arranged in the cell region and the first contact region, The above-mentioned laminated layer includes conductive films and interlayer insulating films alternately laminated in the cell region and the first contact region. The memory device according to claim 1, wherein a source structure is arranged at the lower part of the gate stack described above.

4. The memory device according to claim 3, further comprising a cell plug that penetrates the gate stack in the cell region and contacts the source structure.

5. The memory device according to claim 3, further comprising a first contact connected to at least one of the conductive films in the first contact region.

6. The laminated structure includes a dummy laminate disposed in the second contact region, The above-mentioned laminated layer includes a sacrificial film and an interlayer insulating film that are alternately laminated in the second contact region. An insulating pattern is placed at the bottom of the above dummy laminate. The memory device according to claim 1, wherein a peripheral circuit structure is arranged below the above-mentioned insulating pattern.

7. The memory device according to claim 6, further comprising a second contact that penetrates the dummy laminate and the insulating pattern and is connected to the peripheral circuit structure.

8. The memory device according to claim 1, wherein the first contact region is superimposed on the end of the laminated layer.

9. The above-mentioned first contact area is, The memory device according to claim 1, wherein the second contact region is located in the second direction and the direction opposite to the second direction, with the support pattern in between.

10. The memory device according to claim 3, wherein the widths of at least a portion of the conductive film included in the first contact region in the second direction are different from each other.

11. The memory device according to claim 6, wherein the widths of the sacrificial film included in the second contact region in the second direction are equal to each other.

12. A step of forming a pre-laminate containing first and second material films, The steps include forming cell plugs in the cell regions of the above-mentioned pre-laminated structure, The steps include forming a step structure in a contact region extending in a first direction from the cell region, arranged along a second direction intersecting the first direction, The step of forming a support pattern that includes sub-support patterns that penetrate the above-mentioned contact region and extend in the above-mentioned first direction, thereby separating the contact region into a first contact region and a second contact region surrounded by the above-mentioned support pattern, In the step of forming the above support pattern, A method for manufacturing a memory device, wherein one of the above sub-support patterns is superimposed on at least a portion of the above-mentioned staircase structure, and the above-mentioned second contact region is formed so as not to superimpose on the above-mentioned staircase structure.

13. Before the step of forming the above-mentioned pre-laminate, The step of forming a preliminary source structure, A method for manufacturing a memory device according to claim 12, further comprising the step of forming an insulating pattern that penetrates the above-mentioned preliminary source structure.

14. After the step of separating the above contact area into the first contact area and the second contact area, The steps include forming a slit that penetrates the above-mentioned pre-laminated structure, A step of removing the second material film from the cell region and the first contact region exposed through the slit, The method for manufacturing a memory device according to claim 12, further comprising the step of filling the space from which the second material film has been removed with a third material film to form a gate laminate.

15. In the step of forming the gate stack described above, The method for manufacturing a memory device according to claim 14, wherein the gate stack in the first contact region is formed to include the stepped structure arranged along the second direction.

16. In the step of removing the second substance film described above, The method for manufacturing a memory device according to claim 14, wherein the second material film in the second contact region remains to form a dummy laminate.

17. In the step of forming the above-mentioned dummy laminate, The method for manufacturing a memory device according to claim 16, wherein the dummy laminate in the second contact region is formed so as not to include the stepped structure arranged along the second direction.

18. After the step of forming the dummy laminate described above, The method for manufacturing a memory device according to claim 16, further comprising the step of forming peripheral circuit connection contacts that penetrate the dummy laminate in the second contact region described above.

19. In the step of forming the above support pattern, The method for manufacturing a memory device according to claim 12, wherein the first contact region is formed to overlap the stepped structure.

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