Computer implementation method for defect recognition in wafer imaging datasets, corresponding computer-readable medium, computer program product, and system using such method.

Abstract

The present invention relates to a computer-implemented method for defect recognition in an imaging dataset of a wafer in a charged particle beam system (78) having an embedded system (50), the method including: (i) acquiring the imaging dataset of the wafer; (ii) acquiring model data (44, 44', 44'') for a model architecture (42) of a machine learning model (40, 40', 40'') for defect recognition in the imaging dataset of the wafer, where the model architecture (42) is implemented in the embedded system (50); (iii) transferring the model data to a programmable memory (48, 48', 48'') of the embedded system; and (iv) running the embedded system-implemented model architecture (46) using the transferred model data to apply the machine learning model to the imaging dataset of the wafer to recognize defects.

Description

Technical Field

[0001] Related Applications This application claims the benefit of German Patent Application No. 102022124580.2, filed on September 23, 2022, which is incorporated herein by reference in its entirety.

[0002] The present invention relates to systems and methods for quality control and quality assurance of semiconductor structures, and more particularly, to a computer-implemented method, a computer-readable medium, and a corresponding system for defect recognition in an imaging data set of a wafer with improved throughput. This method, computer-readable medium, and system are based on the implementation of a general machine learning model in an embedded system. This method can be used for quantitative measurement, defect recognition, defect detection, defect classification, defect localization, or defect re-inspection of integrated circuits in a semiconductor wafer, or for process monitoring, process improvement, quality control, or quality assurance during the manufacture of a semiconductor wafer.

Background Art

[0003] Semiconductor manufacturing involves precise manipulation of materials such as silicon or oxides at very fine scales within the nm range, for example, etching. Therefore, in order to ensure high quality standards for the manufactured wafers, a quality control process including quality assurance and quality control is important. Quality assurance refers to a series of activities for ensuring high-quality products by preventing defects that may occur in the development process. Quality control refers to a system for inspecting the final quality of a product. Quality control is part of the quality assurance process.

[0004] Wafers, made from thin slices of silicon, serve as substrates for microelectronic devices containing semiconductor structures built within and on the wafer. These semiconductor structures are constructed layer by layer using repeated processing steps, including repeated chemical, mechanical, thermal, and optical processes. The dimensions, shape, and arrangement of semiconductor structures and patterns are influenced by multiple factors. For example, critical processes in the manufacturing of 3D memory devices are currently etching and deposition. Other involved process steps, such as lithography exposure or injection, can also affect the properties of integrated circuit elements. Therefore, the manufactured semiconductor structures are adversely affected by various imperfections, though rare. Devices for quantitative measurement, defect detection, or defect reinvestigation look for these imperfections. These devices are not only needed during wafer manufacturing. Because this process is complex and highly nonlinear, optimizing manufacturing process parameters is difficult. As a solution, an iterative approach called process window qualification (PWQ) can be applied. In each iteration, different dies on the wafer are exposed to different manufacturing conditions to produce a test wafer based on the best current process parameters. By detecting and analyzing defects in various dies based on a quality assurance process, the best manufacturing process parameters can be selected. In this way, the manufacturing process parameters can be fine-tuned toward optimality. Subsequently, high-precision quality control processes and devices are required for the metrology semiconductor structures within the wafer.

[0005] Therefore, recognized defects are used in root cause analysis. Recognized defects can serve as feedback to improve process parameters of the manufacturing process, such as exposure time and focus variations, during quality assurance, or they can help ensure the quality of the manufactured wafers during quality control. For example, a bridge defect may indicate insufficient etching, a break may indicate excessive etching, consistently occurring defects may indicate a defective mask, and missing structures may suggest the deposition of an unsuitable material, and so on.

[0006] The semiconductor structures that are manufactured are based on prior knowledge. Semiconductor structures are manufactured from a series of layers parallel to the substrate. For example, in logic type samples, metal wires run parallel within metal layers or HAR (high aspect ratio) structures, and metal vias run perpendicular to the metal layers. The angle between metal wires in different layers is either 0° or 90°. On the other hand, in the case of VNAND type structures, their cross-sections are known to be circular on average. Furthermore, a semiconductor wafer has a diameter of 300 mm and is composed of multiple parts, so-called dies, each of which contains at least one integrated circuit pattern, such as a memory chip or a processor chip. During manufacturing, a semiconductor wafer goes through approximately 1000 process steps, and within the semiconductor wafer, more than 100 parallel layers are formed, including transistor layers, intermediate layers between wires, and interconnect layers, and in memory devices, more than 100 including multiple 3D arrays of memory cells.

[0007] The aspect ratio and number of layers in integrated circuits are constantly increasing, and structures are growing into a third (vertical) dimension. The current height of memory stacks exceeds 12 microns. In contrast, feature sizes are decreasing. The minimum feature size or limiting dimension is less than 10 nm, e.g., 7 nm or 5 nm, and in the near future, it will approach feature sizes of less than 3 nm. While the complexity and dimensions of semiconductor structures are growing into a third dimension, the lateral dimensions of integrated semiconductor structures are decreasing. Therefore, measuring the shape, dimensions, and orientation of features and patterns in 3D, as well as their superposition, with high precision becomes difficult. The lateral measurement resolution of charged particle systems is typically limited by the sampling raster of individual image points or the residence time per pixel on the sample, and the diameter of the charged particle beam. The sampling raster resolution can be set within the imaging system and can be adapted to the diameter of the charged particle beam on the sample. While standard raster resolution is less than 2 nm, the limit of raster resolution can be reduced without physical constraints. The diameter of a charged particle beam has limited dimensions that depend on the operating conditions of the charged particle beam and the lens. The beam resolution is limited to about half the beam diameter. The lateral resolution can be less than 2 nm, and can even be less than 1 nm, for example.

[0008] One important task in semiconductor inspection is determining a specific set of parameters of a semiconductor object, such as a high aspect ratio (HAR) structure within the inspection volume. Such parameters may be, for example, dimensions, area, shape, or other measurement parameters. Typically, conventional measurement tasks involve multiple computational steps, such as object detection, feature extraction, and any kind of measurement operation, e.g., calculating distance, radius, or area from extracted features. Each of these many steps requires a large amount of computation.

[0009] Generally, semiconductors contain many repetitive three-dimensional structures. During the manufacturing process or process development, selected physical or geometric parameters of some of several representative three-dimensional structures need to be measured with high accuracy and high throughput. To monitor manufacturing, an inspection volume containing several representative three-dimensional structures is defined. This inspection volume is then analyzed, for example, by slicing and imaging techniques, leading to a high-resolution 3D volumetric image of the inspection volume obtained by slicing and imaging multiple cross-sectional surfaces within the inspection volume.

[0010] The multiple repetitive three-dimensional structures within the inspection volume can exceed hundreds or even thousands of individual structures. This generates a vast number of cross-sectional images; for example, if at least 100 three-dimensional structures are examined by 100 cross-sectional image slices, the number of measurements performed can easily reach over 10,000.

[0011] In addition, current technologies such as multi-beam scanning electron microscopy (SEM) can be used to image large areas of a wafer surface quickly and with high resolution. For this purpose, multi-beam SEM uses multiple single beams in parallel, each beam covering a different portion of the surface, with pixel sizes down to 2 nm. The resulting datasets are enormous and cannot be analyzed manually.

[0012] Machine learning methods can be used to analyze large amounts of data that require extensive measurement. Machine learning methods are well-suited for analyzing large datasets while minimizing user interaction.

[0013] Machine learning is a field of artificial intelligence. Machine learning methods generally involve building parametric machine learning models based on training data consisting of a large number of samples. After training, this method generalizes the knowledge gained from the training data to new samples that have not been encountered before, thereby enabling predictions on new data. There are many machine learning methods, such as linear regression, k-means, neural networks, or deep learning techniques.

[0014] Deep learning is a type of machine learning that uses artificial neural networks modeled after the human brain, containing numerous hidden layers between input and output layers. This vast internal structure allows these networks to gradually extract high-level features from raw input data. Each level learns to transform the input data into slightly more abstract and complex representations, thus deriving both low- and high-level knowledge from the training data. Hidden layers can have different sizes and tasks, such as convolutional layers, pooling layers, or fully connected layers.

[0015] During quality control and quality assurance, algorithm speed is a critical factor in achieving high wafer throughput. To obtain high-speed algorithms, embedded systems can be used to implement machine learning models for quality assurance and quality control of acquired wafer imaging datasets.

[0016] For example, US2021 / 0097673A1 and US2021 / 0158498A1 both disclose machine learning models for defect recognition in wafer imaging datasets, which can be implemented using embedded systems such as FPGAs.

[0017] For software running on conventional processors, numerous pre-programmed libraries are available to minimize programming effort and time. This is not the case for embedded systems. Furthermore, each software update requires reprogramming of the embedded system. Therefore, programming embedded systems requires considerable programming effort and time. [Overview of the Initiative] [Problems that the invention aims to solve]

[0018] Therefore, an object of the present invention is to provide a method for obtaining a versatile machine learning model on an embedded system that can be reused for various use cases or various imaging datasets. Another object of the present invention is to reduce the effort, time, and resources required to program a machine learning model on an embedded system for defect recognition in a wafer imaging dataset. Another object of the present invention is to reduce the computation time of the machine learning model. Another object of the present invention is to adapt the machine learning model on an embedded system to a wafer quality control or quality assurance process. A further object of the present invention is to improve throughput during a wafer quality control or quality assurance process. Another object of the present invention is to minimize the execution time of a wafer quality control or quality assurance process. In general, an object of the present invention is to provide a wafer inspection method for measuring semiconductor structures in an inspection volume with high throughput and high accuracy. An object of the present invention is to provide a generalized wafer inspection method for measuring semiconductor structures in an inspection volume that can be quickly adapted to changes in the measurement task, measurement system, or the semiconductor object under consideration. A further object of the present invention is to provide a fast, robust, and reliable measurement method for a set of parameters representing a semiconductor structure in an inspection volume with high accuracy and reduced measurement artifacts. Finally, an objective of the present invention is to enable a new business model for selling systems that include machine learning algorithms.

[0019] These objectives are achieved by the present invention as specified in the independent claims. Advantageous embodiments and further developments of the present invention are specified in the dependent claims. [Means for solving the problem]

[0020] Embodiments of the present invention relate to a computer implementation method, a computer-readable medium, and a system for implementing a machine learning model on an embedded system for defect recognition in an image dataset of a wafer.

[0021] A first embodiment includes a computer-implemented method for defect recognition in an imaging dataset of wafers in a charged particle beam system having an embedded system, the method comprising: (i) acquiring an imaging dataset of wafers; (ii) acquiring model data for a machine learning model architecture for defect recognition in the imaging dataset of wafers, wherein the model architecture is implemented in the embedded system; (iii) transferring the model data to the programmable memory of the embedded system; and (iv) applying the machine learning model to the imaging dataset of wafers to recognize defects, including running the embedded system implemented model architecture using the transferred model data. The recognized defects can be used, for example, in a quality assurance system and / or a quality control system, particularly for wafers, but can also be used for other manufactured objects.

[0022] A machine learning model is the result of a machine learning method applied to training data. This model represents what has been learned by the machine learning method. It includes the model architecture, model data, and prediction method.

[0023] Model architecture typically includes so-called hyperparameters that define the design or structure of a machine learning model, which are not usually learned from the training data. Hyperparameters can be defined by the user, for example, or obtained using the AutoML method. Hyperparameters for a neural network include, for example, the number of layers, layer size, filter type, optimizer, and upsampling scheme. Hyperparameters for a decision tree include, for example, the number of tree levels and the number of decision nodes at each tree level. Hyperparameters for a support vector machine include, for example, the number and format of hyperplanes. Hyperparameters for a clustering method include, for example, the number of clusters.

[0024] Model data includes a data structure specific to rules, numerical values, or any other method required to make predictions for new data samples. Model data is learned from training data. The model data of a neural network includes, for example, weights learned from training data. The model data of a decision tree includes, for example, the specific decisions made at each node learned from training data. The model data of a support vector machine includes, for example, matrices and vectors that define a specific hyperplane learned from training data. The model data of a clustering method includes, for example, specific cluster positions learned from training data.

[0025] A prediction method is a procedure that shows how to make predictions for new data using model data. The application of a machine learning method or machine learning model to an imaging data set means the application of a prediction method based on a trained model that includes a model architecture and model data to the imaging data set.

[0026] By separating the model architecture from the learned model data, the model architecture can be implemented on an embedded system to obtain short execution times and high throughput. On the other hand, the learned model data in the programmable memory of the embedded system can be dynamically updated. In this way, the machine learning model on the embedded system can be adapted to various use cases or, for example, retrained to prepare for various imaging data sets. Various imaging data sets can occur, for example, when the image acquisition conditions change or the imaging data set is modified. Furthermore, the implementation effort for the user is reduced.

[0027] The second embodiment of the present invention relates to a computer-implemented method for defect recognition in an imaging data set of a wafer in a charged particle beam system comprising at least one embedded system, the method comprising: (i) acquiring an imaging data set of the wafer; (ii) defining an embedded system implementation model architecture of a machine learning model for defect recognition in the imaging data set of the wafer by specifying the flow of data through some of a plurality of logic block circuits in one of the at least one embedded system, the plurality of logic block circuits including one or more modules of at least one model architecture of at least one machine learning model for defect recognition; (iii) acquiring model data of the embedded system implementation model architecture; (iv) transferring the model data to a programmable memory of the embedded system; (v) applying the machine learning model to the imaging data set of the wafer to recognize defects, including executing the embedded system implementation model architecture using the transferred model data.

[0028] The recognized defects can be used, for example, in a quality assurance system and / or in a quality control system, particularly for wafers, but can also be used for other manufactured objects. Due to the modularity of the model architecture, different modules can be combined to form new model architectures and previously implemented modules can be reused in different model architectures, making the implementation of machine learning models on embedded systems even more flexible and versatile. In this way, not only the model data but also the model architecture can be dynamically changed or adapted to different use cases without requiring a large implementation effort.

[0029] Throughout this document, the term "some" elements refers to a single element, multiple elements, or all elements.

[0030] In the embodiments of the first or second embodiment, the machine learning model for defect recognition in the wafer imaging dataset is from the group including defect detection models, defect classification models, defect location models, defect segmentation models, anomaly detection models, anomaly classification models, anomaly location models, and anomaly segmentation models.

[0031] An anomaly refers to a deviation of a semiconductor structure from a pre-defined standard. Generally, defects are also anomalies, but not all anomalies are defects. For example, anomalies can occur due to noise or rare structures in the imaging dataset.

[0032] Charged particle beam systems include, but are not limited to, scanning electron microscopes (SEMs) and focused ion beam microscopes such as helium ion microscopes. A further example of a charged particle beam system is a corrected scanning electron microscope that includes corrective means for correcting chromatic and spherical aberrations.

[0033] In various embodiments of the present invention, the embedded system can be a field-programmable gate array (FPGA), a digital signal processor (DSP), an arithmetic logic unit (ALU), an application-specific integrated circuit (ASIC), and the like.

[0034] In various embodiments of the present invention, the machine learning model for defect recognition in the acquired imaging dataset of a wafer may be from the group including defect detection models, defect classification models, defect localization models, defect segmentation models, anomaly detection models, anomaly classification models, anomaly localization models, and anomaly segmentation models.

[0035] In an embodiment of the second embodiment, at least one model architecture of at least one machine learning model for defect recognition includes a neural network model architecture.

[0036] According to an embodiment of the second embodiment, one or more modules are head modules, and the head modules are modules that include the output layer of a neural network.

[0037] For example, one or more head modules may include the fully connected output layer and / or the convolutional output layer of a neural network.

[0038] Furthermore, one or more modules can be tail modules, which are modules that contain several hidden layers of the neural network.

[0039] In one embodiment, at least one tail module, in particular each tail module, contains all the hidden layers of the neural network.

[0040] In another embodiment, at least one tail module, and in particular each tail module, includes several hidden layers that form a semantic entity. The term “semantic entity” refers to several hidden layers that complement each other and together perform a specific function within the neural network, forming a functional unit.

[0041] The subdivision of the model architecture into head and tail modules significantly reduces the programming and application effort for the user. The head module contains the output layer of the neural network and is therefore a task-specific module. By swapping the head module with another module, the task of the neural network can be changed; for example, a defect detection model architecture containing a convolutional output layer can become a defect classification model architecture containing a fully connected output layer.

[0042] A tail module contains several hidden layers of a neural network. By swapping tail modules, the size of the feature maps of the hidden layers can be easily adapted between small and large problems that require fewer or more features to produce satisfactory results. Thus, according to a further embodiment of the second embodiment, at least two of the tail modules contain the same number of hidden layers, and the size of the feature maps of the corresponding hidden layers differs by the same multiple.

[0043] According to a further embodiment of the second embodiment, each of the one or more modules is either a head module containing the output layer of a neural network, or a tail module containing several hidden layers of a neural network.

[0044] Head modules and tail modules can be generated from a neural network by dividing the neural network into one or more sets of output layers and hidden layers. One or more modules can be generated from at least one model architecture of a neural network by dividing each model architecture into a head module containing the output layers of the neural network and at least one tail module containing several hidden layers of the neural network. In particular, each model architecture of a neural network can be divided into a task-specific head module and a single tail module, which allows for particularly little effort in specifying the flow of data through this number of modules.

[0045] In an embodiment of the second embodiment, the method may further include determining whether the model architecture of a machine learning model can be implemented by multiple logic blocks in at least one of the embedded systems, before specifying the flow of data through some of the multiple logic blocks; generating one or more modules of the model architecture of the machine learning model in response to determining that the model architecture cannot be implemented; and implementing the said one or more modules in at least one of the embedded systems. In this way, the number of modules and embedded system-implemented model architectures increases with the number of use cases, and the system becomes increasingly flexible and versatile.

[0046] In the embodiments of the first or second embodiment, the model data for the embedded system implementation model architecture is obtained by training a machine learning model that includes the aforementioned model architecture. In addition, or alternatively, the model data for the embedded system implementation model architecture may be read from a database. In addition, or alternatively, the model data for the embedded system implementation model architecture may also be provided by an external service that creates a new business model. The new business model provides a one-time sale of a system having the embedded system implementation model architecture, and periodic updates of the model data as a service, for example, to improve defect recognition results or to adapt the system to different use cases.

[0047] In embodiments of the first and second embodiments, the model data is transferred to the programmable memory of the embedded system by copying. Alternatively, the model data may be transferred to the programmable memory of the embedded system by replacing the hardware block containing the programmable memory of the embedded system with a new hardware block containing the model data to be transferred.

[0048] In any embodiment or aspect of the first and second embodiments, for quality assurance or quality control, recognized defects may be monitored, for example, in real time or buffered. For this purpose, recognized defects may be directed to a display device or dashboard. In addition, or alternatively, recognized defects may be stored in long-term memory. In addition, or alternatively, recognized defects may be cached in memory. Recognized defects may also be analyzed to update the embedded system implementation model architecture in step (ii).

[0049] A third embodiment of the present invention includes a computer implementation method according to any one of the embodiments or examples of the first or second embodiment of the present invention, the computer implementation method comprising the steps of: selecting at least one imaging acquisition parameter according to an imaging sampling strategy until a convergence criterion is met before acquiring an imaging dataset of a wafer in step (i); acquiring an imaging dataset of a wafer based on the aforementioned at least one imaging acquisition parameter; generating training data from the acquired imaging dataset of a wafer; selecting a model architecture and training a related machine learning model based on the generated training data; determining the quality of the model architecture and at least one imaging acquisition parameter by calculating a related objective function value of an objective function that evaluates the quality of the trained machine learning model; and after these iterations, selecting one of the model architectures and the corresponding at least one imaging acquisition parameter based on the objective function value, wherein the imaging dataset of a wafer in step (i) is acquired based on the selected at least one imaging acquisition parameter, and the embedded system implementation model architecture in step (ii) includes the model architecture of the selected machine learning model. In this way, the image acquisition process is optimized with respect to criteria defined by the objective function, such as system throughput, execution time of the defect detection method, or system power consumption.

[0050] A fourth embodiment of the present invention relates to a computer implementation method for defect recognition in a wafer imaging dataset, the method comprising: iterating through the steps of: selecting at least one image acquisition parameter according to an imaging sampling strategy and acquiring a wafer imaging dataset based on the aforementioned at least one image acquisition parameter until a convergence criterion is met; generating training data from the acquired wafer imaging dataset; selecting a model architecture and training a relevant machine learning model based on the generated training data; evaluating the quality of the trained machine learning model by calculating a relevant objective function value for the objective function; after the last iteration, selecting one of the trained machine learning models based on the objective function value; and applying the selected trained machine learning model to the wafer imaging dataset acquired based on the corresponding at least one image acquisition parameter in order to recognize defects.

[0051] According to the third or fourth embodiment, at least one image acquisition parameter is from the group including, for example, imaging time, image resolution, pixel size, electron wave landing energy, and residence time.

[0052] In embodiments of the third or fourth embodiment, the step of selecting a model architecture includes selecting at least one hyperparameter that defines the model architecture of the machine learning model, for example using an automated machine learning (AutoML) technique, according to an architecture sampling strategy. This procedure is advantageous because the image acquisition process is optimized together with the hyperparameter of the machine learning model with respect to the objective function.

[0053] In the third or fourth embodiment, the objective function includes a measure of the complexity of the model architecture. In further embodiments, the objective function includes a measure of execution time, as well as / or a measure of throughput and / or data rate, as well as / or a measure of power consumption. In further embodiments, the objective function includes a measure of the quality of defect detection. In further embodiments, the objective function includes a measure of the bit size of the input data for the machine learning model. By selecting one or more of these measures in the objective function, it is possible to reduce the complexity of the architecture and, therefore, reduce the system execution time or improve throughput.

[0054] An embodiment of any aspect or any embodiment further includes determining one or more measurements of defects recognized in the imaging dataset of a wafer, in particular size, area, dimension, shape parameter, distance, radius, aspect ratio, type, number of defects, density, spatial distribution of defects, presence of any defects (i.e., whether a defect is detected), etc. Based on one or more of these measurements, the embodiment may further include evaluating the quality of the wafer based on one or more measurements and at least one quality evaluation rule. Based on one or more measurements, the embodiment may include controlling at least one wafer manufacturing process parameter based on one or more measurements of defects recognized in the imaging dataset of a wafer. The wafer manufacturing process parameter includes, but is not limited to, exposure time, etching, deposition, injection, heat treatment, and parameters of other processes involved during manufacturing. Other defects arise from defects or contamination from various sources, e.g., from modification or particle contamination of the lithography mask.

[0055] The present invention also includes a computer-readable medium storing a computer program executable by a computing device, the computer program including code for performing a method according to any aspect or embodiment of the invention.

[0056] The present invention also relates to a computer program product that includes instructions, which, when the program is executed by the computer, cause the computer to perform a method according to either an embodiment or an example of the present invention.

[0057] The present invention also relates to a system for managing the quality of wafers manufactured in a semiconductor manufacturing plant, the system comprising an imaging device adapted to provide an imaging dataset of wafers, one or more processing devices, optionally at least one embedded system, and one or more machine-readable hardware storage devices containing instructions executable by one or more processing devices to perform operations including a method for evaluating the quality of wafers.

[0058] The present invention also includes a system for controlling the manufacturing of wafers in a semiconductor manufacturing plant, the system comprising means for manufacturing wafers controlled by at least one manufacturing process parameter, an imaging device adapted to provide an imaging dataset of wafers, one or more processing devices, optionally an embedded system or module implementing a model architecture of a machine learning model for defect recognition in the aforementioned imaging dataset of wafers, wherein the embedded system or module comprises a programmable memory for transferring model data to the embedded system, and one or more machine-readable hardware storage devices containing instructions executable by one or more processing devices to perform operations including a method for controlling at least one wafer manufacturing process parameter.

[0059] Any of the above systems may include a database, a display device, and / or a user interface.

[0060] Although the embodiments and examples of the present invention have been described in relation to semiconductor wafers, it should be understood that the present invention is not limited to semiconductor wafers and may also be applied to, for example, reticles or masks for semiconductor manufacturing or other manufactured objects.

[0061] The present invention, as described by the examples and embodiments, is not limited to those embodiments and embodiments, but can be carried out by those skilled in the art in various combinations or modifications thereof. [Brief explanation of the drawing]

[0062] [Figure 1] This figure shows the schematic cell structure of an imaging dataset from a wafer with three defects. [Figure 2] This figure shows a flowchart of the steps in an exemplary computer implementation method for defect recognition according to a first embodiment of the present invention. [Figure 3] This figure shows the use of model architecture and model data isolation for flexible implementation of machine learning models into embedded systems. [Figure 4] This figure shows a flowchart of the steps in an exemplary computer implementation method for defect recognition according to a second embodiment of the present invention. [Figure 5] This figure illustrates a particularly flexible and versatile method for implementing machine learning models in systems that have at least one embedded system. [Figure 6] This diagram illustrates the use of embedded systems in the form of FPGAs in various use cases based on the separation of hardware-related and software-related components. [Figure 7] This figure shows a schematic implementation of the first and second modules of the neural network model architecture. [Figure 8] This diagram shows the subdivision of the model architecture in the form of a neural network into head modules and tail modules. [Figure 9] This diagram shows different head and tail modules for various model architectures. [Figure 10] This figure shows a process for implementing new use cases in a system by computer implementation according to various embodiments of the present invention. [Figure 11] This figure shows a flowchart of the steps in an exemplary computer implementation method for defect recognition according to a third embodiment of the present invention. [Figure 12] This figure shows a flowchart of the steps in an exemplary computer implementation method for defect recognition according to a third embodiment of the present invention. [Figure 13] This figure shows a flowchart of the steps in an exemplary computer implementation method for defect recognition according to a third embodiment of the present invention. [Figure 14] This figure shows a flowchart of the steps in an exemplary computer implementation method for defect recognition according to a fourth embodiment of the present invention. [Figure 15] This figure shows a system that can be used to control the quality of wafers manufactured in a semiconductor manufacturing plant. [Figure 16] This figure shows a system that can be used to control the manufacturing of wafers in a semiconductor manufacturing plant. [Figure 17] This figure shows a system that can be used to control the quality of wafers manufactured in a semiconductor manufacturing plant. [Figure 18] This figure shows a system that can be used to control the manufacturing of wafers in a semiconductor manufacturing plant. [Modes for carrying out the invention]

[0063] Advantageous embodiments of the present invention are described below and schematically illustrated in the figures. Throughout the figures and description, the same reference numerals are used to describe the same features or components.

[0064] Figure 1 shows the schematic cell structures 10, 10', and 10'' of imaging datasets 12, 12', and 12'' of three defect measurement sites on wafer 226. In this schematic diagram, cells 14, 14', and 14'' are identical and regularly distributed across each of the imaging datasets 12, 12', and 12''. The cell structures 10, 10', and 10'' include defects 16 such as "open," "atrophied," or "merged," i.e., deviations of the semiconductor structure from a priori defined criteria. Recognizing defects 16 in the imaging datasets 12, 12', and 12' of wafer 226 is important for quality control and quality assurance processes. Quality assurance ensures that the techniques, technologies, methods, and processes for wafer manufacturing are carried out according to requirements. Quality assurance aims to improve the parameters or conditions of wafer manufacturing processes in the manufacturing plant, such as the deposition process, exposure process, and etching process. For this purpose, known and unknown defects must be recognized and analyzed. In contrast, quality control aims to guarantee the quality of the final manufactured product in the in-line manufacturing process. For this purpose, known defects must be identified and analyzed.

[0065] Machine learning models can be used to process vast amounts of data containing various known and unknown defects, requiring only limited user interaction.

[0066] A machine learning model is the result of a machine learning method performed on training data. A machine learning model represents what has been learned by the machine learning method. A machine learning model includes a model architecture, model data, and prediction methods. The model architecture includes a generalized structure or design of the machine learning model, defined by hyperparameters, such as neurons in a neural network and the connections between them. The model data includes data structures specific to values, numbers, or any other method, through which a generalized structure is embodied to solve a particular machine learning problem and to make predictions for new data samples, such as the weights of a neural network. The prediction method is a procedure that shows how to make predictions for new data using the model data, such as a forward-pass algorithm for a neural network. Applying a machine learning method or machine learning model to data means applying a prediction method based on the trained model to the data.

[0067] Machine learning models in various embodiments of the present invention can be any type of machine learning model, including, but not limited to, decision tree-based models, linear regression-based models, neural network-based models, Bayesian network-based models, support vector machine-based models, and nearest neighbor-based models, to name a few. The machine learning models provided can also be combinations of various types of models. Furthermore, models can be provided in any type of format. For example, neural network models can be provided using representative models such as AlexNet, GoogleNet, ResNet, and DenseNet, or using other types of neural network formats. However, in various embodiments, the types and formats of models are not limited to those described above. Models can be pre-processed and trained in some embodiments, but not required in others. Trained models can also be loaded from one or more files.

[0068] For example, a decision tree is a machine learning model that includes a model architecture in the form of a tree of if-then statements. The hyperparameters of the decision tree's model architecture define the tree structure, including, for example, the number of tree levels and the number of decision nodes. A decision tree includes model data in the form of specific values ​​of if-then statements, and a prediction method that defines how to apply if-then statements to input data.

[0069] A Support Vector Machine (SVM) is a machine learning model that includes a model architecture in the form of at least one hyperplane. The hyperparameters of the SVM's model architecture define at least one hyperplane, including, for example, the number and form of the hyperplanes. An SVM includes model data in the form of matrices, vectors, or values ​​that define a particular hyperplane, and a prediction method that defines the assignment of output values ​​to input data based on at least one hyperplane.

[0070] A neural network is a machine learning model that includes a model architecture in the form of a graph structure. The hyperparameters of the neural network's model architecture define the structure of the neural network, including a generalized structure, or, for example, the topology and size of the neural network. - Type and / or parameters of the loss function - Bottleneck size - Bottleneck filter size (number of features in the bottleneck), - Initial filter size (the number of filters in the first layer of the network; other network features are scaled proportionally to the first layer), - Initial learning rate, - Learning rate decay coefficient, - Use of Momentum, - Number of epochs, - Regularization scale, - Size and contents of the training set (number of statues), - The type of convolution used, - Upsampling method, - Inter-layer connections, - Number of layers in the model, - Sample representing the dataset, - Size of layers in the model, - Types of layers in the model, - Filter size, - Dropout rate, - Kernel size of the convolutional layer, - Use of Nesterov acceleration gradient, - Types of optimization algorithms, - etc.

[0071] The model data for a neural network includes model weights, which include a vector or matrix containing specific values ​​that define the transfer function of the neurons in the hidden layer. The transfer function of a neuron transforms the neuron's input data into output data, which is then passed to one or more other neurons in the neural network. Transfer functions include, for example, a sigmoid function, a step function (threshold), a piecewise linear function, a Gaussian function, or a combination thereof. The prediction method of the neural network defines the forward path of the input data through the network to obtain the result.

[0072] The hyperparameters of a machine learning model's architecture are not typically learned from the data. Instead, these hyperparameters can be selected, for example, by an expert, or automatically optimized using AutoML techniques, particularly in the case of neural networks using Neural Architecture Search (NAS) methods. These techniques automatically search for the optimal hyperparameter values ​​for a machine learning model's architecture. Based on an objective function that evaluates the quality of the set of hyperparameter values, AutoML techniques typically operate on an iterative principle: predicting at least one hyperparameter value based on previously selected hyperparameter values ​​and relevant values ​​of the objective function; setting up the machine learning model's architecture according to the selected hyperparameter values ​​and training the machine learning model based on training data; evaluating the objective function for the predicted at least one hyperparameter based on the trained machine learning model; and, after the last iteration, selecting at least one hyperparameter value that produces the best objective function value.

[0073] In contrast, model data, such as the weights of a neural network, are learned from training data.

[0074] The hyperparameters of a machine learning model's training algorithm generally do not affect the performance of the model architecture, but they do affect the speed and quality of the training process. Examples of algorithm hyperparameters are the learning rate and the mini-batch size.

[0075] Both quality assurance and quality control processes require defects to be recognized as accurately and quickly as possible in order to achieve high throughput or short algorithm execution times. System throughput can be measured, for example, by the area of ​​a wafer inspected at a specific resolution within a given time, or by the time required to inspect a specific area of ​​a wafer at a resolution of 1 nm, for example, 1 cm. 2 The wafers can be processed within 24 hours.

[0076] Embedded systems are often chosen for digital data processing to meet demanding execution time requirements. However, using embedded systems involves significant design and configuration effort because conventional pre-programmed libraries are not available for programming embedded systems.

[0077] Taking such limitations into consideration, various embodiments of the present invention relate to a novel method for implementing machine learning models in embedded systems. This method utilizes a specific structure of a machine learning model defined above, which includes a generalized model architecture and model data specific to a use case. By implementing only the model architecture of the machine learning model on an embedded system and dynamically loading the trained model data into the programmable memory of the embedded system, the implemented machine learning model architecture can be reused for other use cases or retrained for various imaging datasets, thereby saving resources, user effort, and computation time.

[0078] An overall method of the first embodiment of the present invention is shown in Figure 2. Figure 2 shows a flowchart of steps in an exemplary computer implementation method 22 for defect recognition in imaging datasets 12, 12', 12'' of wafer 226 in a charged particle beam system 78 with embedded systems 50, 50', the method comprising: in imaging step 26, acquiring imaging datasets 12, 12', 12'' of wafer 226; and in model data step 28, acquiring model data 44, 44', 44'' of a model architecture 42 for machine learning models 40, 40', 40'' for defect recognition in imaging datasets 12, 12', 12'' of wafer 226. The process involves obtaining the machine learning models 40, 40', 40'' to be implemented in the embedded systems 50, 50', including: obtaining the model architecture 42, obtaining the model data transfer step 30, transferring the model data 44, 44', 44'' to the programmable memory 48, 48', 48'' of the embedded systems 50, 50', and applying the model architecture 46 to the embedded systems using the transferred model data 44, 44', 44'' in the application step 32, applying the machine learning models 40, 40', 40'' to the imaging dataset 12, 12', 12'' of the wafer 226 to recognize defects 16. The recognized defects 16 can be used, for example, in quality assurance systems 228, 234 and / or quality control systems 212, 232, particularly on the wafer 226, but can also be used on other manufactured objects. These steps may be repeated when a new use case 34 is defined or when the model architecture or model data is updated.

[0079] Figure 3 illustrates the use of separation of model architectures 42 and model data 44, 44', 44'' for flexible implementation of machine learning models 40, 40', and 40'' in the embedded system 50. Three machine learning models 40, 40', and 40'', which include the same model architecture 42 but different model data 44, 44', and 44'', for example, a neural network with three different sets of weights for three different use cases, can be implemented in the embedded system 50 by implementing model architecture 42 in the embedded system 50, generating an embedded system implemented model architecture 46, and transferring the respective model data 44, 44', and 44'' to the programmable memory 48 of the embedded system 50. In this way, different use cases can be easily implemented in the embedded system 50. Furthermore, the model data 44 of the machine learning model 40 can be easily adapted or improved. For example, if improved model data 44', 44'' is available, such as by retraining the machine learning model 40, or if the requirements of the machine learning model 40 change, for example, if an unknown defect occurs in the imaging datasets 12, 12', 12'' and the machine learning model 40 needs to be retrained, the new model data 44', 44'' can be easily transferred to the programmable memory 48 of the embedded system 50. This allows the implementation of the machine learning model 40 in the embedded system to improve throughput and reduce execution time, while saving effort and time.

[0080] In one embodiment, the wafer 226 includes various measurement sites containing various semiconductor structures to be investigated. Using the method according to the first embodiment, during the inspection of the wafer 226, it is possible to quickly switch from a first defect inspection task using a first imaging dataset 12 acquired at a first measurement site to a second defect inspection task using a second imaging dataset 12' acquired at a second measurement site of the wafer 226. During the inspection of the wafer 226, a first predefined model data 44 is acquired from the memory of the charged particle beam system 78 and transferred to the programmable memory 48 of the embedded system 50 for the execution of the first defect inspection task. During the inspection of the wafer 226, a second predefined model data 44' is acquired from the memory of the charged particle beam system 78 and transferred to the programmable memory 48 of the embedded system 50 for the execution of the second defect inspection task. In one embodiment, a third defect inspection task is added to the inspection of wafer 226 for a third imaging dataset 12'' acquired at a third measurement site of wafer 226. For the third defect inspection task, third model data 44'' is determined for a model architecture 42 performed in the embedded system 50. An example of determining the third model data 44'' for a new defect inspection task is described further below in a third embodiment. The newly determined third model data 44'' is stored in the memory of the charged particle beam system 78 and transferred to the programmable memory 48 of the embedded system 50 for the execution of the third defect inspection task. The model data 44, 44', and 44'' are stored in the memory of the charged particle beam system 78 and associated with different defect inspection tasks corresponding to different imaging datasets 12, 12', and 12'' acquired by the charged particle beam system 78 at different measurement sites of wafer 226.

[0081] The flexibility and modularity of this method can be further enhanced by subdividing the model architecture into several FPGA implementation modules that can be combined to form various types of machine learning architectures.

[0082] An overall method of a second embodiment of the present invention is shown in Figure 4. Figure 4 shows a flowchart of steps in an exemplary computer implementation method 52 for defect recognition in imaging datasets 12, 12', 12'' of wafer 226 in a charged particle beam system 78 comprising at least one embedded system 50, 50', the method comprising: an imaging step 56 to acquire imaging datasets 12, 12', 12'' of wafer 226; a data flow specification step 58 to specify a data flow 74 through several logic block circuits 72', 72''' of multiple logic block circuits 72', 72', 72''', 74', 74', 74'''' in one of the at least one embedded system 50, 50', the method defines an embedded system implementation model architecture 46 of machine learning models 40, 40', 40'' for defect recognition in imaging datasets 12, 12', 12'' of wafer 226, the method comprising multiple The logic block circuits 72, 72', 72'', 72'''', 74, 74', 74'''' include one or more modules 102, 104 of at least one model architecture 42 of at least one machine learning model 40, 40', 40'' for defect recognition; the machine learning model 40, 40', 40'' is applied to an imaging dataset 12, 12', 12'' of a wafer 226, including defining the logic block circuits 72, 72', 72'', 72'''', at least one model architecture 42 of at least one machine learning model 40, 40', 40'' for defect recognition; in a model data step 60, model data step 60, model data transfer step 62, model data transfer step 62, model data transfer step 62, model data transfer step 64 The recognized defects 16 can be used, for example, in a quality assurance system 115 and / or a quality control system 117, particularly on wafers 226, but can also be used on other manufactured objects.These steps may be repeated when a new use case 66 is defined or when the model architecture or model data is updated.

[0083] Figure 5 illustrates a particularly flexible and versatile method for implementing a machine learning model 40 in a charged particle beam system 78 having two embedded systems 50, 50'. The embedded systems 50, 50' each comprise modules of different model architectures, each implemented by multiple logic block circuits 72, 72', 72'', 72''', 74, 74', 74'', 74'''. To implement a particular model architecture 42 in the charged particle beam system 78, several logic block circuits 72', 72'''' are selected in one of the embedded systems 50, and a data flow 74 is specified by interconnecting a selected number of logic block circuits 72', 72'''' within the embedded system 50. The model data 44 can be transferred to the programmable memory 48' of the embedded system 50, as described above. In this way, by interconnecting a number of logic block circuits 72', 72'' corresponding to the modules of the model architecture 42, not only different model data 44, 44', 44'' but also different model architectures 42 containing various modules can be easily implemented, thus reducing the effort required to implement machine learning models in a charged particle beam system 78 equipped with embedded systems 50, 50'. The modularity of the machine learning model, combined with the possibility of dynamic reconstruction provided by the embedded systems, makes it possible to achieve the aforementioned objectives.

[0084] Whenever a new use case 34, 66 occurs, the machine learning model 40 can be retrained, and new model data 44', 44'' can be transferred to the programmable memory 48, 48', 48'' of the embedded systems 50, 50' without changing the embedded system implementation model architecture 46. The separation of the model architecture 42 to the embedded system implementation, as well as the generation of model data 40, 40', 40'' and its transfer to the programmable memory 48, 48', 48'' of the embedded systems 50, 50', allows for easy replacement of model data 44, 44', 44'' in the case of new use cases 34, 66, thus significantly reducing the time and effort required to implement the machine learning model 40 on the embedded systems 50, 50'. In this way, the embedded system program for machine learning becomes more flexible, reusable, and versatile. Simultaneously, a new business model is enabled, and a charged particle beam system including at least one embedded system 50, 50' which includes multiple logic block circuits 72, 72', 72'', 72'''', 74, 74', 74'''' of the implemented model architecture 46 that implements a module of machine learning architecture, is sold to the customer only once, while the model data 44, 44', 44'' can be updated periodically, for example, using a service contract, or whenever use cases or requirements change.

[0085] Figure 6 illustrates the use of FPGA 51 in various configurations for embedded systems 50, 50' for different use cases. An FPGA is an integrated circuit designed to be assembled by the customer or designer after manufacturing. The configuration of an FPGA is typically specified using a hardware description language. An FPGA includes an array of programmable logic blocks and a hierarchy of reconfigurable interconnects that allow the blocks to be wired together. Logic blocks can be configured to perform complex combinational functions or to function as simple logic gates such as AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. Many FPGAs can be reprogrammed to perform different logic functions, enabling flexible and reconfigurable computing. FPGA 51 includes an adaptive logic module 80, an M512 block 82, an M4K block 84, a high-speed I / O channel 86 including dynamic phase alignment (DPA), an I / O channel 88 including an external memory interface circuit, a digital signal processing block 90, an M-RAM block 92, and a phase-locked loop 94. New use cases can be realized in the same charged particle beam system 78 simply by swapping the model data 44, 44', and 44'' in the programmable memory 48 of FPGA 51, without the additional effort of reprogramming FPGA 51.

[0086] The model data 44, 44', and 44'' of the FPGA implemented model architecture 46 can be obtained in various ways. For example, the model data 44, 44', and 44'' of the FPGA implemented model architecture 46 can be read from a database 225. The model data 44, 44', and 44'' of the FPGA implemented model architecture 46 can also be obtained by training machine learning models 40, 40', and 40'' that include the aforementioned model architecture 46. After training, the obtained model data 44, 44', and 44'' can be stored in the database 225 for use in further applications. Furthermore, the model data 44, 44', and 44'' can be provided by an external service that enables dynamic updates of the model data 44, 44', and 44'' for improvement or adaptation of the model data 44, 44', and 44'' to changed requirements. Such a service can be used as a new business model that separates hardware, which has an embedded system containing each module of the implemented model architecture and is sold only once, from model data that can be updated periodically. In this way, the use of embedded systems 50, 50' for implementing machine learning models 40, 40', 40'' allows for time and effort savings, high system flexibility, optimization of defect recognition methods, and simultaneous maximization of throughput and reduction of execution time.

[0087] In embodiments of the first and second embodiments of the present invention, the model data 44, 44', 44'' can be transferred to the programmable memory 48, 48', 48'' of the embedded systems 50, 50' by copying. Alternatively, the model data 44, 44', 44'' can be transferred to the programmable memory 48, 48', 48'' of the embedded systems 50, 50' by replacing the hardware block containing the programmable memory 48, 48', 48'' of the embedded systems 50, 50' with a new hardware block containing the model data 44, 44', 44'' to be transferred.

[0088] To provide the user with defect recognition results for quality evaluation or quality control, the recognized defects 16 can be directed, for example, to a display device 227 or a dashboard, enabling real-time monitoring of the detected defects 16. In other embodiments of the first or second embodiment, the recognized defects 16 may be stored in long-term memory for further analysis, for example, to generate statistics about the defects 16. In further embodiments, the recognized defects may be cached in memory for a specified time, for example 48 hours, to enable further analysis of the detected defects 16, but without requiring a large amount of memory. In another embodiment, the recognized defects are analyzed in step (ii) to update the embedded system implementation model architecture 46, for example, the defect recognition results are used to receive feedback from downstream applications, followed by updating each module of the embedded system implementation model architecture, for example, to address data drift.

[0089] A charged particle beam system 78 in a second embodiment of the present invention comprises at least one embedded system 50, 50' to enable the implementation of various machine learning models 40, 40', 40'' based on various model architectures 42 within the same charged particle beam system 78. Each model architecture may be implemented in separate embedded systems 50, 50' within the charged particle beam system 78. Various model architectures 42 may also be implemented in the same embedded systems 50, 50'. To make the system even more flexible and versatile, the model architecture 42 of the machine learning models 40, 40', 40'' may be divided into one or more modules and implemented in multiple logic block circuits 72, 72', 72'', 72'''', 74, 74', 74'''' in one or more of the at least one embedded system 50, 50'. In this way, by specifying the data flow 74 through the required number of logic block circuits 72', 72''' during the application of the defect recognition method, and by interconnecting the aforementioned logic block circuits 72', 72''' as shown and explained with respect to Figure 7, a new model architecture 42 of machine learning models 40, 40', 40'' can be easily implemented in a charged particle beam system 78.

[0090] Figure 7 shows a schematic implementation of the embedded system for the first module 102 and the second module 104 of the neural network model architecture. Input data for both modules 102 and 104 is available via the input data bus 98. Model data in the form of weights 100 for each module 102 and 104 is available via programmable memory 48 on the embedded system 50. The first module 102 has one convolutional layer including a single 2x2 filter based on multiplication 110 of the input data on the input data bus 98 with weights 100 corresponding to the first module 102. The second module 104 has two convolutional 2x2 filters based on multiplication 110 of the input data on the input data bus 98 with weights 100 corresponding to the second module 104. When defining the data flow 74, modules 102 and 104 can be selected using a multiplexer 108, which is configured, for example, by the user via programmable configuration memory 106.

[0091] A module of a model architecture may include parts of the model architecture, such as one or more layers of a neural network, subtrees of a decision tree, one or more hyperplanes of an SVM, or one or more sets of nodes of a graph structure, such as in a Hidden Markov Model.

[0092] According to an embodiment of the second embodiment, at least one model architecture of at least one machine learning model for defect recognition includes, for example, a neural network model architecture for deep learning. This provides the advantage that the neural network is particularly well-suited to being subdivided into logic block circuits by subdivision into layers, thereby reducing the effort required to program the embedded system and specify the flow of data through the logic block circuits.

[0093] According to an embodiment of the second embodiment, one or more modules may be head modules, which are modules that include the output layer of a neural network. The output layer generates the result of the neural network when presented with input data, such as classification into one of several classes, a binary output, or one or more specific return values. The output layer is task-specific, i.e., it can be used only for a particular task. For example, one or more head modules may include a fully connected output layer and / or a convolutional output layer of a neural network. The fully connected output layer of a neural network is specifically designed for tasks such as classification, for example, because this output layer is not restricted by spatial context. The convolutional layer of a neural network is specifically designed for tasks such as defect detection, anomaly detection, or defect segmentation, due to consideration of spatial context.

[0094] According to an embodiment of the second embodiment, one or more modules are tail modules, and each tail module is a module containing several hidden layers of a neural network. This allows for combinations of multiple hidden layers into a single tail module, thereby reducing programming effort and the effort required when specifying data flow.

[0095] The separation of the head module and / or tail module offers the advantages of flexibility and versatility, as the task imposed on the neural network can be easily changed by swapping the head module to alter the data flow, and the tail module can be used in many different model architectures without additional effort.

[0096] In addition, the subdivision of the model architecture into head and tail modules allows for semantic combinations of hidden layers that perform specific tasks within the model architecture, into a single tail module. In this way, the modular structure of the model architecture is further simplified, reducing programming effort and the effort required to specify data flow.

[0097] For example, Figure 8 shows the subdivision of the model architecture 42 in the form of a neural network 114 into a head module 116 and a tail module 118. Figure 8 shows the neural network 114, which includes hidden layers 122, 123 and an output layer 120 obtained using filters of the indicated spatial size and feature size. The neural network 114 includes a head module 116 containing the output layer 120 of the neural network 114 and a single tail module 118. The head module 116 contains the output layer 120 of the neural network 114, while the tail module 118 contains some of the hidden layers 122, 123 of the neural network 114, in particular all of the hidden layers 122, 123. The output layer is a 1×1×32 filter-per-pooling layer and is therefore adapted to solve a defect detection task, an anomaly detection task, or a segmentation task based on a feature map containing 32 features generated by the last hidden layer 123. The separation of task-specific head modules 116 from the rest of the model architecture is beneficial because it allows the head modules 116 to be easily swapped with different head modules 116 to impose different tasks on the model architecture in different applications. For example, head modules 116 can be adapted for classification tasks.

[0098] Figure 9 shows different head modules 124, 126 and tail modules 128, 130, 132, 134, 136, 138 of various model architectures. This modular structure allows a set of model architectures to be realized on embedded systems 50, 50' by combining one or more different tail modules 128, 130, 132, 134, 136, 138 with one of the head modules 124, 126. The head modules 124, 126 can be task-specific. For example, head module 124 with a filter size of 1 × 1 × D (where D is the number of features) is suitable for anomaly detection tasks, defect detection tasks, or segmentation tasks, while head module 126 with a filter size of 1 × 1 × CS (where S stands for softmax and C is the number of classes) is suitable for classification tasks. The advantage of this modularity is that, in order to realize the model architecture on the embedded system 50', the task of the neural network can be easily changed by simply swapping the head modules 124, 126, for example, the output layer of the neural network, without changing the hidden layers of the neural network, for example, by using tail modules 128, 130, 132, 134, 136, 138, which define the data flow 74, for example, in order to realize the model architecture on the embedded system 50', 50'.

[0099] According to another embodiment of the second embodiment, at least one tail module, in particular each tail module, can contain all the hidden layers 122, 123 of the neural network 114, as shown in Figure 8. This is beneficial because each neural network 114 consists of only a single head module 116 and a single tail module 118. This allows for a particularly simple implementation of the neural network as an embedded system, and a particularly simple specification of the data flow through the logical block circuitry of the embedded system, as there are fewer blocks that need to be interconnected.

[0100] According to further embodiments of the second embodiment, at least one tail module, in particular each tail module, may include several hidden layers of the neural network that form semantic entities. The term “semantic entity” refers to several hidden layers 122, 123 that form a functional unit in the sense that they complement each other and together perform specific functions within the neural network 114. For example, the hidden layer of tail module 128 is a semantic entity because it forms a functional unit for reducing input data. The same applies to the hidden layer of tail module 132. The hidden layer of tail module 136 forms a functional entity because it forms a bottleneck for reducing the dimensionality of the data, for example, for representing an autoencoder. The same applies to the hidden layer of tail module 138. The hidden layer of tail module 130 is a semantic entity because it forms a functional unit for expanding the data. The same applies to the hidden layer of tail module 134. By defining tail modules that form semantic entities, only a small number of functional entities that perform specific functions in the model architecture need to be interconnected to specify the data flow, thus reducing the effort required to implement the model architecture on one or more embedded systems.

[0101] According to a further embodiment of the second embodiment, at least two of the tail modules contain the same number of hidden layers, and the size of the feature maps of the corresponding hidden layers differs by the same multiple. The hidden layers of the two modules correspond to each other with respect to their rank in the order of the hidden layers of the modules, for example, the second hidden layer of one module corresponds to the second hidden layer of another module. This allows for the implementation of neural networks that consider a different number of features, for example, by using small, medium, or large modules for the same task. In a further embodiment of the second embodiment, for each tail module, there exists at least one other tail module containing the same number of hidden layers, and the size of the feature maps of the corresponding hidden layers differs by the same multiple. For example, Figure 9 shows two tail modules 128 and 132 containing the same number, i.e., three hidden layers. The size of the feature maps of the corresponding first layers 129 and 129' is 32 and 16, respectively, differing by a factor of two. The size of the feature maps of the corresponding second layers 131 and 131' is 16 and 8, respectively, differing by a factor of two. The feature map sizes of the corresponding third layers 133 and 133' are 8 and 4, respectively, which are also twice as large. Thus, modules 128 and 132 perform the same task, differing only in the complexity of their feature maps. For example, tail modules 136 and 138 contain only a single corresponding hidden layer, and their feature map sizes differ by a factor of 10. In this way, model architectures considering varying amounts of features, such as small, medium, or large model architectures, can be implemented in the same embedded system, enabling the adaptation of the model architecture size to the difficulty of the machine learning task. By replacing the corresponding logic block circuit of the small tail module 138 with the logic block circuit of the large tail module 136, model architectures with even more or fewer features can be easily implemented on the embedded system. In this way, the implementation of the model architecture in the embedded system becomes particularly flexible in adapting to the requirements of the machine learning task being solved.

[0102] In Figure 9, anomaly or defect detection based on a larger U-net model architecture that considers more features can be performed, for example, by specifying a data flow that interconnects tail modules 128, 136, and 130 with head module 124. Here, tail module 128 reduces the input data, tail module 136 represents a bottleneck used to obtain a representation of the input data with very low dimensionality, and tail module 130 expands the data, so the combination of these tail modules 128, 136, and 130 represents the structure of an autoencoder. Head module 124 represents a convolutional layer for computing the results of the defect or anomaly detection task. Such a large model architecture is useful for more complex defect or anomaly detection tasks that require more features to be considered. To perform anomaly or defect detection based on a smaller U-net model architecture that considers only a few features, tail modules 132, 138, and 134 can be interconnected with head module 124. The combination of tail modules 132, 138, and 134 also represents an autoencoder, but with fewer features and a smaller bottleneck. The head module 124 represents a convolutional layer for calculating the results of a defect or anomaly detection task. Such a small model architecture is useful for less complex defect or anomaly detection tasks that require fewer features to be considered.

[0103] The module structure shown in Figure 9 can also be used for segmentation tasks. Here, a large U-net model architecture can be implemented on an embedded system by interconnecting the tail module 128 with the head module 124. To obtain a small U-net model architecture on an embedded system, the tail module 132 can be interconnected with the head module 124. The head module 124 is a convolutional layer used to compute the results of the segmentation task, i.e., the assignment of each pixel of the imaging dataset to a specific class. Depending on the difficulty of the segmentation task, more or fewer features should be considered, and therefore, a large model architecture or a small architecture may be useful, respectively.

[0104] The module structure shown in Figure 9 can also be used for classification tasks. By specifying the data flow that interconnects tail modules 128, 136, and 130 with head module 126, classification based on a larger U-net model architecture that considers more features can be performed. Again, this combination of tail modules 128, 136, and 130 represents the structure of an autoencoder. Head module 126 represents a fully connected softmax layer for computing the results of the classification task. Such a large model architecture is useful for more complex classification tasks that require more features to be considered. To perform classification based on a smaller U-net model architecture that considers only a few features, tail modules 132, 138, and 134 can be interconnected with head module 126. The combination of tail modules 132, 138, and 134 also represents an autoencoder, but with fewer features and smaller bottlenecks. Head module 126 represents a fully connected layer for computing the results of the classification task. Such a small model architecture is useful for less complex classification tasks that require fewer features to be considered.

[0105] In this way, large, medium, or small model architectures can be easily implemented on embedded systems, making the system highly flexible to various requirements for different tasks. In addition, the modular implementation of model architectures with various feature map sizes on embedded systems simplifies the testing of different model architectures during quality assurance to find the best model architecture in terms of quality and execution time.

[0106] According to an embodiment of the second embodiment, each of the one or more modules is either a head module including the output layer of a neural network, or a tail module including several hidden layers of a neural network. In addition, the one or more modules may include at least one head module and at least one tail module.

[0107] According to an embodiment of the second embodiment, one or more modules are generated from at least one model architecture of a neural network by dividing each model architecture into a head module containing the output layer of the neural network and at least one, in particular a single, tail module containing several hidden layers of the neural network. In this way, the modules implemented on at least one embedded system in a charged particle beam system directly correspond to the model architecture containing all the hidden layers of the neural network, so these neural networks can be easily implemented in the system.

[0108] According to a second embodiment of the present invention, before specifying the data flow through some of the multiple logic block circuits, it is advantageous to determine whether the model architecture of a trained machine learning model can be realized by multiple logic block circuits in one of the at least one embedded systems, and in response to determining that the model architecture cannot be realized, to generate one or more modules of the model architecture of the trained machine learning model and implement the said one or more modules in one of the at least one embedded systems. In this way, for a particular machine learning task and the corresponding machine learning model, it can be checked whether the model architecture of the machine learning model can be realized by various modules already implemented in the embedded systems of the charged particle beam system. If it cannot be realized, the missing modules can be determined and implemented in one of the embedded systems of the charged particle beam system in order to make the model architecture representable by the logic block circuits of the aforementioned embedded systems in the charged particle beam system. This process is shown in Figure 10.

[0109] Figure 10 illustrates the process of implementing new use cases 34, 66 in a charged particle beam system 78 by a computer implementation method according to one or more embodiments or examples of the present invention. Following the start 142, the group determination step 144 determines a group of machine learning models required to solve the new use cases 34, 66. The group may include, for example, defect detection models, segmentation models, or classification models. If a use case belongs to a new group that has not yet been implemented in the system ("yes" 170), in the use case collection step 154, the expert collects information on possible use cases for this group. In the model architecture definition step 156, the expert defines a general-purpose model architecture for this group, including the determined possible use cases. Next, in the feasibility step 158, the expert determines whether the defined model architecture is feasible on an existing embedded system in the charged particle beam system 78. If it is not feasible ("no" 180), the defined model is generalized on a new embedded system in the charged particle beam system 78 in the model implementation step 160. If feasible ("Yes" 178), in the data acquisition and training step 150, training data and ground truth data are acquired and a machine learning model for the new use cases 34, 66 is trained. In the model data storage step 152, the expert saves the generated model data, e.g., neural network weights, to a database. In the model data retrieval step 162, the trained model data is read from the database in order to run the machine learning model on the embedded system within the charged particle beam system 78. In the model data transfer step 164, the determined model data is downloaded from the database and transferred to the programmable memory of the embedded system, so that the model architecture of the machine learning model for the new use cases 34, 66 can be implemented in the charged particle beam system 78. Finally, in the data processing step 166, the machine learning model to be implemented in the embedded system is run in real time on the input data, and then the process is stopped (168).Instead, if the use case belongs to a new group that has already been implemented in the system ("No" 172), it is determined whether the use case is a new use case 34 or 66 that has not yet been implemented in the system ("Yes" 174) or not ("No" 176). If the use case is a new use case 34 or 66, the model architecture for this group has already been implemented in the system, but model data needs to be generated for the new use cases 34 or 66. Therefore, in the problem input step 148, the machine learning problem is input into the predefined model architecture for this group that has already been implemented in the system. Next, in the data acquisition and training step 150, the model data is acquired as described above, and the process continues as described above. On the other hand, if the use case has already been implemented in the system ("No" 176), the model architecture and model data are already available, and the process continues with the model data retrieval step 162 as described above.

[0110] As shown above, the implementation of a model architecture for machine learning models on embedded systems, based on tail modules and task-specific head modules that can be interconnected to form a data flow through multiple logic block circuits on the embedded system, combined with easily interchangeable model data in the programmable memory of the embedded system, results in a highly flexible, adaptable, and versatile implementation of machine learning models on embedded systems.

[0111] A third embodiment of the present invention is described below with reference to Figure 11. Figure 11 shows a flowchart of the steps in an exemplary computer implementation method 182 for defect recognition. This method includes a computer implementation method 22, 52 according to a first or second embodiment of the present invention or any embodiment or aspect thereof, which further includes iterations 194 of the steps, in which, before acquiring an imaging dataset of a wafer in step (i), until a convergence criterion, e.g., the maximum number of steps is met, in an imaging parameter step 184, at least one imaging parameter is selected according to an imaging sampling strategy and an imaging dataset of a wafer is acquired based on the aforementioned at least one imaging parameter; in a training data generation step 186, training data is generated from the acquired imaging dataset of the wafer; in a machine learning model training step 188, a model architecture is selected and a related machine learning model is trained based on the generated training data; in a quality evaluation step 190, the quality of the model architecture and at least one imaging parameter is determined by calculating a relevant objective function value of an objective function that evaluates the quality of the trained machine learning model; and after the last iteration 194, in a selection step 192, one of the model architectures and the corresponding at least one imaging parameter is selected based on the objective function value. In steps (i) 26, 56 of the computer implementation of the first or second embodiment of the present invention or any embodiment or aspect thereof, the image data set of the wafer is acquired based on at least one selected image acquisition parameter, and in steps (ii) 28, 58 of the computer implementation of the first or second embodiment of the present invention or any embodiment or aspect thereof, the embedded system implementation model architecture includes a model architecture of a selected machine learning model. This embodiment is illustrated in Figures 12 and 13, and the model architecture and the corresponding at least one image acquisition parameter selected in selection step 192 are used in steps 26, 28, 56, 58 of the computer implementation 22, 52.

[0112] Referring to Figure 14, a fourth embodiment of the present invention is described below. The fourth embodiment of the present invention is a computer implementation method 196 for defect recognition in a wafer imaging dataset, the method comprising iterations 210 of the following steps: an image acquisition parameter step 198 in which an image acquisition parameter is selected according to an imaging sampling strategy and an image imaging dataset of wafers is acquired based on the aforementioned at least one image acquisition parameter, until a convergence criterion, e.g., a maximum number of steps is met; a training data generation step 200 in which training data is generated from the acquired image imaging dataset of wafers is generated; a machine learning model training step 202 in which a model architecture is selected and a relevant machine learning model is trained based on the generated training data; a quality evaluation step 204 in which the quality of the trained machine learning model is evaluated by calculating a relevant objective function value of the objective function; after the last iteration 210, a selection step 206 in which one of the trained machine learning models is selected based on the objective function value; and an application step 208 in which the selected trained machine learning model is applied to an image imaging dataset of wafers acquired based on the corresponding at least one image acquisition parameter in order to recognize defects. The identified defects can be used in the wafer quality assurance system and / or quality control system.

[0113] A method according to a third or fourth embodiment of the present invention has the advantage that at least one image acquisition parameter used to generate a wafer imaging dataset, and therefore training data, as well as the model architecture of the machine learning model, can be optimized together before implementing the model architecture in one of the embedded systems within the charged particle beam system. In this process, the model architecture can be optimized with respect to various criteria, for example, to reduce execution time, to further improve the throughput of the charged particle beam system, to reduce the complexity of the model architecture, or to improve the quality of predictions of the machine learning model.

[0114] At least one image acquisition parameter can be derived from a group including, for example, imaging time, image resolution, pixel size, electron wave landing energy, and residence time.

[0115] In embodiments of the third or fourth embodiment of the present invention, the step of selecting a model architecture 42 includes selecting at least one hyperparameter that defines the model architecture 42 of the machine learning models 40, 40', 40'' according to an architecture sampling strategy. The architecture sampling strategy may include several hyperparameters selected by the user, or hyperparameters automatically sampled according to AutoML techniques and sampling strategies for hyperparameters known to those skilled in the art, such as a tree-structured Palzen estimator or an asynchronous continuous halving strategy. This is beneficial because the hyperparameters of the machine learning model can be automatically optimized along with at least one image acquisition parameter.

[0116] In embodiments of the third or fourth embodiment of the present invention, the objective function may include a measure of the complexity of the model architecture 42. The measure of complexity may include, for example, the size of the model architecture 42, e.g., the number of layers and / or neurons in the neural network 114, the number of hyperplanes in the SVM, the number of levels and / or nodes in the decision tree, or the number of nodes and connections in the graph structure. The measure of complexity may allow smaller model architectures 42 to be used to solve machine learning tasks, thereby reducing the execution time of the machine learning models 40, 40', 40'', improving the throughput of the charged particle beam system 78, and requiring less space on the embedded systems 50, 50', thus providing the advantage that more model architectures 42 can be implemented in the embedded systems 50, 50' within the charged particle beam system 78.

[0117] In another embodiment of the third or fourth embodiment of the present invention, the objective function may include a measure of execution time, and / or a measure of throughput and / or data rate, and / or a measure of power consumption.

[0118] In another embodiment of a third or fourth embodiment of the present invention, the objective function may include measures of defect recognition quality, such as the loss function of the neural network 114 applied to the training data, or any other measure known to those skilled in the art for measuring the prediction error of the machine learning models 40, 40', 40'' on training data generated using at least one image acquisition parameter.

[0119] In further embodiments of the third or fourth embodiment of the present invention, the objective function may include a measure of the bit amount of input data for the machine learning models 40, 40', 40'', for example, the number of input bits in the input layer of the machine learning models 40, 40', 40''. In this way, the complexity of the model architecture 42 can be reduced. This has the advantage of reducing the execution time of the machine learning models 40, 40', 40'' due to the smaller amount of data that needs to be processed. Furthermore, a model architecture 42 with a reduced input bit amount can be more easily implemented on embedded systems 50, 50' by reducing the spatial requirements. In this way, a wider variety of model architectures 42 can be implemented on the embedded systems 50, 50' of the charged particle beam system 78. If a very large model architecture 42 is not suitable for implementation on the embedded systems 50, 50', the size of the model architecture 42 can be reduced by reducing the input bit amount, thereby increasing the likelihood that the machine learning models 40, 40', 40'' can be implemented on the embedded systems 50, 50'.

[0120] In one embodiment of the embodiments of the present invention, the computer implementation method further includes determining one or more measurements of defects recognized in the imaging dataset of a wafer, in particular size, area, dimensions, shape parameters, distance, radius, aspect ratio, type, number of defects, density, and spatial distribution of defects. The aforementioned measurements may be calculated for a specific region, for example, a user-defined mask, die boundary, or die core, or for the entire imaging dataset.

[0121] Wafer quality can be evaluated based on one or more measurements and at least one quality evaluation rule, for example, according to DIN-ISO quality specifications that define upper limits on the acceptable tolerance of sub-ideal wafers. For example, the density of a particular type of defect in the die core may be 1 nm. 2 The number of hits should be less than 10.

[0122] According to any one embodiment of the present invention, at least one wafer manufacturing process parameter can be controlled based on one or more measurements of defects recognized in a wafer imaging dataset.

[0123] The present invention also relates to a computer-readable medium storing a computer program executable by a computing device, the computer program including code for performing a method according to any embodiment of the present invention. The computer program includes a data I / O driver for low-latency hardware, a program for configuring the low-latency hardware to perform image processing functions, a program for performing error checking, and the like.

[0124] Figure 15 schematically shows a system 212 that may be used to control the quality of wafers 226 manufactured in a semiconductor manufacturing plant. System 212 includes an imaging device 214 and a processing device 216. The imaging device 214 is coupled to the processing device 216. The imaging device 214 is configured to acquire an imaging dataset 12 of wafer 226. Wafer 226 may include semiconductor structures, such as transistors, field-effect transistors, memory cells, etc. Exemplary implementations of the imaging device 214 are a SEM or multi-beam SEM, a helium ion microscope (HIM), or a cross-beam device including a FIB and SEM, or any charged particle beam imaging device. The processing device 216 is coupled to at least one embedded system 50 having programmable memory 48.

[0125] The imaging device 214 can provide the imaging dataset 12 to the processing device 216. The processing device 216 includes a processor, which is implemented as, for example, a CPU 218 or a GPU. The processor can receive the imaging dataset 12 via the interface 220. The processor can read program code from memory 222. The processor can execute the program code. When executing the program code, the processor performs techniques such as those described herein, for example, evaluating the quality of a wafer based on one or more measurements and at least one quality evaluation rule, defect recognition, transferring model data to the programmable memory 48 of the embedded system 50, training machine learning models 40, 40', 40'', specifying a data flow 74 through several local block circuits 72, 72', 72'', 72''', 76, 76', 76''' of the embedded system 50, 50', applying the machine learning model 42 implemented on the embedded system 50, 50' to the data, measuring the recognized defects 16, optimizing at least one image acquisition parameter, and so on. For example, the processor can read program code from memory 222 and then execute the computer implementations shown in Figures 2, 4, 10, 11, 12, and 13, respectively. The processing device 216 may optionally include a user interface 224 for receiving user input, such as the type of defect measurement, quality evaluation rules, and machine learning model parameters. The processing device 216 may optionally include a display device 227 for displaying defect recognition results to the user, for example, in real time or buffered. The processing device 216 may also optionally include a database 225 for storing, for example, machine learning models 40, 40', 40'', 40'', 40''', model architectures 42, or a group of model data 44, 44', 44'' for different trained machine learning models 40, 40', 40''.

[0126] Figure 16 schematically shows a system 228 that may be used to control the manufacturing of wafers 226 in a semiconductor manufacturing plant. System 228 comprises the same components as those shown in Figure 15, and the above description also applies to each component in this figure. In addition, system 228 has means 230 for manufacturing wafers 226 controlled by at least one wafer manufacturing process parameter. For this purpose, an imaging data set 12 is provided to a processing device 216 using an imaging device 214. The processor of the processing device 216 is configured to perform one of the methods disclosed according to the first, second, or third embodiments of the present invention, which includes controlling at least one wafer manufacturing process parameter based on one or more measured characteristics of defects 16 recognized in the imaging data set 12 of wafers 226. For example, detected bridge defects 16 indicate insufficient etching, so the amount of etching is increased; detected break defects 16 indicate excessive etching, so the amount of etching is reduced; consistently occurring anomalies or defects 16 indicate a defective mask, so the mask must be checked; and anomalies or defects 16 resulting from missing structures suggest a suboptimal material deposition, so the material deposition is modified.

[0127] Figure 17 schematically illustrates a system 232 that may be used to control the quality of wafers 226 manufactured in a semiconductor manufacturing plant. System 232 includes an imaging device 214 and a processing device 216. The imaging device 214 is coupled to the processing device 216. The imaging device 214 is configured to acquire an imaging dataset 12 of wafer 226. Wafer 226 may include semiconductor structures, such as transistors including field-effect transistors and memory cells. Exemplary implementations of the imaging device 214 are a SEM or multi-beam SEM, a helium-ion microscope (HIM), or a cross-beam device including a FIB and SEM, or any charged particle imaging device.

[0128] The imaging device 214 can provide the imaging dataset 12 to the processing device 216. The processing device 216 includes a processor, which is implemented as, for example, a CPU 218 or a GPU. The processor can receive the imaging dataset 12 via the interface 220. The processor can read program code from memory 222. The processor can execute the program code. When executing the program code, the processor performs techniques such as those described herein, according to a fourth embodiment of the present invention, e.g., defect recognition, measuring recognized defects, and optimizing at least one image acquisition parameter along with the model architecture of a machine learning model. For example, once the processor has read the program code from memory 222, it can execute the computer implementation shown in Figure 14. The processing device 216 may optionally include a user interface 224 for receiving user input, e.g., the type of defect measurement, quality evaluation rules, parameters of a machine learning model, etc. The processing device 216 may optionally include a display device 227 for displaying the defect recognition results to the user, e.g., in real time or buffered.

[0129] Figure 18 schematically shows a system 234 that may be used to control the manufacturing of wafers 226 in a semiconductor manufacturing plant. System 228 comprises the same components as those shown in Figure 17, and the above description also applies to each component in this figure. In addition, system 234 has means 230 for manufacturing wafers 226 controlled by at least one wafer manufacturing process parameter. For this purpose, an imaging device 214 is used to provide an imaging dataset 12 to a processing device 216. The processor of the processing device 216 is configured to perform one of the disclosed methods, which includes controlling at least one wafer manufacturing process parameter based on one or more measured characteristics of defects 16 recognized in the imaging dataset 12 of wafers 226. For example, detected bridge defects 16 indicate insufficient etching, so the amount of etching is increased; detected break defects 16 indicate excessive etching, so the amount of etching is reduced; consistently occurring anomalies or defects 16 indicate a defective mask, so the mask must be checked; and anomalies or defects 16 resulting from missing structures suggest a suboptimal material deposition, so the material deposition is modified.

[0130] Embodiments, examples, and aspects of the present invention may be described by the following sections.

[0131] 1. A computer-aided method 22 for defect recognition in imaging datasets 12, 12', 12'' of a wafer 226 in a charged particle beam system 78 equipped with embedded systems 50, 50', wherein the method is: i. Obtain imaging datasets 12, 12', and 12'' of wafer 226. ii. To obtain model data 44, 44', 44'' of the model architecture 42 for machine learning models 40, 40', 40'' for defect recognition in imaging datasets 12, 12', 12'' of wafer 226, wherein the model architecture 42 is implemented and obtained in embedded systems 50, 50'. iii. Transfer the model data 44, 44', 44'' to the programmable memory 48, 48', 48'' of the embedded system 50, 50'. iv. Applying machine learning models 40, 40', 40'' to imaging datasets 12, 12', 12'' of wafer 226, including running an embedded system implementation model architecture 46 using the transferred model data 44, 44', 44'', to recognize defects 16. Computer implementation method 22, including.

[0132] 2. A computer-aided method 52 for defect recognition in imaging datasets 12, 12', 12'' of a wafer 226 in a charged particle beam system 78 comprising at least one embedded system 50, 50', wherein the method is i. Obtain imaging datasets 12, 12', and 12'' of wafer 226. ii. Define an embedded system implementation model architecture 46 for machine learning models 40, 40', 40'' for defect recognition in imaging datasets 12, 12', 12'' of wafer 226 by specifying a data flow 74 through some logic block circuits 72', 72', 72''', 74, 74', 74'', 74'''' in one of at least one embedded system 50, 50', wherein the multiple logic block circuits 72, 72', 72'', 72''', 74, 74', 74'', 74'''' include one or more modules 102, 104 of at least one model architecture 42 for at least one machine learning model 40, 40', 40'' for defect recognition. iii. Obtain model data 44, 44', and 44'' of the embedded system implementation model architecture 46. iv. Transfer model data 44, 44', 44'' to programmable memory 48, 48', 48'' of embedded system 50, 50'. v. Applying machine learning models 40, 40', 40'' to imaging datasets 12, 12', 12'' of wafer 226, including running an embedded system implementation model architecture 46 using the transferred model data 44, 44', 44'', to recognize defects 16. Computer implementation method 52, including.

[0133] 3. The computer implementation method described in Section 2, wherein at least one model architecture 42 of at least one machine learning model 40, 40', 40'' for defect recognition includes a model architecture 42 of a neural network 114.

[0134] 4.1 or more modules 102, 104 are head modules 116, 124, 126, and the head modules 116, 124, 126 are modules containing the output layer 120 of the neural network 114, as described in paragraph 3.

[0135] 5.1 or more head modules 116, 124, 126 include a fully connected output layer and / or a convolutional output layer of the neural network 114, as described in Section 4.

[0136] 6. A computer implementation according to any one of paragraphs 3 to 5, wherein one or more modules 102, 104 are tail modules 118, 128, 130, 132, 134, 136, 138, and the tail modules 118, 128, 130, 132, 134, 136, 138 are modules containing several hidden layers 122 of the neural network 114.

[0137] 7. The computer implementation method described in Section 6, wherein at least one tail module 118, 128, 130, 132, 134, 136, 138, in particular, each tail module 118, 128, 130, 132, 134, 136, 138 includes all the hidden layers 122 of the neural network 114.

[0138] 8. A computer implementation as described in paragraph 6 or 7, wherein at least one tail module 118, 128, 130, 132, 134, 136, 138, in particular, each tail module 118, 128, 130, 132, 134, 136, 138 includes several hidden layers 122 that form a semantic entity.

[0139] 9. A computer implementation of any one of paragraphs 6 to 8, wherein at least two of the tail modules 118, 128, 130, 132, 134, 136, and 138 contain the same number of hidden layers 122 and 123, and the feature map sizes of the corresponding layers 129, 129', 131, 131', 133, and 133' differ by the same multiple.

[0140] 10. A computer implementation according to any one of paragraphs 3 to 9, wherein each of the one or more modules 102, 104 is either a head module 116, 124, 126 containing an output layer 120 of a neural network 114, or a tail module 118, 128, 130, 132, 134, 136, 138 containing several hidden layers 122 of a neural network 114.

[0141] 11. A computer implementation of any one of paragraphs 3 to 10, wherein one or more modules 102, 104 are generated from at least one model architecture 42 of the neural network 114, by dividing each model architecture 42 into head modules 116, 124, 126 containing the output layer 120 of the neural network 114 and at least one tail module 118, 128, 130, 132, 134, 136, 138 containing several hidden layers 122 of the neural network 114.

[0142] 12. The computer implementation method described in Section 11, wherein each model architecture 42 of the neural network 114 is divided into task-specific head modules 116, 124, 126 and single tail modules 118, 128, 130, 132, 134, 136, 138.

[0143] 13. A computer implementation method according to any one of paragraphs 2 to 12, further comprising: determining whether the model architecture 42 of a machine learning model 40, 40', 40'' can be realized by the multiple logic block circuits 72, 72', 72'', 74, 74', 74'', 74''' in one of the at least one embedded system 50, 50' before specifying a data flow 74 through some of the multiple logic block circuits 72', 72''', 72''', 74, 74', 74'''; generating one or more modules 102, 104 of the model architecture 42 of the machine learning model 40, 40', 40'' in response to determining that the model architecture 42 cannot be realized; and implementing the aforementioned one or more modules 102, 104 in one of the at least one embedded system 50, 50'.

[0144] 14. A computer implementation method according to any one of paragraphs 1 to 13, wherein the machine learning models 40, 40', and 40'' for defect recognition are from the group including defect detection models, defect classification models, defect location models, defect segmentation models, anomaly detection models, anomaly classification models, anomaly location models, and anomaly segmentation models.

[0145] 15. A computer implementation method as described in any of paragraphs 1 to 14, wherein model data 44, 44', and 44'' of the embedded system implementation model architecture 46 are obtained by training machine learning models 40, 40', and 40'' that include the aforementioned model architecture.

[0146] 16. A computer implementation method described in any one of paragraphs 1 to 15, wherein the model data 44, 44', and 44'' of the embedded system implementation model architecture 46 are read from the database 225.

[0147] 17. A computer implementation method described in any one of paragraphs 1 to 16, wherein the model data 44, 44', and 44'' of the embedded system implementation model architecture 46 are provided by an external service.

[0148] 18. The computer implementation described in any one of paragraphs 1 to 17, wherein model data 44, 44', and 44'' are transferred by copy to the programmable memory 48, 48', and 48'' of the embedded system 50, 50'.

[0149] 19. A computer implementation according to any one of paragraphs 1 to 18, wherein model data 44, 44', 44'' is transferred to the programmable memory 48, 48', 48'' of the embedded system 50, 50' by replacing the hardware block containing the programmable memory 48, 48', 48'' of the embedded system 50, 50' with a new hardware block containing the model data 44, 44', 44'' to be transferred.

[0150] 20. The computer implementation method 22, 52 described in any one of paragraphs 1 to 19, wherein the recognized defect 16 is directed toward the display device 227 or the dashboard.

[0151] 21. A computer implementation method described in any one of paragraphs 1 to 20, wherein the recognized defect 16 is stored in long-term memory.

[0152] 22. A computer implementation method described in any one of paragraphs 1 to 21, wherein the recognized defect 16 is cached in memory.

[0153] 23. In step ii, the recognized defect 16 is analyzed in order to update the embedded system implementation model architecture 46, according to the computer implementation method described in any one of paragraphs 1 to 22.

[0154] 24. A computer implementation according to any one of paragraphs 1 to 23, wherein the embedded system 50, 50' is a field-programmable gate array 51.

[0155] 25. Before obtaining the wafer imaging datasets 12, 12', and 12'' in step i, - Until the convergence criteria are met, - Select at least one image acquisition parameter according to the imaging sampling strategy, and acquire imaging datasets 12, 12', and 12'' of wafer 226 based on the aforementioned at least one image acquisition parameter. • To generate training data from the acquired imaging datasets 12, 12', and 12'' of wafer 226. Select a model architecture 42 and train the associated machine learning models 40, 40', and 40'' based on the generated training data. • Determine the quality of the model architecture 42 and at least one image acquisition parameter by calculating the relevant objective function values ​​of the objective function that evaluates the quality of the trained machine learning model 40, 40', and 40''. The step of repeating this step, - A step of selecting one of the model architectures 42 and at least one corresponding image acquisition parameter based on the objective function value. It further includes, Computer implementation method 182 as described in any one of paragraphs 1 to 24, wherein in step i, imaging datasets 12, 12', 12'' of wafer 226 are acquired based on at least one selected image acquisition parameter, and in step ii, the embedded system implementation model architecture 46 includes a model architecture 42 of selected machine learning models 40, 40', 40''.

[0156] 26. The computer implementation method described in Section 25, wherein the step of selecting a model architecture 42 includes selecting at least one hyperparameter that defines the model architecture 42 of the machine learning models 40, 40', and 40'' according to an architecture sampling strategy.

[0157] 27. A computer implementation method as described in Section 26, wherein the objective function includes a measure of the complexity of the model architecture.

[0158] 28. A computer implementation described in any one of paragraphs 25 to 27, wherein the objective function includes a measure of execution time, and / or a measure of throughput and / or data rate, and / or a measure of power consumption.

[0159] 29. A computer implementation method described in any one of paragraphs 25 to 28, wherein the objective function includes a measure of the quality of defect recognition.

[0160] 30. A computer-aided method according to any one of paragraphs 25 to 29, wherein at least one image acquisition parameter is from the group including imaging time, image resolution, pixel size, electron wave landing energy, and residence time.

[0161] 31. A computer implementation method described in any one of paragraphs 25 to 30, wherein the objective function includes a measure of the bit amount of input data for machine learning models 40, 40', and 40''.

[0162] 32. A computer-aided method 196 for defect recognition in imaging datasets 12, 12', and 12'' of wafer 226, wherein the method is: - Until the convergence criteria are met, - Select at least one image acquisition parameter according to the imaging sampling strategy, and acquire imaging datasets 12, 12', and 12'' of wafer 226 based on the aforementioned at least one image acquisition parameter. • To generate training data from the acquired imaging datasets 12, 12', and 12'' of wafer 226. Select a model architecture 42 and train the associated machine learning models 40, 40', and 40'' based on the generated training data. • Evaluate the quality of the trained machine learning model 40, 40', and 40'' by calculating the relevant objective function values ​​for the objective function. Repeating this step, - Select one of the trained machine learning models 40, 40', or 40'' based on the objective function value. - To recognize defect 16, apply selected trained machine learning models 40, 40', 40'' to imaging datasets 12, 12', 12'' of wafer 226 acquired based on at least one corresponding image acquisition parameter. Computer implementation method 196, including.

[0163] 33. The computer implementation method described in Section 32, wherein the step of selecting a model architecture 42 includes selecting at least one hyperparameter that defines the model architecture 42 of the machine learning models 40, 40', and 40'' according to an architecture sampling strategy.

[0164] 34. A computer implementation method as described in Section 33, wherein the objective function includes a measure of the complexity of the model architecture.

[0165] 35. A computer implementation method described in any one of paragraphs 32 to 34, wherein the objective function includes a measure of execution time, and / or a measure of throughput and / or data rate, and / or a measure of power consumption, during defect recognition.

[0166] 36. A computer implementation method described in any one of paragraphs 32 to 35, wherein the objective function includes a measure of the quality of defect recognition.

[0167] 37. A computer-aided method according to any one of paragraphs 32 to 36, wherein at least one image acquisition parameter is from the group including imaging time, image resolution, pixel size, electron wave landing energy, and residence time.

[0168] 38. A computer implementation method described in any one of paragraphs 32 to 37, wherein the objective function includes a measure of the bit amount of input to machine learning models 40, 40', and 40''.

[0169] 39. A computer implementation method according to any one of paragraphs 1 to 31, further comprising determining one or more measurements of defects 16 recognized in imaging datasets 12, 12', 12'' of wafer 226, in particular size, area, dimensions, shape parameters, distance, radius, aspect ratio, type, number of defects, density, spatial distribution of defects, etc.

[0170] 40. A computer implementation method according to paragraph 39, further comprising evaluating the quality of the wafer 226 based on one or more measurements and at least one quality evaluation rule.

[0171] 41. The computer implementation method according to paragraph 39, further comprising controlling at least one wafer manufacturing process parameter based on one or more measurements of defects recognized in a wafer imaging dataset.

[0172] 42. A computer implementation method according to any one of paragraphs 32 to 38, further comprising determining one or more measurements of defects 16 recognized in imaging datasets 12, 12', 12'' of wafer 226, in particular size, area, dimensions, shape parameters, distance, radius, aspect ratio, type, number of defects, density, spatial distribution of defects, presence of defects, etc.

[0173] 43. A computer implementation method according to paragraph 42, further comprising evaluating the quality of the wafer 226 based on one or more measurements and at least one quality evaluation rule.

[0174] 44. A computer-aided implementation of the method described in paragraph 42, further comprising controlling at least one wafer manufacturing process parameter based on one or more measurements of defects 16 recognized in imaging datasets 12, 12', 12'' of wafer 226.

[0175] 45. A computer-readable medium storing a computer program executable by a computing device, wherein the computer program includes code for performing any one of the methods described in paragraphs 1 through 44.

[0176] 46. ​​A computer program product that includes instructions such that, when the program is executed by a computer, the computer causes the computer to execute any one of the methods described in paragraphs 1 through 44.

[0177] 47. A system 212 for controlling the quality of wafers 226 manufactured in a semiconductor manufacturing plant, - Imaging device 214 adapted to provide imaging datasets 12, 12', 12'' of wafer 226. - One or more processing devices 216, - At least one embedded system 50, 50', - One or more machine-readable hardware storage devices containing instructions that can be executed by one or more processing devices 216 to perform an operation including the method of paragraph 40. System 212, which includes the above.

[0178] 48. A system 228 for controlling the manufacturing of wafers 226 in a semiconductor manufacturing plant, - Means 230 for manufacturing a wafer 226 controlled by at least one manufacturing process parameter, - Imaging device 214 adapted to provide imaging datasets 12, 12', 12'' of wafer 226. - One or more processing devices 216, - At least one embedded system 50, 50', - One or more machine-readable hardware storage devices containing instructions that can be executed by one or more processing devices 216 to perform an operation including the method of paragraph 41. System 228, which includes the above.

[0179] 49. Database 225 further comprises systems 212, 228 as described in paragraph 47 or 48.

[0180] 50. A system 232 for controlling the quality of wafers 226 manufactured in a semiconductor manufacturing plant, - Imaging device 214 adapted to provide imaging datasets 12, 12', 12'' of wafer 226. - One or more processing devices 216, - One or more machine-readable hardware storage devices containing instructions that can be executed by one or more processing devices 216 to perform an operation including the method of paragraph 43. System 232, which includes the above.

[0181] 51. A system 234 for controlling the manufacturing of wafers 226 in a semiconductor manufacturing plant, - Means 230 for manufacturing a wafer 226 controlled by at least one manufacturing process parameter, - Imaging device 214 adapted to provide imaging datasets 12, 12', 12'' of wafer 226. - One or more processing devices 216, - One or more machine-readable hardware storage devices containing instructions that can be executed by one or more processing devices 216 to perform an operation including the method of paragraph 44. System 234, which includes the above.

[0182] 52. Systems 212, 228, 232, 234 as described in any one of paragraphs 47 to 51, further comprising a display device 227.

[0183] 53. Systems 212, 228, 232, and 234 described in any one of paragraphs 47 through 52, further comprising a user interface 224. [Explanation of symbols]

[0184] 10, 10', 10'' cell structure 12, 12', 12'' imaging dataset 14, 14', 14'' cells 16 Defects 22. Computerized Implementation Method 26 Imaging Steps 28 Model Data Steps 30 Model Data Transfer Steps 32 Application Steps 34 New Use Cases 40, 40', 40'' Machine Learning Models 42 Model Architectures 44, 44', 44'' Model Data 46 Embedded Systems Implementation Model Architecture 48, 48', 48'' Programmable Memory 50, 50' Embedded Systems 51 Field-Programmable Gate Arrays 52 Computer-Assisted Implementation Method 56 Imaging Steps 58 Data flow specification step 60 Model Data Steps 62 Model Data Transfer Steps 64 Application Steps 66 New Use Cases 72, 72', 72'', 72'''' logic block circuits 74 Data Flow 76, 76', 76'', 76'''' Logic block circuit 78 Charged Particle Beam System 80 Adaptive Logic Modules 82 M512 block 84 M4K Blocks 86 high-speed I / O channels including Dynamic Phase Alignment (DPA) 88 I / O channels including external memory interface circuitry 90 Digital signal processing blocks 92 M-RAM blocks 94 Phase-Locked Loop 96 Programmable Memory 98 Input data bus 100 weight 102 First Module 104 Second module 106 Configuration Memory 108 Multiplexer 110 Multiplication Add 112 114 Neural Networks 116 Head Module 118 Tail Module 120 output layers 122 Hidden Layers 123 The final hidden layer 124 head module 126 Head Module 128 Tail Module 129, 129' Corresponding first layer 130 Tail Module 131, 131' Corresponding second layer 132 Tail Module 133, 133' Corresponding third layer 134 Tail Module 136 Tail Module 138 Tail Module 142 Start Determination of 144 groups 146. Determining Use Cases 148 Problem Input Step 150 data acquisition and training steps 152 Model Data Saving Step 154 Steps to collect use cases 156 Model Architecture Definition Steps 158 Feasibility Steps 160 Model Implementation Steps 162 Model Data Search Steps 164 Model Data Transfer Steps 166 Data Processing Systems 168 Stop 170 Yes 172 No 174 Yes 176 No 178 Yes 180 No 182 Computerized Implementation Method 184 Image acquisition parameter step 186 Training Data Generation Steps 188 Machine Learning Model Training Steps 190 Quality Evaluation Steps 192 Selection Steps 194 repetitions 196 Computerized Implementation Method 198 Image acquisition parameter step 200 training data generation steps 202 Machine Learning Model Training Steps 204 Quality Evaluation Steps 206 Selection Steps 208 Application Steps 210 repetitions 212 System 214 Imaging devices 216 Processing Devices 218 CPU 220 Interfaces 222 memory 224 User Interface 225 Databases 226 wafers 227 Display Devices 228 Systems 230 means 232 System 234 System

Claims

1. A computer-aided method (22) for defect recognition in an imaging dataset (12, 12', 12'') of a wafer (226) in a charged particle beam system (78) equipped with an embedded system (50, 50'), wherein the method is i. Obtain the imaging dataset (12, 12', 12'') of the wafer (226). ii. To acquire model data (44, 44', 44'') of the model architecture (42) of a machine learning model (40, 40', 40'') for defect recognition in the imaging dataset (12, 12', 12'') of the wafer (226), wherein the model architecture (42) is implemented in the embedded system (50, 50'). iii. Transferring the model data (44, 44', 44'') to the programmable memory (48, 48', 48'') of the embedded system (50, 50'), iv. Applying a machine learning model (40, 40', 40'') to an imaging dataset (12, 12', 12'') of a wafer (226), including running the embedded system implementation model architecture (46) using the transferred model data (44, 44', 44''), to recognize defects (16). Includes, Before obtaining the wafer imaging dataset (12, 12', 12'') in step (i), - Until the convergence criteria are met, - Select at least one image acquisition parameter according to the imaging sampling strategy, and acquire an imaging dataset (12, 12', 12'') of the wafer (226) based on the at least one image acquisition parameter. - To generate training data from the acquired imaging dataset (12, 12', 12'') of the wafer (226), - Select a model architecture (42) and train the associated machine learning models (40, 40', 40'') based on the generated training data. - Determine the quality of the model architecture (42) and the at least one image acquisition parameter by calculating the relevant objective function values ​​of the objective function that evaluates the quality of the trained machine learning model (40, 40', 40''), The step of repeating this step, - A step of selecting one of the model architectures (42) and the corresponding at least one image acquisition parameter based on the objective function value. It further includes, A computer implementation (22) wherein, in step (i), the imaging dataset (12, 12', 12'') of the wafer (226) is acquired based on the selected at least one image acquisition parameter, and the embedded system implementation model architecture (46) in step (ii) includes the model architecture (42) of the selected machine learning model (40, 40', 40'').

2. A computer-aided method (52) for defect recognition in an imaging dataset (12, 12', 12'') of a wafer (226) in a charged particle beam system (78) comprising at least one embedded system (50, 50'), wherein the method is i. Obtain the imaging dataset (12, 12', 12'') of the wafer (226). ii. Defining an embedded system implementation model architecture (46) of a machine learning model (40, 40', 40'') for defect recognition in the imaging dataset (12, 12', 12'') of the wafer (226) by specifying the data flow (74) through some logic block circuits (72', 72''', 74, 74', 74''', 74''', 74''', 40''', 72''', 72''', 72''', 742''', 72''', 72''', 72''', 72''', 72''', 72''', 72''', 72''', 72''', 72''', 72''', 72''', 72''', 72''', 72''', 72''', 72''', 72''', 72''', 72''' iii. Obtain model data (44, 44', 44'') of the embedded system implementation model architecture (46), iv. Transferring the model data (44, 44', 44'') to the programmable memory (48, 48', 48'') of the embedded system (50, 50'), v. Applying the machine learning model (40, 40', 40'') to the imaging dataset (12, 12', 12'') of the wafer (226), including running the embedded system implementation model architecture (46) using the transferred model data (44, 44', 44''), to recognize defects (16). Includes, The at least one model architecture (42) of the at least one machine learning model (40, 40', 40'') for defect recognition includes a model architecture (42) of a neural network (114), A computer implementation (52) in which one or more modules (102, 104) are head modules (116, 124, 126), and the head modules (116, 124, 126) are modules that include an output layer (120) of a neural network (114).

3. The computer implementation method according to claim 2, wherein one or more modules (102, 104) are tail modules (118, 128, 130, 132, 134, 136, 138), and the tail modules (118, 128, 130, 132, 134, 136, 138) are modules that include several hidden layers (122) of a neural network (114).

4. The computer implementation method according to claim 3, wherein at least two of the tail modules (118, 128, 130, 132, 134, 136, 138) include the same number of hidden layers (122, 123), and the feature map sizes of the corresponding layers (129, 129', 131, 131', 133, 133') differ by the same multiple.

5. The computer implementation method according to claim 2, wherein each module (102, 104) among the one or more modules (102, 104) is either a head module (116, 124, 126) containing an output layer (120) of a neural network (114), or a tail module (118, 128, 130, 132, 134, 136, 138) containing several hidden layers (122) of a neural network (114).

6. The computer implementation method according to claim 2, wherein each model architecture (42) is divided into head modules (116, 124, 126) containing the output layer (120) of the neural network (114) and at least one tail module (118, 128, 130, 132, 134, 136, 138) containing several hidden layers (122) of the neural network (114), so that one or more modules (102, 104) are generated from at least one model architecture (42) of the neural network (114).

7. The computer implementation method according to claim 6, wherein each model architecture (42) of the neural network (114) is divided into task-specific head modules (116, 124, 126) and a single tail module (118, 128, 130, 132, 134, 136, 138).

8. Before specifying the data flow (74) through some of the logic block circuits (72', 72''') among the plurality of logic block circuits (72, 72', 72''', 74, 74', 74'', 74'''), the model architecture (42) of the machine learning model (40, 40', 40'') is defined in one of the at least one embedded system (50, 50') as the plurality of logic block circuits (72, 72', 72''', 72''', 74, 74', 74'', 74'' The computer implementation method according to claim 2, further comprising: determining whether it can be realized by '') and, in response to determining that the model architecture (42) cannot be realized, generating one or more modules (102, 104) of the model architecture (42) of the machine learning model (40, 40', 40'') and implementing the one or more modules (102, 104) in one of the at least one embedded system (50, 50').

9. The computer implementation method according to claim 1, wherein the model data (44, 44', 44'') of the embedded system implementation model architecture (46) is obtained by training a machine learning model (40, 40', 40'') that includes the model architecture.

10. The computer implementation method according to claim 1, wherein the model data (44, 44', 44'') is transferred to the programmable memory (48, 48', 48'') of the embedded system (50, 50') by replacing the hardware block including the programmable memory (48, 48', 48'') of the embedded system (50, 50') with a new hardware block including the model data (44, 44', 44'') to be transferred.

11. The step of selecting a model architecture (42) includes selecting at least one hyperparameter that defines the model architecture (42) of the machine learning model (40, 40', 40'') according to an architecture sampling strategy, The objective function includes a measure of the complexity of the model architecture (42), and / or a measure of execution time, and / or a measure of throughput and / or data rate, and / or a measure of power consumption and / or a measure of the quality of defect recognition, The computer implementation method according to claim 1.

12. The computer-aided method according to claim 1, wherein the at least one image acquisition parameter is from the group including imaging time, image resolution, pixel size, electron wave landing energy, and residence time.

13. A computer implementation method (196) for defect recognition in an imaging dataset (12, 12', 12'') of a wafer (226), wherein the method is - Until the convergence criteria are met, - Select at least one image acquisition parameter according to the imaging sampling strategy, and acquire an imaging dataset (12, 12', 12'') of the wafer (226) based on the at least one image acquisition parameter. - To generate training data from the acquired imaging dataset (12, 12', 12'') of the wafer (226), - Select a model architecture (42) and train the associated machine learning models (40, 40', 40'') based on the generated training data. - Evaluate the quality of the trained machine learning model (40, 40', 40'') by calculating the relevant objective function values ​​of the objective function. Repeating this step, - Select one of the trained machine learning models (40, 40', 40'') based on the objective function value. - To recognize defects (16), apply the selected trained machine learning model (40, 40', 40'') to the image dataset (12, 12', 12'') of the wafer (226) acquired based on the corresponding at least one image acquisition parameter. Includes, A computer-aided method (196) wherein the at least one image acquisition parameter is from the group including imaging time, image resolution, pixel size, electron wave landing energy, and residence time.

14. The step of selecting a model architecture (42) includes selecting at least one hyperparameter that defines the model architecture (42) of the machine learning model (40, 40', 40'') according to an architecture sampling strategy, The objective function includes a measure of the complexity of the model architecture (42), and / or a measure of execution time, and / or a measure of throughput and / or data rate, and / or a measure of power consumption during defect recognition and / or a measure of the quality of defect recognition, The computer implementation method according to claim 13.

15. The computer-aided method according to claim 1, further comprising determining one or more measurements of the recognized defect (16) in the imaging dataset (12, 12', 12'') of the wafer (226).

16. The computer implementation method according to claim 15, further comprising evaluating the quality of the wafer (226) based on one or more measurements and at least one quality evaluation rule.

17. The computer implementation method according to claim 15, further comprising controlling at least one wafer manufacturing process parameter based on one or more measurements of the recognized defects in the imaging dataset of the wafer.

18. A computer-readable medium storing a computer program executable by a computing device, wherein the computer program includes code for performing the method of claim 1.

19. A computer program that includes instructions, wherein the instructions cause the computer to execute the method of claim 1 when the program is executed by the computer.

20. A system (212) for managing the quality of wafers (226) manufactured in a semiconductor manufacturing plant, - Imaging device (214) adapted to provide an imaging dataset (12, 12', 12'') of a wafer (226), - One or more processing devices (216), - At least one embedded system (50, 50'), - One or more machine-readable hardware storage devices that include instructions executable by one or more processing devices (216) to perform an operation including the method of claim 16. A system (212) comprising the above.

21. A system (228) for controlling the manufacturing of wafers (226) in a semiconductor manufacturing plant, - Means (230) for manufacturing a wafer (226) controlled by at least one manufacturing process parameter, - Imaging device (214) adapted to provide an imaging dataset (12, 12', 12'') of a wafer (226), - One or more processing devices (216), - At least one embedded system (50, 50'), - One or more machine-readable hardware storage devices that include instructions executable by one or more processing devices (216) to perform an operation including the method of claim 17. A system (228) that includes the following:

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