Switch circuit and power supply circuit

Abstract

Provided are a switch circuit and a power supply circuit capable of reducing power consumption.　A switch circuit (25) comprises: an electric field effect switch element (M1) that can switch between an ON state and an OFF state according to the potential (VC1) of a control terminal (TP1); and a control circuit (18a) which, when maintaining one among the ON state and the OFF state of the switch element (M1), supplies the control terminal (TC1) with a first level potential that causes the switch element (M1) to be in the one state, and when changing the switch element (M1) from the one state to the other state among the ON state and the OFF state, charges or discharges and then floats the control terminal (node N1) via resistors (M2, M3), and supplies a second level potential that causes the switch element (M1) to be in the other state.

Description

Switching and power supply circuits

[0001] The present invention relates to a switch circuit and a power supply circuit.

[0002] There is known a power supply circuit that converts the voltage of power generated by a power generation element such as an energy harvesting element and stores the power in a capacitor or other storage device. In such a power supply circuit, switching for converting the power voltage is achieved by a field effect transistor (FET) and a control circuit that controls the gate voltage of the FET (see, for example, Patent Document 1).

[0003] JP 2014-33494 A

[0004] In Patent Document 1, the gate voltage that turns on the MOSFET (M1) is generated by dividing the voltage between the node between the power generating element and the MOSFET (M1) and ground using resistors R2 and R3 (see Figure 1 of Patent Document 1). However, while the MOSFET (M1) is in the on state, current continues to flow through resistors R2 and R3, resulting in increased power consumption. This affects the power consumption of circuits that require low power consumption, such as circuits that use so-called energy harvesting elements as power supply elements when the power supply circuit of Patent Document 1 is used. This effect is not limited to the circuit of Patent Document 1, but occurs in similar circuits with similar switching functions.

[0005] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a switch circuit and a power supply circuit that are capable of reducing power consumption.

[0006] The present invention provides a switch circuit comprising: a field-effect switch element that can be switched between an on state and an off state according to the potential of a control terminal; and a control circuit that, when maintaining one of the on state and off state of the switch element, supplies a first level potential to the control terminal for causing the switch element to change to one of the states, and, when changing the switch element from one of the states to the other of the on state and off state, charges or discharges the control terminal via a resistor and then makes it floating, and supplies a second level potential for causing the switch element to change to the other state.

[0007] In the above configuration, the control circuit may be configured to float the control terminal when supplying the first level potential to the control terminal.

[0008] In the above configuration, the switch element may be an element that turns on and off the electromotive force supplied from the power generating element.

[0009] In the above configuration, the switch element may be an element that turns on and off the supply of power to the sensor circuit.

[0010] The above configuration may further include a maintenance circuit that maintains the potential of the control terminal within a predetermined range.

[0011] In the above configuration, the sustain circuit may include a diode connected to the control terminal.

[0012] In the above configuration, the switch element may be a first FET having a source connected to a first terminal, a drain connected to a second terminal, and a gate connected to a first node capacitively coupled to a first control terminal.

[0013] In the above configuration, the circuit may further include a second FET having a source connected to the first node, a drain connected to the first terminal, and a gate, wherein either of the states is an off state, and the control circuit, when switching the first FET from an off state to an on state, switches the connection between the source and drain of the second FET to an off state and connects the first node to a reference potential via the resistor, and then disconnects the first node from the first terminal and the reference potential and supplies the second level potential to the first control terminal.

[0014] In the above configuration, a third FET may be provided having a source connected to the reference potential, a drain connected to the first node, and a gate, the resistance being a resistance between the source and drain of the third FET, and a saturation current may flow in the third FET when the first node is connected to the reference potential via the second FET.

[0015] In the above configuration, a rectifying element may be provided, in which the direction of a second node capacitively coupled from the first node to a second control terminal is a forward direction, the second FET is an N-type, the gate of the second FET is connected to the second node, the first FET is a P-type, and the first node is connected to the reference potential via the rectifying element, the second node, and the resistor.

[0016] In the above configuration, a rectifying element may be provided, in which the direction from a second node capacitively coupled to a second control terminal to the first node is a forward direction, the second FET is a P-type and connected to the second node capacitively coupled to the second control terminal, the first FET is an N-type, and the first node is connected to the reference potential via the rectifying element, the second node, and the resistor.

[0017] In the above configuration, the control circuit can be configured to, when the first FET maintains its on state, supply the second level potential to the first control terminal and supply the second control terminal with a third level potential that turns the second FET to an off state, and, when turning the first FET from an on state to an off state, supply the second control terminal with a fourth level potential that turns the second FET to an on state, and then supply the first level potential to the first control terminal and supply the third level potential to the second control terminal.

[0018] In the above configuration, when the first FET is changed from an on state to an off state, the control circuit may be configured to supply the third level potential to the second control terminal, and then supply the first level potential to the first control terminal.

[0019] The above configuration may further include a determination circuit that determines, when the first FET maintains its off state, whether the input voltage input to the first terminal has changed by a certain voltage from the input voltage when the first FET was previously switched from an on state to an off state, and the control circuit, when determining that the input voltage has changed by a certain voltage, supplies the first control terminal with the second level and the second control terminal with the fourth level, and thereafter supplies the first level to the first control terminal and the third level to the second control terminal.

[0020] In the above configuration, the determination circuit may include a comparator that compares the voltage of a third node capacitively coupled to the first terminal with a fixed voltage and outputs the comparison result to the control circuit.

[0021] In the above configuration, the input voltage input to the first terminal may be higher than the reference potential, and the first FET may be a PFET.

[0022] In the above configuration, the input voltage input to the first terminal may be lower than the reference potential, and the first FET may be an NFET.

[0023] In the above configuration, the power generating element may be a vibration power generating element.

[0024] The present invention is a power supply circuit including the above switch circuit.

[0025] According to the present invention, it is possible to provide a switch circuit and a power supply circuit that can reduce power consumption.

[0026] FIG. 1 is a circuit diagram showing a first embodiment of a power supply circuit using a switch circuit shown in FIG. 3 in detail. FIG. 2 is a timing chart showing the on / off states of switches constituting the voltage conversion circuit shown in FIG. 1 and a current IL flowing through an inductor. FIG. 3 is a detailed circuit diagram of a switch circuit constituting the power supply circuit of the first embodiment, showing details of a switch indicated as HSW in FIG. 1 and its control circuit. FIG. 4 is a timing chart showing time variations in each voltage and on / off state of the switch circuit shown in FIG. 3. FIG. 5 is a detailed circuit diagram of a switch circuit constituting a power supply circuit of the second embodiment, showing details of a switch indicated as HSW in FIG. 1 and its control circuit. FIG. 6 is a timing chart showing time variations in each voltage and on / off state of the switch circuit shown in FIG. 5. FIG. 7 is a detailed circuit diagram of a switch circuit constituting a power supply circuit of the third embodiment, showing details of a switch indicated as HSW in FIG. 1 and its control circuit. FIG. 8 is a timing chart showing time variations in each voltage, current, and on / off state of the switch circuit shown in FIG. 7. Fig. 9 is a detailed circuit diagram of a switch circuit constituting a power supply circuit of Example 4, showing details of the switch shown as HSW in Fig. 1 and its control circuit. Fig. 10(a) is a block diagram showing an example of a power supply circuit of the present invention, in which a switch circuit of any of Examples 1 to 4 and their modifications is used in a voltage conversion circuit 64. Fig. 10(b) is a block diagram showing a system of a sensor circuit in which a switch circuit of any of Examples 1 to 4 and their modifications is used.

[0027] Hereinafter, an embodiment will be described with reference to the drawings.

[0028] Fig. 1 is a circuit diagram showing a first embodiment of a power supply circuit using a switch circuit whose details are shown in Fig. 3. The output current of a power generating element 10 is input to an input terminal Tin of a voltage conversion circuit 12 in Fig. 1. When a power generating element that outputs an AC current is used as the power generating element 10, the output current of the power generating element 10 is rectified by a rectifier circuit 11 and input to the input terminal Tin.

[0029] The power generating element 10 is an energy harvesting element such as a vibration power generating element. The vibration power generating element is, for example, a piezoelectric element using a piezoelectric material or a MEMS element using a MEMS (Micro Electro Mechanical System). The vibration power generating element is installed, for example, on a road or a bridge, and generates power from vibrations caused by pedestrians or vehicles passing by. When a vibration power generating element is used as the power generating element 10, the generated power is a minute AC power that changes with the state of vibration. When a piezoelectric element is used, the output voltage is relatively higher than the several volts generally required for electronic circuit operation. In the first embodiment, the rectifier circuit 11 makes the input to the input terminal Tin positive with respect to ground.

[0030] Nodes N01 to N04 are provided between the input terminal Tin and the output terminal Tout of the voltage conversion circuit 12. The voltage conversion circuit 12 of this embodiment steps down the relatively high voltage from the power generation element 10 and outputs it to the output terminal Tout. The switch HSW is a high-side switch provided on the high-voltage side (referred to as the high side) of the voltage conversion circuit 12. One end of the switch HSW, a terminal Tsw1, is connected to the node N01, and the other end, a terminal Tsw2, is connected to the node N02. One end of the inductor L1 is connected to the node N02, and the other end is connected to the node N03. One end of the switch SW3 is connected to the node N03, and the other end is connected to the node N04. One end of the capacitor C01 on the primary side of the voltage conversion circuit 12 is connected to the node N01, and the other end is connected to ground (reference potential). One end of the capacitor C02 on the secondary side of the voltage conversion circuit 12 is connected to the node N04, and the other end is connected to ground. The switch SW1 has one end connected to the node N02 and the other end connected to the ground, and the switch SW2 has one end connected to the node N03 and the other end connected to the ground.

[0031] The control unit 14 outputs control signals Sh and S1 to S3 to the switches HSW and SW1 to SW3, respectively. The switches HSW and SW1 to SW3 are turned on or off based on the control signals Sh and S1 to S3, respectively. In this embodiment, the control unit 14 generates the control signal Sh at a constant cycle. The frequency of the control signal Sh is sufficiently higher than the frequency of the AC component contained in the electromotive force output from the power generating element 10 and the rectifier circuit 11. The frequency of the control signal Sh is determined so as to achieve impedance matching for efficiently transmitting the electromotive force output from the power generating element 10 and the rectifier circuit 11 to the voltage conversion circuit 12. The control unit 14 may also detect the voltages Vin and Vout and output the control signals Sh and S1 to S3 based on the voltages Vin and Vout.

[0032] When a positive current with respect to ground is input from the power generating element 10 to the input terminal Tin via the rectifier circuit 11, the capacitor C01 is charged. The potential of the capacitor C01 with respect to ground on the node N01 side is referred to as the input voltage Vin of the input terminal Tin. The charge of the capacitor C01 moves to the capacitor C02 due to the operation of the voltage conversion circuit 12, i.e., the operation of the switches HSW, SW1, SW2, and SW3 in the voltage conversion circuit 12, which will be described later. The potential of the capacitor C02 with respect to ground on the node N04 side is referred to as the voltage Vout of the output terminal Tout.

[0033] FIG. 2 is a timing chart showing the on / off states of the switches constituting the voltage conversion circuit shown in FIG. 1 and the current IL flowing through the inductor. FIG. 2 shows the value of the input voltage Vin, the on and off states of the switches in FIG. 1, the current IL flowing through the inductor L1, and the value of the output voltage Vout. Time t00 in FIG. 2 represents a certain timing during operation of the power supply circuit. At that time, current from the power generation element 10 is stored in capacitor C01, and the resulting voltage Vin is Vin1. Charge is also stored in capacitor C02 due to the voltage conversion operation described below, and the resulting voltage Vout is Vout1. At time t00, the control unit 14 maintains switches HSW and SW1 to SW3 in the off state.

[0034] The charge stored in capacitor C01 increases due to the current generated by power generating element 10, and after voltage Vin exceeds a predetermined threshold voltage, at time t01, control unit 14 turns on switches HSW and SW2 while maintaining switches SW1 and SW3 in an off state. This causes current IL to begin flowing from capacitor C01 to ground via node N01, switch HSW, inductor L1, and switch SW2. Control unit 14 may detect voltage Vin at input terminal Tin and turn on switches HSW and SW2 when voltage Vin exceeds a predetermined threshold voltage, or may turn on switches HSW and SW2 periodically. Between times t01 and t02, current IL gradually increases, and voltage Vin gradually decreases as the charge in capacitor C01 is released. Magnetic field energy is stored in inductor L1.

[0035] At time t02, the voltage Vin becomes voltage Vin2. The voltage Vout is voltage Vout1. At time t02, when the current IL becomes IL1, the control unit 14 turns off the switches HSW and SW2 and turns on the switches SW1 and SW3. The control unit 14 detects the voltage Vin at the input terminal Tin, and when the voltage Vin becomes Vin2, the control unit 14 may turn off the switches HSW and SW2 and turn on the switches SW1 and SW3, or may turn off the switches HSW and SW2 and turn on the switches SW1 and SW3 at a predetermined interval. Between times t02 and t03, the magnetic field energy stored in the inductor L1 causes the current IL to flow from ground through the switch SW1, inductor L1, and switch SW3. As the capacitor C02 is charged, the voltage Vout increases.

[0036] At time t03, the control unit 14 turns off the switches SW1 and SW3 and maintains the switches HSW and SW2 in the off state. The control unit 14 may detect the voltage Vout at the output terminal Tout and turn off the switches SW1 and SW3 when the voltage Vout reaches a predetermined threshold voltage, or may turn off the switches SW1 and SW3 at a predetermined interval. After time t03, the current IL is 0, the voltage Vin is Vin2, and the voltage Vout is Vout2. The voltages Vout1 and Vout2 may be lower or higher than the voltages Vin1 and Vin2. The voltages Vout1 and Vout2 can be set by appropriately setting the capacitance values ​​of the capacitors C01 and C02 and the on / off timing of the switches HSW and SW1 to SW3.

[0037] FIG. 3 is a detailed circuit diagram of a switch circuit constituting the power supply circuit of the first embodiment, showing details of the switch designated as HSW in FIG. 1 and its control circuit. Hereinafter, a FET with a P-type channel conductivity will be referred to as a PFET, and a FET with an N-type channel conductivity will be referred to as an NFET. The on / off state of PFET M1 corresponds to the on / off state of switch HSW. As shown in FIG. 3 , in switch circuit 25 of the first embodiment, the source of PFET M1 (first FET) is connected to terminal Tsw1 (first terminal), the drain is connected to terminal Tsw2 (second terminal), and the gate is connected to node N1 (first node). A control signal VC1 (first control signal) is input to one end of capacitor C1 (first capacitor), and the other end is connected to node N1. That is, the gate is capacitively coupled to control terminal TC1 (first control terminal). The source of NFET M2 (second FET) is connected to node N1, its drain is connected to terminal Tsw1, and its gate is connected to control terminal TC2, to which control signal VC2 is input via capacitor C2 (second capacitor). The source of NFET M3 (third FET) is connected to ground (reference potential), its drain is connected to node N1, and its gate is connected to control terminal TC3, to which control signal VC3 is input. Control circuit 18a receives control signal Sh, which is output by control unit 14 of FIG. 1. Control circuit 18a controls the states of PFET M1, NFET M2, and NFET M3 by changing the levels of control signals VC1, VC2, and VC3 at a timing based on the control signal Sh.

[0038] Fig. 4 is a timing chart showing the time variations in the voltages and on / off states of the switch circuit shown in Fig. 3. As shown in Fig. 4, between times t10 and t11, during which switch HSW maintains its off state, control circuit 18a sets control signal VC1 to high level H (voltage X), control signal VC2 to high level H, and control signal VC3 to low level L. Because NFET M2 is on, voltage G1 is at voltage Vin, and PFET M1 is off.

[0039] The control unit 14 in FIG. 1 detects the voltage Vin at the input terminal Tin, and when it determines at time t01 in FIG. 2 that the voltage Vin exceeds a predetermined threshold voltage, it outputs a control signal Sh to instruct the switch HSW to switch from an OFF state to an ON state. The control unit 14 may output the control signal Sh to switch the switch HSW from an OFF state to an ON state at a predetermined period. When the control signal Sh instructs the switch HSW to switch from an OFF state to an ON state, the control circuit 18a executes an operation to switch the PFET M1 from an OFF state to an ON state between times t11 and t13. At time t11, the control circuit 18a sets the control signal VC2 to low level L, sets the control signal VC3 to high level H, and maintains the control signal VC1 at high level H. This turns NFET M2 off and NFET M3 on. A current Im3 flows from node N1 to ground. When the voltage difference between node N1 and ground is in the saturation region of NFET M3 (the region where the drain current is saturated), current Im3 is substantially constant regardless of the voltage difference between node N1 and ground, causing voltage G1 at node N1 to gradually decrease due to current Im3 between times t11 and t12 in FIG.

[0040] When control circuit 18a determines that a predetermined period has elapsed since time t11, at time t12, it sets control signal VC3 to low level L, maintains control signal VC1 at high level H, and maintains control signal VC2 at low level L. NFET M3 is turned off. Between times t12 and t13, voltage G1 remains substantially constant. When control circuit 18a determines that a predetermined period has elapsed since time t12, at time t13 it sets control signal VC1 to low level L, maintains control signal VC3 at low level L, and maintains control signal VC2 at low level L. As a result, voltage G1 is reduced from voltage Vin by voltage difference X (the difference between high level H and low level L of control signal VC1), becoming voltage Vin-X. PFET M1 is turned on. Current IP flows through inductor L1 of FIG. 1, and gradually increases after time t12. Thus, NFET M2 is off when PFET M1 remains on. After time t12, node N1 becomes floating, but if the time between times t12 and t13 is short, for example, on the order of a few microseconds, fluctuations in voltage G1 do not substantially pose a problem. In order to set voltage G1 to voltage Vin-X, it is preferable that the timing at which control signal VC1 is set to low level L be after the timing at which control signal VC3 is set to low level L.

[0041] As described above, according to the first embodiment, when the control circuit 18a changes PFET M1 from an off state to an on state, it charges or discharges node N1 via resistor (NFET M3) (between times t11 and t12). Then, node N1 is floated (time t12), and after a predetermined time, the control signal VC1 is set to low level L (the second level that turns PFET M1 on) (time t13). This causes PFET M1 to turn on. While current flows through NFET M3 between times t11 and t12, NFET M3 is off from time t13 onward, so the potential of node N1 is floating. Therefore, no current flows between terminal Tsw1 and ground. This reduces power consumption compared to the case of Patent Document 1, in which current continues to flow through resistors R2 and R3 while the MOSFET (M1) (see FIG. 1 of Patent Document 1) is on.

[0042] Furthermore, when switching PFET M1 from an off state to an on state, control circuit 18a switches NFET M2 off, disconnects node N1 from terminal Tsw1 (time t11), and then connects node N1 to ground via NFET M3 (between times t11 and t12). Control circuit 18a then disconnects node N1 from ground (time t12) and supplies a low level L to control terminal TC1 (time t13). This allows voltage G1 to be stably maintained at voltage Vin-X due to the reduction in voltage G1 caused by the capacitive coupling of capacitor C1 and the reduction in voltage G1 caused by current Im3 through NFET M3. This allows PFET M1 to be stably switched from an off state to an on state. This allows voltage conversion circuit 12 to operate stably when it should, improving conversion efficiency.

[0043] In this embodiment, a PFET may be used for the third FET corresponding to NFET M3. To use a PFET for the third FET, the control signal VC3 that turns the first switch on is set to voltage G1-X. Because voltage G1 fluctuates as shown in the graph of FIG. 4, a generation circuit that generates the control signal VC3 in response to fluctuations in voltage G1 is provided. On the other hand, when an NFET is used for the third FET corresponding to NFET M3, the control signal VC3 can be set to a constant voltage (high level H) relative to ground to turn the third FET on, making it easy to generate the control signal VC3. Therefore, the first switch can be stably turned on at a predetermined timing. When an NFET is used for the first switch, the aforementioned generation circuit is not required, as compared to when a PFET is used, and the power consumption of the generation circuit does not increase the power consumption of the entire power supply circuit. Furthermore, when an NFET is used for the third FET, the control circuit 18a is configured to output the control signal VC3, which is a voltage value set so that a saturation current flows between the source and drain of NFET M3 when the control signal VC3 is high level H (first level). This allows current Im3 to be constant regardless of the voltage difference between node N1 and ground. Therefore, by setting the interval between times t11 and t12, the decrease in voltage G1 from time t11 to time t12 can be kept approximately constant regardless of the voltage value of voltage Vin. Therefore, voltage G1 at time t13 can be set to approximately voltage Vin-X regardless of the voltage value of voltage Vin. Therefore, PFET M1 can be stably switched from an off state to an on state. This allows voltage conversion circuit 12 to operate when it should, improving conversion efficiency.

[0044] In this embodiment, a PFET may be used for the second FET corresponding to NFETM2. To use a PFET for the second FET, a generation circuit is provided that generates voltage Vin-X as the control signal VC2 that turns on the second FET. On the other hand, when an NFET is used for the second switch corresponding to NFETM2, the control signal VC2 is simply set to a constant voltage (high level H) relative to voltage G1 or ground when turning on the second FET, making it easy to generate the control signal VC2. Therefore, the second FET can be stably turned on at a predetermined timing. When an NFET is used for the second FET, the aforementioned generation circuit is not required, as compared to when a PFET is used, and the power consumption of the generation circuit does not increase the power consumption of the entire power supply circuit.

[0045] In the above-described Example 1, the first FET having a first terminal Tsw1 connected to the power generating element 10, a second terminal Tsw2, a source connected to the first terminal Tsw1, a drain connected to the second terminal Tsw2, and a gate connected to a first node N1 capacitively coupled to the first control terminal TC2 was defined as the PFET M1 in FIG. 3 .

[0046] When the first FET M1 maintains either the off state or the on state, a first level at which the first FET M1 is in either of the two states is supplied to the first control terminal TC1, and when the first FET M1 is changed from either of the two states to the other of the off state and the on state, the first node N1 is charged or discharged via a resistor, thereafter the first node N1 is made floating, and a control circuit 18a that supplies VC1, VC2, and VC3 to the first control terminal TC1 is configured.

[0047] In this embodiment, the control signal Sh has a constant period, and its frequency is sufficiently higher than the frequency of the AC component contained in the electromotive force output from the power generating element 10 and the rectifier circuit 11. However, the power consumption of the FETs M1 to M3 increases in proportion to the frequency of the control signal Sh. Therefore, in order to transmit the power generated in the power generating element 10 to the capacitor C02 in the subsequent stage as efficiently as possible, it is preferable that the frequency of the control signal Sh is low.

[0048] Furthermore, as described above, in the first embodiment, the control signal Sh is generated at a constant cycle. However, instead of at a constant cycle, the control signal Sh may be generated by detecting with a comparator that the voltage of the secondary-side capacitor C02 (node ​​N04) has reached a predetermined voltage required to drive the load. Alternatively, the control signal Sh may be generated by detecting with a comparator that the voltage of the primary-side capacitor C01 (node ​​N01) has reached a predetermined voltage. In FIG. 4, the control signal VC3 may go high level H after the switch SW5 is turned off.

[0049] In the first modification of the first embodiment, the control terminal TC2 and the gate of NFET M2 are capacitively coupled. As a result, when the control circuit 18a switches the control signal VC2 from low level L to high level H, the voltage G2 at the gate of NFET M2 goes high level H. This turns NFET M2 on. However, because the gate of NFET M2 is floating, the voltage G2 is unstable.

[0050] In the first embodiment, depending on the cycle in which the control signal VC1 is set to high and low levels or circuit constants such as the saturation current value between the source and drain of NFET M3, it is possible that voltage G2 may not be stable during the period in which the gate of NFET M2 is floating. In this case, the operation of switch HSW (PFET M1) may become unstable, and the power supply circuit as a whole may not exhibit the desired performance. In the second embodiment, a switch circuit that exhibits the desired performance as a power supply circuit even in such a case is described.

[0051] FIG. 5 is a detailed circuit diagram of a switch circuit constituting a power supply circuit according to a second embodiment, showing details of the switch designated as HSW in FIG. 1 and its control circuit. As shown in FIG. 5 , in the switch circuit 26 according to the second embodiment, a control signal VC2 is input to one end of a capacitor C2 (second capacitor), and the other end is connected to a node N2 (second node). A diode D (rectifying element) has an anode connected to a node N1 and a cathode connected to a node N2 between an NFET M2 and the capacitor C2. The forward direction is from node N1 to N2. The drain of an NFET M3 is connected to node N1 via the node N2 and the diode D. An NFET M2 (second FET) has a source connected to node N1, a drain connected to a terminal Tsw1, and a gate connected to a node N2 capacitively coupled to a control terminal TC2 (second control terminal). The rest of the configuration of the power supply circuit is the same as that of the first embodiment, and therefore a description thereof will be omitted.

[0052] 6 is a timing chart showing the voltages and on / off changes over time of the switch circuit shown in FIG. 5. As shown in FIG. 6, between times t10 and t11 when the switch HSW remains in the off state, the control circuit 18b sets the control signal VC1 to high level H (voltage X), the control signal VC2 to low level L, and the control signal VC3 to low level L. In the same state as from time t16 onwards, the voltage G1 is set to voltage Vin. The voltage G2 is voltage Vin-ΔV, where ΔV is the forward voltage drop of the diode D.

[0053] When control signal Sh commands switch HSW to be switched from an off state to an on state, control circuit 18b switches PFET M1 from an off state to an on state between times t11 and t13. At time t11, control circuit 18b raises control signal VC3 to high level H while maintaining control signals VC1 and VC2 at high level H and low level L, respectively. This turns NFET M3 on, causing current Im3 to flow from nodes N2 and N1 to ground. Between times t11 and t12, current Im3 reduces voltage G2, and current flows from node N1 to N2 via diode D, reducing voltage G1.

[0054] At time t12, control circuit 18b sets control signal VC3 to low level L and maintains control signals VC1 and VC2 at high level H and low level L, respectively. NFET M3 is turned off. Voltage G2 becomes VG2. Voltage G1 becomes VG2+ΔV. Between time t12 and t13, voltage G1 remains approximately constant. At time t13, control circuit 18b sets control signal VC1 to low level L and maintains control signals VC2 and VC3 at low level L. As a result, voltage G1 becomes voltage Vin-X. PFET M1 is turned on, and current IP flows. Between time t13 and t14, when switch HSW remains on, control circuit 18b sets control signals VC1 to VC3 at low level L.

[0055] The control unit 14 in FIG. 1 detects the voltage Vin at the input terminal Tin, and when it determines that the voltage Vin has reached a predetermined threshold voltage at time t02 in FIG. 2, it outputs a control signal Sh to instruct the switch HSW to switch from an ON state to an OFF state. The control unit 14 may output the control signal Sh to switch the switch HSW from an ON state to an OFF state at a predetermined period. When the control signal Sh instructs the switch HSW to switch from an ON state to an OFF state, the control circuit 18b executes an operation to switch the PFET M1 from an ON state to an OFF state between times t14 and t16. At time t14, the control circuit 18b sets the control signal VC2 to a high level H and maintains the control signals VC1 and VC3 at a low level L. Between times t14 and t15, the voltage G2 at the node N2 capacitively coupled to the control terminal TC2 rises. Because the NFET M2 is turned on, the voltage G1 gradually rises. When voltage G1 rises above the threshold voltage of PFET M1, PFET M1 turns off and current IP becomes 0. If voltage G1 rises above the threshold voltage of PFET M1 later than time t14, PFET M1 turns on later than time t14.

[0056] At time t15, the control circuit 18b sets the control signal VC2 to low level L and maintains the control signals VC1 and VC3 at low level L. The voltage G2 decreases. When the voltage G2 becomes lower than the voltage G1-ΔV, a current flows from the node N1 to the node N2 via the diode D. As a result, the voltage G1 decreases slightly and the voltage G2 increases slightly, so that the voltages G1 and G2 reach an equilibrium state.

[0057] At time t16, control circuit 18b sets control signal VC1 to high level H and maintains control signals VC2 and VC3 at low level L. Voltage G1 at node N1, which is capacitively coupled to control terminal TC1, rises. Current flows from node N1 to N2 via diode D, causing voltage G2 to rise. Since NFET M2 is fully on, voltage G1 becomes voltage Vin. Voltage G2 becomes voltage Vin-ΔV. Since voltage G2 stabilizes, voltage G1 also stabilizes, and PFET M1 stabilizes in the off state.

[0058] According to the second embodiment, when PFET M1 is changed from an off state to an on state, as well as when PFET M1 is changed from an on state to an off state, control circuit 18b charges or discharges node N2 through a resistor (i.e., the resistor between the source and drain of NFET M2) (between times t14 and t15). Control circuit 18b then floats node N2 (at time t15) and supplies a low level L to control terminal TC2 (at time t16). Thus, in the second embodiment, when PFET M1 remains in either the off state or the on state, control circuit 18b supplies a first level potential (a level that causes PFET M1 to be in either the off state or the on state) to control terminal TC1. When PFET M1 is changed from either the off state or the on state to the other of the off state or the on state, control circuit 18b charges or discharges node N1 through a resistor (between times t11 and t12 and between t14 and t15). Thereafter, control circuit 18b floats node N1 (times t12 and t15) and supplies a second level potential (a level that puts PFET M1 in the other of the off and on states) to control terminal TC1 (times t13 and t16).

[0059] Thus, PFET M1 (switch element) is a field-controlled switch element whose on and off states are switched according to the potential (voltage G1) of its gate, which is its control terminal. When maintaining the state of PFET M1, control circuit 18a supplies a first level potential to the gate that causes PFET M1 to enter either the off state or the on state. When changing PFET M1 from either of the two states to the other of the off state and on state, control circuit 18a supplies a second level potential to the gate that causes PFET M1 to enter the other state after charging or discharging it via a resistor and then floating it. As a result, when PFET M1 maintains the on or off state, node N1 is floating, thereby reducing power consumption.

[0060] Furthermore, in the second embodiment, capacitor C2, diode D, and NFET M2 are provided as a maintenance circuit that maintains voltage G1 within a predetermined range. As a result, when PFET M1 is switched from the off state to the on state, if NFET M3 is switched on from time t11 to time t12, current flows from node N1 to ground via diode D and node N2, causing voltages G1 and G2 to drop. Therefore, NFET M2 can be switched from the on state to the off state and PFET M1 can be switched from the off state to the on state, regardless of the voltage value of voltage Vin.

[0061] When PFET M1 remains on, as at times t13 and t14, control circuit 18b supplies a low-level L (second level) potential to control terminal TC1 and a low-level L (third level that turns NFET M3 off) potential to control terminal TC2. When PFET M1 is switched from on to off, as at times t14 to t16, control circuit 18b supplies a high-level H (fourth level that turns NFET M3 on) potential to control terminal TC2, then supplies a low-level L (third level) potential to control terminal TC2, and then supplies a high-level H (first level) potential to control terminal TC1. When control signal VC2 goes high and voltage G2 rises, NFET M2 turns on, raising voltages G1 and G2. Then, control signal VC1 goes high, further raising voltage G1. This allows voltage G1 to be stabilized at voltage Vin, and voltage G2 to be stabilized at voltage Vin+ΔV.

[0062] When switching PFET M1 from the ON state to the OFF state, control circuit 18b supplies a low level L (third level) to control terminal TC2 at time t15, and then supplies a high level H (first level) to control terminal TC1 at time t16, a predetermined time later. This allows control terminal TC1 to be supplied with a high level H (second level) after the transient response of voltage G2 via capacitor C2 has stabilized. This further stabilizes voltages G1 and G2. This allows PFET M1 to be stably switched to the OFF state when switching PFET M1 from the ON state to the OFF state. This prevents unintended current from flowing through voltage conversion circuit 12, improving the conversion efficiency of voltage conversion circuit 12.

[0063] The high level H of the control signal VC2 is, for example, 2 V, and the high level H of the control signal VC1 is, for example, 1 V. In this way, it is preferable that the high level H of the control signal VC2 is higher than the high level H of the control signal VC1. This allows the voltage G2 to be increased further between times t14 and t15. This allows the PFET M1 to be more stably turned off, thereby improving the conversion efficiency of the voltage conversion circuit 12.

[0064] 7 is a detailed circuit diagram of a switch circuit constituting the power supply circuit of Example 3, and is a circuit diagram showing details of the switch indicated as HSW in FIG. 1 and its control circuit. In Examples 1 and 2, the control signal Sh has a constant period, and its frequency is sufficiently higher than the frequency of the AC component contained in the electromotive force output from the power generating element 10 and the rectifier circuit 11. As the frequency of the control signal Sh increases, the power consumption of the FETs M1 to M3 increases in proportion. Therefore, in order to transmit the power generated in the power generating element 10 to the downstream capacitor C02 as efficiently as possible, it is preferable that the frequency of the control signal Sh be low. However, during the period when the electromotive force of the power generating element 10 is large and the switch HSW is in the off state between the intervals when the control signal Sh goes high and low, that is, during the period when the node N1 is set to be applied with a voltage in a floating state that prevents current from flowing between the source and drain of FET M1, if the voltage Vin rises significantly (for example, 0.3 V or more) and becomes a voltage that flows as a minute current between the source and drain of FET M1, the charge of capacitor C01 will no longer contribute to voltage conversion by the amount of that minute current, and there is a risk that the voltage conversion efficiency will decrease.

[0065] In view of this risk, in the third embodiment, to further improve voltage conversion efficiency, as shown in FIG. 7, in a switch circuit 27 of the third embodiment, a decision circuit 15 includes a comparator 16, an NFET M4, and a capacitor C3. When voltage Vin fluctuates above Vref, the decision circuit 15 outputs a reset signal Vr to a control circuit 18c. This reset signal Vr resets the gate potential of PFET M1 to the same potential as voltage Vin, similar to the control signal Sh in the second embodiment. In FIG. 7, one end of capacitor C3 is connected to a node N4 between the source of PFET M1 and terminal Tsw1, and the other end is connected to node N3 (third node). That is, node N3 is capacitively coupled to terminal Tsw1. NFET M4 has a source connected to ground, a drain connected to node N3, and a gate connected to a control terminal TC4 to which a control signal VC4 is input. Comparator 16 has a positive input terminal connected to node N3, a negative input terminal to which a reference voltage Vref is input, and an output terminal to which a reset signal Vr is output. The comparator 16 outputs a high level H as the reset signal Vr when the voltage Vm of the node N3 is equal to or higher than the reference voltage Vref, and outputs a low level L as the reset signal Vr when the voltage Vm is lower than the reference voltage Vref. The reference voltage Vref is, for example, 0.3 V.

[0066] The control circuit 18c receives the control signal Sh output by the control unit 14 and the reset signal Vr output by the comparator 16. The control circuit 18c outputs control signals VC1 to VC4 based on the control signal Sh and the reset signal Vr. The other configurations are the same as those in the second embodiment, and therefore, description thereof will be omitted.

[0067] FIG. 8 is a timing chart showing the time variations in the voltages, currents, and on / off states of the switch circuit shown in FIG. 7 . As shown in FIG. 8 , the input current Iin input from the rectifier circuit 11 to terminal Tsw1 varies depending on the amount of power generated by the power generating element 10. Here, however, it is assumed to be a very small value, Iin1, until time t20, and then Iin2 after time t20. In this timing chart, current Iin1 has almost no effect on voltage Vin or other parameters. Therefore, voltage Vin remains nearly constant from time t10 to t13 and from t14 to t20. Between times t13 and t14, charge transfers from capacitor C1 to C2, resulting in a slight decrease in voltage Vin. The changes in control signals VC1 to VC3, voltages G1 and G2, and current IP between times t10 and t16 are the same as those shown in FIG. 6 for the second embodiment, and therefore will not be described again. Because NFET M4 turns on at a predetermined timing, as described below, voltage Vm is zero at time t10. Between times t10 and t16, the control signal VC4 is at low level L, and the reset signal Vr is maintained at low level L.

[0068] After time t20, when the current Iin from the power generating element 10 increases to Iin2 and the voltage Vin gradually increases from voltage Vin0, the voltage at node N4 gradually increases. The voltage Vm at node N3 capacitively coupled to node N4 gradually increases from 0.

[0069] At time t21, the control circuit 18c detects the voltage Vin at the terminal Tsw1, and when the voltage Vin exceeds the voltage Vin0+Vref, the voltage Vm exceeds the reference voltage Vref, and the comparator 16 outputs a high level H as the reset signal Vr. When the reset signal Vr becomes a high level H, the control circuit 18c sets the control signal VC1 to a low level L and the control signal VC2 to a high level H, while maintaining the control signals VC3 and VC4 at a low level L. The voltage G1 at the node N1 capacitively coupled to the control terminal TC1 decreases. The voltage G2 at the node N2 capacitively coupled to the control terminal TC2 increases. Note that the timing at which the control signal VC1 is set to a low level L and the timing at which the control signal VC2 is set to a high level H may differ slightly within the range in which the above operation is possible.

[0070] Between times t21 and t22, current flows from node N1 to N2 via diode D, causing voltages G1 and G2 to rise slightly. At time t22, control circuit 18c sets control signal VC2 to low level L, maintaining control signals VC1, VC3, and VC4 at low level L. Voltage G2 at node N2, which is capacitively coupled to control terminal TC2, drops. Current flows from node N1 to N2 via diode D, causing voltage G1 to drop slightly. At time t23, control circuit 18c sets control signals VC1 and VC4 to high level H, maintaining control signals VC2 and VC3 at low level L. Just as voltage G1 became voltage Vin0 of voltage Vin at time t16, voltage G1 becomes Vin0+Vref, which is a voltage of voltage Vin. NFET M4 is turned on, causing voltage Vm at node N3 to drop to 0 V. The timing at which the control signal VC1 is set to high level H and the timing at which the control signal VC4 is set to high level H may be slightly different as long as the voltage Vm of the node N3 can be appropriately set to 0 V. At time t24, the control circuit 18c sets the control signal VC4 to low level L, maintains the control signal VC1 at high level H, and maintains the control signals VC2 and VC3 at low level L.

[0071] In the switch circuit of Example 2 described in FIG. 5 , when PFET M1 switches from the on state to the off state at time t16 when voltage Vin is at voltage Vin0, voltage G1 is at voltage Vin0, the voltage difference between the source and gate of PFET M1 is nearly zero, and PFET M1 is in the off state. After that, even if voltage Vin is not high after time t20, voltage G1 maintains voltage Vin0. Therefore, the gate voltage of PFET M1 becomes lower than the source voltage. This may cause PFET M1 to turn on. When PFET M1 turns on, current flows through PFET M1, reducing the conversion efficiency of voltage conversion circuit 12.

[0072] The comparator 16 compares the voltage Vm at the node N3 with the reference voltage Vref and outputs the comparison result to the control circuit 18c, thereby enabling the determination circuit 15 to determine whether the voltage Vin has changed from the voltage Vin0 to a higher voltage (farther from the reference potential 0V) by a constant voltage equivalent to the reference voltage Vref.

[0073] According to the third embodiment, when PFET M1 is in the off state, determination circuit 15 determines whether voltage Vin has changed by a certain voltage (Vref) from voltage Vin0 (the voltage when PFET M1 was last switched from the on state to the off state) to a higher voltage (farther from reference potential 0 V). When control circuit 18c determines that voltage Vin has changed by the certain voltage (Vref), it supplies a low level L (second level) to control terminal TC1 and a high level H (fourth level) to control terminal TC2, and then supplies a high level H (first level) to control terminal TC1 and a low level L (third level) to control terminal TC2. As a result, when voltage Vin increases from voltage Vin0 by at least reference voltage Vref, it can reset voltage G1 at the gate of PFET M1 to voltage Vin. Therefore, when voltage Vin increases from voltage Vin0 and FET M1 is normally controlled to be in the off state, a minute current is prevented from flowing between the source and drain of FET M1, and the charge in the primary capacitor is prevented from leaking out, thereby preventing a decrease in the conversion efficiency of voltage conversion circuit 12.

[0074] In the third embodiment, the control signal Sh has a constant period, and as mentioned above, it is desirable that its frequency be low. However, when the control signal SH and the reset signal Vr are generated almost simultaneously, the operation according to the control signal Sh takes priority.

[0075] Example 4 is an example in which the input voltage Vin from the power generating element 10 is lower than the ground potential. FIG. 9 is a detailed circuit diagram of a switch circuit constituting the power supply circuit of Example 4, showing details of the switch designated as HSW in FIG. 1 and its control circuit. As shown in FIG. 9, in switch circuit 28 of Example 4, NFETs M1a, M2a, M3a, and M4a are used instead of PFETs M1, M2, M3, and M4 shown in FIG. 7 of Example 3, respectively. The cathode of diode D is connected to node N1, and the anode is connected to node N2, with the forward direction being from node N2 to N1. The negative input terminal of comparator 16a is connected to node N3, and a reference voltage Vref is input to the positive input terminal. The control circuit is 18d. The other configuration is the same as in FIG. 7 of Example 3, and description thereof will be omitted. The high level H and low level L of control signals VC1 to VC4 are opposite to those in FIG. 8. The voltage X, the voltage Vin0 and the reference voltage Vref are negative.

[0076] As in Examples 1 to 3, when the input voltage Vin is higher than ground (reference potential), the first FET is a PFET M1, and the second and third FETs are NFETs M2 and M3, respectively. The first and fourth levels are high level H, and the second and third levels are low level L. On the other hand, when the input voltage Vin is lower than ground (reference potential), the first FET is an NFET M1a, and the second and third FETs are PFETs M2a and M3a, respectively. The first and fourth levels are low level L, and the second and third levels are high level H. In this way, the second and third FETs are NFETs and PFETs, and have channel conductivity types opposite to that of the first FET.

[0077] In Examples 1 to 4, the PFET is in an off state when the gate voltage (voltage of the gate relative to the source) is 0 V and is in an on state when the gate voltage is lower than a negative threshold voltage. The NFET is in an off state when the gate voltage is 0 V and is in an on state when the gate voltage is higher than a positive threshold voltage. The PFET and NFET are, for example, MOS (Metal Oxide Semiconductor) FETs using silicon. The diode D is, for example, a diode formed by diode-connecting an FET. Although an FET has been described as an example of a switch element, Examples 1 to 4 can be applied to the switch element as long as the switch element is a field-effect element in which the potential of its control terminal (gate) operates in a floating state. The switch element may be any field-effect switch element in which the potential applied to the control terminal switches the on state and off state of the conduction channel depending on the electric field formed in the conduction channel by the electric potential. For example, a bipolar transistor or an IGBT (Insulated Gate Bipolar Transistor) combined with an FET may be used.

[0078] The high and low levels of the control signals VC1 to VC4 may be any voltage, as long as the high level is higher than the low level for the same control signal, and the high level voltages of different control signals may be different from each other, and the low levels may be different from each other.

[0079] By using the switches of Examples 1 to 4 in the voltage conversion circuit 12 of Fig. 1, it is possible to stably control the switches of the voltage conversion circuit 12. Although Fig. 1 illustrates an example of a step-down / step-up voltage conversion circuit as the power supply circuit, the power supply circuit may also be a step-down voltage conversion circuit, a step-up voltage conversion circuit, or an inverting voltage conversion circuit. Furthermore, the power supply circuit may also be a power conversion circuit that converts AC to DC.

[0080] 10(a) is a block diagram showing an embodiment of a power supply circuit of the present invention, in which the switch circuit of any of the first to fourth embodiments and their modifications is used in a voltage conversion circuit 64. As shown in Fig. 10(a), the system includes a power generation element 60, rectifier circuits 61 and 62, a matching circuit 63, a voltage conversion circuit 64, a charge management circuit 65, a capacitor 66, a cold start circuit 67, and a boost circuit 68.

[0081] The power generating element 60 is, for example, the power generating element 10 in FIG. 1 and generates minute AC power. The rectifier circuit 61 is, for example, a diode bridge, and the rectifier circuit 62 is, for example, a synchronous rectifier circuit. The matching circuit 63 matches the output impedance of the rectifier circuits 61 and 62 with the input impedance of the voltage conversion circuit 64. The voltage conversion circuit 64 is, for example, the voltage conversion circuit 12 in FIG. 1 and is a DC-DC converter. The charge management circuit 65 stores electricity in an appropriate one of the multiple capacitors 66. The capacitors 66 are, for example, capacitors. The charge management circuit 65 monitors the voltages across the multiple capacitors and charges the appropriate one with the generated power. The cold start circuit 67 charges the capacitor 66 with the output current of the rectifier circuit 61 when the capacitor 66 is almost depleted. The boost circuit 68 is, for example, a charge pump and generates a voltage used for the rectifier circuit 62, the voltage conversion circuit 64, etc.

[0082] The operation of the system will now be described. When the power generating element 60 generates minute amounts of power while the capacitor 66 is barely charged, the rectifier circuit 61 rectifies the minute amounts of power. The rectifier circuit 61, like a diode bridge, can perform rectification without an external power source. The current rectified by the rectifier circuit 61 passes through the cold start circuit 67 to the charge management circuit 65 and is stored in the capacitor 66. When the capacitor 66 is charged to a sufficient voltage, the boost circuit 68 boosts the voltage of the capacitor 66 to a voltage used by the rectifier circuit 62 and the voltage conversion circuit 64. The voltage of the capacitor 66 is, for example, 1 V, and the output voltage of the boost circuit 68 is, for example, 2 V. If the rectifier circuit 62 and the voltage conversion circuit 64 operate using the voltage of the capacitor 66, the boost circuit 68 may be omitted.

[0083] The matching circuit 63 increases the input power when the power generation amount of the power generating element 60 is large and the generated current is large, and increases the input power when the power generation amount of the power generating element 60 is small and the generated current is small. This matches the output impedance of the power generating element 60 with the input impedance of the rectifier circuits 61 and 62. The matching circuit 63 switches between the rectifier circuits 61 and 62 depending on the input voltage. For example, if the rectifier circuits 61 and 62 are a diode bridge and a synchronous rectifier circuit, respectively, loss due to the on-voltage of the diodes increases when the input voltage is 1 V or less. For this reason, the rectifier circuit 62 is used. When the input voltage is 1 V or more, the rectifier circuit 61 is used.

[0084] The voltage conversion circuit 64 converts the input voltage set by the matching circuit 63 into a voltage to be charged to the capacitor 66. The voltage of the capacitor 66 is, for example, 1 V or 3.3 V. The charge management circuit 65 monitors the voltages of the multiple capacitors 66 and charges the appropriate capacitor 66 with the generated power.

[0085] In a system using a power generating element 60 that generates such minute power, the input voltage of the voltage conversion circuit 64 changes. This causes the switch HSW (see FIG. 1 ), which is the high-side switch of the voltage conversion circuit 64, to operate stably, which may reduce the conversion efficiency of the voltage conversion circuit 64. By using the switch circuits of Examples 1 to 4 as the switch HSW of the voltage conversion circuit, the switch HSW can be stably controlled, and a reduction in the conversion efficiency of the voltage conversion circuit 64 can be suppressed.

[0086] 10B is a block diagram showing a system of a sensor circuit in which the switch circuit of any one of Examples 1 to 4 and its modified examples is used. As shown in FIG. 10B, the switch element of the switch circuit 71 of Examples 1 to 4 turns on and off the power supply from the power supply 70 to the sensor circuit 72. As such, the switch element of the switch circuit of Examples 1 to 4 is not limited to an element that turns on and off the electromotive force supplied from the power generating element. The switch circuits of Examples 1 to 4 may be used in circuits other than power supply circuits, such as low-power IoT (Internet of Things) devices or edge devices.

[0087] Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as set forth in the claims.

[0088] 10 Power generating element 12 Voltage conversion circuit 14 Control unit 16 Comparator 18a to 18d Control circuit

Claims

1. A field effect switch element connected between a first terminal and a second terminal and switched between an on state and an off state depending on the potential of a control terminal; a control circuit which supplies a first level potential to the control terminal for turning the switch element into the on state when maintaining the on state of the switch element, and which connects the control terminal to the first terminal to set the potential of the control terminal to the potential of the first terminal when turning the switch element from the on state to the off state, and then floats the control terminal and supplies a second level potential for turning the switch element into the off state; A switch circuit comprising:

2. 2. The switch circuit according to claim 1, wherein, when the switch element is changed from the off state to the on state, the control circuit charges or discharges the control terminal via a resistor, and then makes the control terminal floating, and supplies the first level potential.

3. 2. The switch circuit according to claim 1, wherein the switch element is an element that turns on and off an electromotive force supplied from a power generating element.

4. 2. The switch circuit according to claim 1, wherein the switch element is an element that turns on and off the supply of power to a sensor circuit.

5. 2. The switch circuit according to claim 1, further comprising a maintaining circuit for maintaining the potential of said control terminal within a predetermined range.

6. 6. The switch circuit according to claim 5, wherein the sustaining circuit includes a diode connected to the control terminal.

7. 2. The switch circuit according to claim 1, wherein the switch element is a first FET having a source connected to a first terminal, a drain connected to a second terminal, and a gate connected to a first node capacitively coupled to a first control terminal.

8. A first FET having a source connected to a first terminal, a drain connected to a second terminal, and a gate connected to a first node capacitively coupled to a first control terminal, the first FET being switched between an on state and an off state depending on the potential of the gate; a second FET having a source connected to the first node, a drain connected to the first terminal, and a gate; a control circuit which, when maintaining the off state of the first FET, supplies a first level potential to the first node for turning the first FET into an off state, and, when turning the first FET from an off state to an on state, turns off a node between the source and drain of the second FET, connects the first node to a reference potential via a resistor to charge or discharge the first node, and then disconnects the first node from the first terminal and the reference potential to make the first node floating, and supplies, to the first control terminal, a second level potential for turning the first FET into an on state; A switch circuit comprising:

9. a third FET having a source connected to the reference potential, a drain connected to the first node, and a gate; 9. The switch circuit according to claim 8, wherein the resistor is a resistor between the source and drain of the third FET, and a saturation current flows through the third FET when the first node is connected to the reference potential via the second FET.

10. a rectifying element having a forward direction of a second node capacitively coupled from the first node to a second control terminal; the second FET is an N-type, the gate of the second FET is connected to the second node; the first FET is a P-type; The switch circuit according to claim 8 , wherein the first node is connected to the reference potential via the rectifying element, the second node, and the resistor.

11. a rectifying element having a forward direction from a second node capacitively coupled to a second control terminal to the first node; the second FET is P-type and is connected to a second node capacitively coupled to the second control terminal; the first FET is an N-type; The switch circuit according to claim 8 , wherein the first node is connected to the reference potential via the rectifying element, the second node, and the resistor.

12. 11. The switch circuit according to claim 10, wherein the control circuit, when the first FET maintains an on state, supplies the first control terminal with the second level potential and supplies the second control terminal with a third level potential for turning the second FET into an off state, and, when turning the first FET from an on state to an off state, supplies the second control terminal with a fourth level potential for turning the second FET into an on state, and thereafter supplies the first level potential to the first control terminal and supplies the third level potential to the second control terminal.

13. 13. The switch circuit according to claim 12, wherein when the first FET is changed from an on state to an off state, the control circuit supplies the third level potential to the second control terminal and then supplies the first level potential to the first control terminal.

14. a determination circuit that determines, when the first FET is maintained in an off state, whether the input voltage has changed by a certain voltage from the input voltage when the first FET was previously switched from an on state to an off state; 13. The switch circuit according to claim 12, wherein the control circuit, when determining that the input voltage has changed by a certain voltage, supplies the first control terminal with the second level and the second control terminal with the fourth level, and thereafter supplies the first control terminal with the first level and the second control terminal with the third level.

15. The determination circuit includes:

15. The switch circuit according to claim 14, further comprising a comparator that compares a voltage at a third node capacitively coupled to the first terminal with a fixed voltage and outputs a comparison result to the control circuit.

16. 9. The switch circuit according to claim 8, wherein an input voltage input to the first terminal is higher than the reference potential, and the first FET is a PFET.

17. 9. The switch circuit according to claim 8, wherein an input voltage input to the first terminal is lower than the reference potential, and the first FET is an NFET.

18. The switch circuit according to claim 3 , wherein the power generating element is a vibration power generating element.

19. A power supply circuit comprising the switch circuit according to claim 1.

20. A first FET having a source connected to a first terminal, a drain connected to a second terminal, and a gate connected to a first node capacitively coupled to a first control terminal, the first FET being switched between an on state and an off state depending on the potential of the gate; a second FET having a source connected to the first node, a drain connected to the first terminal, and a gate connected to a second node capacitively coupled to a second control terminal; a control circuit for controlling the first FET and the second FET, The control circuit includes: supplying a first level potential from the first control terminal to the first node to turn on the first FET when maintaining the first FET in an on state; when changing the first FET from an on state to an off state, a potential that turns on the source and drain of the second FET is supplied from the second control terminal to the second node, thereby connecting the first node and the second node to the first terminal via a resistor and charging or discharging, and then a potential that turns off the source and drain of the second FET is supplied from the second control terminal to the second node, thereby disconnecting the first node and the second node from the first terminal and floating them, and after floating them, a second level potential that turns the first FET into an off state is supplied to the first control terminal. Switch circuit.