Semiconductor device and manufacturing method for semiconductor device

Abstract

This semiconductor device comprises a first lead, a second lead, a third lead, a semiconductor element, a sealing resin, and a cover layer. The sealing resin has a bottom surface and an outer surface. A recess having an inner surface is formed on the bottom surface of the sealing resin. The second lead has a rear surface exposed from the bottom surface, and a side surface exposed from the outer surface. The cover layer contains a metal element and covers the rear surface and the side surface. The recess is located between the first lead and the second lead. The second lead and at least one of the first lead and the third lead have an inner end surface exposed from the inner surface of the recess.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0002] Patent Document 1 discloses an example of a semiconductor device. The semiconductor device includes a columnar conductor that is electrically connected to a semiconductor element. The columnar conductor has a back surface and a side surface that are exposed from the sealing resin. The semiconductor device further includes external electrodes that cover the back surface and the side surface. With this configuration, when the semiconductor device is mounted on a wiring board, solder creeps up to the portion of the external electrode that covers the side surface. This makes it easy to visually check the bonding state of the semiconductor device to the wiring board.

[0003] Forming the external electrodes of the semiconductor device disclosed in Patent Document 1 requires a process for exposing the side surfaces of the columnar conductors from the encapsulation resin. This reduces the manufacturing efficiency of the semiconductor device. Furthermore, because the external electrodes are formed by electroless plating, it takes a relatively long time to deposit the metal layer that will become the external electrodes. This further reduces the manufacturing efficiency of the semiconductor device.

[0004] Japanese Patent Application Laid-Open No. 2020-27850

[0005] In view of the above circumstances, one objective of the present disclosure is to provide a semiconductor device and a manufacturing method thereof that enable a coating layer to be more efficiently formed to cover the back and side surfaces of leads exposed from the sealing resin.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes a first lead, a second lead adjacent to the first lead in a direction perpendicular to the thickness direction of the first lead, a third lead adjacent to the second lead in a direction perpendicular to the thickness direction, a first semiconductor element mounted on the first lead and electrically connected to the second lead, a sealing resin covering the first semiconductor element, a portion of each of the first lead, the second lead, and the third lead, and a coating layer containing a metal element. The sealing resin has a bottom surface facing the thickness direction and an outer side surface connected to the bottom surface and facing outward from the sealing resin in a direction perpendicular to the thickness direction. A recess is formed in the sealing resin, recessed from the bottom surface, and the recess has an inner side surface connected to the bottom surface and facing inward from the sealing resin in a direction perpendicular to the thickness direction. The second lead has a back surface exposed from the bottom surface and a side surface connected to the back surface and exposed from the outer side surface. The coating layer covers the back surface and the side surface. The recess is located between the first lead and the second lead. The second lead and at least one of the first lead and the third lead have inner end faces exposed from the inner side surface.

[0007] A second aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: mounting a semiconductor element on one of a plurality of leads, each of which has a back surface and a side surface connected to the back surface; and forming an encapsulating resin that covers a portion of each of the plurality of leads and the semiconductor element. In the encapsulating resin forming step, the back surface and the side surface of at least one of the plurality of leads are exposed from the encapsulating resin. At least two of the plurality of leads are connected to each other by a connecting strip containing the same composition as the plurality of leads. The manufacturing method also comprises, after the encapsulating resin forming step, forming a coating layer by electrolytic plating that covers the back surface and the side surface exposed from the encapsulating resin and contains a metal element; and, after the coating layer forming step, cutting the connecting strip by removing a portion of the encapsulating resin from the side where the back surface is exposed.

[0008] According to the above-described configuration of the present disclosure, it is possible to more efficiently form a coating layer that covers the rear and side surfaces of the leads exposed from the sealing resin.

[0009] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0010] FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1 , seen through a sealing resin. FIG. 3 is a bottom view of the semiconductor device shown in FIG. 1 . FIG. 4 is a right side view of the semiconductor device shown in FIG. 1 . FIG. 5 is a left side view of the semiconductor device shown in FIG. 1 . FIG. 6 is a rear view of the semiconductor device shown in FIG. 1 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 2 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2 . FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 2 . FIG. 10 is a partial enlarged view of FIG. 7 . FIG. 11 is a partial enlarged view of FIG. 9 . FIG. 12 is a plan view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 13 is a plan view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 14 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 15 is a plan view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 16 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 17 is a bottom view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 18 is a partially enlarged cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 19 is a partially enlarged cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 20 is a plan view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 21 is a partially enlarged cross-sectional view of a first modified example of the semiconductor device shown in FIG. 1 . FIG. 22 is a partially enlarged cross-sectional view of a second modified example of the semiconductor device shown in FIG. 1 . FIG. 23 is a partially enlarged cross-sectional view of a third modified example of the semiconductor device shown in FIG. 1 . FIG. 24 is a partially enlarged cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 23 . FIG. 25 is a plan view of a semiconductor device according to a second embodiment of the present disclosure, seen through a sealing resin. FIG. 26 is a bottom view of the semiconductor device shown in FIG. 25 . FIG. 27 is a right side view of the semiconductor device shown in FIG. 25 . FIG. 28 is a rear view of the semiconductor device shown in FIG. 25 . FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG. 25 . FIG. 30 is a partially enlarged view of FIG. 29 . Fig. 31 is a plan view illustrating a manufacturing process of the semiconductor device shown in Fig. 25. Fig. 32 is a plan view illustrating a manufacturing process of the semiconductor device shown in Fig. 25. Fig. 33 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in Fig. 25. Fig. 34 is a bottom view illustrating a manufacturing process of the semiconductor device shown in Fig. 25.35 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 25 . FIG. 36 is a bottom view illustrating a manufacturing process of the semiconductor device shown in FIG. 25 . FIG. 37 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 25 . FIG. 38 is a plan view of a semiconductor device according to a third embodiment of the present disclosure, seen through a sealing resin. FIG. 39 is a bottom view of the semiconductor device shown in FIG. 38 . FIG. 40 is a cross-sectional view taken along line XL-XL in FIG. 38 . FIG. 41 is a cross-sectional view taken along line XLI-XLI in FIG. 38 . FIG. 42 is a cross-sectional view taken along line XLII-XLII in FIG. 38 . FIG. 43 is a partial enlarged view of FIG. 40 . FIG. 44 is a plan view of a semiconductor device according to a fourth embodiment of the present disclosure, seen through a sealing resin. FIG. 45 is a bottom view of the semiconductor device shown in FIG. 44 . FIG. 46 is a bottom view of a semiconductor device according to a fifth embodiment of the present disclosure. FIG. 47 is a cross-sectional view of the semiconductor device shown in FIG. 46 . FIG. 48 is a cross-sectional view of the semiconductor device shown in FIG. 46 . FIG. 49 is a partially enlarged view of FIG.

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0012] A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to Figures 1 to 11. The semiconductor device A10 is surface-mounted on a wiring substrate. The semiconductor device A10 includes a plurality of leads 10, a plurality of semiconductor elements 20, a plurality of conductive members 30, a sealing resin 40, and a coating layer 50. For ease of understanding, Figure 2 shows the sealing resin 40 through a transparent line (two-dot chain line).

[0013] In describing the semiconductor device A10, for convenience, the thickness direction of the multiple leads 10 (and therefore any one lead 10) will be referred to as the "thickness direction z." A direction perpendicular to the thickness direction z will be referred to as the "first direction x." A direction perpendicular to the thickness direction z and the first direction x will be referred to as the "second direction y." The semiconductor device A10 is rectangular when viewed in the thickness direction z.

[0014] As shown in FIG. 2 , the multiple leads 10 carry multiple semiconductor elements 20 and form part of the conductive path between the wiring board on which the semiconductor device A10 is mounted and the multiple semiconductor elements 20. All of the multiple leads 10 are made of a common lead frame. Therefore, the multiple leads 10 all have the same composition. The composition of the multiple leads 10 includes copper (Cu) (i.e., each lead 10 contains copper). The multiple leads 10 include a first lead 101, a second lead 102, a third lead 103, and a fourth lead 104.

[0015] 2, the second lead 102 is located adjacent to the first lead 101 in the first direction x. The third lead 103 is located adjacent to the second lead 102 in the second direction y. The fourth lead 104 is located adjacent to the third lead 103 in the first direction x and adjacent to the first lead 101 in the second direction y.

[0016] As shown in Figures 2, 3, 7 and 9, the second lead 102 and the third lead 103 have a main surface 112, two back surfaces 122, two side surfaces 13, a first outer end surface 141, an inner end surface 15, an inner peripheral surface 16, a canopy portion 17, an outer convex portion 18 and an inner convex portion 19.

[0017] As shown in Figures 7 and 9, the main surface 112 faces the thickness direction z. The main surface 112 is covered with the sealing resin 40. The two back surfaces 122 face the opposite side to the main surface 112 in the thickness direction z. The two main surfaces 112 are positioned apart from each other in the second direction y. The two back surfaces 122 are exposed from the sealing resin 40. As shown in Figures 3 and 7, the two side surfaces 13 are individually connected to the two back surfaces 122 and face the first direction x. The two side surfaces 13 are exposed from the sealing resin 40.

[0018] 2 , 3 , 6 , and 9 , the first outer end surface 141 faces outward from the sealing resin 40 in the second direction y. The first outer end surface 141 is exposed from the sealing resin 40. The area of ​​the first outer end surface 141 is smaller than the area of ​​each of the two side surfaces 13. The first outer end surface 141 is connected to the main surface 112 and is located away from the two back surfaces 122.

[0019] 2 , 3 , and 11 , the inner end surface 15 faces inward of the sealing resin 40 in the second direction y. The inner end surface 15 is exposed from the sealing resin 40. The area of ​​the inner end surface 15 is smaller than the area of ​​each of the two side surfaces 13. The inner end surface 15 is connected to the main surface 112 and is located away from the two back surfaces 122 and the two side surfaces 13.

[0020] 2, 3, 7, and 9, the inner circumferential surface 16 is connected to the two rear surfaces 122 and faces in a direction perpendicular to the thickness direction z. The inner circumferential surface 16 is covered with a sealing resin 40.

[0021] As shown in Figures 2, 3, 7, and 9, the eaves portion 17 protrudes from the inner circumferential surface 16 in a direction perpendicular to the thickness direction z. The eaves portion 17 includes a main surface 112. The eaves portion 17 has a protruding surface 171 that faces the opposite side to the main surface 112 in the thickness direction z. The protruding surface 171 is connected to the inner circumferential surface 16 and is located between the main surface 112 and the two back surfaces 122 in the thickness direction z. The eaves portion 17 is covered with a sealing resin 40.

[0022] 2 , 3 , and 9 , the outward protrusion 18 protrudes outward from the eaves portion 17 in the second direction y from the sealing resin 40. The outward protrusion 18 includes a main surface 112 and a first outer end surface 141. The lower surface of the outward protrusion 18, which faces the same side as the two back surfaces 122 in the thickness direction z, is flush with the protruding surface 171 of the eaves portion 17.

[0023] 2 , 3 , and 11 , the inward protrusion 19 protrudes inward from the eave portion 17 in the second direction y into the sealing resin 40. The inward protrusion 19 includes a main surface 112 and an inner end surface 15. The lower surface of the inward protrusion 19, which faces the same side as the two back surfaces 122 in the thickness direction z, is flush with the protruding surface 171 of the eave portion 17.

[0024] 2, 3, 7, and 8, the first lead 101 and the fourth lead 104 have a mounting surface 111, a mounting surface 121, a first outer end surface 141, two second outer end surfaces 142, an inner end surface 15, an inner peripheral surface 16, a canopy portion 17, an outer convex portion 18, and an inner convex portion 19. Of these, the configurations of the inner end surface 15, the inner peripheral surface 16, the canopy portion 17, the outer convex portion 18, and the inner convex portion 19 are similar to the configurations of the inner end surface 15, the inner peripheral surface 16, the canopy portion 17, the outer convex portion 18, and the inner convex portion 19 of the second lead 102 and the third lead 103, and therefore will not be described here.

[0025] As shown in FIG. 7 , the mounting surface 111 faces the same side as the main surfaces 112 of the second lead 102 and the third lead 103 in the thickness direction z. The mounting surface 111 is covered with the sealing resin 40. Any one of the plurality of semiconductor elements 20 is mounted on the mounting surface 111. The mounting surface 121 faces the opposite side to the mounting surface 111 in the thickness direction z. The mounting surface 121 is exposed from the sealing resin 40. As shown in FIG. 3 , the area of ​​the mounting surface 121 is smaller than the area of ​​each of the two back surfaces 122 of the second lead 102 and the third lead 103.

[0026] 2 , 3 , 6 , and 8 , the first outer end surfaces 141 of the first lead 101 and the fourth lead 104 face outward from the sealing resin 40 in the second direction y. Therefore, the direction in which the first outer end surfaces 141 face is different from the direction in which the two side surfaces 13 of the second lead 102 and the third lead 103 face. The first outer end surfaces 141 are exposed from the sealing resin 40. The area of ​​the first outer end surfaces 141 is smaller than the area of ​​each of the two side surfaces 13. The first outer end surfaces 141 are connected to the mounting surface 111 and are located away from the mounting surface 121.

[0027] 3 and 7 , the two second outer end surfaces 142 are connected to the mounting surface 121 and face the first direction x. The two second outer end surfaces 142 face the same direction as the two side surfaces 13 of the second lead 102 and the third lead 103, and face the opposite direction from the two side surfaces 13. The two second outer end surfaces 142 are located apart from each other in the second direction y. The two second outer end surfaces 142 are exposed from the sealing resin 40. The area of ​​each of the two second outer end surfaces 142 is larger than the area of ​​the first outer end surfaces 141 of the first lead 101 and the fourth lead 104.

[0028] 2 and 8, the plurality of semiconductor elements 20 are individually mounted on the mounting surface 111 of the first lead 101 and the mounting surface 111 of the fourth lead 104. In the semiconductor device A10, the plurality of semiconductor elements 20 are diodes.

[0029] 10, the plurality of semiconductor elements 20 have a first electrode 21 and a second electrode 22. The first electrode 21 is provided on the side of the first lead 101 facing the mounting surface 111. The first electrode 21 corresponds to an anode electrode.

[0030] 42 , the second electrode 22 is provided on the opposite side of the first electrode 21 in the thickness direction z. The second electrode 22 faces either the mounting surface 111 of the first lead 101 or the mounting surface 111 of the fourth lead 104. The second electrode 22 corresponds to a cathode electrode.

[0031] As shown in FIGS. 2 and 8 , the multiple semiconductor elements 20 include a first semiconductor element 201 and a second semiconductor element 202. The first semiconductor element 201 is mounted on the mounting surface 111 of the first lead 101. As shown in FIG. 10 , the second electrode 22 of the first semiconductor element 201 is bonded to the mounting surface 111 of the first lead 101 via a bonding layer 29. The bonding layer 29 is conductive. The bonding layer 29 is, for example, solder. Alternatively, the bonding layer 29 may be a sintered metal containing silver (Ag). As a result, the second electrode 22 of the first semiconductor element 201 is electrically connected to the first lead 101. The second electrode 22 of the second semiconductor element 202 is bonded to the mounting surface 111 of the fourth lead 104 via the bonding layer 29. As a result, the second electrode 22 of the second semiconductor element 202 is electrically connected to the fourth lead 104.

[0032] As shown in FIG. 2 , the plurality of conductive members 30 include two first members 31. One of the two first members 31 is bonded to the first electrode 21 of the first semiconductor element 201 and the main surface 112 of the second lead 102 via bonding layers 29, respectively. As a result, the first electrode 21 of the first semiconductor element 201 is electrically connected to the second lead 102. The other of the two first members 31 is bonded to the first electrode 21 of the second semiconductor element 202 and the main surface 112 of the third lead 103 via bonding layers 29, respectively. As a result, the first electrode 21 of the second semiconductor element 202 is electrically connected to the third lead 103. The two first members 31 are metal clips. The two first members 31 contain copper. Alternatively, the two first members 31 may be wires.

[0033] As shown in FIGS. 7 to 9 , the sealing resin 40 covers a portion of each of the leads 10, the semiconductor elements 20, and the conductive members 30. The sealing resin 40 has electrical insulation properties. The sealing resin 40 is made of a material containing, for example, black epoxy resin. As shown in FIGS. 4 and 5 , the sealing resin 40 has a top surface 41, a bottom surface 42, an outer side surface 43, and a recess 44.

[0034] 7 to 9 , the top surface 41 and the bottom surface 42 face opposite each other in the thickness direction z. Of these, the bottom surface 42 faces the same side in the thickness direction z as the two back surfaces 122 of the second lead 102 and the third lead 103. The two back surfaces 122 and the mounting surfaces 121 of the first lead 101 and the fourth lead 104 are exposed from the bottom surface 42.

[0035] 3 to 5 , the outer surface 43 is connected to the top surface 41 and the bottom surface 42, and faces outward from the sealing resin 40 in a direction perpendicular to the thickness direction z. The outer surface 43 includes a pair of first surfaces 431 and a pair of second surfaces 432.

[0036] As shown in Fig. 3 , the pair of first surfaces 431 face opposite each other in the first direction x. As shown in Fig. 4 and Fig. 7 , two side surfaces 13 of the second lead 102 and the third lead 103 are exposed from one of the pair of first surfaces 431. As shown in Fig. 5 and Fig. 7 , two second outer end surfaces 142 of the first lead 101 and the fourth lead 104 are exposed from the other of the pair of first surfaces 431.

[0037] As shown in Fig. 3 , the pair of second surfaces 432 face opposite each other in the second direction y. As shown in Figs. 1 , 8 and 9 , the first outer end surface 141 of the first lead 101 and the first outer end surface 141 of the second lead 102 are exposed from one of the pair of second surfaces 432. As shown in Figs. 6 , 8 and 9 , the first outer end surface 141 of the fourth lead 104 and the first outer end surface 141 of the third lead 103 are exposed from the other of the pair of second surfaces 432.

[0038] 3 to 5, the recess 44 is recessed from the bottom surface 42 in the thickness direction z. The recess 44 is a groove extending in a direction perpendicular to the thickness direction z. In the semiconductor device A10, the recess 44 extends in the first direction x. Both sides of the recess 44 in the first direction x are connected to a pair of first surfaces 431 of the outer side surface 43. As a result, the bottom surface 42 is divided into two regions by the recess 44.

[0039] As shown in FIG. 3 , the fourth lead 104 is located adjacent to the first lead 101 with the recess 44 interposed therebetween. The third lead 103 is located adjacent to the second lead 102 with the recess 44 interposed therebetween. As shown in FIG. 11 , the recess 44 has an inner side surface 441. The inner side surface 441 is connected to the bottom surface 42 and faces inward of the sealing resin 40 in a direction perpendicular to the thickness direction z. The inner side surface 441 further includes a pair of regions spaced apart from each other in a direction perpendicular to the thickness direction z and the direction in which the recess 44 extends (the second direction y in the semiconductor device A10). The inner end surfaces 15 of the first lead 101 and the fourth lead 104 and the inner end surfaces 15 of the second lead 102 and the third lead 103 are exposed from the pair of regions.

[0040] 11 , the recess 44 has an intermediate surface 442. The intermediate surface 442 faces the same side as the bottom surface 42 in the thickness direction z and is connected to an inner side surface 441. In the semiconductor device A10, the intermediate surface 442 is located farther from the bottom surface 42 in the thickness direction z than the main surfaces 112 of the second lead 102 and the third lead 103 are.

[0041] As shown in FIGS. 2 , 3 , and 7 , the coating layer 50 covers the two back surfaces 122 and two side surfaces 13 of the second lead 102 and the third lead 103. Furthermore, the coating layer 50 covers the mounting surfaces 121 and the two second outer end surfaces 142 of the first lead 101 and the fourth lead 104. The first outer end surfaces 141 and the inner end surfaces 15 of the leads 10 are not covered by the coating layer 50. The composition of the coating layer 50 includes a metal element. The metal element is, for example, tin (Sn). Alternatively, the metal element may include at least one of nickel (Ni), palladium (Pd), and gold (Au). The metal element included in the coating layer 50 is preferably an element that improves the wettability of the solder used when mounting the semiconductor device A10 on a wiring board.

[0042] Next, an example of a manufacturing method of the semiconductor device A10 will be described with reference to Figures 12 to 20. Here, the cross-sectional positions of Figures 14 and 16 are the same as the cross-sectional position of Figure 7. The cross-sectional positions of Figures 18 and 19 are the same as the cross-sectional position of Figure 11.

[0043] 12 , a plurality of semiconductor elements 20 are individually mounted on the mounting surfaces 111 of the first lead 101 and the fourth lead 104 of the plurality of leads 10. The mounting surfaces 111 are located on the opposite side in the thickness direction z from the back surfaces 122 of the second lead 102 and the third lead 103 of the plurality of leads 10. Thereafter, a plurality of conductive members 30 are individually bonded to the first electrodes 21 of the plurality of semiconductor elements 20 and the main surfaces 112 of the second lead 102 and the third lead 103.

[0044] 12 , the multiple leads 10 are connected to a frame body 80 via tie bars 81. Furthermore, at least any two of the multiple leads 10 are connected to each other by a connecting band 82. In the semiconductor device A10, the first lead 101 and the fourth lead 104, and the second lead 102 and the third lead 103 are connected to each other by the connecting band 82. The frame body 80, the tie bars 81, and the connecting band 82 are made of the same composition as the multiple leads 10. Therefore, the frame body 80, the tie bars 81, and the connecting band 82 are all conductive.

[0045] 13 and 14 , a sealing resin 40 is formed to cover a portion of each of the leads 10, the semiconductor elements 20, and the conductive members 30. The sealing resin 40 is formed by transfer molding. In this process, the back surface 122 and the side surface 13 of at least one of the leads 10 (the second lead 102 and the third lead 103) are exposed from the sealing resin 40. Furthermore, in this process, the mounting surface 121 and the two second outer end surfaces 142 of each of the first lead 101 and the fourth lead 104 are also exposed from the sealing resin 40.

[0046] 15 and 16 , a coating layer 50 containing a metal element is formed by electrolytic plating to cover the rear surface 122 and the side surface 13 exposed from the sealing resin 40. The coating layer 50 is, for example, a tin plating layer. In this process, the mounting surfaces 121 of the first lead 101 and the fourth lead 104 and the two second outer end surfaces 142 are also covered with the coating layer 50.

[0047] Next, as shown in FIG. 17 , the connecting strips 82 are cut by removing a portion of the sealing resin 40 from the side where the back surface 122 is exposed in the thickness direction z. A cutting device such as a dicing blade or a laser is used to cut the connecting strips 82. FIG. 18 shows the state of the two leads 10 before the connecting strips 82 are cut. FIG. 19 shows the state of the two leads 10 after the connecting strips 82 are cut. As shown in FIG. 19 , this step forms a recess 44 in the sealing resin 40, and inner end faces 15 appear from the two leads 10 that were connected by the connecting strip 82.

[0048] 20 , the tie bars 81 are cut to separate the leads 10 from the frame body 80. This step causes first outer end surfaces 141 to appear from the leads 10 that were connected by the tie bars 81. By going through the above steps, the semiconductor device A10 is obtained.

[0049] Next, a semiconductor device A11, which is a first modification of the semiconductor device A10, will be described with reference to Fig. 21. The cross-sectional position of Fig. 21 is the same as that of Fig. 11.

[0050] 21 , the semiconductor device A11 differs from the semiconductor device A10 in the configuration of the inward end faces 15 and inward protrusions 19 of the second lead 102 and the third lead 103. The lower surfaces of the inward protrusions 19, which face the same side as the back surface 122 in the thickness direction z, are spaced apart from the protruding surface 171 of the eave portion 17 toward the main surface 112 in the thickness direction z. The upper surfaces of the inward protrusions 19, which face the same side as the main surface 112 in the thickness direction z, correspond to the main surface 112. The inward end faces 15 are connected to the main surface 112. As a result, the area of ​​the inward end faces 15 is smaller than the area of ​​the inward end faces 15 of the second lead 102 and the third lead 103 in the semiconductor device A10. The configurations of the inward end faces 15 and inward protrusions 19 of the first lead 101 and the fourth lead 104 are also similar to this configuration.

[0051] Next, a semiconductor device A12, which is a second modification of the semiconductor device A10, will be described with reference to Fig. 22. The cross-sectional position of Fig. 22 is the same as that of Fig. 11.

[0052] 22 , the semiconductor device A12 differs from the semiconductor device A10 in the configurations of the inner end faces 15 and inner protrusions 19 of the second lead 102 and the third lead 103 and the configuration of the recesses 44 of the sealing resin 40. The upper surfaces of the inner end faces 15, which face the same side as the main surface 112 in the thickness direction z, are spaced apart from the main surface 112 toward the side where the back surface 122 is located in the thickness direction z. The lower surfaces of the inner protrusions 19, which face the same side as the back surface 122 in the thickness direction z, correspond to the protruding surfaces 171 of the eave portions 17. The inner end faces 15 are connected to the protruding surfaces 171. As a result, the area of ​​the inner end faces 15 is smaller than the area of ​​the inner end faces 15 of the second lead 102 and the third lead 103 in the semiconductor device A10. The configurations of the inner end faces 15 and inner protrusions 19 of the first lead 101 and the fourth lead 104 are also similar to this configuration.

[0053] 22 , in the thickness direction z, the intermediate surface 442 of the recess 44 is located between the main surface 112 and the back surface 122. Therefore, the depth of the recess 44 is smaller than the depth of the recess 44 of the semiconductor device A10.

[0054] Next, a semiconductor device A13, which is a third modification of the semiconductor device A10, will be described with reference to Figures 23 and 24. The cross-sectional positions of Figures 23 and 24 are the same as the cross-sectional position of Figure 11.

[0055] 23 , in the semiconductor device A13, the configurations of the inward end faces 15 and the inward protrusions 19 of the second lead 102 and the third lead 103 are different from those of the semiconductor device A10. The lower surfaces of the inward protrusions 19, which face the same side as the back surface 122 in the thickness direction z, are flush with the back surface 122. The lower surfaces of the inward protrusions 19 are covered with a coating layer 50. The upper surfaces of the inward protrusions 19, which face the same side as the main surface 112 in the thickness direction z, correspond to the main surface 112. The inward end faces 15 are connected to the main surface 112.

[0056] 24 shows the state before cutting the connecting strip 82 in the step of cutting the connecting strip 82 shown in FIG. 17 during the manufacturing process of the semiconductor device A13. The connecting strip 82 connects the overhanging portion 17 of the second lead 102 and the overhanging portion 17 of the third lead 103. When cutting the connecting strip 82, both ends of the connecting strip 82 connected to the overhanging portion 17 are left, thereby obtaining the semiconductor device A13. Therefore, the dimension of the long side of the inner end surface 15 (dimension in the thickness direction z) is equal to the dimension of each of the long sides of the two side surfaces 13 of the second lead 102 and the two side surfaces 13 of the third lead 103. Therefore, the area of ​​the inner end surface 15 is larger than the area of ​​each of the inner end surfaces 15 of the second lead 102 and the third lead 103 in the semiconductor device A10. However, the dimension of the short side of the inner end surface 15 is smaller than the dimension of each of the short sides of the two side surfaces 13. Therefore, in the semiconductor device A13, the area of ​​the inner end face 15 is smaller than the area of ​​each of the two side faces 13. The configurations of the inner end faces 15 and the inner protrusions 19 of the first lead 101 and the fourth lead 104 are also similar to this configuration.

[0057] Next, the effects of the semiconductor device A10 will be described.

[0058] The semiconductor device A10 includes a second lead 102 having a back surface 122 and a side surface 13 exposed from the sealing resin 40, and a covering layer 50 covering the back surface 122 and the side surface 13. The sealing resin 40 has an inner side surface 441 and a recess 44 recessed from the bottom surface 42. The second lead 102 and at least one of the first lead 101 and the third lead 103, which are positioned between the second lead 102 and the recess 44, have an inner end surface 15 exposed from the inner side surface 441.

[0059] In the manufacturing process of the semiconductor device A10, in the step of forming the sealing resin 40 shown in FIGS. 13 and 14, the sealing resin 40 is formed so that the back surface 122 and side surface 13 of the second lead 102 are exposed from the sealing resin 40. Then, in the step of forming the covering layer 50 shown in FIGS. 15 and 16, the covering layer 50 can be formed by electrolytic plating. At this stage, at least two leads 10, including the second lead 102, are connected by a connecting strip 82 that contains the same composition as the leads 10, i.e., is conductive. This configuration allows even leads 10 that are not connected to the frame body 80 by tie bars 81 to be electrically connected to the frame body 80. Then, by performing the step of cutting the connecting strip 82 shown in FIG. 17, electrical insulation is achieved between the two leads 10 connected by the connecting strip 82. The inner end surface 15 and the recess 44 of the semiconductor device A10 are traces resulting from this step. Thereafter, a step of cutting the tie bars 81 shown in FIG. 20 is carried out, so that all of the leads 10 are electrically insulated from one another.

[0060] Therefore, in the semiconductor device A10, the coating layer 50 covering the back surface 122 and side surface 13 of the second lead 102 can be easily formed by electrolytic plating. Therefore, in the semiconductor device A10, a step of exposing the side surface 13 from the sealing resin 40 after forming the sealing resin 40 is not necessary. Furthermore, the efficiency of forming the coating layer 50 can be improved compared to when the coating layer 50 is formed by electroless plating. As described above, according to the semiconductor device A10 and its manufacturing method, the coating layer 50 covering the back surface 122 and side surface 13 of the lead 10 (second lead 102) exposed from the sealing resin 40 can be more efficiently formed.

[0061] The recess 44 in the sealing resin 40 is a groove extending in a direction perpendicular to the thickness direction z. The inner surface 441 of the recess 44 includes a pair of regions spaced apart in a direction perpendicular to the thickness direction z and the direction in which the recess 44 extends. The recess 44 of this configuration is obtained by using a cutting device such as a dicing blade in the step of cutting the connecting strip 82 shown in FIG. 17 during the manufacturing process of the semiconductor device A10. Using such a cutting device allows the connecting strip 82 to be cut efficiently. Furthermore, when the bottom surface 42 of the sealing resin 40 is divided into multiple regions by the recess 44, the connecting strip 82 can be smoothly cut without slowing down the cutting speed, thereby suppressing a decrease in the manufacturing efficiency of the semiconductor device A10.

[0062] The inner end surface 15 of the second lead 102 is located away from the side surface 13. This prevents defects caused by cutting the connecting strip 82 from occurring in the portion of the coating layer 50 covering the side surface 13 during the step of cutting the connecting strip 82 shown in FIG.

[0063] The area of ​​the inner end face 15 of the second lead 102 is smaller than the area of ​​the side face 13. This makes it possible to suppress metal burrs from occurring on the edge of the inner end face 15 during the process of cutting the connecting band 82 shown in FIG. 17 during the manufacturing process of the semiconductor device A10. Furthermore, the inner end face 15 is located away from the back surface 122. This makes it possible to prevent a decrease in the bonding strength of the semiconductor device A10 to the wiring board due to the metal burrs when the semiconductor device A10 is mounted on the wiring board.

[0064] The inner end surface 15 of the second lead 102 is connected to the main surface 112. In this configuration, it is desirable that the intermediate surface 442 of the recess 44 in the sealing resin 40 is located farther from the bottom surface 42 of the recess 44 than the main surface 112. This allows the connecting strips 82 to be reliably cut in the step of cutting the connecting strips 82 shown in FIG.

[0065] The first lead 101 has a first outer end surface 141 that faces in a direction different from the direction in which the side surface 13 of the second lead 102 faces and is exposed from the outer surface 43 of the sealing resin 40. The outer surface 43 is a trace left by the step of cutting the tie bar 81 shown in Figure 20 during the manufacturing process of the semiconductor device A10. This makes it possible to prevent defects caused by cutting the tie bar 81 from occurring in the portion of the covering layer 50 covering the side surface 13 in this step.

[0066] The first outer end surface 141 of the first lead 101 is located away from the mounting surface 121. Here, in the manufacturing process of the semiconductor device A10, in the step of cutting the tie bars 81 shown in Fig. 20, metal burrs are generated on the edges of the first outer end surface 141. Therefore, by adopting this configuration, when the semiconductor device A10 is mounted on a wiring board, it is possible to prevent a decrease in the bonding strength of the semiconductor device A10 to the wiring board due to the metal burrs.

[0067] The first lead 101 has a second outer end surface 142 that is connected to the mounting surface 121 and exposed from the outer surface 43 of the sealing resin 40. If the first lead 101 has at least the first outer end surface 141, the covering layer 50 that covers the mounting surface 121 and the second outer end surface 142 can be easily formed by electrolytic plating in the step of forming the covering layer 50 shown in Figures 15 and 16 during the manufacturing process of the semiconductor device A10. This makes it easy to visually check the bonding state of not only the second lead 102 but also the first lead 101 to the wiring board when the semiconductor device A10 is mounted on a wiring board.

[0068] The area of ​​the mounting surface 121 of the first lead 101 is larger than the area of ​​the back surface 122 of the second lead 102. The first semiconductor element 201 is mounted on the first lead 101. This allows the heat generated from the first semiconductor element 201 to be more efficiently released to the outside.

[0069] The semiconductor device A10 further includes a fourth lead 104 on which a second semiconductor element 202 is mounted. The recess 44 of the sealing resin 40 is also located between the first lead 101 and the fourth lead 104. The first lead 101 and the fourth lead 104 have inner end faces 15 exposed from inner surfaces 441 of the recess 44. As a result, in the process of forming the covering layer 50 shown in FIGS. 15 and 16 during the manufacturing process of the semiconductor device A10, the covering layer 50 that covers not only the first lead 101 but also the mounting surface 121 and second outer end face 142 of the fourth lead 104 can be easily formed by electrolytic plating.

[0070] In the semiconductor devices A11 and A12, the inner end surface 15 of the second lead 102 is smaller in area than the inner end surface 15 of the second lead 102 in the semiconductor device A10. This makes it possible to suppress metal burrs from forming on the edge of the inner end surface 15 during the process of cutting the connecting band 82 shown in FIG. 17 during the manufacturing process of the semiconductor device A10. Furthermore, in the semiconductor device A12, the depth of the recess 44 in the sealing resin 40 is smaller than the depth of the recess 44 in the semiconductor device A10. This makes it possible to reduce the volume of sealing resin 40 removed during the process of cutting the connecting band 82 shown in FIG. 17 during the manufacturing process of the semiconductor device A10. This contributes to suppressing a decrease in the strength of the sealing resin 40.

[0071] A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 25 to 30. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Figure 25 shows the sealing resin 40 through a transparent view, which is indicated by imaginary lines.

[0072] In the semiconductor device A20, the configurations of the leads 10 and the sealing resin 40 are different from those of the semiconductor device A10 described above.

[0073] As shown in FIGS. 26 to 28 , a pair of first surfaces 431 on the outer side surfaces 43 of the sealing resin 40 have a first region 431A, a second region 431B, and a third region 431C. The first region 431A is connected to the top surface 41 of the sealing resin 40. The second region 431B is connected to the bottom surface 42 of the sealing resin 40 and is located more inward in the sealing resin 40 than the first region 431A. Two side surfaces 13 of the second lead 102 and the third lead 103 are exposed from one of the second regions 431B of the pair of first surfaces 431. Two second outer end surfaces 142 of the first lead 101 and the fourth lead 104 are exposed from the other of the second regions 431B of the pair of first surfaces 431. The third region 431C is located between the top surface 41 and the bottom surface 42 in the thickness direction z, and is connected to the first region 431A and the second region 431B. The third region 431C faces the same side as the bottom surface 42 in the thickness direction z.

[0074] 29 and 30 , the covering layer 50 is located more inward in the sealing resin 40 than the first regions 431A of the pair of first surfaces 431 of the outer side surface 43. As shown in Fig. 26 , when viewed in the thickness direction z, the third regions 431C of the pair of first surfaces 431 overlap the covering layer 50. The third regions 431C are located closer to the top surfaces 41 than the main surfaces 112 of the second lead 102 and the third lead 103 in the thickness direction z.

[0075] Next, an example of a method for manufacturing the semiconductor device A20 will be described with reference to Figures 31 to 37. Here, Figures 33, 35 and 37 are taken at the same cross-sectional position as Figure 29.

[0076] 31 , a plurality of semiconductor elements 20 are individually mounted on the mounting surfaces 111 of the first lead 101 and the fourth lead 104 of the plurality of leads 10. Then, a plurality of conductive members 30 are individually bonded to the first electrodes 21 of the plurality of semiconductor elements 20 and the main surfaces 112 of the second lead 102 and the third lead 103 of the plurality of leads 10.

[0077] 31 , the frame body 80 has a plurality of first frame portions 801 and a plurality of second frame portions 802. The plurality of first frame portions 801 extend along the first direction x and are spaced apart from one another in the second direction y. The plurality of second frame portions 802 extend along the second direction y and are spaced apart from one another in the first direction x. Both ends of each of the plurality of second frame portions 802 are connected to two first frame portions 801 that are adjacent to one another in the second direction y. The tie bar 81 is connected to the plurality of first frame portions 801. In the semiconductor device A20, each of the plurality of leads 10 is connected to one of two second frame portions 802 that are adjacent to one another in the first direction x.

[0078] 32 and 33 , a sealing resin 40 is formed to cover a portion of each of the plurality of leads 10, the plurality of semiconductor elements 20, and the plurality of conductive members 30. The sealing resin 40 is formed over the entire frame body 80 by compression molding. In this process, the back surface 122 of at least one of the plurality of leads 10 (the second lead 102 and the third lead 103) is exposed from the sealing resin 40. Furthermore, in this process, the mounting surfaces 121 of the first lead 101 and the fourth lead 104 are also exposed from the sealing resin 40.

[0079] Next, as shown in FIGS. 34 and 35 , the multiple second frame portions 802 are removed from the side where the back surface 122 is exposed in the thickness direction z. The multiple second frame portions 802 are removed by half-cut dicing. At this time, a portion of each of the multiple leads 10 located at the boundary with the multiple second frame portions 802 and a portion of the sealing resin 40 located at the boundary with the multiple second frame portions 802 are also removed. Through this process, multiple grooves 83 are formed in the sealing resin 40, recessed in the thickness direction z and extending along the second direction y. Two grooves 83 adjacent to each other in the first direction x among the multiple grooves 83 reveal two side surfaces 13 of each of the second lead 102 and the third lead 103 and two second outer end surfaces 142 of each of the first lead 101 and the fourth lead 104.

[0080] 36 and 37 , a coating layer 50 is formed by electrolytic plating to cover the rear surface 122 and side surface 13 exposed from the sealing resin 40. In this process, the mounting surface 121 of each of the first lead 101 and the fourth lead 104 and the two second outer end surfaces 142 are also covered with the coating layer 50. Thereafter, the connecting strip 82 is cut by removing a portion of the sealing resin 40 from the side where the rear surface 122 is exposed in the thickness direction z. The cutting method for the connecting strip 82 is the same as the cutting method in the manufacturing process of the semiconductor device A10 shown in FIGS. 17 to 19 .

[0081] Finally, the sealing resin 40 and the tie bars 81 are cut in a grid pattern along the first direction x and the second direction y, thereby separating the leads 10 from the frame body 80. Through the above steps, the semiconductor device A20 is obtained.

[0082] Next, the effects of the semiconductor device A20 will be described.

[0083] The semiconductor device A20 includes a second lead 102 having a back surface 122 and a side surface 13 exposed from the sealing resin 40, and a coating layer 50 covering the back surface 122 and the side surface 13. The sealing resin 40 has an inner surface 441 and a recess 44 recessed from the bottom surface 42. The second lead 102 and at least one of the first lead 101 and the third lead 103, which are positioned between the second lead 102 and the recess 44, have an inner end surface 15 exposed from the inner surface 441. Therefore, the semiconductor device A20 also enables the coating layer 50 covering the back surface 122 and the side surface 13 of the lead 10 (second lead 102) exposed from the sealing resin 40 to be more efficiently formed. Furthermore, by having a configuration similar to that of the semiconductor device A10, the semiconductor device A20 also achieves the effects of this configuration.

[0084] In the semiconductor device A20, a pair of first surfaces 431 of the outer surface 43 of the sealing resin 40 has a first region 431A, a second region 431B, and a third region 431C. This configuration is obtained by removing the multiple second frame portions 802 after forming the sealing resin 40 in the manufacture of the semiconductor device A20. Until the multiple second frame portions 802 are removed, each of the multiple leads 10 is connected to one of the multiple second frame portions 802. This allows the sealing resin 40 to be formed over the entire frame body 80 by compression molding. Therefore, forming the sealing resin 40 is easier than in the case of the semiconductor device A10.

[0085] A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to FIGS. 38 to 43. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, FIG. 38 shows the sealing resin 40 in a perspective view. In FIG. 38, the transparent sealing resin 40 is shown by imaginary lines.

[0086] In the semiconductor device A30, the configurations of the leads 10, the semiconductor elements 20, the conductive members 30, and the sealing resin 40 are different from those of the semiconductor device A10 described above.

[0087] 38 and 39 , the multiple leads 10 further include a fifth lead 105 and a sixth lead 106 in addition to the first lead 101, the second lead 102, the third lead 103, and the fourth lead 104. The fifth lead 105 is located adjacent to the second lead 102 in the second direction y and is located on the opposite side of the second lead 102 from the third lead 103 in the second direction y. The sixth lead 106 is located adjacent to the third lead 103 in the second direction y and is located on the opposite side of the second lead 102 from the third lead 103 in the second direction y.

[0088] As shown in FIGS. 38, 39 and 41, the fifth lead 105 and the sixth lead 106 have a main surface 112, a back surface 122, a side surface 13, a first outer end surface 141, an inner circumferential surface 16, a canopy portion 17 and an outward convex portion 18.

[0089] 38 and 39 , the second lead 102 and the third lead 103 have a main surface 112, a back surface 122, a side surface 13, an inner end face 15, an inner circumferential surface 16, an overhang portion 17, and an inward protrusion 19. Furthermore, the inner end face 15 of the second lead 102 includes a region facing inward of the sealing resin 40 in the first direction x, and a region facing inward of the sealing resin 40 in the second direction y. Accordingly, the inward protrusion 19 of the second lead 102 includes a region protruding from the overhang portion 17 inward of the sealing resin 40 in the first direction x, and a region protruding from the overhang portion 17 inward of the sealing resin 40 in the second direction y.

[0090] 38 and 39 , the first lead 101 has a mounting surface 111, a mounting surface 121, a first outer end surface 141, two second outer end surfaces 142, an inner end surface 15, an inner peripheral surface 16, a visor portion 17, an outer convex portion 18, and an inner convex portion 19. The inner end surface 15 of the first lead 101 includes a region facing inward of the sealing resin 40 in the first direction x and a region facing inward of the sealing resin 40 in the second direction y. Accordingly, the inward convex portion 19 of the first lead 101 includes a region protruding from the visor portion 17 inward of the sealing resin 40 in the first direction x and a region protruding from the visor portion 17 inward of the sealing resin 40 in the second direction y. The configuration of the fourth lead 104 is similar to the configuration of the fourth lead 104 of the semiconductor device A10, and therefore description thereof will be omitted here.

[0091] In the semiconductor device A30, the multiple semiconductor elements 20 are n-channel, vertical-structure metal-oxide-semiconductor field-effect transistors (MOSFETs). The multiple semiconductor elements 20 include a compound semiconductor substrate. The compound semiconductor substrate is primarily made of silicon carbide (SiC). Alternatively, the compound semiconductor substrate may be primarily made of silicon (Si). Alternatively, the multiple semiconductor elements 20 may be other switching elements such as insulated gate bipolar transistors (IGBTs). In the semiconductor device A30, the multiple semiconductor elements 20 also include a first semiconductor element 201 and a second semiconductor element 202.

[0092] 42 , the plurality of semiconductor elements 20 have first electrodes 21, second electrodes 22, and gate electrodes 23. The first electrodes 21 are provided on the side of the first leads 101 facing the mounting surface 111. A current corresponding to the power converted by the semiconductor elements 20 flows through the first electrodes 21. In other words, the first electrodes 21 correspond to source electrodes.

[0093] 42 , the second electrode 22 is provided on the opposite side to the first electrode 21 in the thickness direction z. The second electrode 22 faces either the mounting surface 111 of the first lead 101 or the mounting surface 111 of the fourth lead 104. A current corresponding to the power before being converted by the semiconductor element 20 flows through the second electrode 22. In other words, the second electrode 22 corresponds to a drain electrode.

[0094] 42 , the gate electrode 23 is provided on the same side as the first electrode 21 in the thickness direction z, and is located away from the first electrode 21. A gate voltage for driving the semiconductor element 20 is applied to the gate electrode 23. As shown in FIG. 38 , the area of ​​the gate electrode 23 is smaller than the area of ​​the first electrode 21 when viewed in the thickness direction z.

[0095] 38 , the plurality of conductive members 30 include two first members 31 and two second members 32. One of the two first members 31 is bonded to the first electrode 21 of the first semiconductor element 201 and to the main surface 112 of the fifth lead 105 via bonding layers 29. As a result, the first electrode 21 of the first semiconductor element 201 is electrically connected to the fifth lead 105. The other of the two first members 31 is bonded to the first electrode 21 of the second semiconductor element 202 and to the main surface 112 of the sixth lead 106 via bonding layers 29. As a result, the first electrode 21 of the second semiconductor element 202 is electrically connected to the sixth lead 106.

[0096] 38 , one of the two second members 32 is bonded to the gate electrode 23 of the first semiconductor element 201 and the main surface 112 of the second lead 102. As a result, the gate electrode 23 of the first semiconductor element 201 is electrically connected to the second lead 102. The other of the two second members 32 is bonded to the gate electrode 23 of the second semiconductor element 202 and the main surface 112 of the third lead 103. As a result, the gate electrode 23 of the second semiconductor element 202 is electrically connected to the third lead 103. The two second members 32 are wires. The two second members 32 contain gold. Alternatively, the two second members 32 may contain aluminum (Al) or copper.

[0097] As shown in FIG. 38, when viewed in the thickness direction z, the plurality of conductive members 30 are positioned away from the inner end surfaces 15 of the plurality of leads 10 (first lead 101, second lead 102, and third lead 103).

[0098] As shown in FIGS. 39 to 41 , the recess 44 of the sealing resin 40 includes a first groove 44A and a second groove 44B. The first groove 44A extends in a first direction x. Both sides of the first groove 44A in the first direction x are connected to a pair of first surfaces 431 of the outer side surface 43. The second groove 44B extends in a second direction y. Both sides of the second groove 44B in the second direction y are connected to a pair of second surfaces 432 of the outer side surface 43. The second groove 44B intersects with the first groove 44A. The bottom surface 42 of the sealing resin 40 is divided into four regions by the recess 44.

[0099] 39 , the fourth lead 104 is located adjacent to the first lead 101 with the first groove 44A in between. The third lead 103 is located adjacent to the second lead 102 with the first groove 44A in between. From the inner side surface 441 of the first groove 44A, a region of the inner end surface 15 of the first lead 101 facing the second direction y, the inner end surface 15 of the fourth lead 104, a region of the inner end surface 15 of the second lead 102 facing the second direction y, and the inner end surface 15 of the third lead 103 are exposed. As shown in FIGS. 39 and 43 , the first lead 101 is located adjacent to the second lead 102 with the second groove 44B in between. From the inner side surface 441 of the second groove 44B, a region of the inner end face 15 of the first lead 101 facing the first direction x and a region of the second lead 102 facing the first direction x are exposed.

[0100] Next, the effects of the semiconductor device A30 will be described.

[0101] The semiconductor device A30 includes a second lead 102 having a back surface 122 and a side surface 13 exposed from the sealing resin 40, and a coating layer 50 covering the back surface 122 and the side surface 13. The sealing resin 40 has an inner surface 441 and a recess 44 recessed from the bottom surface 42. The second lead 102 and at least one of the first lead 101 and the third lead 103, which are positioned between the second lead 102 and the recess 44, have an inner end surface 15 exposed from the inner surface 441. Therefore, the semiconductor device A30 also enables the coating layer 50 covering the back surface 122 and the side surface 13 of the lead 10 (second lead 102) exposed from the sealing resin 40 to be more efficiently formed. Furthermore, by having a configuration similar to that of the semiconductor device A10, the semiconductor device A30 also achieves the effects of this configuration.

[0102] In the semiconductor device A30, the recess 44 in the sealing resin 40 includes a first groove 44A extending in the first direction x and a second groove 44B extending in the second direction y. As a result, the inner end surface 15 of the second lead 102 includes a region facing the first direction x and a region facing the second direction y. With this configuration, even if the second lead 102 and the third lead 103 do not have the first outer end surface 141, the coating layer 50 that covers the back surface 122 and the side surface 13 of the second lead 102 and the third lead 103 can be easily formed by electrolytic plating.

[0103] When viewed in the thickness direction z, the plurality of conductive members 30 are located away from the inner end surfaces 15 of the plurality of leads 10. This reduces the risk of cutting the plurality of conductive members 30 together with the connecting bands 82 in the step of cutting the connecting bands 82 (see FIG. 17 ) in the manufacturing process of the semiconductor device A30.

[0104] A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described with reference to Figures 44 and 45. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, Figure 44 shows a view through the sealing resin 40. In Figure 44, the transparent sealing resin 40 is shown by imaginary lines.

[0105] In the semiconductor device A40, the configurations of the leads 10, the conductive members 30, and the sealing resin 40 are different from those of the semiconductor device A10. Furthermore, in the semiconductor device A40, the semiconductor element 20 is composed of one first semiconductor element 201.

[0106] As shown in FIGS. 44 and 45 , the multiple leads 10 include a first lead 101, a second lead 102, a third lead 103, and a fifth lead 105. The semiconductor device A40 does not include a fourth lead 104. The first lead 101 has a mounting surface 111, a mounting surface 121, two first outer end faces 141, four second outer end faces 142, an inner end face 15, an inner peripheral surface 16, a canopy portion 17, two outer protrusions 18, and an inner protrusion 19. The inner end face 15 of the first lead 101 faces inward of the sealing resin 40 in the first direction x. Accordingly, the inward protrusion 19 of the first lead 101 protrudes inward of the sealing resin 40 in the first direction x from the canopy portion 17. The first lead 101 is configured such that the first lead 101 and the fourth lead 104 of the semiconductor device A10 are integrated together.

[0107] 44 and 45 , the second lead 102 has a main surface 112, a back surface 122, a side surface 13, an inner end surface 15, an inner peripheral surface 16, a visor portion 17, and an inward protrusion 19. The inner end surface 15 of the second lead 102 faces the first direction x. Accordingly, the inward protrusion 19 of the second lead 102 protrudes from the visor portion 17 in the first direction x. The configuration of the third lead 103 is similar to that of the third lead 103 of the semiconductor device A10, and therefore a description thereof will be omitted here. Furthermore, the configuration of the fifth lead 105 is similar to that of the fifth lead 105 of the semiconductor device A30, and therefore a description thereof will be omitted here.

[0108] In the semiconductor device A40, the first semiconductor element 201 (semiconductor element 20) is an n-channel type vertical structure MOSFET, similar to the semiconductor device A30.

[0109] As shown in FIG. 44 , the multiple conductive members 30 include a first member 31, a second member 32, and a third member 33. The first member 31 is bonded to the first electrode 21 of the first semiconductor element 201 and the main surface 112 of the third lead 103 via bonding layers 29. As a result, the first electrode 21 of the first semiconductor element 201 is electrically connected to the third lead 103. The second member 32 is bonded to the gate electrode 23 of the first semiconductor element 201 and the main surface 112 of the fifth lead 105. As a result, the gate electrode 23 of the first semiconductor element 201 is electrically connected to the fifth lead 105. The third member 33 is bonded to the first electrode 21 of the first semiconductor element 201 and the main surface 112 of the second lead 102. As a result, the first electrode 21 of the first semiconductor element 201 is electrically connected to the second lead 102. The third member 33 is a wire. The composition of the third member 33 includes gold. Alternatively, the composition of the third member 33 may include aluminum or copper.

[0110] 45 , the recess 44 in the sealing resin 40 is a groove extending in the second direction y. Both sides of the recess 44 in the second direction y are connected to a pair of second surfaces 432 of the outer surface 43. The first lead 101 is located next to the second lead 102 with the recess 44 sandwiched therebetween. From the inner surface 441 of the recess 44, the inner end surface 15 of the first lead 101 and the inner end surface 15 of the second lead 102 are exposed.

[0111] Next, the effects of the semiconductor device A40 will be described.

[0112] The semiconductor device A40 includes a second lead 102 having a back surface 122 and a side surface 13 exposed from the sealing resin 40, and a coating layer 50 covering the back surface 122 and the side surface 13. The sealing resin 40 has an inner surface 441 and a recess 44 recessed from the bottom surface 42. The second lead 102 and at least one of the first lead 101 and the third lead 103, which are positioned between the second lead 102 and the recess 44, have an inner end surface 15 exposed from the inner surface 441. Therefore, the semiconductor device A40 also enables the coating layer 50 covering the back surface 122 and the side surface 13 of the lead 10 (second lead 102) exposed from the sealing resin 40 to be more efficiently formed. Furthermore, by having a configuration similar to that of the semiconductor device A10, the semiconductor device A40 also achieves the effects of this configuration.

[0113] In the semiconductor device A40, the semiconductor element 20 is composed of one first semiconductor element 201. Therefore, the present disclosure can be applied regardless of the number of semiconductor elements 20.

[0114] A semiconductor device A50 according to a fifth embodiment of the present disclosure will be described with reference to FIGS. 46 to 49. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. Here, for ease of understanding, FIG. 46 shows the sealing resin 40 through which the sealing resin 40 is seen. In FIG. 46, the seen-through sealing resin 40 is shown by imaginary lines. The cross-sectional position in FIG. 47 is the same as the cross-sectional position in FIG. 8, which shows the semiconductor device A10. The cross-sectional position in FIG. 48 is the same as the cross-sectional position in FIG. 9, which shows the semiconductor device A10.

[0115] The semiconductor device A50 differs from the semiconductor device A10 described above in that it further includes an insulator 60.

[0116] As shown in Figures 46 to 49, the insulator 60 is filled in the recess 44 of the sealing resin 40. The insulator 60 is, for example, a resin used for underfill. The inner end surface 15 of each of the multiple leads 10 is covered with the insulator 60. The insulator 60 is in contact with the intermediate surface 442 of the recess 44. However, as long as the insulator 60 is configured to cover two inner end surfaces 15 that face each other with the recess 44 therebetween, the insulator 60 may be spaced apart from the intermediate surface 442.

[0117] The semiconductor device A50 includes a second lead 102 having a back surface 122 and a side surface 13 exposed from the sealing resin 40, and a coating layer 50 covering the back surface 122 and the side surface 13. The sealing resin 40 has an inner surface 441 and a recess 44 recessed from the bottom surface 42. The second lead 102 and at least one of the first lead 101 and the third lead 103, which are positioned between the second lead 102 and the recess 44, have an inner end surface 15 exposed from the inner surface 441. Therefore, the semiconductor device A50 also enables the coating layer 50, which covers the back surface 122 and the side surface 13 of the lead 10 (second lead 102) exposed from the sealing resin 40, to be more efficiently formed. Furthermore, by having a configuration similar to that of the semiconductor device A10, the semiconductor device A50 also achieves the effects of this configuration.

[0118] The semiconductor device A50 further includes an insulator 60 filled in the recess 44 of the sealing resin 40. This prevents solder from adhering to the inner end faces 15 of two adjacent leads 10 sandwiching the recess 44 when the semiconductor device A50 is mounted on a wiring board. This prevents short-circuiting between two adjacent leads 10 sandwiching the recess 44 therebetween.

[0119] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0120] The present disclosure includes the embodiments described in the following appendices.

[0121] Supplementary Note 1. A semiconductor device comprising: a first lead; a second lead located adjacent to the first lead in a direction perpendicular to the thickness direction of the first lead; a third lead located adjacent to the second lead in the direction perpendicular to the thickness direction; a first semiconductor element mounted on the first lead and conducting to the second lead; a sealing resin covering the first semiconductor element and portions of the first lead, the second lead, and the third lead; and a coating layer containing a metal element, wherein the sealing resin has a bottom surface facing the thickness direction and an outer side surface connected to the bottom surface and facing outward from the sealing resin in the direction perpendicular to the thickness direction, a recess recessed from the bottom surface is formed in the sealing resin, and the recess has an inner side surface connected to the bottom surface and facing inward from the sealing resin in the direction perpendicular to the thickness direction, the second lead has a back surface exposed from the bottom surface and a side surface connected to the back surface and exposed from the outer side surface, and the coating layer covers the back surface and the side surface, A semiconductor device according to claim 1, wherein the recess is a groove extending in a direction perpendicular to the thickness direction, the inner surface includes a pair of regions spaced apart in a direction perpendicular to the thickness direction and the direction in which the recess extends, and the inner end surface is exposed from the pair of regions. Supplementary Note 3. A semiconductor device according to claim 2, wherein the bottom surface is divided into a plurality of regions by the recess. Supplementary Note 4. A semiconductor device according to claim 3, wherein the recess includes a first groove and a second groove, and the second groove intersects with the first groove. Supplementary Note 5. A semiconductor device according to any one of Supplements 1 to 4, wherein the inner end surface of the second lead is located away from the side surface. Supplementary Note 6. A semiconductor device according to claim 5, wherein an area of ​​the inner end surface of the second lead is smaller than an area of ​​the side surface. Appendix 7. The semiconductor device according to Appendix 6, wherein the inner end surface of the second lead is located away from the back surface.Appendix 8. The semiconductor device according to Appendix 6 or 7, wherein the second lead has a main surface facing the opposite side to the back surface in the thickness direction, and the inner end surface is connected to the main surface. Appendix 9. The semiconductor device according to Appendix 8, wherein the recess has an intermediate surface facing the same side as the bottom surface in the thickness direction and connected to the inner side surface, and the intermediate surface is located farther from the bottom surface in the thickness direction than the main surface. Appendix 10. The semiconductor device according to any of Appendixes 1 to 9, wherein the first lead has a first outer end surface exposed from the outer side surface, and the direction in which the first outer end surface faces is different from the direction in which the side surface faces. Appendix 11. The semiconductor device according to Appendix 10, wherein the first lead has a mounting surface exposed from the bottom surface, and the first outer end surface is located farther from the mounting surface. Appendix 12. The semiconductor device according to Appendix 11, wherein the area of ​​the mounting surface is larger than the area of ​​the back surface. Appendix 13. The semiconductor device according to Appendix 11 or 12, wherein the first lead is connected to the mounting surface and has a second outer end surface exposed from the outer side surface, and the covering layer covers the mounting surface and the second outer end surface. Appendix 14. The semiconductor device according to Appendix 13, wherein the direction in which the second outer end surface faces is the same as the direction in which the side surface faces, and the second outer end surface faces the opposite side to the side surface. Appendix 15. The semiconductor device according to Appendix 14, wherein the area of ​​the second outer end surface is larger than the area of ​​the first outer end surface. Appendix 16. The semiconductor device described in any one of appendixes 1 to 15, further comprising: a fourth lead located adjacent to the first lead in a direction perpendicular to the thickness direction; and a second semiconductor element mounted on the fourth lead and conductive to the third lead, wherein the sealing resin covers a portion of the fourth lead and the second semiconductor element, the recess is also located between the first lead and the fourth lead, and the first lead and the fourth lead have the inner end surfaces.Supplementary Note 17. A method for manufacturing a semiconductor device, comprising the steps of: mounting a semiconductor element on any one of a plurality of leads, each of which has a back surface and a side surface connected to the back surface; and forming a sealing resin that covers a portion of each of the plurality of leads and the semiconductor element, wherein in the step of forming the sealing resin, the back surface and the side surface of at least any one of the plurality of leads are exposed from the sealing resin, and at least any two of the plurality of leads are connected to each other by a connecting band made of the same composition as the plurality of leads, and further comprising the steps of: after the step of forming the sealing resin, forming a coating layer by electrolytic plating that covers the back surface and the side surface exposed from the sealing resin and contains a metal element; and after the step of forming the coating layer, cutting the connecting band by removing a portion of the sealing resin from the side where the back surface is exposed.

[0122] A10, A20, A30: semiconductor device 10: lead 101: first lead 102: second lead 103: third lead 104: fourth lead 105: fifth lead 106: sixth lead 111: mounting surface 112: main surface 121: mounting surface 122: back surface 13: side surface 141: first outer end surface 142: second outer end surface 15: inner end surface 16: inner circumferential surface 17: canopy portion 171: protruding surface 18: outward convex portion 19: inward convex portion 20: semiconductor element 201: first semiconductor element 202: second semiconductor element 21: first electrode 22: second electrode 23: gate electrode 29: bonding layer 30: conductive member 31: first member 32: second member 33: third member 40: Sealing resin 41: Top surface 42: Bottom surface 43: Outer surface 431: First surface 431A: First region 431B: Second region 431C: Third region 432: Second surface 44: Recess 441: Inner surface 442: Intermediate surface 50: Covering layer 60: Insulator 80: Frame 801: First frame portion 802: Second frame portion 81: Tie bar 82: Connecting band 83: Groove z: Thickness direction x: First direction y: Second direction

Claims

1. The first lead; a second lead positioned adjacent to the first lead in a direction perpendicular to a thickness direction of the first lead; a third lead located adjacent to the second lead in a direction perpendicular to the thickness direction; a first semiconductor element mounted on the first lead and electrically connected to the second lead; a sealing resin that covers a portion of each of the first lead, the second lead, and the third lead, and the first semiconductor element; A coating layer containing a metal element; Equipped with the sealing resin has a bottom surface facing the thickness direction and an outer surface connected to the bottom surface and facing outward from the sealing resin in a direction perpendicular to the thickness direction, a recessed portion recessed from the bottom surface is formed in the sealing resin, the recess has an inner side surface that is connected to the bottom surface and faces inward of the sealing resin in a direction perpendicular to the thickness direction, the second lead has a back surface exposed from the bottom surface and a side surface connected to the back surface and exposed from the outer surface, the covering layer covers the back surface and the side surface, the recess is between the first lead and the second lead, The second lead and at least one of the first lead and the third lead have an inner end surface exposed from the inner side surface.

2. The recess is a groove extending in a direction perpendicular to the thickness direction, the inner surface includes a pair of regions spaced apart from each other in a direction perpendicular to the thickness direction and the direction in which the recess extends, The semiconductor device according to claim 1 , wherein the inner end surface is exposed from the pair of regions.

3. The semiconductor device according to claim 2 , wherein said bottom surface is divided into a plurality of regions by said recessed portion.

4. the recess includes a first groove and a second groove, The semiconductor device according to claim 3 , wherein the second trench intersects with the first trench.

5. The semiconductor device according to claim 1 , wherein the inner end surface of the second lead is located away from the side surface.

6. 6. The semiconductor device according to claim 5, wherein an area of ​​said inner end face of said second lead is smaller than an area of ​​said side face.

7. The semiconductor device according to claim 6 , wherein the inner end surface of the second lead is located away from the rear surface.

8. the second lead has a main surface facing a side opposite to the back surface in the thickness direction, The semiconductor device according to claim 6 , wherein the inner end surface is connected to the main surface.

9. the recess has an intermediate surface facing the same side as the bottom surface in the thickness direction and connected to the inner surface, The semiconductor device according to claim 8 , wherein the intermediate surface is located farther from the bottom surface than the main surface is in the thickness direction.

10. the first lead has a first outer end surface exposed from the outer side surface, 10. The semiconductor device according to claim 1, wherein a direction in which said first outer end surface faces is different from a direction in which said side surface faces.

11. the first lead has a mounting surface exposed from the bottom surface, The semiconductor device according to claim 10 , wherein the first outer end surface is located away from the mounting surface.

12. The semiconductor device according to claim 11 , wherein an area of ​​said mounting surface is larger than an area of ​​said back surface.

13. the first lead has a second outer end surface connected to the mounting surface and exposed from the outer side surface; The semiconductor device according to claim 11 , wherein the covering layer covers the mounting surface and the second outer end surface.

14. The direction in which the second outer end surface faces is the same as the direction in which the side surface faces, The semiconductor device according to claim 13 , wherein the second outer end surface faces in a direction opposite to the side surface.

15. The semiconductor device according to claim 14 , wherein an area of ​​said second outer end face is larger than an area of ​​said first outer end face.

16. a fourth lead located adjacent to the first lead in a direction perpendicular to the thickness direction; a second semiconductor element mounted on the fourth lead and in electrical communication with the third lead; the sealing resin covers a portion of the fourth lead and the second semiconductor element, The recess is also located between the first lead and the fourth lead, 10. The semiconductor device according to claim 1, wherein the first lead and the fourth lead have the inner end surface.

17. A step of mounting a semiconductor element on any one of a plurality of leads, each of which has a back surface and a side surface connected to the back surface; forming a sealing resin that covers a portion of each of the plurality of leads and the semiconductor element; In the step of forming the sealing resin, the rear surface and the side surface of at least any of the plurality of leads are exposed from the sealing resin, At least two of the plurality of leads are connected to each other by a connecting band having the same composition as the plurality of leads; forming a coating layer by electrolytic plating after the step of forming a sealing resin, the coating layer covering the back surface and the side surface exposed from the sealing resin and containing a metal element; The method for manufacturing a semiconductor device further comprises, after the step of forming the covering layer, a step of cutting the connecting strip by removing a part of the sealing resin from the side where the back surface is exposed.