Display device, display system, and display drive method

Abstract

This display device comprises: a receiver circuit capable of receiving first image data indicating a full image having a first resolution, and second image data corresponding to part of the full image and indicating a first partial image having a second resolution higher than the first resolution; a display unit having a plurality of pixels; and a display drive circuit capable of performing first driving in which the plurality of pixels are driven with a first number of pixels as units on the basis of the first image data, and second driving in which of the plurality of pixels, two or more pixels provided to an area corresponding to the first partial image are driven with a second number of pixels, smaller than the first number, as units on the basis of the second image data.

Description

Display device, display system, and display driving method

[0001] The present disclosure relates to a display device that displays an image, a display system, and a display driving method.

[0002] Some display devices generate a frame image based on a low-resolution overall image and a high-resolution partial image, and display the generated frame image (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2019-197224

[0004] Display devices are desired to have high image quality, and further improvements in image quality are expected.

[0005] It is desirable to provide a display device, a display system, and a display driving method that can improve image quality.

[0006] A display device according to an embodiment of the present disclosure includes a receiving circuit, a display unit, and a display drive circuit. The receiving circuit is configured to receive first image data representing an entire image at a first resolution and second image data representing a first partial image at a second resolution higher than the first resolution, the first image data representing a portion of the entire image. The display unit has a plurality of pixels. The display drive circuit is configured to perform a first drive operation for driving the plurality of pixels in units of a first number of pixels based on the first image data, and a second drive operation for driving two or more pixels of the plurality of pixels that are provided in an area corresponding to the first partial image in units of a second number of pixels that is smaller than the first number, based on the second image data.

[0007] A display system according to an embodiment of the present disclosure includes an image generation device and a display device. The image generation device is configured to transmit first image data representing an entire image at a first resolution and second image data representing a first partial image at a second resolution higher than the first resolution, the first image data corresponding to a portion of the entire image. The display device includes a receiving circuit, a display unit, and a display drive circuit. The receiving circuit is configured to receive the first image data and the second image data. The display unit has a plurality of pixels. The display drive circuit is configured to perform a first drive that drives the plurality of pixels in units of a first number of pixels based on the first image data, and a second drive that drives two or more pixels of the plurality of pixels that are provided in an area corresponding to the first partial image in units of a second number of pixels that is smaller than the first number, based on the second image data.

[0008] A display driving method in one embodiment of the present disclosure includes transmitting first image data indicating an entire image at a first resolution and second image data indicating a first partial image at a second resolution higher than the first resolution, which corresponds to a portion of the entire image; receiving the first image data and the second image data; performing a first drive based on the first image data to drive a plurality of pixels in units of a first number of pixels; and performing a second drive based on the second image data to drive two or more pixels among the plurality of pixels that are provided in an area corresponding to the first partial image in units of a second number of pixels that is less than the first number.

[0009] In a display device, a display system, and a display driving method according to an embodiment of the present disclosure, a receiving circuit receives first image data and second image data. The first image data is data representing an entire image at a first resolution. The second image data is data representing a first partial image at a second resolution higher than the first resolution, corresponding to a portion of the entire image. A first driving process is performed based on the first image data, in which a first number of pixels are driven as a unit. Furthermore, a second driving process is performed based on the second image data, in which two or more pixels of the plurality of pixels provided in an area corresponding to the first partial image are driven as a second number of pixels less than the first number.

[0010] 1 is a block diagram illustrating an example configuration of a display system according to an embodiment of the present disclosure. FIG. 1 is an explanatory diagram illustrating an example of a display image of the head-mounted display shown in FIG. 1. FIG. 1 is an explanatory diagram illustrating an example of an overall image and a partial image generated by the image generating device shown in FIG. 1. FIG. 1 is an explanatory diagram illustrating an example of image data of an overall image according to a reference example. FIG. 1 is an explanatory diagram illustrating an example of image data of an overall image and a partial image. FIG. 1 is an explanatory diagram illustrating an example of image data transmitted by the image generating device shown in FIG. 1. FIG. 1 is a block diagram illustrating an example configuration of the display panel shown in FIG. 1. FIG. 1 is an explanatory diagram illustrating an example of a display operation in the display system shown in FIG. 1. FIG. 1 is an explanatory diagram illustrating an example of a display operation in the head-mounted display shown in FIG. 1. FIG. 1 is an explanatory diagram illustrating an example of pixel driving. FIG. 12 is another explanatory diagram illustrating an example of pixel driving. FIG. 13 is a block diagram illustrating an example configuration of a display system according to a modified example. FIG. 14 is an explanatory diagram illustrating an example of a display image of the head-mounted display shown in FIG. 12. FIG. 15 is a block diagram illustrating an example configuration of a display system according to another modified example. FIG. 16 is an explanatory diagram illustrating an example of pixel driving according to another modified example. FIG. 17 is a table illustrating an example characteristic of a display system according to another modified example. FIG. 18 is an explanatory diagram illustrating an example of an overall image and a partial image according to another modified example. FIG. 19 is a table illustrating an example characteristic of a display system according to another modified example. FIG. 10 is an explanatory diagram showing an example of a full image and a partial image according to another modified example. FIG. 11 is an explanatory diagram showing an example of image data of a full image and a partial image according to another modified example. FIG. 12 is an explanatory diagram showing an example of a display operation in a head mounted display according to another modified example. FIG. 13 is an explanatory diagram showing an example of a full image and a partial image according to another modified example. FIG. 14 is an explanatory diagram showing an example of image data of a full image and a partial image according to another modified example. FIG. 15 is an explanatory diagram showing an example of a display operation in a head mounted display according to another modified example. FIG. 16 is an explanatory diagram showing an example of a full image and a partial image according to another modified example. A table showing an example of a characteristic of a display system according to another modified example. An explanatory diagram showing an example of image data of a full image and a partial image according to another modified example. An explanatory diagram showing an example of a display operation in a head mounted display according to another modified example. An explanatory diagram showing an example of driving a pixel according to another modified example.FIG. 44 is an explanatory diagram showing an example of an operation of a display system according to another modified example. FIG. 45 is an explanatory diagram showing an example of a display operation in a head-mounted display according to another modified example. FIG. 46 is an explanatory diagram showing an example of a display image in a head-mounted display according to another modified example. FIG. 47 is an explanatory diagram showing an example of an entire image and a partial image generated by an image generating device according to another modified example. FIG. 48 is an explanatory diagram showing an example of image data of an entire image and a partial image according to another modified example. FIG. 49 is an explanatory diagram showing an example of a display operation in a display system according to another modified example. FIG. 49 is an explanatory diagram showing an example of a display operation in a head-mounted display according to another modified example. FIG. 49 is a table showing an example of a characteristic of a display system according to another modified example. FIG. 49 is a block diagram showing an example of a configuration of a display system according to another modified example. FIG. 49 is an explanatory diagram showing an example of image data of an entire image and a partial image according to another modified example. FIG. 49 is a block diagram showing an example of a configuration of a display system according to another modified example. FIG. 49 is a table showing an example of an operation of a display system according to another modified example. FIG. 49 is another table showing an example of an operation of a display system according to another modified example. FIG. 49 is a block diagram showing an example of a configuration of a display panel according to another modified example. FIG. 49 is a circuit diagram showing an example of a configuration of the pixel shown in FIG. 43. 44 is a circuit diagram illustrating another example of the configuration of the pixel shown in FIG. 43. FIG. ... perspective view illustrating an external configuration of a head mounted display according to an application example. FIG. 44 is a perspective view illustrating an external configuration of another head mounted display according to an application example. FIG. 44 is a front view illustrating an external configuration of a digital still camera according to another application example. FIG. 44 is a rear view illustrating an external configuration of a digital still camera according to another application example. FIG. 44 is a rear view illustrating an external configuration of a television device according to another application example. FIG. 44 is a rear view illustrating an external configuration of a smartphone according to another application example. FIG. 44 is an explanatory diagram illustrating an example of the configuration of a vehicle according to another application example. FIG. 44 is another explanatory diagram illustrating an example of the configuration of a vehicle according to another application example.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order: 1. Embodiment 2. Application Example

[0012] 1 shows an example of the configuration of a display system (display system 1) according to an embodiment. Note that a display device and a display driving method according to an embodiment of the present disclosure are embodied in this embodiment, and will be described together.

[0013] The display system 1 includes an image generation device 10 and a head-mounted display 20. The display system 1 is used for applications such as augmented reality (AR) and virtual reality (VR). When generating an image, the display system 1 is configured to perform foveated rendering, which renders an area of ​​gaze at a high resolution and other areas at a low resolution. In this example, communication between the image generation device 10 and the head-mounted display 20 is performed using an interface such as HDMI (registered trademark) (High-Definition Multimedia Interface) or MIPI (registered trademark). Note that, although this communication is performed via wired communication in this example, it is not limited thereto and may be performed via wireless communication.

[0014] In the display system 1, the head-mounted display 20 displays an image based on an image signal SP transmitted from the image generation device 10. An acceleration sensor 22 (described later) of the head-mounted display 20 detects movements such as the orientation of the head-mounted display 20. An eye-tracking sensor 23 (described later) of the head-mounted display 20 detects the direction of the eyes of a user wearing the head-mounted display 20, thereby detecting which part of the displayed image the user is looking at. The head-mounted display 20 supplies a detection signal SD including these detection results to the image generation device 10. The image generation device 10 generates an image (full image P1) corresponding to the orientation of the head-mounted display 20 based on the detection result of the acceleration sensor 22. The image generation device 10 also generates an image (partial image P2) including the part of the full image P1 that the user is looking at based on the detection result of the eye-tracking sensor 23. When displayed on the head-mounted display 20, the resolution of the partial image P2 is higher than the resolution of the full image P1. The image generating device 10 transmits to the head mounted display 20 an image signal SP including image data DT1 representing the entire image P1 and image data DT2 representing the partial image P2.

[0015] The image generating device 10 is configured to generate an image to be displayed on the head-mounted display 20. The image generating device 10 includes an image generating circuit 11, a transmitting circuit 12, and a receiving circuit 13.

[0016] The image generation circuit 11 is configured to perform a predetermined process, such as a rendering process, to generate an image to be displayed on the head-mounted display 20. The image generation circuit 11 generates an entire image P1 showing a scene in the virtual space corresponding to the orientation of the head-mounted display 20, based on the detection result of the acceleration sensor 22 included in the data supplied from the receiving circuit 13. The image generation circuit 11 also generates a partial image P2 showing a portion of the scene in the virtual space corresponding to the orientation of the head-mounted display 20 that the user is looking at, based on the detection result of the eye-tracking sensor 23 included in the data supplied from the receiving circuit 13.

[0017] FIG. 2 shows an example of a display image P20 displayed on the head-mounted display 20. The display image P20 includes an image of a person 9. In this example, a user wearing the head-mounted display 20 is looking at the image of the person 9. The eye tracking sensor 23 of the head-mounted display 20 detects the direction of the user's eyes to detect which part of the display image P20 the user is looking at. The image generation circuit 11 determines a partial region R2 of the entire region R1 of the display image P20 that includes the part the user is looking at, based on the detection result of the eye tracking sensor 23 included in the data supplied from the receiving circuit 13. In this example, the horizontal size (horizontal direction in FIG. 2 ) of the partial region R2 is half the horizontal size of the entire region R1, and the vertical size (vertical direction in FIG. 2 ) of the partial region R2 is half the vertical size of the entire region R1. In other words, the area of ​​the partial region R2 is ¼ the area of ​​the entire region R1. The image generating circuit 11 generates an entire image P1 relating to the entire region R1, and also generates a partial image P2 relating to the partial region R2.

[0018] FIG. 3 shows an example of an entire image P1 and a partial image P2 generated by the image generation circuit 11. In FIG. 3, the squares represent pixels in the image data. The entire image P1 is a low-resolution image of the entire region R1 (FIG. 2). The partial image P2 is a high-resolution image of the partial region R2. The partial image P2 is a high-resolution image of the image of the partial region R2 in the entire image P1. In this example, each pixel in the entire image P1 corresponds to four pixels PIX (described below) in the head-mounted display 20, and each pixel in the partial image P2 corresponds to one pixel PIX in the head-mounted display 20. In this example, the number of pixels in the entire image P1 and the number of pixels in the partial image P2 are equal to each other. Each of the entire image P1 and the partial image P2 is also referred to as a sub-frame image.

[0019] Fig. 4A schematically shows image data when only the entire image is displayed without foveal rendering. This image data shows image data of a high-resolution entire image that can be used when writing multiple pixel values ​​to multiple pixels PIX in the head-mounted display 20. Fig. 4B schematically shows image data of an entire image P1 and a partial image P2 according to the present technology.

[0020] As described above, each pixel in the entire image P1 corresponds to four pixels PIX, so the number of pixels in the horizontal direction (number of horizontal pixels) of the entire image P1 ( FIG. 4B ) is 50% of the number of horizontal pixels of the high-resolution entire image shown in FIG. 4A , and the number of pixels in the vertical direction (number of vertical pixels) of the entire image P1 is 50% of the number of vertical pixels of the high-resolution entire image. In other words, the horizontal pixel count ratio of the entire image P1 is 50%, and the vertical pixel count ratio of the entire image P1 is 50%. Therefore, the amount of image data for the entire image P1 is ¼ of the amount of image data for the high-resolution entire image.

[0021] Furthermore, as described above, the area of ​​partial region R2 is 1 / 4 of the area of ​​entire region R1, so the number of horizontal pixels (number of horizontal pixels) of partial image P2 ( FIG. 4B ) is 50% of the number of horizontal pixels of the high-resolution entire image shown in FIG. 4A , and the number of vertical pixels (number of vertical pixels) of partial image P2 is 50% of the number of vertical pixels of the high-resolution entire image. In other words, the horizontal pixel count ratio of partial image P2 is 50%, and the vertical pixel count ratio of partial image P2 is 50%. Therefore, the amount of image data for partial region R2 is 1 / 4 of the amount of image data for the high-resolution entire image.

[0022] In this example, the horizontal pixel count ratio of the entire image P1 and the partial image P2 is equal to each other, the vertical pixel count ratio of the entire image P1 and the partial image P2 is equal to each other, and the total data volume of the entire image P1 and the partial image P2 is half the data volume of the high-resolution entire image.

[0023] The image generating circuit 11 generates the entire image P1 and the partial image P2. The image generating circuit 11 then supplies the image data of the generated entire image P1, the image data of the generated partial image P2, and data on the position of the partial image P2 in the entire image P1 to the transmitting circuit 12.

[0024] The transmission circuit 12 (FIG. 1) is configured to generate an image signal SP based on the data supplied from the image generation circuit 11 and transmit this image signal SP to the head-mounted display 20. Specifically, the transmission circuit 12 generates image data DT1 representing an entire image P1 based on image data of the entire image P1, and generates image data DT2 representing a partial image P2 based on image data of the partial image P2 and data regarding the position of the partial image P2. The transmission circuit 12 then transmits the image signal SP including the image data DT1 and the image data DT2 to the head-mounted display 20.

[0025] 5 is a schematic diagram illustrating an example of the image signal SP. The transmission circuit 12 transmits the image data DT1 and DT2 in a time-division manner. Specifically, the transmission circuit 12 alternately transmits the image data DT1 representing the entire image P1 and the image data DT2 representing the partial image P2.

[0026] The receiving circuit 13 (FIG. 1) is configured to receive the detection signal SD transmitted from the head-mounted display 20. The receiving circuit 13 then supplies the image generating circuit 11 with data on the detection results of the acceleration sensor 22 and the eye tracking sensor 23, which are included in the detection signal SD.

[0027] The head-mounted display 20 includes a receiving circuit 21 , an acceleration sensor 22 , an eye tracking sensor 23 , a processor 24 , a transmitting circuit 25 , a display controller 26 , and a display panel 27 .

[0028] The receiving circuit 21 is configured to receive the image signal SP transmitted from the image generating device 10. The receiving circuit 21 then supplies the processor 24 with image data DT1 representing the entire image P1 and image data DT2 representing the partial image P2, which are included in the image signal SP.

[0029] The acceleration sensor 22 is configured to detect movements such as the orientation of the head-mounted display 20. For example, a six-axis inertial sensor can be used as the acceleration sensor 22. This allows the display system 1 to generate an entire image P1 in the virtual space according to the orientation of the head-mounted display 20.

[0030] The eye tracking sensor 23 is configured to detect the direction of the eyes of a user wearing the head-mounted display 20. This allows the display system 1 to detect which part of the displayed image the user is looking at, and to generate a high-resolution partial image P2 that includes the part the user is looking at.

[0031] The processor 24 is configured to control the operation of the head-mounted display 20 and includes, for example, a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit). Specifically, the processor 24 performs predetermined image processing based on, for example, the image data DT1 and DT2 supplied from the receiving circuit 21, and supplies image data of the entire image P1 included in the image data DT1, image data of the partial image P2 included in the image data DT2, and data regarding the position of the partial image P2 included in the image data DT2 to the display controller 26. The processor 24 also supplies the detection results of the acceleration sensor 22 and the eye tracking sensor 23 to the transmitting circuit 25 and causes the transmitting circuit 25 to transmit these detection results.

[0032] The transmission circuit 25 is configured to transmit a detection signal SD, which includes the detection results of the acceleration sensor 22 and the eye tracking sensor 23 supplied from the processor 24 , to the image generation device 10 .

[0033] The display controller 26 is configured to control the operation of the display panel 27 based on the image data of the entire image P1, the image data of the partial image P2, and data on the position of the partial image P2, which are supplied from the processor 24.

[0034] The display panel 27 is configured to display an image based on the control of the display controller 26. In this example, the display panel 27 is an organic EL (Electro Luminescence) display panel. However, the display panel 27 is not limited to this, and may be, for example, a liquid crystal display panel.

[0035] 6 shows an example of the configuration of the display panel 27. The display panel 27 has a pixel array 31, a pixel signal generating circuit 32, and a scanning circuit 33.

[0036] The pixel array 31 has a plurality of signal lines SGL, a plurality of control lines CTL, and a plurality of pixels PIX.

[0037] The signal lines SGL extend in the vertical direction (the longitudinal direction in FIG. 6 ) and are arranged in parallel in the horizontal direction (the lateral direction in FIG. 6 ). Each of the signal lines SGL supplies a pixel signal generated by the pixel signal generation circuit 32 to the pixel PIX.

[0038] The plurality of control lines CTL extend in the horizontal direction (the horizontal direction in FIG. 6) and are arranged in parallel in the vertical direction (the vertical direction in FIG. 6). Each of the plurality of control lines CTL supplies a control signal generated by the scanning circuit 33 to the pixel PIX.

[0039] The plurality of pixels PIX are arranged in a matrix in the pixel array 31. Each of the plurality of pixels PIX is controlled based on a control signal supplied via a control line CTL, and a pixel signal supplied via a signal line SGL is written to each of the plurality of pixels PIX. As a result, each of the plurality of pixels PIX is configured to emit light at a luminance corresponding to the written pixel signal. One row of pixels PIX arranged in parallel in the horizontal direction constitutes a pixel line L.

[0040] The pixel signal generating circuit 32 is configured to generate pixel signals based on image data to be displayed, and to apply the generated pixel signals to each of the plurality of signal lines SGL.

[0041] The scanning circuit 33 is configured to generate a control signal and apply the generated control signal to each of the plurality of control lines CTL, thereby scanning the plurality of pixels PIX with one or more pixel lines L as a scanning unit.

[0042] Here, the receiving circuit 21 corresponds to a specific example of a "receiving circuit" in the present disclosure. The entire image P1 corresponds to a specific example of a "entire image" in the present disclosure. The image data DT1 corresponds to a specific example of a "first image data" in the present disclosure. The partial image P2 corresponds to a specific example of a "partial image" in the present disclosure. The image data DT2 corresponds to a specific example of a "second image data" in the present disclosure. The pixel array 31 corresponds to a specific example of a "display unit" in the present disclosure. The display controller 26, the pixel signal generating circuit 32, and the scanning circuit 33 correspond to a specific example of a "display drive circuit" in the present disclosure. The eye tracking sensor 23 corresponds to a specific example of a "first sensor" in the present disclosure. The acceleration sensor 22 corresponds to a specific example of a "second sensor" in the present disclosure. The transmitting circuit 25 corresponds to a specific example of a "transmitting circuit" in the present disclosure.

[0043] [Operation and Function] Next, the operation and function of the display system 1 according to the present embodiment will be described.

[0044] (Overall Operation Overview) First, an overview of the overall operation of the display system 1 will be described with reference to FIG. 1 . The receiving circuit 13 of the image generating device 10 receives a detection signal SD transmitted from the head-mounted display 20 and supplies data on the detection results of the acceleration sensor 22 and the eye tracking sensor 23, which are included in the detection signal SD, to the image generating circuit 11. The image generating circuit 11 generates an entire image P1 that shows a scene in virtual space corresponding to the orientation of the head-mounted display 20, based on the detection results of the acceleration sensor 22, which are included in the data supplied from the receiving circuit 13. The image generating circuit 11 also generates a partial image P2 that shows a portion of the scene corresponding to the orientation of the head-mounted display 20 that the user is looking at, based on the image data of the entire image P1, and generates image data DT2 that shows the partial image P2 based on the image data of the partial image P2 and data on the position of the partial image P2. Then, the transmission circuit 12 transmits the image signal SP including the image data DT1 and the image data DT2 to the head mounted display 20.

[0045] The receiving circuit 21 of the head-mounted display 20 receives the image signal SP transmitted from the image generating device 10 and supplies the image data DT1 indicating the entire image P1 and the image data DT2 indicating the partial image P2, which are included in the image signal SP, to the processor 24. The processor 24 performs predetermined image processing based on the image data DT1 and DT2 supplied from the receiving circuit 21, and supplies the image data of the entire image P1 included in the image data DT1, the image data of the partial image P2 included in the image data DT2, and data regarding the position of the partial image P2 to the display controller 26. The display controller 26 controls the operation of the display panel 27 based on the image data of the entire image P1, the image data of the partial image P2, and the data regarding the position of the partial image P2, which are supplied from the processor 24. The display panel 27 displays an image under the control of the display controller 26.

[0046] The acceleration sensor 22 detects movements such as the orientation of the head-mounted display 20. The eye-tracking sensor 23 detects the orientation of the eyes of a user wearing the head-mounted display 20. The processor 24 supplies the detection results of the acceleration sensor 22 and the eye-tracking sensor 23 to the transmission circuit 25. The transmission circuit 25 transmits a detection signal SD including the detection results of the acceleration sensor 22 and the eye-tracking sensor 23 supplied from the processor 24 to the image generation device 10.

[0047] (Detailed Operation) The head mounted display 20 generates a display image P20 based on the image data DT1 and image data DT2 supplied in a time-division manner.

[0048] 7 shows an example of a display operation in the head mounted display 20. The head mounted display 20 alternately receives image data DT1 representing an entire image P1 and image data DT2 representing a partial image P2.

[0049] When the head-mounted display 20 receives the image data DT1, the display controller 26 controls the pixels PIX on the display panel 27 to be driven in units of four pixels PIX, based on the image data of the entire image P1 included in the image data DT1. As a result, the display panel 27 displays a display image P21 including the low-resolution entire image P1.

[0050] When the head-mounted display 20 receives the image data DT2, the display controller 26 controls the plurality of pixels PIX on the display panel 27, which are arranged in an area corresponding to the partial image P2, to be driven on a pixel-by-pixel basis, based on the image data of the partial image P2 included in the image data DT2 and data on the position of the partial image P2. At this time, the plurality of pixels PIX on the display panel 27 in an area other than the area corresponding to the partial image P2 maintain their display. As a result, the display panel 27 displays a display image P22 including the high-resolution partial image P2.

[0051] The head mounted display 20 repeats such an operation when the image data DT1 is received and an operation when the image data DT2 is received.

[0052] Figure 8 shows a more detailed example of the display operation in the head-mounted display 20, where (A) shows the waveform of the synchronization signal Vsync, (B) shows the input image, (C) shows the operation of the display panel 27, and (D) shows the display image displayed on the display panel 27.

[0053] The pair of the entire image P1 and the partial image P2 is supplied at a period T. In this example, the period T is, for example, 8.3 msec (= 1 / 120 Hz). The entire image P1 and the partial image P2 are each supplied at a period Ts. The period Ts is, for example, 4.2 msec (= 1 / 240 Hz).

[0054] At timing t11, a pulse of the synchronization signal Vsync is generated (FIG. 8(A)). During the period from timing t11 to t12, the receiving circuit 21 of the head-mounted display 20 receives image data DT1 representing the entire image P1 (FIG. 8(B)). Since the input image is the entire image P1, the display controller 26 controls the plurality of pixels PIX on the display panel 27 to be driven in units of four pixels PIX, based on the image data of this entire image P1.

[0055] 9 shows the operation of driving pixels PIX. In the display panel 27, the scanning circuit 33 scans multiple pixels PIX by using two pixel lines L as a scanning unit US. The pixel signal generation circuit 32 also applies the same pixel signal to two adjacent signal lines SGL. As a result, the same pixel signal is written to four pixels PIX in the two selected pixel lines L. In this way, the display panel 27 drives multiple pixels PIX by using four pixels PIX as a unit UD.

[0056] As shown by the bold lines in Fig. 8(C), in this example, the scanning circuit 33 sequentially scans two pixel lines L as a scanning unit from the bottom to the top of the pixel array 31. This allows the operating frequency to be halved, and power consumption to be reduced, compared to, for example, sequential scanning performed using one pixel line L as a scanning unit. Furthermore, as shown by the shaded area in Fig. 8(C), in this example, the pixel PIX to which a pixel signal has been written emits light for a predetermined period after the pixel signal has been written. In this way, the display panel 27 displays the display image P21 (Fig. 8(D)).

[0057] Next, at timing t12, a pulse of the synchronization signal Vsync is generated (FIG. 8(A)). During the period from timing t12 to t13, the receiving circuit 21 of the head-mounted display 20 receives image data DT2 representing the partial image P2 (FIG. 8(B)). Because the input image is the partial image P2, the display controller 26 controls, based on the image data of this partial image P2 and data regarding the position of this partial image P2, the plurality of pixels PIX of the display panel 27 that are arranged in an area corresponding to the partial image P2, so as to drive each pixel PIX as a unit.

[0058] 10 shows the operation of driving pixels PIX. In the display panel 27, the scanning circuit 33 scans multiple pixels PIX using one pixel line L as a scanning unit US. The pixel signal generation circuit 32 applies multiple pixel signals to multiple signal lines SGL, among the multiple signal lines SGL, that correspond to the region corresponding to the partial image P2. As a result, in the selected pixel line L, multiple pixel signals are written to multiple pixels PIX that correspond to the region corresponding to the partial image P2. On the other hand, pixel signals are not written to multiple pixels PIX that correspond to regions other than the region corresponding to the partial image P2. In this way, the display panel 27 drives multiple pixels PIX using one pixel PIX as a unit UD.

[0059] As shown by the bold line in FIG. 8C , the scanning circuit 33 sequentially scans a region of the pixel array 31 corresponding to the partial image P2, with one pixel line L as the scanning unit US. Unlike the period from timing t11 to t12, during this period, sequential scanning is performed with one pixel line L as the scanning unit US, so the scanning speed is half the scanning speed during the period from timing t11 to t12. This allows the operating frequency to be halved, and power consumption to be reduced, compared to, for example, sequential scanning from the bottom to the top of the display panel 27. Furthermore, as shown by the shaded area in FIG. 8C , in this example, the pixels PIX in the pixel line L to which the pixel PIX to which the pixel signal is written belongs emit light for a predetermined period after the pixel signal is written. Furthermore, pixels PIX in a pixel line L near the bottom, to which no pixel signal has been written, emit light for the same period as pixels PIX to which pixel signals have been written first, and pixels PIX in a pixel line L near the top, to which no pixel signal has been written, emit light for the same period as pixels PIX to which pixel signals have been written last. In this way, the display panel 27 displays a display image P22 (FIG. 8(D)). Of this display image P22, the image in the region other than partial region R2 is written between times t11 and t12, and the image in partial region R2 is written between times t12 and t13.

[0060] In this manner, during the period from timing t11 to timing t13, the head-mounted display 20 displays an image based on the pair of the entire image P1 and the partial image P2 included in the image data DT1 and DT2. The head-mounted display 20 first displays a display image P21 based on the entire image P1, and then displays a display image P22 by re-displaying an image of the region of the display image P21 corresponding to the partial image P2 based on the partial image P2. The user grasps the entire image by observing the display image P21, and grasps the details of the image in the partial region R2 by observing the display image P22. From the perspective of latency, the timing at which the user grasps the entire image is important. In this case, the latency of the head-mounted display 20 is, for example, the time Δt from timing t11, when the input of the image data DT1 begins, to when the pixel PIX located at the center in the vertical direction of the display panel 27 begins to emit light. In this example, this time Δt is approximately half the time corresponding to the period Ts. Specifically, for example, when the period Ts is 4.2 msec (= 1 / 240 Hz), the time Δt can be set to about 2 msec.

[0061] The display system 1 thereafter repeats the operations from timing tt to t13. For example, during the period from timing t13 to t14, the receiving circuit 21 of the head-mounted display 20 receives image data DT1 representing the entire image P1 (FIG. 8B). Based on this image data DT1, the head-mounted display 20 displays a display image P21, similar to the operation during the period from timing t11 to t12 (FIGS. 8C and 8D). Furthermore, during the period from timing t14 to t15, the receiving circuit 21 of the head-mounted display 20 receives image data DT2 representing the partial image P2 (FIG. 8B). Based on this image data DT2, the head-mounted display 20 displays a display image P22, similar to the operation during the period from timing t12 to t13 (FIGS. 8C and 8D).

[0062] Fig. 11 shows another example of the display operation in the head mounted display 20. In this example, the light emitting operation shown by the shaded area in Fig. 11(C) is different from the example in Fig. 8. That is, in the example in Fig. 8, the display panel 27 emits light in accordance with the timing of line sequential scanning, but in this example, the pixels PIX in the entire area emit light at the same timing.

[0063] For example, during the period from timing t21 to timing t22, the receiving circuit 21 of the head mounted display 20 receives image data DT1 representing an entire image P1 (FIG. 11B). Since the input image is the entire image P1, the display controller 26 controls the plurality of pixels PIX on the display panel 27 to be driven in units of four pixels PIX, based on the image data of this entire image P1.

[0064] In this example, the scanning circuit 33 sequentially scans two pixel lines L as a scanning unit US from the bottom to the top of the pixel array 31 ( FIG. 11(C) ). Then, as indicated by the hatched area in FIG. 11(C) , when pixel signals are written to all pixels PIX in the display panel 27, the pixels PIX emit light at the same timing for a predetermined period of time. In this way, the display panel 27 displays a display image P21 ( FIG. 11(D) ).

[0065] For example, during the period from timing t22 to t23, the receiving circuit 21 of the head mounted display 20 receives image data DT2 representing the partial image P2 (FIG. 11B). Since the input image is the partial image P2, the display controller 26 controls, based on the image data of the partial image P2 and data on the position of the partial image P2, the plurality of pixels PIX arranged in an area corresponding to the partial image P2 among the plurality of pixels PIX on the display panel 27, so as to drive each pixel PIX as a unit.

[0066] The scanning circuit 33 sequentially scans the pixels PIX in the region corresponding to the partial image P2, using one pixel line L as the scanning unit US (FIG. 11C). Then, as indicated by the hatched area in FIG. 11C, after pixel signals have been written to all the pixels PIX in the display panel 27, the pixels PIX emit light at the same timing for a predetermined period of time. In this way, the display panel 27 displays the display image P22 (FIG. 11D).

[0067] In this way, during the period from timing t21 to t23, the head-mounted display 20 displays an image based on the pair of the entire image P1 and the partial image P2 included in the image data DT1 and DT2. In this case, the latency of the head-mounted display 20 is, for example, the time Δt from timing t11, when the input of the image data DT1 begins, to the time when half of the display panel 27 is scanned. In this example, this time Δt is approximately the same as the time corresponding to the period Ts. Specifically, for example, when the period Ts is 4.2 msec (= 1 / 240 Hz), the time Δt can be approximately 4 msec.

[0068] In this manner, the display system 1 receives first image data (image data DT1) representing a low-resolution overall image P1 and second image data (image data DT2) representing a high-resolution partial image P2 corresponding to a portion of the overall image P1. Then, a first drive is performed in which the plurality of pixels PIX are driven in units of four pixels PIX based on the first image data (image data DT1), and a second drive is performed in which two or more pixels among the plurality of pixels PIX that are provided in a region corresponding to the partial image P2 are driven in units of one pixel PIX based on the second image data (image data DT2). As a result, the display system 1 first displays a display image P21 based on the overall image P1, and then displays a display image P22 by re-displaying the image of the region of the display image P21 that corresponds to the partial image P2 based on the partial image P2. The user can grasp the overall image by observing the display image P21, and the details of the image in the partial region R2 by observing the display image P22. This reduces the time Δt from when the input of image data DT1 starts until the pixel PIX at the center in the vertical direction of the display panel 27 starts to emit light, thereby reducing latency, and as a result, the image quality of the display system 1 can be improved.

[0069] Furthermore, the display system 1 performs a second drive in which two or more pixels provided in an area corresponding to the partial image P2 among the plurality of pixels PIX are driven on a pixel-by-pixel basis based on the second image data (image data DT2). This allows the display system 1 to display, for example, the portion that the user is looking at with high resolution, thereby improving image quality.

[0070] Furthermore, the display system 1 receives first image data (image data DT1) representing a low-resolution entire image P1 and second image data (image data DT2) representing a high-resolution partial image P2 corresponding to a portion of the entire image P1. As a result, as shown in FIG. 4B , the display system 1 can reduce the amount of image data DT1 and DT2 compared to the amount of image data for the high-resolution entire image. As a result, the display system 1 can reduce the transmission bandwidth required for transmitting the image signal SP from the image generating device 10 to the head-mounted display 20.

[0071] Furthermore, since the transmission band can be reduced in this way in the display system 1, the image data DT1 and the image data DT2 can be transmitted in a short time. As a result, the frame rate can be increased in the display system 1, and the image quality can be improved.

[0072] Furthermore, the display system 1 performs a first drive in which the plurality of pixels PIX are driven in units of four pixels PIX based on first image data (image data DT1), and a second drive in which two or more pixels provided in an area corresponding to the partial image P2 among the plurality of pixels PIX are driven in units of one pixel PIX based on second image data (image data DT2). As a result, the display system 1 does not necessarily require a frame memory, unlike a case in which the entire image P1 and the partial image P2 are combined in advance and the combined image is displayed. In this way, if a frame memory is not provided, for example, the circuit configuration can be simplified, and costs can be reduced, for example.

[0073] [Effects] As described above, in this embodiment, first image data representing a low-resolution overall image and second image data representing a high-resolution partial image corresponding to a part of the overall image are received. Then, a first drive is performed in which a plurality of pixels are driven in units of four pixels based on the first image data, and a second drive is performed in which two or more pixels provided in an area corresponding to the partial image among the plurality of pixels are driven in units of one pixel based on the second image data. This can improve image quality.

[0074] In this embodiment, a second drive is performed based on the second image data to drive two or more pixels among the multiple pixels that are arranged in an area corresponding to a partial image, one pixel at a time, thereby improving image quality.

[0075] In this embodiment, first image data representing a low-resolution overall image and second image data representing a high-resolution partial image corresponding to a portion of the overall image are received, thereby improving image quality.

[0076] [Modification 1] In the above embodiment, the image generation circuit 11 generates the partial image P2 based on the detection result of the eye tracking sensor 23, but this is not limited to this. This modification will be described in detail below.

[0077] 12 shows an example of the configuration of a display system 1A. The display system 1A includes an image generation device 10A and a head-mounted display 20A.

[0078] The image generating device 10A includes an image generating circuit 11A. The image generating circuit 11A generates an entire image P1 that shows a scene in a virtual space according to the orientation of the head-mounted display 20, based on the detection result of the acceleration sensor 22 included in the data supplied from the receiving circuit 13. The image generating circuit 11A also generates a partial image P2 that includes a portion of the entire image P1 where the image changes.

[0079] 13 shows an example of an entire image P1. In this example, an image of a person 9 is moving within the entire image P1. The image generation circuit 11A determines a partial region R2 that includes a changing image based on the entire image P1. The image generation circuit 11A then generates a partial image P2 related to the partial region R2. That is, since the user is likely to look at the changing portion of the displayed image, the image generation circuit 11A generates a partial image P2 for the changing portion. The image generation circuit 11A then supplies the generated image data of the entire image P1, image data of the partial image P2, and data regarding the position of the partial image P2 within the entire image P1 to the transmission circuit 12.

[0080] The head-mounted display 20A ( FIG. 12 ) includes a receiving circuit 21, an acceleration sensor 22, a processor 24A, a transmitting circuit 25, a display controller 26, and a display panel 27. That is, the head-mounted display 20A according to this modification is the head-mounted display 20 ( FIG. 1 ) according to the above-described embodiment, except that the eye tracking sensor 23 is omitted and the processor 24 is replaced with a processor 24A. The processor 24A performs predetermined image processing based on, for example, the image data DT1 and DT2 supplied from the receiving circuit 21, and supplies the image data of the entire image P1 included in the image data DT1, the image data of the partial image P2 included in the image data DT2, and data regarding the position of the partial image P2 included in the image data DT2 to the display controller 26. The processor 24A also supplies the detection results of the acceleration sensor 22 to the transmitting circuit 25 and causes the transmitting circuit 25 to transmit these detection results.

[0081] [Variation 2] In the above embodiment, an image generated by the image generation circuit 11 is displayed, but this is not limiting. For example, as in the display system 1B shown in Fig. 14, an image captured by an image sensor 28B may also be displayed to achieve so-called video see-through. This display system 1B includes a head-mounted display 20B. The head-mounted display 20B includes an image sensor 28B and a processor 24B.

[0082] The image sensor 28B is configured to capture an image in front of the user wearing the head-mounted display 20B, for example. The processor 24B performs predetermined image processing based on the image data DT1 and DT2 supplied from the receiving circuit 21 and the captured image generated by the image sensor 28B, and supplies the image data of the entire image, image data of the partial images, and data on the positions of the partial images to the display controller 26.

[0083] [Variation 3] In the above embodiment, when displaying the entire image P1, the plurality of pixels PIX on the display panel 27 are driven in units of four pixels PIX, but this is not limited to this. Instead, various numbers of pixels PIX can be driven in units, as shown in Figures 15 and 16. For example, two pixels PIX (2 x 1) arranged side by side in the horizontal direction can be driven as a unit, or eight pixels PIX (4 x 2) including four pixels PIX in the horizontal direction and two pixels PIX in the vertical direction can be driven as a unit, or 32 pixels PIX (8 x 4) including eight pixels PIX in the horizontal direction and four pixels PIX in the vertical direction can be driven as a unit. Alternatively, for example, two (1 × 2) pixels PIX arranged side by side in the vertical direction may be driven as a unit, or eight (2 × 4) pixels PIX including two pixels PIX in the horizontal direction and four pixels PIX in the vertical direction may be driven as a unit, or 32 (4 × 8) pixels PIX including four pixels PIX in the horizontal direction and eight pixels PIX in the vertical direction may be driven as a unit, or four (2 × 2) pixels PIX including two pixels PIX in the horizontal direction and two pixels PIX in the vertical direction may be driven as a unit, or 16 (4 × 4) pixels PIX including four pixels PIX in the horizontal direction and four pixels PIX in the vertical direction may be driven as a unit, or 64 (8 × 8) pixels PIX including eight pixels PIX in the horizontal direction and eight pixels PIX in the vertical direction may be driven as a unit. In this example, even-numbered pixels PIX are driven as a unit, but this is not limiting, and for example, odd-numbered pixels PIX may be driven as a unit.

[0084] In this way, by driving a plurality of pixels PIX as a unit, it is possible to reduce the transmission bandwidth. That is, if the bandwidth utilization rate when driving one pixel PIX as a unit is taken as 100%, for example, when driving four (2×2) pixels PIX as a unit as in the above embodiment, the number of pixels in the entire image P1 is reduced to 1 / 4, so the bandwidth utilization rate is 25%. Furthermore, for example, when driving 16 (4×4) pixels PIX as a unit, the number of pixels in the entire image P1 is reduced to 1 / 16, so the bandwidth utilization rate is 6.25%.

[0085] The user can grasp the overall image by observing display image P21, and can grasp the details of the image in partial region R2 on which the user is gazing by observing display image P22. In this way, because the user is not gazing at the overall image P1, the user is unlikely to notice a degradation in image quality even when multiple pixels PIX are driven as a unit. Therefore, in the display system according to this modification, by appropriately setting the number of pixels PIX, which are the drive units, it is possible to reduce the transmission bandwidth while suppressing degradation in image quality.

[0086] [Variation 4] In the above embodiment, the horizontal pixel count ratio of partial image P2 is set to 50% and the vertical pixel count ratio of partial image P2 is set to 50% as shown in Fig. 4B, but this is not limited to this. Instead, the horizontal pixel count ratio and the vertical pixel count ratio of partial image P2 can be set to various values.

[0087] For example, as shown in FIGS. 17 and 18, taking into consideration that the human visual field is wide in the horizontal direction, the ratio of the number of horizontal pixels in the partial image P2 may be made larger than the ratio of the number of vertical pixels.

[0088] Figures 19 to 21 show an example where the horizontal pixel count ratio of partial image P2 is 100% and the vertical pixel count ratio is 50%, where Figure 19 shows the entire image P1 and partial image P2, Figure 20 shows a schematic representation of the image data of the entire image P1 and partial image P2, and Figure 21 shows an example of display operation.

[0089] 20, the number of horizontal pixels of partial image P2 is 100% of the number of horizontal pixels of the high-resolution entire image, and the number of vertical pixels of partial image P2 is 50% of the number of vertical pixels of the high-resolution entire image. On the other hand, the number of vertical pixels of entire image P1 is the same as in the above embodiment (FIG. 4B).

[0090] As shown in Figure 21, during the period from timing t31 to t32, the receiving circuit 21 of the head-mounted display 20 receives image data DT1 indicating an entire image P1 as shown in Figure 20 (Figure 21(B)). Based on this image data DT1, the head-mounted display 20 displays a display image P21 (Figures 21(C) and 21(D)), similar to the above-described embodiment (Figures 8 and 9). Furthermore, during the period from timing t32 to t33, the receiving circuit 21 receives image data DT2 indicating a partial image P2 as shown in Figure 20 (Figure 21(B)). Based on this image data DT2, the head-mounted display 20 displays a display image P22 (Figures 21(C) and 21(D)), similar to the above-described embodiment (Figures 8 and 10).

[0091] As shown in Fig. 21, in the display system, image data DT1 representing entire image P1 is transmitted during the period from timing t31 to t32, and image data DT2 representing partial image P2 is transmitted during the period from timing t32 to t33. As shown in Fig. 20, the amount of image data for partial image P2 is greater than the amount of image data for entire image P1, so the transmission bandwidth is determined by the image data DT2 representing partial image P2. Therefore, when the horizontal pixel count ratio of partial image P2 is 100% and the vertical pixel count ratio is 50%, the bandwidth usage rate is 100%, as shown in Fig. 18.

[0092] Figures 22 to 24 show an example where the horizontal pixel count ratio of partial image P2 is 75% and the vertical pixel count ratio is 50%, Figure 19 shows the entire image P1 and partial image P2, Figure 20 shows a schematic representation of the image data of the entire image P1 and partial image P2, and Figure 21 shows an example of display operation.

[0093] 23, the number of horizontal pixels of partial image P2 is 75% of the number of horizontal pixels of the high-resolution entire image, and the number of vertical pixels of partial image P2 is 50% of the number of vertical pixels of the high-resolution entire image. On the other hand, the number of vertical pixels of entire image P1 is the same as in the above embodiment (FIG. 4B).

[0094] As shown in Figure 24, during the period from timing t41 to t42, the receiving circuit 21 of the head-mounted display 20 receives image data DT1 indicating the entire image P1 as shown in Figure 23 (Figure 24(B)). Based on this image data DT1, the head-mounted display 20 displays a display image P21 as in the above-described embodiment (Figures 8 and 9) (Figures 24(C) and (D)). Furthermore, during the period from timing t42 to t43, the receiving circuit 21 receives image data DT2 indicating the partial image P2 as shown in Figure 23 (Figure 24(B)). Based on this image data DT2, the head-mounted display 20 displays a display image P22 as in the above-described embodiment (Figures 8 and 10) (Figures 24(C) and (D)).

[0095] In this example, as shown in Figure 23, the amount of image data for partial image P2 is greater than the amount of image data for entire image P1, so the transmission bandwidth is determined by the image data DT2 representing partial image P2. Therefore, if the horizontal pixel count ratio of partial image P2 is 75% and the vertical pixel count ratio is 50%, the bandwidth usage rate is 75%, as shown in Figure 18. In this example, the transmission bandwidth can be reduced.

[0096] In the above example, the ratio of the number of horizontal pixels in the partial image P2 is set to be larger than the ratio of the number of vertical pixels, but this is not limitative. Instead, for example, the ratio of the number of vertical pixels in the partial image P2 may be set to be larger than the ratio of the number of horizontal pixels.

[0097] Also, for example, as shown in FIGS. 25 and 26, the horizontal and vertical pixel number ratios of partial image P2 may be changed while keeping the horizontal and vertical pixel number ratios the same.

[0098] 19 to 21, there is excess transmission bandwidth during the period from timing t31 to t32. By effectively utilizing the excess transmission bandwidth during the period from timing t31 to t32, it is possible to increase the resolution of the entire image P1, as will be described below.

[0099] Figures 27 to 29 show examples of increasing the resolution of the overall image P1 when the horizontal pixel count ratio of the partial image P2 is 100% and the vertical pixel count ratio is 50%, where Figure 27 schematically shows the image data of the overall image P1 and the partial image P2, Figure 28 shows an example of the display operation, and Figure 29 shows the operation of driving pixel PIX.

[0100] 27, the number of pixels in the horizontal direction (number of horizontal pixels) of the entire image P1 is 100% of the number of horizontal pixels of the high-resolution entire image, and the number of pixels in the vertical direction (number of vertical pixels) of the entire image P1 is 50% of the number of vertical pixels of the high-resolution entire image. In this example, the horizontal resolution of the entire image P1 is doubled compared to the example in FIG.

[0101] As shown in Fig. 28, during the period from timing t51 to timing t52, the receiving circuit 21 of the head mounted display 20 receives image data DT1 indicating the entire image P1 as shown in Fig. 27 (Fig. 28(B)). Since the input image is the entire image P1, the display controller 26 controls the plurality of pixels PIX on the display panel 27 to be driven in units of two pixels PIX, based on the image data of this entire image P1.

[0102] 29 , in the display panel 27, the scanning circuit 33 scans a plurality of pixels PIX by using two pixel lines L as a scanning unit US. The pixel signal generation circuit 32 applies a plurality of pixel signals to a plurality of signal lines SGL, respectively. As a result, the same pixel signal is written to two pixels PIX in the two selected pixel lines L. In this way, the display panel 27 drives a plurality of pixels PIX by using two pixels PIX as a unit UD.

[0103] As shown by the bold lines in Fig. 28(C), the scanning circuit 33 sequentially scans two pixel lines L as a scanning unit from the bottom to the top of the pixel array 31 in this example. Then, as shown by the shaded area in Fig. 28(C), the pixels PIX to which pixel signals have been written emit light for a predetermined period after the pixel signals have been written in this example. In this way, the display panel 27 displays the display image P21 (Fig. 28(D)).

[0104] During the period from timing t52 to timing t53, the receiving circuit 21 receives image data DT2 indicating the partial image P2 as shown in Fig. 27 (Fig. 28(B)). Based on this image data DT2, the head mounted display 20 displays the display image P22 (Figs. 28(C) and (D)), similar to the above embodiment (Figs. 8 and 10).

[0105] [Variation 5] In the above embodiment, image data DT1 representing the entire image P1 and image data DT2 representing the partial image P2 are alternately transmitted. However, this is not limiting. For example, as shown in FIG. 30 , the image data to be transmitted may be changed based on the detection results of the acceleration sensor 22 and the eye tracking sensor 23. In this display system 1, image data DT1 representing the entire image P1 and image data DT2 representing the partial image P2 are essentially alternately transmitted. In this example, during the period T motion, the user significantly changes the orientation of their head. The acceleration sensor 22 detects movements such as the orientation of the head-mounted display 20. The transmission circuit 25 of the head-mounted display 20 then transmits a detection signal SD including the detection results of the acceleration sensor 22 to the image generation device 10. The reception circuit 13 of the image generation device 10 receives this detection signal SD, and the image generation circuit 11 continues to repeatedly generate the entire image P1 during the period T motion in which the orientation of the head-mounted display 20 continues to change based on the detection results of the acceleration sensor 22. The transmission circuit 12 generates image data DT1 representing the entire image P1 based on the image data of the entire image P1 and transmits an image signal SP including the image data DT1. That is, the transmission circuit 12 of the image generating device 10 continues to repeatedly transmit the image data DT1 representing the entire image P1 during the period Tmotion. The reception circuit 21 of the head-mounted display 20 receives this image data DT1. The head-mounted display 20 then displays a display image P21 including the entire image P1 based on the image data DT1. That is, the head-mounted display 20 continues to repeatedly display the display image P21 including the entire image P1 during the period Tmotion. When the user stops turning their head, the period Tmotion ends, and the display system 1 alternately transmits the image data DT1 representing the entire image P1 and the image data DT2 representing the partial image P2. This allows the user to view the display image P21 including the entire image P1 in accordance with their head movement with short latency when they move their head, thereby reducing the risk of the user feeling motion sickness.

[0106] In this example, the display system 1 repeatedly transmits the image data DT1 representing the entire image P1 when the user significantly changes the direction of their head, but this is not limited to this. Instead, for example, the image data DT1 representing the entire image P1 may be repeatedly transmitted when the user significantly changes the portion of the displayed image that they are viewing. In this case, the display system 1 repeatedly transmits the image data DT1 representing the entire image P1 based on the detection results of the eye tracking sensor 23.

[0107] [Variation 6] In the above embodiment, one image data DT1 and one image data DT2 are transmitted alternately, but this is not limited to this. For example, one image data DT1 and multiple image data DT2 may be transmitted alternately. Furthermore, the number of multiple image data DT2 may be changeable. Below, an example in which one image data DT1 and three image data DT2 are transmitted alternately will be described in detail.

[0108] 31 shows an example of the display operation of the head mounted display 20 according to this modification, where (A) shows the waveform of the synchronization signal Vsync, (B) shows an input image, (C) shows the operation of the display panel 27, and (D) shows a display image displayed on the display panel 27. The entire image P1 and the partial image P2 are each supplied at a period Ts. The period Ts is, for example, 4.2 msec (= 1 / 240 Hz).

[0109] During the period from timing t61 to t62, the receiving circuit 21 of the head-mounted display 20 receives image data DT1 representing the entire image P1 (FIG. 31(B)). Based on this image data DT1, the head-mounted display 20 displays a display image P21 (FIGS. 31(C) and 31(D)), similar to the above-described embodiment (FIGS. 8 and 9). Furthermore, during the period from timing t62 to t63, the receiving circuit 21 receives image data DT2 representing the partial image P2 (FIG. 31(B)). Based on this image data DT2, the head-mounted display 20 displays a display image P22 (FIGS. 31(C) and 31(D)), similar to the above-described embodiment (FIGS. 8 and 10). Furthermore, during the period from timing t63 to t64, the receiving circuit 21 receives image data DT2 representing the partial image P2 (FIG. 31(B)). Based on this image data DT2, the head-mounted display 20 displays the display image P22 (FIGS. 31(C) and (D)), similar to the above-described embodiment (FIGS. 8 and 10). During the period from timing t64 to t65, the receiving circuit 21 receives image data DT2 representing the partial image P2 (FIG. 31(B)). Based on this image data DT2, the head-mounted display 20 displays the display image P22 (FIGS. 31(C) and (D)), similar to the above-described embodiment (FIGS. 8 and 10).

[0110] 32 shows another example of the display operation of the head mounted display 20 according to this modification. In this example, similar to the example of FIG. 11, the pixels PIX in the entire area of ​​the display panel 27 emit light at the same timing.

[0111] In this modification, the frequency of generating the partial image P2 is higher than in the above embodiment in which the entire image P1 and the partial image P2 are generated alternately. When generating the partial image P2, the image generation circuit 11 does not need to perform rendering processing on the image outside the partial image P2. Therefore, in this modification, power consumption can be further reduced. Furthermore, when, for example, three partial images P2 are to be the same image, the image generation circuit 11 can reduce the number of times the partial image P2 is generated, thereby reducing power consumption.

[0112] [Variation 7] In the above embodiment, two sub-frames (full image P1 and partial image P2) are provided, but this is not limiting, and instead, three or more sub-frames may be provided. An example in which three sub-frames are provided will be described in detail below.

[0113] The image generation circuit 11 according to this modification generates an entire image P1 showing a scene in the virtual space corresponding to the orientation of the head-mounted display 20, based on the detection result of the acceleration sensor 22 included in the data supplied from the receiving circuit 13. Furthermore, the image generation circuit 11 generates partial images P2 and P3 showing portions of the scene in the virtual space corresponding to the orientation of the head-mounted display 20 that the user is looking at, based on the detection result of the eye-tracking sensor 23 included in the data supplied from the receiving circuit 13.

[0114] FIG. 33 shows an example of a display image P20 displayed on the head-mounted display 20. Based on the detection results of the eye tracking sensor 23 included in the data supplied from the receiving circuit 13, the image generation circuit 11 determines partial regions R2 and R3 of the entire region R1 of the display image P20, which include the portion of the image the user is looking at. In this example, the horizontal size (horizontal direction in FIG. 33 ) of the partial region R2 is half the horizontal size of the entire region R1, and the vertical size (vertical direction in FIG. 33 ) of the partial region R2 is half the vertical size of the entire region R1. That is, the area of ​​the partial region R2 is ¼ the area of ​​the entire region R1. Also, in this example, the horizontal size of the partial region R3 is half the horizontal size of the partial region R2, and the vertical size of the partial region R3 is half the vertical size of the partial region R2. That is, the area of ​​the partial region R3 is ¼ the area of ​​the partial region R2. In this example, the center position of the partial region R3 is the same as the center position of the partial region R2.

[0115] FIG. 34 shows an example of an entire image P1 and partial images P2 and P3 generated by the image generation circuit 11. The entire image P1 is a low-resolution image of the entire region R1 ( FIG. 33 ). The partial image P2 is a medium-resolution image of the partial region R2. The partial image P3 is a high-resolution image of the partial region R3. In this example, each pixel in the entire image P1 corresponds to 16 pixels PIX in the head-mounted display 20, each pixel in the partial image P2 corresponds to four pixels PIX in the head-mounted display 20, and each pixel in the partial image P3 corresponds to one pixel PIX in the head-mounted display 20. In this example, the number of pixels in the entire image P1, the number of pixels in the partial image P2, and the number of pixels in the partial image P3 are all equal.

[0116] Fig. 35 is a schematic representation of image data for an entire image P1 and partial images P2 and P3. The image data shown as a whole in Fig. 35 represents high-resolution image data for an entire image that can be used when writing a plurality of pixel values ​​to a plurality of pixels PIX in the head-mounted display 20.

[0117] The number of pixels in the horizontal direction (number of horizontal pixels) of the entire image P1 is 25% of the number of horizontal pixels of the high-resolution entire image shown in Fig. 35, and the number of pixels in the vertical direction (number of vertical pixels) of the entire image P1 is 25% of the number of vertical pixels of the high-resolution entire image. In other words, the horizontal pixel count ratio of the entire image P1 is 25%, and the vertical pixel count ratio of the entire image P1 is 25%.

[0118] The number of pixels in the horizontal direction (number of horizontal pixels) of partial image P2 is 25% of the number of horizontal pixels of the entire high-resolution image, and the number of pixels in the vertical direction (number of vertical pixels) of partial image P2 is 25% of the number of vertical pixels of the entire high-resolution image. In other words, the horizontal pixel count ratio of partial image P2 is 25%, and the vertical pixel count ratio of partial image P2 is 25%.

[0119] The number of pixels in the horizontal direction (number of horizontal pixels) of partial image P3 is 25% of the number of horizontal pixels of the entire high-resolution image, and the number of pixels in the vertical direction (number of vertical pixels) of partial image P3 is 25% of the number of vertical pixels of the entire high-resolution image. In other words, the horizontal pixel count ratio of partial image P3 is 25%, and the vertical pixel count ratio of partial image P3 is 25%.

[0120] In this example, the horizontal pixel count ratio of the entire image P1 and the partial images P2 and P3 is equal to each other, and the vertical pixel count ratio of the entire image P1 and the partial images P2 and P3 is equal to each other. Furthermore, the total data volume of the entire image P1 and the partial images P2 and P3 is 3 / 16 of the data volume of the high-resolution entire image.

[0121] 36 shows an example of a display operation in the head mounted display 20 according to this modification. The head mounted display 20 cyclically receives image data DT1 indicating an entire image P1, image data DT2 indicating a partial image P2, and image data DT3 indicating a partial image P3 in this order.

[0122] When the head-mounted display 20 receives the image data DT1, the display controller 26 controls the pixels PIX on the display panel 27 to be driven in units of 16 pixels PIX, based on the image data of the entire image P1 included in the image data DT1. As a result, the display panel 27 displays a display image P21 including the low-resolution entire image P1.

[0123] When the head-mounted display 20 receives the image data DT2, the display controller 26 controls the plurality of pixels PIX on the display panel 27, which are arranged in an area corresponding to the partial image P2, to be driven in units of four pixels PIX, based on the image data of the partial image P2 included in the image data DT2 and data on the position of the partial image P2. At this time, the plurality of pixels PIX on the display panel 27 in an area other than the area corresponding to the partial image P2 maintain their display. As a result, the display panel 27 displays a display image P22 including the medium-resolution partial image P2.

[0124] When the head-mounted display 20 receives the image data DT3, the display controller 26 controls the pixels PIX on the display panel 27, which are arranged in an area corresponding to the partial image P3, to be driven on a pixel-by-pixel basis, based on the image data of the partial image P3 included in the image data DT3 and data on the position of the partial image P3. At this time, the pixels PIX on the display panel 27 in an area other than the area corresponding to the partial image P3 maintain their display. As a result, the display panel 27 displays a display image P23 including the low-resolution partial image P2.

[0125] FIG. 37 shows an example of a more detailed display operation in the head mounted display 20.

[0126] During the period from timing t71 to timing t72, the receiving circuit 21 of the head mounted display 20 receives image data DT1 representing the entire image P1 (FIG. 37(B)). Since the input image is the entire image P1, the display controller 26 controls the plurality of pixels PIX on the display panel 27 to be driven in units of 16 pixels PIX, based on the image data of this entire image P1.

[0127] In the display panel 27, the scanning circuit 33 scans a plurality of pixels PIX in units of four pixel lines L. The pixel signal generation circuit 32 applies the same pixel signal to the four signal lines SGL. As a result, the same pixel signal is written to 16 pixels PIX in the selected four pixel lines L. In this way, the display panel 27 drives a plurality of pixels PIX in units of 16 pixels PIX.

[0128] As shown by the thick lines in Fig. 37(C), the scanning circuit 33 sequentially scans eight pixel lines L as a scanning unit from the bottom to the top of the pixel array 31 in this example. Then, as shown by the hatched area in Fig. 37(C), when pixel signals have been written to all pixels PIX in the display panel 27, the multiple pixels PIX emit light at the same timing for a predetermined period. In this way, the display panel 27 displays the display image P21 (Fig. 37(D)).

[0129] Next, during the period from timing t72 to timing t73, the receiving circuit 21 of the head mounted display 20 receives image data DT2 representing the partial image P2 (FIG. 37B). Since the input image is the partial image P2, the display controller 26 controls, based on the image data of the partial image P2 and data on the position of the partial image P2, the plurality of pixels PIX arranged in an area corresponding to the partial image P2, among the plurality of pixels PIX on the display panel 27, so as to drive in units of four pixels PIX.

[0130] In the display panel 27, the scanning circuit 33 scans the plurality of pixels PIX in units of two pixel lines L. The pixel signal generation circuit 32 applies the same pixel signal to two of the plurality of signal lines SGL that are associated with the region corresponding to the partial image P2. As a result, the same pixel signal is written to four pixels PIX in the two selected pixel lines L. In this way, the display panel 27 drives the plurality of pixels PIX in units of four pixels PIX.

[0131] As shown by the thick lines in Fig. 37(C), the scanning circuit 33 sequentially scans two pixel lines L as a scanning unit in the region of the pixel array 31 corresponding to the partial image P2. Then, as shown by the hatched area in Fig. 37(C), when pixel signals have been written to all of the pixels PIX in the display panel 27, the pixels PIX emit light at the same timing for a predetermined period. In this way, the display panel 27 displays the display image P22 (Fig. 37(D)).

[0132] Next, during the period from timing t73 to timing t74, the receiving circuit 21 of the head mounted display 20 receives image data DT3 representing partial image P2 (FIG. 37B). Since the input image is partial image P3, the display controller 26 controls, based on the image data of partial image P3 and data on the position of partial image P3, a plurality of pixels PIX arranged in an area corresponding to partial image P2, among a plurality of pixels PIX on the display panel 27, to be driven on a pixel-by-pixel basis.

[0133] In the display panel 27, the scanning circuit 33 scans the pixels PIX by using one pixel line L as a scanning unit. The pixel signal generation circuit 32 applies pixel signals to the signal lines SGL that correspond to the region of the partial image P3. In this way, the display panel 27 drives the pixels PIX by using one pixel PIX as a unit.

[0134] As shown by the thick line in Fig. 37(C), the scanning circuit 33 sequentially scans one pixel line L as a scanning unit in the region of the pixel array 31 corresponding to the partial image P3. Then, as shown by the hatched area in Fig. 37(C), when pixel signals have been written to all pixels PIX in the display panel 27, the multiple pixels PIX emit light at the same timing for a predetermined period. In this way, the display panel 27 displays the display image P23 (Fig. 37(D)).

[0135] FIG. 38 shows the bandwidth utilization rates in the display system 1 according to the above embodiment and the display system 1 according to this modification. When the number of subframes is two, as in the above embodiment, the total data volume of the entire image P1 and the partial images P2 is 50% of the data volume of the high-resolution entire image, as shown in FIG. 4B , resulting in a bandwidth utilization rate of 50%. On the other hand, when the number of subframes is three, as in this modification, the total data volume of the entire image P1 and the partial images P2 and P3 is 3 / 16 of the data volume of the high-resolution entire image, as shown in FIG. 35 , resulting in a bandwidth utilization rate of 19%. In this way, this modification can reduce the bandwidth utilization rate. Furthermore, the operating frequency can be reduced, thereby reducing power consumption.

[0136] [Variation 8] In the above embodiment, the image data of the entire image P1 and the image data of the partial image P2 are transmitted without compression, but this is not limited to this, and for example, the image data may be compressed. A display system 1C according to this variation will be described in detail below.

[0137] 39 shows an example of the configuration of a display system 1C. The display system 1C includes an image generating device 10C and a head-mounted display 20C.

[0138] The image generating device 10C includes an image generating circuit 11C. The image generating circuit 11C includes an image compression circuit 19C. The image compression circuit 19C is configured to compress, for example, one or both of the entire image P1 and the partial image P2. The image compression circuit 19C can set whether or not to perform compression on a subframe basis. Furthermore, if compression is performed, the image compression circuit 19C can set the compression rate on a subframe basis. For example, if MIPI is used for communication, VESA (Video Electronics Standards Association)-DSC (Display Stream Compression) in MIPI can be used.

[0139] The head mounted display 20C includes a processor 24C. The processor 24C includes an image restoration circuit 29C. The image restoration circuit 29C is configured to restore the image compressed by the image compression circuit 19C.

[0140] For example, as shown in FIG. 20 , if the horizontal pixel ratio of partial image P2 is 100% and the vertical pixel ratio is 50%, the data volume of partial image P2 is larger than the data volume of entire image P1. In this case, waste of transmission bandwidth occurs. Therefore, in the display system 1C, the image compression circuit 19C compresses partial image P2, thereby reducing the data volume of image data of partial image P2 compared to the case of FIG. 20 , as shown in FIG. 40 . In FIG. 40 , the shaded area indicates a compressed image. In this example, the image compression circuit 19C compresses partial image P2 at a compression rate of 50%. As a result, the transmission bandwidth can be reduced. The compressed partial image P2 is restored by the image restoration circuit 29C. The head-mounted display 20C displays an image based on the restored partial image P2 in the same manner as in FIG. 21 .

[0141] [Variation 8] In the above embodiment, the head-mounted display 20C is provided with the acceleration sensor 22 and the eye tracking sensor 23. However, this is not limiting. For example, these sensors may not be provided as shown in a display system 1D illustrated in FIG. 41 . This display system 1D includes an image generation device 10D and a head-mounted display 20D. The image generation device 10D includes an image generation circuit 11D. The image generation circuit 11D generates an entire image P1 to be displayed on the head-mounted display 20D. The image generation circuit 11D also generates a partial image P2 that includes a portion of the entire image P1 where the image changes. The head-mounted display 20D includes a processor 24D. The processor 24D performs predetermined image processing based on, for example, the image data DT1 and DT2 supplied from the receiving circuit 21, and supplies the image data of the entire image P1 included in the image data DT1, the image data of the partial image P2 included in the image data DT2, and data regarding the position of the partial image P2 included in the image data DT2 to the display controller 26.

[0142] [Modification 9] The above embodiment can be applied to various color systems, as shown in FIGS. 42A to 42C.

[0143] For example, as shown in case C1 ( FIG. 42A ), the present invention may be applied to an RGB system. In this example, the red image (R), green image (G), and blue image (B) of the entire image P1 are low-resolution images. Based on these images, the display panel 27 performs a display drive operation for the entire image P1, with four pixels PIX arranged in two rows and two columns as a unit. Furthermore, the red image (R), green image (G), and blue image (B) of the partial image P2 are high-resolution images. Based on these images, the display panel 27 performs a display drive operation for the partial image P2, with one pixel PIX as a unit. In this case, the bandwidth utilization rate is 50%, as in the case of the above embodiment ( FIG. 4 ).

[0144] Also, for example, as shown in cases C2 to C5, it may be applied to a YUV system using a luminance signal and color difference signals.

[0145] For example, in the example shown in Case C2 ( FIG. 42A ), the luminance image (Y), the first chrominance image (U), and the second chrominance image (V) of the entire image P1 are low-resolution images. Based on these images, the display controller 26 generates low-resolution red, green, and blue images (R, G, and B). The display panel 27 performs a display drive operation for the entire image P1, with each image consisting of four pixels PIX arranged in two rows and two columns, based on the generated images. The luminance image (Y), the first chrominance image (U), and the second chrominance image (V) of the partial image P2 are high-resolution images. Based on these images, the display controller 26 generates high-resolution red, green, and blue images (R, G, and B). The display panel 27 performs a display drive operation for the partial image P2, with each pixel PIX as a unit, based on the generated images. The bandwidth utilization rate in this case is 50%, as in the case of the above embodiment ( FIG. 4 ).

[0146] For example, in the example shown in Case C3 ( FIG. 42B ), the luminance image (Y), the first color-difference image (U), and the second color-difference image (V) of the entire image P1 are low-resolution images. The display controller 26 generates low-resolution red, green, and blue images (R, G, and B) based on these images. The display panel 27 performs a display drive operation for the entire image P1, with each unit consisting of four pixels PIX arranged in two rows and two columns, based on the generated images. The luminance image (Y) of the partial image P2 is a high-resolution image, while the first and second color-difference images (U, V) are low-resolution images. That is, because human visual sensitivity to luminance is high but human visual sensitivity to color differences is low, the luminance image has a high resolution, and the color-difference images have a low resolution. The display controller 26 generates high-resolution red (R), green (G), and blue (B) images based on these images, and the display panel 27 performs a display drive operation for the partial image P2 on a pixel-by-pixel basis based on the generated images. In this case, the bandwidth utilization rate is 37.5%.

[0147] For example, in the example shown in Case C4 ( FIG. 42B ), the luminance image (Y) of the entire image P1 is a low-resolution image, and the first and second chrominance images (U) and (V) are images with even lower resolution. In this example, the pixels of the first and second chrominance images (U) and (V) correspond to eight (4×2) pixels PIX. The display controller 26 generates low-resolution red, green, and blue images (R, G, and B) based on these images, and the display panel 27 performs display drive operations for the entire image P1, with each unit consisting of four pixels PIX arranged in two rows and two columns, based on the generated images. Furthermore, the luminance image (Y) of the partial image P2 is a high-resolution image, and the first and second chrominance images (U) and (V) are medium-resolution images. In this example, the pixels of the first and second chrominance images (U) and (V) correspond to two (2×1) pixels PIX. The display controller 26 generates high-resolution red (R), green (G), and blue (B) images based on these images, and the display panel 27 performs a display drive operation for the partial image P2 on a pixel-by-pixel basis based on the generated images. In this case, the bandwidth utilization rate is 33.3%.

[0148] For example, in the example shown in case C5 ( FIG. 42C ), the luminance image (Y) of the entire image P1 is a low-resolution image, and the first and second chrominance images (U) and (V) are images with even lower resolution. In this example, the pixels of the first and second chrominance images (U) and (V) correspond to 16 (4×4) pixels PIX. The display controller 26 generates low-resolution red, green, and blue images (R, G, and B) based on these images, and the display panel 27 performs display drive operations for the entire image P1 in units of four pixels PIX arranged in two rows and two columns based on the generated images. Furthermore, the luminance image (Y) of the partial image P2 is a high-resolution image, and the first and second chrominance images (U) and (V) are low-resolution images. The display controller 26 generates a high-resolution red image (R), green image (G), and blue image (B) based on these images, and the display panel 27 performs a display drive operation for the partial image P2 in units of one pixel PIX based on the generated images. In this case, the bandwidth utilization rate is 25%.

[0149] [Modification 10] In the above embodiment, the display panel 27 shown in Fig. 6 is used, but the present invention is not limited to this. A display panel 27E according to this modification will be described in detail below.

[0150] 43 shows an example of the configuration of a display panel 27E. The display panel 27E has a pixel array 31E, a pixel signal generating circuit 32, a scanning circuit 33, and a driving circuit 34E.

[0151] The pixel array 31E has a plurality of signal lines SGL, a plurality of control lines CTL, a plurality of control lines WSEN, and a plurality of pixels PIX. The plurality of control lines WSEN extend in the vertical direction (the longitudinal direction in FIG. 43 ) and are arranged in parallel in the horizontal direction (the lateral direction in FIG. 43 ). Each of the plurality of control lines WSEN supplies a control signal generated by the drive circuit 34E to the pixel PIX.

[0152] The drive circuit 34E is configured to generate a control signal and apply the generated control signal to a plurality of control lines WSEN, thereby controlling which of the plurality of pixels PIX the pixel signal generated by the pixel signal generation circuit 32 is to be written to.

[0153] FIG. 44 shows an example configuration of a pixel PIX. A pixel array including this pixel PIX has a control line WSL. The control line CTL shown in FIG. 43 includes this control line WSL. The pixel PIX has transistors MN01 to MN03, a capacitor C01, and a light-emitting element EL. Transistors MN01 to MN03 are N-type metal oxide semiconductor field effect transistors (MOSFETs). The gate of transistor MN01 is connected to a control line WSEN, the drain is connected to a signal line SGL, and the source is connected to the drain of transistor MN02. The gate of transistor MN02 is connected to the control line WSL, the drain is connected to the source of transistor MN01, and the source is connected to the gate of transistor MN03 and capacitor C01. One end of capacitor C01 is connected to the source of transistor MN02 and the gate of transistor MN03, and the other end is connected to the source of transistor MN03 and the anode of light-emitting element EL. The gate of the transistor MN03 is connected to the source of the transistor MN02 and one end of the capacitor C01, the drain is connected to the power supply line VCCP, and the source is connected to the other end of the capacitor C01 and the anode of the light-emitting element EL. The light-emitting element EL is, for example, an organic EL light-emitting element, and has an anode connected to the source of the transistor MN03 and the other end of the capacitor C01 and a cathode connected to the power supply line Vcath.

[0154] With this configuration, in pixel PIX, transistors MN01 and MN02 are turned on, and the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. Transistor MN03 passes a current corresponding to the voltage across capacitor C01 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, pixel PIX emits light at a brightness corresponding to the pixel signal.

[0155] As shown in FIG. 8, during the period from timing t11 to t12, the receiving circuit 21 of the head-mounted display 20 receives image data DT1 representing an entire image P1 (FIG. 8(B)). Because the input image is the entire image P1, the display controller 26 controls the driving of the multiple pixels PIX in the display panel 27E in units of four pixels PIX based on the image data of this entire image P1. As shown in FIG. 9, during these periods from timing t11 to t12, the scanning circuit 33 of the display panel 27E scans the multiple pixels PIX using two pixel lines L as a scanning unit US. The driving circuit 34E activates (high level) all control lines WSEN. The pixel signal generating circuit 32 applies the same pixel signal to two adjacent signal lines SGL. As a result, the same pixel signal is written to four pixels PIX in the two selected pixel lines L. In this way, the display panel 27E drives a plurality of pixels PIX, with four pixels PIX serving as a unit UD.

[0156] Also, as shown in FIG. 8 , during the period from timing t12 to t13, the receiving circuit 21 of the head-mounted display 20 receives image data DT2 representing partial image P2 ( FIG. 8(B) ). Because the input image is partial image P2, the display controller 26 controls, based on the image data of partial image P2 and data regarding the position of partial image P2, the pixels PIX of the display panel 27E, arranged in an area corresponding to partial image P2, to be driven on a pixel-by-pixel basis. As shown in FIG. 10 , during the period from timing t12 to t13, the scanning circuit 33 of the display panel 27E scans the pixels PIX, using one pixel line L as the scanning unit US. The driving circuit 34E activates (high-level) the control lines WSEN associated with the area corresponding to partial image P2 and inactivates (low-level) the other control lines WSEN. The pixel signal generation circuit 32 applies a plurality of pixel signals to a plurality of signal lines SGL among the plurality of signal lines SGL that correspond to the region corresponding to the partial image P2. As a result, in a selected pixel line L, a plurality of pixel signals are written to a plurality of pixels PIX that correspond to the region corresponding to the partial image P2. On the other hand, no pixel signals are written to a plurality of pixels PIX that correspond to regions other than the region corresponding to the partial image P2. In this way, the display panel 27E drives a plurality of pixels PIX, each pixel PIX acting as a unit UD.

[0157] The configuration of the pixel PIX is not limited to the example shown in Fig. 44. Several examples will be described below.

[0158] FIG. 45 shows another example of the configuration of pixel PIX. A pixel array including this pixel PIX has control lines WSL, DSL, and AZSL. The control line CTL shown in FIG. 43 includes these control lines WSL, DSL, and AZSL. This pixel PIX has transistors MP11 and MP12, capacitors C11 and C12, transistors MP13 to MP15, and a light-emitting element EL. Transistors MP11 to MP15 are P-type MOSFETs. The gate of transistor MP11 is connected to control line WSEN, its source is connected to signal line SGL, and its drain is connected to the source of transistor MP12. The gate of transistor MP12 is connected to control line WSL, its source is connected to the drain of transistor MP11, and its drain is connected to the gate of transistor MP14 and capacitor C12. One end of capacitor C11 is connected to the power supply line VCCP, and the other end is connected to capacitor C12, the drain of transistor MP13, and the source of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, the source is connected to the power supply line VCCP, and the drain is connected to the source of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the drain of transistor MP12 and the other end of capacitor C12, the source is connected to the drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the drain is connected to the anode of the light-emitting element EL and the source of transistor MP15. The gate of the transistor MP15 is connected to the control line AZSL, the source is connected to the drain of the transistor MP14 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS.

[0159] With this configuration, in pixel PIX, transistors MP11 and MP12 are turned on, and the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal on control line DSL. While transistor MP13 is on, transistor MP14 passes a current corresponding to the voltage across capacitor C12 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal on control line AZSL. While transistor MP15 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0160] FIG. 46 shows another example of the configuration of pixel PIX. A pixel array including this pixel PIX has control lines WSL, DSL, and AZSL. The control line CTL shown in FIG. 43 includes these control lines WSL, DSL, and AZSL. This pixel PIX has transistors MN21 and MN22, a capacitor C21, transistors MN23 to MN25, and a light-emitting element EL. Transistors MN21 to MN25 are N-type MOSFETs. The gate of transistor MN21 is connected to control line WSEN, its drain is connected to signal line SGL, and its source is connected to the drain of transistor MN22. The gate of transistor MN22 is connected to control line WSL, its drain is connected to the source of transistor MN21, and its source is connected to the gate of transistor MN24 and capacitor C21. One end of capacitor C21 is connected to the source of transistor MN22 and the gate of transistor MN24, and the other end is connected to the source of transistor MN24, the drain of transistor MN25, and the anode of light-emitting element EL. Transistor MN23 has a gate connected to control line DSL, a drain connected to power supply line VCCP, and a source connected to the drain of transistor MN24. Transistor MN24 has a gate connected to the source of transistor MN22 and one end of capacitor C21, a drain connected to the source of transistor MN23, and a source connected to the other end of capacitor C21, the drain of transistor MN25, and the anode of light-emitting element EL. Transistor MN25 has a gate connected to control line AZSL, a drain connected to the source of transistor MN24, the other end of capacitor C21, and the anode of light-emitting element EL, and a source connected to power supply line VSS.

[0161] With this configuration, in pixel PIX, transistors MN21 and MN22 are turned on, and the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal on control line DSL. While transistor MN23 is on, transistor MN24 passes a current corresponding to the voltage across capacitor C21 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal on control line AZSL. While transistor MN25 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0162] FIG. 47 shows another example of the configuration of pixel PIX. A pixel array including this pixel PIX has control lines WSL, DSL, AZSL1, and AZSL2. The control line CTL shown in FIG. 43 includes these control lines WSL, DSL, AZSL1, and AZSL2. This pixel PIX has transistors MP31 and MP32, a capacitor C31, transistors MP33 to MP36, and a light-emitting element EL. Transistors MP31 to MP36 are P-type MOSFETs. The gate of transistor MP31 is connected to control line WSEN, its source is connected to signal line SGL, and its drain is connected to the source of transistor MP32. The gate of transistor MP32 is connected to control line WSL, its source is connected to the drain of transistor MP31, and its drain is connected to the gate of transistor MP33, the source of transistor MP34, and capacitor C31. One end of capacitor C31 is connected to the power supply line VCCP, and the other end is connected to the drain of transistor MP32, the gate of transistor MP33, and the source of transistor MP34. The gate of transistor MP34 is connected to control line AZSL1, the source is connected to the drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31, and the drain is connected to the drain of transistor MP33 and the source of transistor MP35. The gate of transistor MP35 is connected to control line DSL, the source is connected to the drains of transistors MP33 and MP34, and the drain is connected to the source of transistor MP36 and the anode of the light-emitting element EL. The gate of transistor MP36 is connected to control line AZSL2, the source is connected to the drain of transistor MP35 and the anode of the light-emitting element EL, and the drain is connected to power supply line VSS.

[0163] With this configuration, in pixel PIX, transistors MP31 and MP32 are turned on, and the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned on and off based on the signal on control line DSL. While transistor MP35 is on, transistor MP33 passes a current corresponding to the voltage across capacitor C31 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP34 is turned on and off based on the signal on control line AZSL1. While transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned on and off based on the signal on control line AZSL2. While transistor MP36 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0164] FIG. 48 shows another example of the configuration of pixel PIX. A pixel array including this pixel PIX includes control lines WSL1 and WSL2, a control line DSL, control lines AZSL1 and AZSL2, signal lines SGL1 and SGL2, capacitors C48 and C49, and a transistor MP49. The control line CTL shown in FIG. 43 includes control lines WSL1, WSL2, DSL, AZSL1, and AZSL2. The signal line SGL shown in FIG. 43 includes signal lines SGL1 and SGL2. One end of capacitor C48 is connected to signal line SGL1, and the other end is connected to power supply line VSS. One end of capacitor C49 is connected to signal line SGL1, and the other end is connected to signal line SGL2. The transistor MP49 is a P-type MOSFET, with its gate connected to the control line WSL2, its source connected to the signal line SGL1, and its drain connected to the signal line SGL2.

[0165] The pixel PIX includes transistors MP41 and MP42, a capacitor C41, transistors MP43 to MP46, and a light-emitting element EL. Transistors MP41 to MP46 are P-type MOSFETs. The gate of transistor MP41 is connected to a control line WSEN, its source is connected to a signal line SGL2, and its drain is connected to the source of transistor MP42. The gate of transistor MP42 is connected to a control line WSL1, its source is connected to the drain of transistor MP41, and its drain is connected to the gate of transistor MP43 and capacitor C41. One end of capacitor C41 is connected to a power supply line VCCP, and the other end is connected to the drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the drain of transistor MP42 and the other end of capacitor C41, its source is connected to the power supply line VCCP, and its drain is connected to the sources of transistors MP44 and MP45. The gate of transistor MP44 is connected to control line AZSL1, its source is connected to the drain of transistor MP43 and the source of transistor MP45, and its drain is connected to signal line SGL2. The gate of transistor MP45 is connected to control line DSL, its source is connected to the drain of transistor MP43 and the source of transistor MP44, and its drain is connected to the source of transistor MP46 and the anode of light-emitting element EL. The gate of transistor MP46 is connected to control line AZSL2, its source is connected to the drain of transistor MP45 and the anode of light-emitting element EL, and its drain is connected to power supply line VSS.

[0166] With this configuration, in pixel PIX, when transistors MP41 and MP42 are turned on, the voltage across capacitor C41 is set based on the pixel signal supplied from signal line SGL1 via capacitor C49. Transistor MP45 is turned on and off based on the signal on control line DSL. While transistor MP45 is on, transistor MP43 passes a current corresponding to the voltage across capacitor C41 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP43. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP44 is turned on and off based on the signal on control line AZSL1. While transistor MP44 is on, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is turned on and off based on the signal on control line AZSL2. While transistor MP46 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0167] FIG. 49 shows another example of the configuration of pixel PIX. A pixel array including this pixel PIX has control lines WSL, DSL, AZSL1, and AZSL2. The control line CTL shown in FIG. 43 includes these control lines WSL, DSL, AZSL1, and AZSL2. This pixel PIX has transistors MP51 to MP54, a capacitor C51, transistors MP55 to MP60, and a light-emitting element EL. Transistors MP51 to MP60 are P-type MOSFETs. The gate of transistor MP51 is connected to control line WSEN, the source is connected to signal line SGL, and the drain is connected to the source of transistor MP52. The gate of transistor MP52 is connected to control line WSL, the source is connected to the drain of transistor MP51, and the drain is connected to the drain of transistor MP53 and the source of transistor MP54. The gate of transistor MP53 is connected to the control line DSL, its source is connected to the power supply line VCCP, and its drain is connected to the drain of transistor MP52 and the source of transistor MP54. The gate of transistor MP54 is connected to the source of transistor MP55, the drain of transistor MP57, and capacitor C51, its source is connected to the drains of transistors MP52 and MP53, and its drain is connected to the sources of transistors MP58 and MP59. One end of capacitor C51 is connected to the power supply line VCCP, and the other end is connected to the gate of transistor MP54, the source of transistor MP55, and the drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel. The gate of transistor MP55 is connected to the control line AZSL1, its source is connected to the gate of transistor MP54, the drain of transistor MP57, and the other end of capacitor C51, and its drain is connected to the source of transistor MP56. The gate of the transistor MP56 is connected to the control line AZSL1, the source is connected to the drain of the transistor MP55, and the drain is connected to the power supply line VSS.The gate of transistor MP57 is connected to the control line WSL, the drain is connected to the gate of transistor MP54, the source of transistor MP55, and the other end of capacitor C51, and the source is connected to the drain of transistor MP58. The gate of transistor MP58 is connected to the control line WSL, the drain is connected to the drain of transistor MP57, and the source is connected to the drain of transistor MP54 and the source of transistor MP59. The gate of transistor MP59 is connected to the control line DSL, the source is connected to the drain of transistor MP54 and the source of transistor MP58, and the drain is connected to the source of transistor MP60 and the anode of the light-emitting element EL. The gate of transistor MP60 is connected to the control line AZSL2, the source is connected to the drain of transistor MP59 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS.

[0168] With this configuration, in pixel PIX, transistors MP51, MP52, MP54, MP58, and MP57 are turned on, and the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on and off based on the signal on control line DSL. While transistors MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal on control line AZSL1. While transistors MP55 and MP56 are on, the gate voltage of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal on control line AZSL2. During the period in which the transistor MP60 is in the on state, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0169] Fig. 50 shows another example of the configuration of a pixel PIX. A pixel array having this pixel PIX has control lines WSENN and WSENP, control lines WSNL and WSPL, control line AZL, and control line DSL. The control line WSEN shown in Fig. 43 includes control lines WSENN and WSENP. The control line CTL shown in Fig. 43 includes control lines WSNL, WSPL, AZL, and DSL. The signal on the control line WSENN and the signal on the control line WSENP are mutually inverted signals. The signal on the control line WSNL and the signal on the control line WSPL are mutually inverted signals.

[0170] Pixel PIX includes transistors MN61, MP62, MN63, and MP64, capacitors C61 and C62, transistors MN65 to MN67, and a light-emitting element EL. Transistors MN61, MN63, and MN65 to MN67 are N-type MOSFETs, and transistors MP62 and MP64 are P-type MOSFETs. The gate of transistor MN61 is connected to a control line WSENN, the drain is connected to a signal line SGL and the source of transistor MP62, and the source is connected to the drain of transistor MP62, the drain of transistor MN63, and the source of transistor MP64. The gate of transistor MP62 is connected to a control line WSENP, the source is connected to a signal line SGL and the drain of transistor MN61, and the drain is connected to the source of transistor MN61, the drain of transistor MN63, and the source of transistor MP64. The gate of transistor MN63 is connected to control line WSNL, its drain is connected to the source of transistor MN61, the drain of transistor MP62, and the source of transistor MP64, its source is connected to the drain of transistor MP64, capacitors C61 and C62, and the gate of transistor MN65. The gate of transistor MP64 is connected to control line WSPL, its source is connected to the source of transistor MN61, the drain of transistor MP62, and the drain of transistor MN63, and its drain is connected to the source of transistor MN63, capacitors C61 and C62, and the gate of transistor MN65. Capacitor C61 is configured using, for example, a metal oxide metal (MOM) capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, capacitor C62, and the gate of transistor MN65, and the other end connected to power supply line VSS2. Note that capacitor C61 may also be configured using, for example, a metal oxide metal (MOS) capacitor or a metal insulator metal (MIM) capacitor. The capacitor C62 is configured using, for example, a MOS capacitor, and has one end connected to the source of the transistor MN63, the drain of the transistor MP64, one end of the capacitor C61, and the gate of the transistor MN65, and the other end connected to the power supply line VSS2.The capacitor C62 may be configured using, for example, a MOM capacitor or an MIM capacitor. The gate of transistor MN65 is connected to the source of transistor MN63, the drain of transistor MP64, and one end of capacitors C61 and C62, the drain is connected to the power supply line VCCP, and the source is connected to the drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to control line AZL, the drain is connected to the source of transistor MN65 and the drain of transistor MN67, and the source is connected to power supply line VSS1. The gate of transistor MN67 is connected to control line DSL, the drain is connected to the source of transistor MN65 and the drain of transistor MN66, and the source is connected to the anode of the light-emitting element EL.

[0171] With this configuration, in pixel PIX, at least one of transistors MN61 and MP62 is turned on, and at least one of transistors MN63 and MP64 is turned on. This sets the voltage across capacitors C61 and C62 based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal on control line DSL. While transistor MN67 is on, transistor MN65 passes a current corresponding to the voltage across capacitors C61 and C62 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal on control line AZL. Transistor MN66 may also function as a resistor element having a resistance value corresponding to the signal on control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0172] [Other Modifications] Two or more of these modifications may be combined.

[0173] 2. Application Examples Next, application examples of the display systems described in the above embodiments and modifications will be described.

[0174] 51 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0175] (Application Example 2) FIG. 52 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a display image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

[0176] The head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0177] (Application Example 3) Figures 53A and 53B show an example of the appearance of a digital still camera 130, with Figure 53A showing a front view and Figure 53B showing a rear view. This digital still camera 130 is a single-lens reflex camera with interchangeable lenses and includes a camera body 131, a photographing lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 132 is an interchangeable lens unit and is provided near the center of the front of the camera body 311. The grip 133 is provided on the left side of the front of the camera body 311, and is held by the photographer. The monitor 134 is provided to the left of the center of the back of the camera body 131. The electronic viewfinder 135 is provided above the monitor 134 on the back of the camera body 131. By looking through this electronic viewfinder 135, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 132 and determine the composition. The techniques according to the above-described embodiments and the like can be applied to the electronic viewfinder 135.

[0178] 54 shows an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

[0179] 55 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept operation inputs from a user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

[0180] (Application Example 6) Figures 56A and 56B show an example configuration of a vehicle to which the technology of the present disclosure is applied, where Figure 56A shows an example of the interior of the vehicle as seen from the rear of vehicle 200, and Figure 56B shows an example of the interior of the vehicle as seen from the left rear of vehicle 200.

[0181] The vehicle in Figures 56A and 56B has a center display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 106.

[0182] The center display 201 is disposed on the dashboard 261 in a position facing the driver's seat 262 and the passenger's seat 263. While FIG. 56A illustrates an example of a horizontally elongated center display 201 extending from the driver's seat 262 side to the passenger's seat 263 side, the screen size and location of the center display 201 are not limited to this. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display an image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a ToF sensor, and the body temperature of an occupant detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0183] The safety-related information includes information based on sensor detection results, such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger is abandoned. The operation-related information includes gesture information related to passenger operations detected by sensors. The gestures may include operations of various vehicle equipment, such as air conditioning, navigation, audiovisual (AV) equipment, and lighting. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior. By acquiring and storing the life log, it is possible to determine the condition of the passengers at the time of an accident. The health-related information includes the passenger's body temperature detected using a temperature sensor and information on the passenger's health condition estimated based on the detected body temperature. Alternatively, the passenger's health condition information may be estimated based on the passenger's face captured by an image sensor. Furthermore, the passenger's health condition information may be estimated based on the passenger's responses obtained through an automated voice conversation with the passenger. The authentication / identification-related information includes information on a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes information on AV device operations by occupants detected by the sensor, and information on content to be displayed that is appropriate for the occupants detected and recognized by the sensor.

[0184] The console display 202 can be used to display, for example, life log information. The console display 202 is disposed near a shift lever 265 on a center console 264 between a driver's seat 262 and a passenger seat 263. The console display 202 can also display information detected by various sensors. The console display 202 may also display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0185] The head-up display 203 is virtually displayed behind a windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Since the head-up display 203 is often virtually disposed in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as the vehicle speed, the remaining fuel level, and the remaining battery level.

[0186] The digital rearview mirror 204 can not only display the rear of the vehicle, but also display the state of passengers in the rear seats, and can therefore be used to display life log information of passengers in the rear seats, for example.

[0187] The steering wheel display 205 is disposed near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0188] The rear entertainment display 206 is attached to the back side of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. The rear entertainment display 206 may display, for example, information related to the operation of an AV device or an air conditioning system, or may display the results of measurements of the body temperature of the rear seat passengers by the temperature sensor 5.

[0189] The techniques according to the above-described embodiments can be applied to the center display 201, console display 202, head-up display 203, digital rearview mirror 204, steering wheel display 205, and rear entertainment display 206.

[0190] The present technology has been described above by giving embodiments and modifications thereof, as well as examples of application to electronic devices. However, the present technology is not limited to these embodiments and can be modified in various ways.

[0191] In the above-described embodiments, the present technology is applied to a head-mounted display, but is not limited to this and can be applied to various electronic devices capable of displaying images, such as monitors and projectors.

[0192] The present technology can be applied not only to the closed systems shown in the above embodiments, but also to video see-through systems and mixed reality systems.

[0193] This technology can also be applied to various simulators such as flight simulators, gaming, projection mapping, and other applications.

[0194] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0195] The present technology can be configured as follows: According to the present technology configured as follows, it is possible to improve image quality.

[0196] (1) A display device comprising: a receiving circuit capable of receiving first image data representing an entire image at a first resolution and second image data representing a first partial image at a second resolution higher than the first resolution, the first image corresponding to a part of the entire image; a display unit having a plurality of pixels; and a display drive circuit capable of performing a first drive for driving the plurality of pixels in units of a first number of pixels based on the first image data, and a second drive for driving two or more pixels of the plurality of pixels provided in an area corresponding to the first partial image in units of a second number of pixels that is smaller than the first number, based on the second image data. (2) The display device according to (1), wherein the receiving circuit is capable of receiving the second image data after receiving the first image data, and the display drive circuit is capable of performing the second drive after performing the first drive. (3) The display device according to (1) or (2), further comprising: a first sensor capable of detecting which portion of the display area of ​​the display unit the user is observing; and a transmission circuit capable of transmitting the detection result of the first sensor to an image generating device capable of generating the first image data and the second image data, wherein the first partial image is an image corresponding to the detection result of the first sensor. (4) The display device according to (1) or (2), wherein the receiving circuit is capable of receiving a plurality of the second image data, and the plurality of first partial images represented by the plurality of second image data are different from one another. (5) The display device according to any of (1) to (4), wherein the receiving circuit is capable of alternately receiving the first image data and one or more of the second image data. (6) The display device according to any of (1) to (4), wherein the receiving circuit is capable of alternately receiving the first image data and the second image data during a first period, and is capable of successively receiving the first image data of the first image data and the second image data during a second period.(7) The display device according to (6), further comprising: a second sensor capable of detecting a change in the attitude of the display device; and a transmission circuit capable of transmitting the detection result of the second sensor to an image generating device capable of generating the first image data and the second image data, wherein the second period corresponds to a period during which the attitude of the display device is changing. (8) The display device according to any of (1) to (7), wherein the second number is 1. (9) The display device according to any of (1) to (7), wherein the receiving circuit is further capable of receiving third image data indicating a second partial image having a third resolution higher than the second resolution, corresponding to a part of the first partial image, and the display drive circuit is capable of performing third driving, based on the third image data, to drive two or more pixels provided in an area of ​​the plurality of images corresponding to the second partial image, in units of a third number of pixels less than the second number. (10) The display device according to any of (1) to (9), wherein the data amount of the first image data and the data amount of the second image data are equal to each other. (11) The display device according to any one of (1) to (10), further comprising a restoration circuit capable of restoring compressed image data of the first image data and the second image data, wherein at least one of the first image data and the second image data is compressed. (12) The display device according to any one of (1) to (10), further comprising a restoration circuit capable of restoring compressed image data of the first image data and the second image data, wherein both the first image data and the second image data are compressed, and the compression rate of the first image data and the compression rate of the second image data are different from each other.(13) A display system comprising: an image generating device capable of transmitting first image data representing an entire image at a first resolution and second image data representing a first partial image at a second resolution higher than the first resolution, which corresponds to a part of the entire image; and a display device, wherein the display device has: a receiving circuit capable of receiving the first image data and the second image data; a display unit having a plurality of pixels; and a display drive circuit capable of performing a first drive that drives the plurality of pixels in units of a first number of pixels based on the first image data, and a second drive that drives, based on the second image data, two or more pixels of the plurality of pixels that are provided in an area corresponding to the first partial image in units of a second number of pixels that is smaller than the first number. (14) The display system according to (13), wherein the display device further comprises a first sensor capable of detecting which portion of the display area of ​​the display unit the user is observing, and a transmission circuit capable of transmitting a detection result of the first sensor to the image generation device, wherein the image generation device is capable of receiving the detection result of the first sensor transmitted from the transmission circuit, is capable of generating the first partial image based on the detection result of the first sensor, and is capable of generating the second image data representing the first partial image. (15) The display system according to (13), wherein the image generation device is capable of generating the first partial image by detecting a portion of the entire image where the image changes, and is capable of generating the second image data representing the first partial image. (16) The display system according to any one of (13) to (15), wherein the display device further comprises a second sensor capable of detecting a change in the attitude of the display device, and a transmission circuit capable of transmitting the detection result of the second sensor to the image generation device, and the image generation device is capable of receiving the detection result of the second sensor transmitted from the transmission circuit and determining whether to transmit the first image data or the second image data based on the detection result of the second sensor.(17) A display driving method including: transmitting first image data showing an entire image at a first resolution, and second image data showing a first partial image at a second resolution higher than the first resolution, which corresponds to a part of the entire image; receiving the first image data and the second image data; performing a first drive based on the first image data to drive a plurality of pixels in units of a first number of pixels; and performing a second drive based on the second image data to drive two or more pixels of the plurality of pixels that are provided in an area corresponding to the first partial image in units of a second number of pixels that is smaller than the first number.

[0197] This application claims priority based on Japanese Patent Application No. 2021-093716, filed on June 3, 2021, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0198] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. a receiving circuit capable of receiving first image data representing an entire image with a first resolution and second image data representing a first partial image with a second resolution higher than the first resolution, the first partial image corresponding to a part of the entire image; A display unit having a plurality of pixels; a display drive circuit capable of performing a first drive of driving the plurality of pixels in units of a first number of pixels based on the first image data, and a second drive of driving two or more pixels provided in a region corresponding to the first partial image among the plurality of pixels in units of a second number of pixels less than the first number based on the second image data; A display device comprising:

2. the receiving circuit is capable of receiving the second image data after receiving the first image data; The display drive circuit is capable of performing the second drive after performing the first drive. The display device according to claim 1 .

3. The display device includes a first sensor capable of detecting which part of a display area of ​​the display unit a user is observing; a transmission circuit capable of transmitting a detection result of the first sensor to an image generating device capable of generating the first image data and the second image data; Further equipped with The first partial image is an image according to a detection result of the first sensor. The display device according to claim 1 .

4. the receiving circuit is capable of receiving a plurality of the second image data; The first partial images represented by the second image data are different from each other. The display device according to claim 1 .

5. The receiving circuit is capable of alternately receiving the first image data and one or more pieces of the second image data. The display device according to claim 1 .

6. The receiving circuit is capable of alternately receiving the first image data and the second image data during a first period, and is capable of successively receiving the first image data of the first image data and the second image data during a second period. The display device according to claim 1 .

7. the display device includes a second sensor capable of detecting a change in the attitude of the display device; a transmission circuit capable of transmitting the first image data and the second image data to an image generating device capable of generating the first image data and the second image data based on a detection result of the second sensor; In addition, The second period corresponds to a period during which the attitude of the display device is changing. The display device according to claim 6.

8. The second number is 1. The display device according to claim 1 .

9. the receiving circuit is further operable to receive third image data indicating a second partial image having a third resolution higher than the second resolution and corresponding to a portion of the first partial image; The display drive circuit is capable of performing a third drive of driving two or more pixels provided in an area corresponding to the second partial image among the plurality of pixels, with a third number of pixels being smaller than the second number as a unit, based on the third image data. The display device according to claim 1 .

10. The data amount of the first image data and the data amount of the second image data are equal to each other. The display device according to claim 1 .

11. a decompression circuit capable of decompressing compressed image data out of the first image data and the second image data, At least one of the first image data and the second image data is compressed. The display device according to claim 1 .

12. a decompression circuit capable of decompressing compressed image data out of the first image data and the second image data, The first image data and the second image data are both compressed, and the compression ratio of the first image data and the compression ratio of the second image data are different from each other. The display device according to claim 1 .

13. an image generating device capable of transmitting first image data representing an entire image with a first resolution and second image data representing a first partial image with a second resolution higher than the first resolution, the first partial image corresponding to a part of the entire image; Display device and Equipped with The display device includes: a receiving circuit capable of receiving the first image data and the second image data; A display unit having a plurality of pixels; a display drive circuit capable of performing a first drive of driving the plurality of pixels in units of a first number of pixels based on the first image data, and a second drive of driving two or more pixels provided in a region corresponding to the first partial image among the plurality of pixels in units of a second number of pixels less than the first number based on the second image data; have Display system.

14. The display device includes a first sensor capable of detecting which part of a display area of ​​the display unit a user is observing; a transmission circuit capable of transmitting a detection result of the first sensor to the image generating device; and The image generating device is capable of receiving a detection result of the first sensor transmitted from the transmission circuit, capable of generating the first partial image based on the detection result of the first sensor, and capable of generating the second image data representing the first partial image.

14. The display system of claim 13.

15. The image generating device is capable of generating the first partial image by detecting a portion of the entire image where an image changes, and is capable of generating the second image data representing the first partial image.

14. The display system of claim 13.

16. the display device includes a second sensor capable of detecting a change in the attitude of the display device; a transmission circuit capable of transmitting a detection result of the second sensor to the image generating device; Furthermore, The image generating device is capable of receiving a detection result of the second sensor transmitted from the transmission circuit, and is capable of determining which of the first image data and the second image data to transmit based on the detection result of the second sensor.

14. The display system of claim 13.

17. transmitting first image data representing an entire image at a first resolution and second image data representing a first partial image at a second resolution higher than the first resolution, the first partial image corresponding to a portion of the entire image; receiving the first image data and the second image data; performing a first driving process for driving a plurality of pixels in units of a first number of pixels based on the first image data; performing a second driving operation for driving two or more pixels provided in a region corresponding to the first partial image among the plurality of pixels, with a second number of pixels being smaller than the first number, as a unit based on the second image data; A display driving method comprising: