Semiconductor device

Abstract

Provided is a novel semiconductor device. The semiconductor device comprises a first cache, a second cache, a cache controller, and cores, wherein the cache controller has a function that causes data for performing program processing to be stored in the second cache when a temperature of a periphery or an inside of the cores is higher than or equal to a predetermined temperature threshold and causes the data for performing the program processing to be stored in the first cache when the temperature of the periphery or the inside of the cores is lower than the predetermined temperature threshold.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. More specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, arithmetic devices, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, electronic computers, electronic devices, and driving methods thereof or manufacturing methods thereof.

[0003] In recent years, the development of semiconductor devices has progressed, and for example, large scale integration (LSI), central processing units (CPUs), and memories are mainly used in semiconductor devices. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits formed on chips by processing semiconductor wafers and on which electrodes serving as connection terminals are formed. For example, semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards (e.g., printed wiring boards) and used as one of the components in various electronic devices.

[0004] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0005] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0006] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide a plurality of overlapping memory cells.

[0007] JP 2012-257187 A JP 2011-151383 A International Publication No. 2021 / 053473

[0008] M. Oota et. al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0009] A CPU generally includes a core that performs program processing and a cache memory that stores data for the program processing. From the viewpoint of operating speed, the cache memory generally uses an SRAM (Static Random Access Memory) formed by Si transistors (transistors that contain silicon in their channel formation regions). Furthermore, the cache memory is preferably located near the core to exchange data with the core at high speed. Therefore, the cache memory is easily affected by heat generated by the core. For example, the SRAM used in the cache memory is affected by heat generated by the core, resulting in a decrease in operating speed.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device with improved operating speed. Another object is to provide a semiconductor device in which a decrease in operating speed due to an increase in temperature is suppressed. Another object is to provide a semiconductor device with reduced power consumption. Another object is to provide a miniaturized semiconductor device. Another object is to provide a highly integrated semiconductor device. Another object is to provide a novel semiconductor device.

[0011] The above-listed problems do not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of the above-listed problems. Note that problems other than the above-listed problems will become apparent from the description of this specification, drawings, claims, etc., and problems other than the above-listed problems can be extracted from the description of this specification, drawings, claims, etc.

[0012] (1) One aspect of the present invention is a semiconductor device comprising a first cache, a second cache, a cache control unit, and a core, wherein the core has a function of performing program processing, the cache control unit has a function of controlling the second cache to store data for performing program processing when the temperature around or inside the core is equal to or higher than a predetermined temperature threshold, and the cache control unit has a function of controlling the first cache to store data for performing program processing when the temperature around or inside the core is lower than the predetermined temperature threshold.

[0013] (2) In the above (1), the first cache may include a Si transistor, and the second cache may include an OS transistor.

[0014] (3) Furthermore, in the above (2), the semiconductor device may be one including a substrate, a layer on the substrate, and a die on the substrate, wherein the core is provided on the substrate, a portion of the first cache is provided on the layer, and a portion of the second cache is provided on the die, the layer is electrically connected to the substrate through a via formed between the substrate and the layer, and the die is electrically connected to the substrate by joining a first electrode formed on the substrate and a second electrode formed on the die.

[0015] (4) Furthermore, in the above (2), the semiconductor device may include a substrate, a layer on the substrate, and a die on the layer, wherein the core is provided on the substrate, a portion of the first cache is provided on the layer, and a portion of the second cache is provided on the die, the layer is electrically connected to the substrate through a via formed between the substrate and the layer, and the die is electrically connected to the layer by joining a first electrode formed on the layer and a second electrode formed on the die.

[0016] According to one embodiment of the present invention, a semiconductor device with improved operating speed can be provided. Alternatively, a semiconductor device in which a decrease in operating speed due to an increase in temperature is suppressed can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. Alternatively, a miniaturized semiconductor device can be provided. Alternatively, a highly integrated semiconductor device can be provided. Alternatively, a novel semiconductor device can be provided.

[0017] The effects listed above do not preclude the existence of other effects. It is not necessary for one embodiment of the present invention to have all of the effects listed above. Effects other than the effects listed above will become apparent from the description in this specification, drawings, claims, etc., and other effects other than the effects listed above can be extracted from the description in this specification, drawings, claims, etc.

[0018] FIG. 1 is a diagram illustrating a configuration example of a semiconductor device. FIG. 2 is a diagram illustrating a configuration example of a semiconductor device. FIG. 3 is a diagram illustrating a configuration example of a semiconductor device. FIG. 4 is a diagram illustrating a configuration example of a memory device. FIGS. 5A to 5F are diagrams illustrating a configuration example of a memory circuit. FIG. 6 is a flowchart illustrating an operation example of a semiconductor device. FIGS. 7A and 7B are flowcharts illustrating an operation example of a semiconductor device. FIGS. 8A and 8B are flowcharts illustrating an operation example of a semiconductor device. FIG. 9 is a diagram illustrating a configuration example of a semiconductor device. FIG. 10 is a diagram illustrating a configuration example of a semiconductor device. FIG. 11 is a diagram illustrating a configuration example of a semiconductor device. FIGS. 12A to 12C are diagrams illustrating an example of a semiconductor device. FIG. 13 is a diagram illustrating a configuration example of a memory section. FIG. 14A is a diagram illustrating a configuration example of a memory layer. FIG. 14B is a diagram illustrating an equivalent circuit of the memory layer. FIG. 15 is a diagram illustrating an example of a configuration of the memory section. FIG. 16A is a diagram illustrating an example of a memory layer. FIG. 16B is a diagram illustrating an equivalent circuit of the memory layer. FIGS. 17A and 17B are diagrams illustrating configuration examples of a semiconductor device. 18A to 18F are diagrams illustrating configuration examples of electronic devices.

[0019] In this specification, a semiconductor device refers to a device that utilizes semiconductor characteristics, such as a circuit including a semiconductor element (e.g., a transistor, a diode, or a photodiode), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip equipped with an integrated circuit, or an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, for example, a display device, a light-emitting device, an imaging device, an arithmetic device, a control device, a memory device, a signal processing device, a computer, or an electronic device may themselves be a semiconductor device and may also include a semiconductor device.

[0020] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are each an object (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, or a layer, etc.).

[0021] X and Y being electrically connected means that when an object having some kind of electrical action exists between X and Y, it enables the exchange of electrical signals between X and Y. As an example of when X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, or a load) that enable the electrical connection between X and Y can be connected between X and Y.

[0022] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, a logic circuit (for example, an inverter, a NAND circuit, or a NOR circuit), a signal conversion circuit (for example, a digital-to-analog conversion circuit, an analog-to-digital conversion circuit, or a gamma correction circuit), a potential level conversion circuit (for example, a power supply circuit (for example, a step-up circuit or a step-down circuit), or a level shifter circuit that changes the potential level of a signal), a voltage source, a current source, a switching circuit, an amplifier circuit (for example, a circuit that can increase the signal amplitude or current amount, an operational amplifier, a differential amplifier circuit, a source follower circuit, or a buffer circuit), a signal generation circuit, a memory circuit, or a control circuit) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0023] It should be noted that when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit sandwiched between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit sandwiched between them).

[0024] Furthermore, for example, it can be expressed as follows: "X, Y, the source of the transistor (sometimes referred to as one of the first terminal and the second terminal in this specification, etc.), and the drain of the transistor (sometimes referred to as the other of the first terminal and the second terminal in this specification, etc.) are electrically connected to each other, and are electrically connected in the order of X, the source of the transistor, the drain of the transistor, and Y." Alternatively, it can be expressed as follows: "The source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in this order." Alternatively, it can be expressed as follows: "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, it is possible to distinguish between the source and drain of a transistor and determine the technical scope. Note that these expressions are merely examples, and the present invention is not limited to these expressions. Here, X and Y are each an object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

[0025] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0026] Furthermore, in this specification, the term "resistive element" may refer to, for example, a circuit element or wiring having a resistance value higher than 0 Ω. Therefore, in this specification, the term "resistive element" includes, for example, wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, or a coil. Therefore, the term "resistive element" may be replaced with, for example, terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" may be replaced with, for example, terms such as "resistive element." The resistance value may be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, the resistance value may be, for example, 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0027] When a wiring is used as a resistor, the resistance value of the resistor may be determined by the length of the wiring. Alternatively, the resistor may use a conductor having a different resistivity from the conductor used as the wiring. Alternatively, when a semiconductor is used as a resistor, the resistance value of the resistor may be determined by doping impurities into the semiconductor.

[0028] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. Therefore, in this specification, a "capacitive element" is not limited to a circuit element including a pair of electrodes and a dielectric between the electrodes. A "capacitive element" also includes, for example, a parasitic capacitance occurring between wirings, or a gate capacitance occurring between one of the source or drain of a transistor and the gate. Furthermore, terms such as "capacitive element," "parasitic capacitance," or "gate capacitance" can be replaced with terms such as "capacitance." Conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," or "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with, for example, a "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0029] In this specification and the like, a transistor has three terminals called a gate (also referred to as a gate terminal, a gate region, or a gate electrode), a source (also referred to as a source terminal, a source region, or a source electrode), and a drain (also referred to as a drain terminal, a drain region, or a drain electrode). A transistor also has a region where a channel is formed between the drain and the source (also referred to as a channel formation region). A transistor can pass a current between the source and the drain through the channel formation region. The channel formation region is a region through which a current mainly flows. The gate is a control terminal between the source and the drain that controls the amount of current flowing in the channel formation region. The two terminals that function as a source or a drain are input / output terminals of the transistor.

[0030] Note that one of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type of the transistor (n-channel or p-channel) and the level of the potential applied to the three terminals of the transistor. Furthermore, for example, when the direction of current changes during circuit operation, the function as a source and the function as a drain may be interchanged. For this reason, the terms "source" and "drain" are interchangeable in this specification. Furthermore, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) or "the other of the source or drain" (or second electrode or second terminal) are used.

[0031] Depending on the structure, a transistor may have a back gate in addition to the three terminals described above. In this case, in this specification, one of the gate or the back gate of the transistor may be referred to as a first gate, and the other of the gate or the back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification, each gate may be referred to as, for example, a first gate, a second gate, or a third gate.

[0032] In this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used. A multi-gate transistor has channel formation regions connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, a multi-gate transistor can reduce off-state current and improve the transistor's breakdown voltage (improved reliability). Furthermore, when a multi-gate transistor operates in the saturation region, even if the voltage between the drain and source changes, the current between the drain and source does not change significantly, resulting in a voltage-current characteristic with a flat slope. A transistor with a voltage-current characteristic with a flat slope can realize an ideal current source circuit or an active load with a very high resistance value. As a result, a transistor with a voltage-current characteristic with a flat slope can realize, for example, a differential circuit or a current mirror circuit with good characteristics.

[0033] Furthermore, in this specification, when a single circuit element is illustrated on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a single resistor is illustrated on a circuit diagram, the resistor includes two or more resistors electrically connected in series. For example, when a single capacitor is illustrated on a circuit diagram, the capacitor includes two or more capacitors electrically connected in parallel. For example, when a single transistor is illustrated on a circuit diagram, the transistor includes two or more transistors electrically connected in series, with the gates of the respective transistors electrically connected to each other. Similarly, when a single switch is illustrated on a circuit diagram, the switch includes two or more transistors, with the two or more transistors electrically connected in series or parallel, and with the gates of the respective transistors electrically connected to each other.

[0034] Furthermore, in this specification and the like, a "node" can be rephrased as a "terminal," "wiring," "electrode," "conductive layer," "conductor," or "impurity region," depending on, for example, the circuit configuration or the device structure. Furthermore, for example, a "terminal" or "wiring" can be rephrased as a "node."

[0035] Furthermore, in this specification, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative. In other words, a change in the reference potential will change, for example, the potential applied to wiring, the potential applied to a circuit, or the potential output from a circuit.

[0036] Furthermore, in this specification and the like, the terms "high-level potential (also referred to as "high-level potential," "H potential," or "H")" and "low-level potential (also referred to as "low-level potential," "L potential," or "L")" do not refer to any particular potential. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0037] Furthermore, in this specification, "electric current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of positively charged bodies is occurring" can be rephrased as "electrical conduction of negatively charged bodies is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers include electrons, holes, anions, cations, and complex ions. Note that carriers vary depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in, for example, wiring, is the direction in which positive carriers move and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification and the like, unless otherwise specified regarding the positive or negative sign of a current (or the direction of the current), for example, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, for example, a statement such as "current is input to element A" can be rephrased as "current is output from element A," etc.

[0038] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0039] Furthermore, in this specification, terms indicating arrangement, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to drawings. Furthermore, the positional relationship between components changes as appropriate depending on the orientation in which each component is depicted. Therefore, terms indicating arrangement described in this specification are not limited to these terms and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees. Furthermore, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the left (or right) surface of a conductor" by rotating the orientation of the drawing by 90 degrees.

[0040] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0041] Furthermore, in this specification, terms such as "row" or "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, terms such as "row" or "column" used in this specification are not limited to these terms and can be rephrased appropriately depending on the situation. For example, the expression "row direction" can be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0042] Furthermore, in this specification and the like, for example, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" is not limited to the state in which electrode B is formed on insulating layer A. The expression "electrode B overlapping insulating layer A" does not exclude, for example, the state in which electrode B is formed under insulating layer A, or the state in which electrode B is formed on the right (or left) side of insulating layer A.

[0043] Furthermore, in this specification and the like, the terms "adjacent" or "close to" do not limit components to being in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not necessarily mean that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0044] Furthermore, in this specification and the like, terms such as "film" or "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" may be interchangeable with the term "conductive film." For example, the term "insulating film" may be interchangeable with the term "insulating layer." Furthermore, terms such as "film" or "layer" may be interchangeable with other terms depending on the situation without using those terms. For example, the term "conductive layer" or "conductive film" may be interchangeable with the term "conductor." Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or "conductive film." For example, the term "insulating layer" or "insulating film" may be interchangeable with the term "insulator." Furthermore, the term "insulator" may be interchangeable with the term "insulating layer" or "insulating film."

[0045] Furthermore, in this specification and the like, terms such as "electrode," "wiring," or "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include, for example, cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes, for example, cases where multiple "electrodes," "wirings," or "terminals" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal." Furthermore, for example, a "terminal" can be part of a "wiring" or "electrode." Furthermore, for example, terms such as "electrode," "wiring," or "terminal" may be replaced with terms such as "region."

[0046] Furthermore, in this specification and the like, terms such as "wiring," "signal line," or "power line" may be interchangeable depending on the situation. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." The reverse is also true, for example, terms such as "signal line" or "power line" may be changed to the term "wiring." The term "power line" may be changed to the term "signal line." The reverse is also true, for example, terms such as "signal line" may be changed to the term "power line." The term "potential" applied to wiring may be changed to the term "signal" depending on the situation. The reverse is also true, for example, terms such as "signal" may be changed to the term "potential."

[0047] In addition, in this specification, a "switch" has multiple terminals and has the function of switching (selecting) conduction or non-conduction between the terminals. For example, if a switch has two terminals and both terminals are conductive, the switch is said to be in a "conductive state" or "on state." Also, if both terminals are non-conductive, the switch is said to be in a "non-conductive state" or "off state." Note that switching the switch to either the conductive state or the non-conductive state, or maintaining either the conductive state or the non-conductive state, may be referred to as "controlling the conduction state."

[0048] In other words, a switch is a device that has the function of controlling whether or not a current flows. Alternatively, a switch is a device that has the function of selecting and switching the path through which a current flows. For example, an electrical switch or a mechanical switch can be used as the switch. In other words, the switch is not limited to a specific one as long as it can control a current.

[0049] There are types of switches that are normally in a non-conductive state but can be made conductive by controlling the conductive state, and these switches are sometimes called "contact A." There are also types of switches that are normally in a conductive state but can be made non-conductive by controlling the conductive state, and these switches are sometimes called "contact B."

[0050] Examples of electrical switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, or diode-connected transistors), and logic circuits that combine these. Note that when a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0051] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. Such a switch has an electrode that can be mechanically moved, and the movement of the electrode selects a conductive state or a non-conductive state.

[0052] When a transistor is used as a switch, the "conductive state" or "on state" of a transistor refers to, for example, a state in which the source electrode and the drain electrode of the transistor are considered to be electrically short-circuited, or a state in which a current can flow between the source electrode and the drain electrode. For example, the "conductive state" or "on state" may refer to a state in which the voltage between the gate and the source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and the source of a p-channel transistor is lower than the threshold voltage. The "non-conductive state," "cut-off state," or "off state" of a transistor refers to a state in which the source electrode and the drain electrode of the transistor are considered to be electrically cut off. For example, the "non-conductive state," "cut-off state," or "off state" may refer to a state in which the voltage between the gate and the source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and the source of a p-channel transistor is higher than the threshold voltage.

[0053] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to a current that flows between the source and drain when the transistor is in an off state (also referred to as a drain current). Note that in this specification and the like, the drain current and the current that flows between the gate and the source or drain when the transistor is in an off state (also referred to as a gate leakage current) may also be referred to as leakage current.

[0054] In this specification, the "channel length" of a transistor refers to, for example, the distance between the source and the drain in a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate overlap in a top view of the transistor, or the distance between the source and the drain in a region where a channel is formed.

[0055] Furthermore, in this specification, the "channel width" of a transistor refers to, for example, the length of a portion where the source and drain face each other in a region where the semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and the gate overlap in a top view of the transistor, or the length of a portion where the source and drain face each other in a region where a channel is formed.

[0056] In this specification and the like, terms such as "substrate," "wafer," or "die" do not limit the functionality of these components. For example, terms such as "substrate," "wafer," or "die" may be interchangeable depending on the situation.

[0057] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0058] In this specification, the term "having the same or approximately the same height" refers to the same height from a reference surface (e.g., a flat surface such as a substrate surface) in a cross-sectional view. For example, in a semiconductor device manufacturing process, a planarization process may expose the surface of a single layer or multiple layers. In this case, the surface to be planarized has the same height from the reference surface. However, depending on the processing equipment, processing method, or material of the processed surface during the planarization process, the heights of multiple layers may not be strictly equal. In this specification, the term "having the same or approximately the same height" is also used. For example, in a case where there are two layers (here, a first layer and a second layer) with different heights relative to a reference surface, the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less.

[0059] In this specification, "edges that coincide or approximately coincide" refers to the overlapping of at least a portion of the contours between stacked layers when viewed from above. For example, this includes cases in which, in the manufacturing process of a semiconductor device, upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In this specification, this case is also referred to as "edges that coincide or approximately coincide."

[0060] In this specification, when referring to, for example, counting values ​​and measurement values, or to objects, methods, and events that can be converted into counting values ​​or measurement values, terms such as "identical," "the same," "equal," or "uniform" (including synonyms thereof) are used, these terms are intended to include an error of plus or minus 20% unless otherwise specified.

[0061] In this specification and the like, impurities in a semiconductor refer to, for example, elements other than the main component constituting a semiconductor layer. For example, an element having a concentration of less than 0.1 atomic % is an impurity. When a semiconductor contains impurities, for example, the defect state density of the semiconductor may increase, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main component of the oxide semiconductor. In particular, there are hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. When an impurity is mixed in an oxide semiconductor, for example, oxygen vacancies (V Ｏ In some cases, oxygen vacancies (also called oxygen vacancies) may be formed.

[0062] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into, for example, oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply as OSs). For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide is used as a material capable of forming a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, the term "OS transistor" can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0063] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0064] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, these configuration examples can be combined as appropriate.

[0065] The embodiments described in this specification will be described with reference to the drawings. However, the embodiments can be implemented in many different ways. Therefore, those skilled in the art will readily understand that various changes in form and detail can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments. In the drawings illustrating the embodiments, the same reference numerals may be used in different drawings to designate identical or similarly functional parts in the configuration of the invention, thereby avoiding repetitive description. Furthermore, in the drawings, the same hatching patterns may be used and no particular reference numerals may be used to indicate similar functions. Furthermore, for ease of understanding, the drawings may omit the illustration of some components, for example, in perspective views or top views (also referred to as "plan views"). Furthermore, the drawings may omit the illustration of some hidden lines. Furthermore, the drawings may omit notations such as hatching patterns.

[0066] In addition, in the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to, for example, their size or aspect ratio. Note that the drawings are merely schematic illustrations of ideal examples, and are not limited to, for example, the shapes or values ​​shown in the drawings.

[0067] For example, the drawings and the like relating to this specification may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0068] For example, in the drawings and the like relating to this specification, in the actual manufacturing process, layers or resist masks may be unintentionally reduced due to processes such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0069] Furthermore, in the drawings and the like relating to this specification, when showing block diagrams, the components of the present invention may be classified by function and shown as independent blocks. However, for example, when showing an actual circuit or the like in a block diagram, it may be difficult to separate the components by function, and there may be cases where multiple functions are involved in one circuit, or where one function is involved across multiple circuits. Therefore, each block shown in the block diagram is not limited to the components described in this specification and may be rephrased appropriately depending on the situation.

[0070] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. More specifically, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0071] In this specification, when the same symbol is used for multiple elements, particularly when it is necessary to distinguish between them, an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]" may be added to the symbol.

[0072] Embodiment 1 A structural example of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 1 to 5. In addition, an operation example of the semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

[0073] Note that a semiconductor device according to one embodiment of the present invention may be suitably used as part of a central processing unit (CPU), for example.

[0074] 1 is a block diagram illustrating a configuration example of a semiconductor device 100 according to one aspect of the present invention. As shown in FIG. 1, the semiconductor device 100 includes a cache unit 113, a cache control unit 114, a core 115, a thermal detection unit 116, a bus 117, a memory control unit 121, a power control unit 122, and a clock control unit 123. The cache unit 113 includes a first cache 111 (Cache1) and a second cache 112 (Cache2).

[0075] The semiconductor device 100 can include one or more cores 115. As an example, the semiconductor device 100 shown in FIG.

[0076] 1, a temperature sensor 131 and a memory 141 are arranged around the semiconductor device 100. One or both of the temperature sensor 131 and the memory 141 may be arranged inside the semiconductor device 100.

[0077] The core 115 has a function of performing program processing. The core 115 also has a function of sending a read request to the cache control unit 114 to obtain data for performing program processing. The read request includes an address of the memory 141. Note that when the semiconductor device 100 is used as part of a CPU, the core 115 can have a function as an arithmetic unit (also called a processor core).

[0078] The memory 141 has a function of storing data for program processing. Note that when the semiconductor device 100 is used as part of a CPU, the memory 141 can function as a main memory. For example, a dynamic random access memory (DRAM) can be used as the memory 141.

[0079] The memory control unit 121 has a function of controlling the reading or writing of data from or to the memory 141 based on a request from the cache control unit 114 .

[0080] The cache unit 113 has a function of storing data for program processing and the address of the memory 141 where the data is stored in the first cache 111 or the second cache 112. When the semiconductor device 100 is used as part of a CPU, the cache unit 113 can function as a buffer storage device (also called a cache memory). Therefore, the cache unit 113 is preferably arranged near the core 115 in order to exchange data with the core 115 at high speed.

[0081] When the semiconductor device 100 is used in a CPU including a first cache to an Lth cache (L is an integer equal to or greater than 2), the cache unit 113 may function as an Lth cache, for example. Alternatively, the cache unit 113 may function as an L-1th cache, and the memory 141 may function as an Lth cache, for example.

[0082] The cache control unit 114 has a function of receiving a read request from the core 115, and if data corresponding to the address included in the request exists in the cache unit 113, reading the data from the cache unit 113 and outputting it to the core 115. Alternatively, the cache control unit 114 has a function of receiving a read request from the core 115, and if data corresponding to the address included in the request does not exist in the cache unit 113, reading the data from the memory 141 via the memory control unit 121, outputting it to the core 115, and storing it in the cache unit 113.

[0083] The cache control unit 114 also has a function of sending an interrupt request to the core 115 in order to stop or restart program processing.

[0084] The first cache 111 and the second cache 112 are configured with transistors having different temperature characteristics. The first cache 111 can be, for example, a static random access memory (SRAM) configured with Si transistors (transistors containing silicon in their channel formation regions). The second cache 112 can be, for example, an OS memory configured with OS transistors (transistors containing an oxide semiconductor in their channel formation regions). The OS memory is a memory that can retain stored data for a long period of time by using OS transistors with extremely low off-state current.

[0085] Si transistors have a faster operating speed than OS transistors. Furthermore, by electrically connecting the gate of an n-channel Si transistor and the gate of a p-channel Si transistor, Si transistors can be used to form a CMOS circuit (e.g., a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit). A circuit configured with Si transistors can increase the operating speed and reduce power consumption in a steady state. Therefore, Si transistors are preferably used in the cache control unit 114, the core 115, the heat detection unit 116, the memory control unit 121, the power supply control unit 122, the clock control unit 123, and the like, in addition to the first cache 111.

[0086] The OS transistor has a characteristic of extremely low off-state current (current flowing between the source and drain when the transistor is off) because the band gap of the oxide semiconductor in which the channel is formed is 2 eV or more. The off-state current of an OS transistor per 1 μm of channel width at room temperature is 1 aA (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less, or 1 yA (1 x 10 −２４ In the case of a Si transistor, the off-state current per 1 μm of channel width at room temperature can be 1 fA (1×10 −１５ A) or more and 1 pA (1 × 10 −１２Therefore, it can be said that the off-state current of an OS transistor is about 10 orders of magnitude lower than that of a Si transistor.

[0087] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environmental temperature range of room temperature or higher and 200° C. or lower. The on-state current of an OS transistor is unlikely to decrease even in a high-temperature environment. On the other hand, the on-state current of a Si transistor decreases in a high-temperature environment. That is, the on-state current of an OS transistor is higher than that of a Si transistor in a high-temperature environment. Furthermore, an OS transistor can perform a good switching operation even in an environmental temperature range of 125° C. or higher and 150° C. or lower because of its large ratio of on-state current to off-state current. Therefore, a semiconductor device including an OS transistor can operate stably and with high reliability even in a high-temperature environment.

[0088] Therefore, the first cache 111 configured with Si transistors operates faster at low temperatures than the second cache 112 configured with OS transistors. On the other hand, the first cache 111 may operate slower than the second cache 112 because its operating speed decreases as the temperature rises.

[0089] Furthermore, the first cache 111 and the second cache 112 are preferably arranged near the core 115 in order to exchange data with the core 115 at high speed. Therefore, the first cache 111 and the second cache 112 are easily affected by heat generated by the core 115.

[0090] That is, when program processing is performed, heat generated by the core 115 is transferred to the first cache 111 and the second cache 112, causing the temperature to rise, and the first cache 111 may operate slower than the second cache 112. Therefore, the cache control unit 114 can control the cache unit 113 so that the first cache 111 or the second cache 112, whichever operates faster, is used depending on the temperature.

[0091] The cache control unit 114 has a function of controlling the use of the first cache 111 and the second cache 112 by switching between them depending on the temperature around or inside the core 115. This makes it possible to improve the operating speed of the semiconductor device 100. It also makes it possible to suppress a decrease in the operating speed of the semiconductor device 100 due to an increase in temperature.

[0092] The semiconductor layer of the OS transistor preferably contains at least one of indium and zinc. Furthermore, the semiconductor layer of the OS transistor preferably contains, for example, indium, M (M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium, and tin.

[0093] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as "IGZO") as the semiconductor layer. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as "IAZO") may be used as the semiconductor layer. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as "IAGZO") may be used as the semiconductor layer.

[0094] When the semiconductor layer is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include a composition in which In:M:Zn=1:1:1 or thereabouts, a composition in which In:M:Zn=1:1:1.2 or thereabouts, a composition in which In:M:Zn=2:1:3 or thereabouts, a composition in which In:M:Zn=3:1:2 or thereabouts, a composition in which In:M:Zn=4:2:3 or thereabouts, a composition in which In:M:Zn=4:2:4.1 or thereabouts, a composition in which In:M:Zn=5:1:3 or thereabouts, a composition in which In:M:Zn=5:1:6 or thereabouts, a composition in which In:M:Zn=5:1:7 or thereabouts, a composition in which In:M:Zn=5:1:8 or thereabouts, a composition in which In:M:Zn=6:1:6 or thereabouts, and a composition in which In:M:Zn=5:2:5 or thereabouts. Furthermore, the atomic ratio of In in the In-M-Zn oxide may be smaller than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include a composition of In:M:Zn=1:3:2 or a composition thereabout, or a composition of In:M:Zn=1:3:4 or a composition thereabout. Note that a composition thereabout includes a range of plus or minus 30% of the desired atomic ratio.

[0095] The heat detection unit 116 has a function of measuring the temperature using a temperature sensor 131. The heat detection unit 116 also has a function of sending information indicating whether the measured temperature is equal to or higher than a predetermined temperature threshold to the cache control unit 114 via the bus 117.

[0096] The heat detection unit 116 may include an analog-to-digital converter (ADC). By including the ADC in the heat detection unit 116, a temperature sensor that outputs an analog signal can be used as the temperature sensor 131.

[0097] The temperature sensor 131 has a function of outputting a signal corresponding to the temperature to the heat detection unit 116. The temperature sensor 131 may be provided around the core 115 and output a signal corresponding to the temperature around the core 115 to the heat detection unit 116. Alternatively, the temperature sensor 131 may be provided inside the core 115 and output a signal corresponding to the temperature inside the core 115 to the heat detection unit 116. The temperature sensor 131 may be, for example, a resistance temperature detector (e.g., platinum, nickel, or copper), a thermistor, a thermocouple, or an IC temperature sensor. Alternatively, the temperature sensor 131 may be, for example, a semiconductor temperature sensor (e.g., a silicon diode temperature sensor) or a bandgap circuit.

[0098] The cache control unit 114 has a function of receiving information on whether the measured temperature is equal to or higher than a predetermined temperature threshold, and, in accordance with the information, controlling the cache unit 113. In other words, the cache control unit 114 has a function of controlling the cache unit 113 to use the second cache 112 when the temperature of the core 115 is equal to or higher than the predetermined temperature threshold, and to use the first cache 111 when the temperature of the core 115 is lower than the predetermined temperature threshold.

[0099] 1 , when the semiconductor device 100 includes multiple cores 115, the heat detection unit 116 may measure the temperature of each of the multiple cores 115 using a temperature sensor 131 provided around or inside each of the multiple cores 115, and may use the average, median, or maximum of the measured temperatures as the temperature around or inside the core 115. Alternatively, the heat detection unit 116 may measure the temperature using a temperature sensor 131 provided around or inside one core 115 selected from the multiple cores 115, and may use the measured temperature as the temperature around or inside the core 115.

[0100] For example, the heat detection unit 116 may measure the temperature using a temperature sensor 131 provided around or inside the first cache 111 and / or around or inside the second cache 112.

[0101] The bus 117 functions as a transmission path for exchanging information such as data, requests, commands, or signals between the components of the semiconductor device 100 .

[0102] The power supply control unit 122 has a function of controlling the supply of power (e.g., potential VSS and potential VDD) to each component included in the semiconductor device 100. The potential VSS may be, for example, a ground potential. The potential VDD is a potential higher than the potential VSS, and may be, for example, a potential such that the potential difference between the potential VDD and the potential VSS is equal to or greater than the threshold voltage of a transistor. The power supply control unit 122 can stop the supply of power to the first cache 111, for example, by receiving a command to stop the supply of power to the first cache 111. Furthermore, the power supply control unit 122 can stop the supply of power to the second cache 112, for example, by receiving a command to stop the supply of power to the second cache 112.

[0103] The clock control unit 123 has a function of controlling the supply of a clock signal (e.g., signal CLK) to each component included in the semiconductor device 100. For example, the clock control unit 123 can stop the supply of the clock signal to the first cache 111 by receiving a command to stop the supply of the clock signal to the first cache 111. Furthermore, for example, the clock control unit 123 can stop the supply of the clock signal to the second cache 112 by receiving a command to stop the supply of the clock signal to the second cache 112.

[0104] Fig. 2 is a circuit diagram illustrating a detailed configuration example of the cache unit 113 and its surroundings in the semiconductor device 100 shown in Fig. 1. As shown in Fig. 2, the cache unit 113 includes, in addition to the first cache 111 and second cache 112 described above, switches SW11, SW12, SW13, SW14, SW15, SW16, SW17, and SW18.

[0105] The cache control unit 114 can exchange signals ADDR, DATA, HIT, MEM1_EN, MEM1_PW, MEM2_EN, and MEM2_PW with the cache unit 113 (the first cache 111 or the second cache 112).

[0106] The signal ADDR is a signal indicating an address in the memory 141. The signal DATA is data for performing program processing in the core 115. The signal HIT is a signal indicating whether data corresponding to the address of the signal ADDR exists in the first cache 111 or the second cache 112.

[0107] 2, for simplicity of explanation, the cache unit 113 is shown as having one switch SW13 and one switch SW17, but it may be provided with a plurality of switches SW13 and a plurality of switches SW17 in accordance with the number of bits of the signal ADDR. Also, the cache unit 113 is shown as having one switch SW12 and one switch SW16, but it may be provided with a plurality of switches SW12 and a plurality of switches SW16 in accordance with the number of bits of the signal DATA.

[0108] When the cache control unit 114 receives a read request from the core 115, it first sends a signal ADDR to the first cache 111 or the second cache 112. When the first cache 111 or the second cache 112 receives the signal ADDR from the cache control unit 114, it determines whether data corresponding to the address of the memory 141 indicated by the signal ADDR is stored. If the data is stored, it outputs a signal DATA representing the data and a signal HIT indicating that the data exists (also called a cache hit) to the cache control unit 114. If the data is not stored, it outputs a signal HIT indicating that the data does not exist (also called a cache miss) to the cache control unit 114.

[0109] Each of the switches SW11 to SW13 has a function of being turned on or off in response to a signal MEM1_EN. The switch SW14 has a function of being turned on or off in response to a signal MEM1_PW. Each of the switches SW15 to SW17 has a function of being turned on or off in response to a signal MEM2_EN. The switch SW18 has a function of being turned on or off in response to a signal MEM2_PW.

[0110] When the switch SW14 is turned on, the potential VSS is supplied to the first cache 111. When the switch SW14 is turned on, the switch SW11 is turned on, allowing the signal HIT to be exchanged between the cache control unit 114 and the first cache 111. When the switch SW12 is turned on, the signal DATA can be exchanged between the cache control unit 114 and the first cache 111. When the switch SW13 is turned on, the signal ADDR can be exchanged between the cache control unit 114 and the first cache 111.

[0111] That is, when all of the switches SW11 to SW14 are in the ON state, the signals ADDR, DATA, and HIT can be exchanged between the cache control unit 114 and the first cache 111. In the present embodiment and the like, this state is referred to as the first cache 111 being in a valid state. Also, when at least one of the switches SW11 to SW14 is in an OFF state, the signals ADDR, DATA, and HIT are not exchanged between the cache control unit 114 and the first cache 111. In the present embodiment and the like, this state is referred to as the first cache 111 being in an invalid state.

[0112] When switch SW18 is turned on, the potential VSS is supplied to the second cache 112. When switch SW18 is turned on, switch SW15 is turned on, allowing the signal HIT to be exchanged between the cache control unit 114 and the second cache 112. When switch SW16 is turned on, the signal DATA can be exchanged between the cache control unit 114 and the second cache 112. When switch SW17 is turned on, the signal ADDR can be exchanged between the cache control unit 114 and the second cache 112.

[0113] That is, when all of the switches SW15 to SW18 are in the ON state, the signals ADDR, DATA, and HIT can be exchanged between the cache control unit 114 and the second cache 112. In the present embodiment and the like, this state is referred to as the second cache 112 being in a valid state. Also, when at least one of the switches SW15 to SW18 is in an OFF state, the signals ADDR, DATA, and HIT are not exchanged between the cache control unit 114 and the second cache 112. In the present embodiment and the like, this state is referred to as the second cache 112 being in an invalid state.

[0114] The cache control unit 114 can control the cache unit 113 using the signals MEM1_EN, MEM1_PW, MEM2_EN, and MEM2_PW so that one of the first cache 111 and the second cache 112 is in a valid state and the other is in an invalid state. In this embodiment and the like, a state in which the first cache 111 is in a valid state and the second cache 112 is in an invalid state is referred to as a first cache mode. Also, a state in which the second cache 112 is in a valid state and the first cache 111 is in an invalid state is referred to as a second cache mode.

[0115] Therefore, the cache control unit 114 has the function of receiving information from the heat detection unit 116 as to whether the temperature around or inside the core 115 is above a predetermined temperature threshold, and controlling the cache unit 113 to operate in the first cache mode or the second cache mode depending on the information.

[0116] Note that a transistor functioning as a switch can be used for each of the switches SW11 to SW18. In the configuration shown in FIG. 3, the switches SW11, SW12, SW13, SW14, SW15, SW16, SW17, and SW18 are replaced with transistors M11, M12, M13, M14, M15, M16, M17, and M18, respectively.

[0117] 3, for simplicity of explanation, the cache unit 113 is shown as including one transistor M13 and one transistor M17, but may include a plurality of transistors M13 and M17 in accordance with the number of bits of the signal ADDR. Also, the cache unit 113 is shown as including one transistor M12 and one transistor M16, but may include a plurality of transistors M12 and M16 in accordance with the number of bits of the signal DATA.

[0118] OS transistors can be used for each of the transistors M11 to M18. By using OS transistors for the transistors M11 to M18, the ratio of on-state current to off-state current is large even in a high-temperature environment, enabling favorable switching operation. For example, in the first cache mode, even in a high-temperature environment, the on-state current of the transistors M11 to M13 when on is large, and the off-state current of the transistor M18 when off is small. Furthermore, for example, in the second cache mode, even in a high-temperature environment, the on-state current of the transistors M15 to M17 when on is large, and the off-state current of the transistor M14 when off is small. Therefore, the operating speed of the semiconductor device 100 can be improved. Furthermore, the power consumption of the semiconductor device 100 can be reduced. Furthermore, a decrease in the operating speed of the semiconductor device 100 due to an increase in temperature can be suppressed.

[0119] [Example of Cache Configuration] FIG. 4 is a block diagram illustrating an example of the configuration of a storage device 300 that can be suitably used as the second cache 112 according to one aspect of the present invention.

[0120] As shown in FIG. 4, the memory device 300 includes a memory cell section 21 and a drive circuit section 22 .

[0121] The memory cell section 21 includes a plurality of stacked memory cell arrays 90. The memory cell arrays 90 include a plurality of memory cells MC arranged in a matrix. An example of the configuration of the memory cells MC will be described later.

[0122] The drive circuit unit 22 includes a PSW 62 (power switch), a PSW 63, and a peripheral circuit 71. The peripheral circuit 71 includes a peripheral circuit 81, a control circuit 72, and a voltage generation circuit 73.

[0123] In the storage device 300, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Other circuits or signals may also be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside. The signals HIT and RDA are output signals to the outside.

[0124] Signal CLK is a clock signal. Signals BW, CE, and GW are control signals. Signal CE is a chip enable signal. Signal GW is a global write enable signal. Signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal HIT is a signal indicating whether data corresponding to the address signal exists in memory cell unit 21. Signal WDA is write data. Signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by control circuit 72.

[0125] The control circuit 72 is a logic circuit having the function of controlling the overall operation of the memory device 300. For example, the control circuit 72 outputs a signal HIT to indicate whether data corresponding to an address signal exists in the memory cell unit 21. For example, the control circuit 72 performs a logical operation on the signals CE, GW, and BW to determine the operation mode of the memory device 300 (for example, a write operation or a read operation (for example, read mode 1 or read mode 2)). Alternatively, the control circuit 72 generates a control signal for the peripheral circuit 81 so that this operation mode is executed.

[0126] The voltage generating circuit 73 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 73. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 73, and the voltage generating circuit 73 generates a negative voltage.

[0127] The peripheral circuit 81 is a circuit for writing or reading data to or from the memory cells MC, and includes a row decoder 82, a column decoder 84, a row driver 83, a column driver 85, an input circuit 87, an output circuit 88, and a drive circuit 51 including a sense amplifier 55.

[0128] The row decoder 82 and the column decoder 84 have the function of decoding the signal ADDR. The row decoder 82 is a circuit for specifying a row to be accessed. The column decoder 84 is a circuit for specifying a column to be accessed. The row driver 83 has the function of selecting a word line specified by the row decoder 82. The column driver 85 has the function of selecting a bit line specified by the column decoder 84. The drive circuit 51 has the function of writing data to a memory cell MC selected by, for example, the word line selected by the row driver 83 and the bit line selected by the column driver 85, reading data using the sense amplifier 55, or retaining the read data.

[0129] The input circuit 87 has a function of holding a signal WDA. The data held by the input circuit 87 is output to the column driver 85. The output data of the input circuit 87 is data (data Din) to be written to the memory cell MC. The data (data Dout) read from the memory cell MC by the column driver 85 is output to the output circuit 88. The output circuit 88 has a function of holding the data Dout. The output circuit 88 also has a function of outputting the data Dout to the outside of the memory device 300. The data output from the output circuit 88 is the signal RDA.

[0130] The PSW 62 has a function of controlling the supply of the potential VDD to the peripheral circuit 71. The PSW 63 has a function of controlling the supply of the potential VHM to the row driver 83. Here, the potential on the high power supply side of the memory device 300 is the potential VDD, and the potential on the low power supply side is the potential VSS. The potential VHM is a potential used to set the word line to an H level (a potential that turns on a transistor electrically connected to the word line) and is higher than the potential VDD. The PSW 62 is controlled to an ON state or an OFF state by a signal PON1. The PSW 63 is controlled to an ON state or an OFF state by a signal PON2. In FIG. 4 , the number of power domains to which the potential VDD is supplied in the peripheral circuit 71 is one, but multiple power domains may also be used. In this case, the drive circuit unit 22 may be provided with a power switch for each power domain.

[0131] [Configuration Example of Memory Cell] FIG. 5A is a block diagram illustrating a configuration example of a memory circuit that can be suitably used for the memory device 300 of one embodiment of the present invention.

[0132] The block diagram shown in FIG. 5A illustrates a memory cell array 90, a word line driving circuit 91, and a bit line driving circuit 92.

[0133] The memory cell array 90 has memory cells MC arranged in a matrix of m rows and n columns (m and n are positive integers). The memory cells MC are electrically connected to word lines WL_1 to WL_m and bit lines BL_1 to BL_n. In addition to the bit lines and word lines, the memory cells MC may also be electrically connected to, for example, a source line for passing a current, a wiring for applying a potential to a back gate of a transistor, or a capacitor line for setting one electrode of a capacitor at a fixed potential.

[0134] The word line drive circuit 91 is a circuit that outputs a signal for selecting memory cells MC in each row. The word line drive circuit 91 corresponds to, for example, the row decoder 82 and the row driver 83 provided in the drive circuit unit 22 of the memory device 300 described above. The word lines WL_1 to WL_m may include separate word lines for writing and reading. In the following description, a word line selected from the word lines WL_1 to WL_m may be referred to as a word line WL.

[0135] The bit line driver circuit 92 is a circuit for writing data to or reading data from memory cells MC in each column. The bit line driver circuit 92 corresponds to, for example, the driver circuit 51 including the column decoder 84, column driver 85, and sense amplifier 55 provided in the driver circuit unit 22 of the memory device 300 described above. The bit lines BL_1 to BL_n may include separate bit lines for writing and reading. In the following description, a bit line selected from the bit lines BL_1 to BL_n may be referred to as a bit line BL.

[0136] 5B to 5F are diagrams for explaining examples of circuit configurations that the memory cell MC shown in FIG. 5A can have.

[0137] The memory cell MC shown in FIG. 5B includes a transistor M1 and a capacitor C. One of the source and drain of the transistor M1 is electrically connected to one electrode of the capacitor C. The other of the source and drain of the transistor M1 is electrically connected to a bit line BL. The gate of the transistor M1 is electrically connected to a word line WL. The other electrode of the capacitor C is electrically connected to a capacitor line CL. The transistor M1 is an OS transistor. OS transistors have an extremely low off-state current. Therefore, by turning off the transistor M1, a charge corresponding to data can be held in the charge holding node FN. Therefore, the refresh rate of data corresponding to the charge held in the charge holding node FN can be reduced.

[0138] The memory cell MC shown in Figure 5C is a modified example of the memory cell MC shown in Figure 5B. The difference from the transistor M1 in Figure 5B is that the transistor M1 has a back gate, and the back gate and gate are electrically connected to each other, so that the potential of the word line WL is applied from both. This configuration increases the amount of current flowing between the source and drain when the transistor M1 is turned on.

[0139] The memory cell MC shown in Figure 5D is a modified example of the memory cell MC shown in Figure 5B. The difference from the transistor M1 in Figure 5B is that the transistor M1 has a back gate, and by electrically connecting the back gate to the back gate line BGL, a potential different from that of the gate is applied to the back gate. This configuration allows the threshold voltage of the transistor M1 to be controlled, thereby changing the amount of current flowing between the source and drain of the transistor M1.

[0140] The memory cell MC shown in FIG. 5E includes a transistor M1, a transistor M2, and a capacitor C. One of the source and drain of the transistor M1 is electrically connected to the gate of the transistor M2 and one electrode of the capacitor C. The other of the source and drain of the transistor M1 is electrically connected to a write bit line WBL. The gate of the transistor M1 is electrically connected to a write word line WWL. The other electrode of the capacitor C is electrically connected to a read word line RWL. One of the source and drain of the transistor M2 is electrically connected to a read bit line RBL. The other of the source and drain of the transistor M2 is electrically connected to a source line SL. Although the transistor M2 is illustrated as an n-channel transistor, it may be a p-channel transistor. By turning off the transistor M1, charge corresponding to data can be held in the charge holding node FN. The transistor M2 is an OS transistor. Note that the transistor M2 may be a Si transistor. Note that the transistor M1 may have a configuration similar to that of the transistor M1 shown in FIG. 5C or 5D.

[0141] The memory cell MC shown in FIG. 5F includes transistors M1, M2, M3, and a capacitor C. One of the source or drain of transistor M1 is electrically connected to the gate of transistor M2 and one electrode of capacitor C. The other of the source or drain of transistor M1 is electrically connected to a write bit line WBL. The gate of transistor M1 is electrically connected to a write word line WWL. The other electrode of capacitor C is electrically connected to a capacitor line CL. One of the source or drain of transistor M2 is electrically connected to one of the source or drain of transistor M3. The other of the source or drain of transistor M2 is electrically connected to a source line SL. The gate of transistor M3 is electrically connected to a read word line RWL. The other of the source or drain of transistor M3 is electrically connected to a read bit line RBL. Although an n-channel transistor is illustrated as transistor M3, it may be a p-channel transistor. By turning off transistor M1, charge corresponding to data can be held in the charge holding node FN. The transistors M2 and M3 are OS transistors. At least one of the transistors M2 and M3 may be a Si transistor. The transistor M1 may have the same structure as the transistor M1 shown in FIG. 5C or 5D.

[0142] The memory cell configurations shown in FIGS. 5B to 5D are called DOSRAM (registered trademark). DOSRAM is an abbreviation for Dynamic Oxide Semiconductor RAM (Random Access Memory). A configuration using DOSRAM electrically connects one of the source or drain of an OS transistor to one electrode of a capacitor, allowing charge stored in one electrode of the capacitor to be retained when the OS transistor is turned off. A configuration using DOSRAM is particularly effective when the amount of data to be stored increases. For example, DOSRAM can suppress an increase in circuit area compared to a memory cell configured using SRAM (Static RAM). The memory cell configurations shown in FIGS. 5B to 5D are particularly effective in suppressing an increase in circuit area.

[0143] The memory cell configurations shown in FIGS. 5E and 5F are called NOSRAM (registered trademark). NOSRAM is an abbreviation for Nonvolatile Oxide Semiconductor RAM. A configuration using NOSRAM can retain charge accumulated in the gate of a read transistor when the write OS transistor is turned off by electrically connecting one of the source and drain of the write OS transistor to the gate of the read transistor. A configuration using NOSRAM may also be used as a nonvolatile memory. For example, NOSRAM can continue to store data even in a power gating state by turning off the write OS transistor.

[0144] Note that the circuit configurations illustrated in FIGS. 5B to 5F are merely examples, and any configuration can be used as long as it can realize one embodiment of the present invention.

[0145] <Operation Example> An operation example of the semiconductor device 100 according to one embodiment of the present invention will be described. The semiconductor device 100 operates in a normal state or an overheated state. In this embodiment and the like, the normal state is a state in which the temperature T around or inside the core 115 is less than a predetermined temperature threshold Tth (the temperature T is less than the temperature threshold Tth). The overheated state is a state in which the temperature T around or inside the core 115 is equal to or greater than the predetermined temperature threshold Tth (the temperature T is equal to or greater than the temperature threshold Tth). In addition, when the temperature T remains equal to or greater than the temperature threshold Tth for a certain period of time in the normal state, the semiconductor device 100 transitions to the overheated state. In addition, when the temperature T remains less than the temperature threshold Tth for a certain period of time in the overheated state, the semiconductor device 100 transitions to the normal state.

[0146] The temperature threshold Tth may be set to, for example, a temperature of 60° C. or higher and 100° C. or lower, more preferably, a temperature of 60° C. or higher and 80° C. or lower.

[0147] The above-mentioned certain time period is preferably set to a time period of 0.1 seconds or more and 10 seconds or less, and more preferably set to a time period of 0.1 seconds or more and 1 second or less.

[0148] In the normal state, the semiconductor device 100 performs program processing in the core 115 using the first cache 111. That is, in the normal state, the cache unit 113 operates in the first cache mode (the first cache 111 is valid and the second cache 112 is invalid). In addition, in the overheat state, the semiconductor device 100 performs program processing in the core 115 using the second cache 112. That is, in the overheat state, the cache unit 113 operates in the second cache mode (the second cache 112 is valid and the first cache 111 is invalid). Note that, when the semiconductor device 100 transitions from the normal state to the overheat state, it performs processing to switch the operation of the cache unit 113 from the first cache mode to the second cache mode. In addition, when the semiconductor device 100 transitions from the overheat state to the normal state, it performs processing to switch the operation of the cache unit 113 from the second cache mode to the first cache mode.

[0149] 6, 7A, and 7B are flowcharts illustrating an example of operation of the semiconductor device 100. The flowchart shown in FIG. 6 illustrates an example of operation of the semiconductor device 100 in each of the following states: a normal state (first cache mode), a transition from the normal state to an overheated state (switching from the first cache mode to the second cache mode), an overheated state (second cache mode), and a transition from the overheated state to a normal state (switching from the second cache mode to the first cache mode). The flowchart shown in FIG. 7A illustrates an example of a process (Process A) for switching from the first cache mode to the second cache mode. The flowchart shown in FIG. 7B illustrates an example of a process (Process B) for switching from the second cache mode to the first cache mode.

[0150] [Normal State (First Cache Mode)] While program processing is being executed (step S01), the following operations are performed. In the normal state, it is assumed that program processing is being executed in at least one core 115 included in the semiconductor device 100. First, the heat detection unit 116 measures the temperature T around or inside the core 115 using the temperature sensor 131 (step S02). Then, the heat detection unit 116 sends information indicating whether the temperature T is equal to or greater than a predetermined temperature threshold value Tth (i.e., whether the temperature T is equal to or greater than the temperature threshold value Tth) to the cache control unit 114 via the bus 117.

[0151] Next, the cache control unit 114 receives information from the heat detection unit 116 indicating whether the temperature T is equal to or greater than the temperature threshold value Tth, and determines whether the system is in an overheated state (whether the temperature T has remained equal to or greater than the temperature threshold value Tth for a certain period of time) (step S03). If the system is in a normal state (not in an overheated state), the cache control unit 114 determines whether the second cache 112 is valid (step S08). In the normal state, the system is in the first cache mode (the second cache 112 is not valid), so the process returns to step S01.

[0152] That is, while the program processing is being executed in the normal state, the semiconductor device 100 repeats steps S01, S02, S03, and S08 in order.

[0153] [Transition from Normal State to Overheat State (Switching from First Cache Mode to Second Cache Mode)] Continuing execution of program processing in the normal state may cause the temperature T around or inside the core 115 to rise and exceed a predetermined temperature threshold Tth (temperature T is equal to or greater than temperature threshold Tth). If the temperature T remains equal to or greater than temperature threshold Tth for a certain period of time, an overheat state is determined in step S03. If an overheat state is determined, the cache control unit 114 determines whether the first cache 111 is valid (step S04). Immediately after transitioning from the normal state to the overheat state, the first cache mode is active (the first cache 111 is valid), so the first cache mode is switched to the second cache mode (steps S05 to S07). After switching from the first cache mode to the second cache mode, the process returns to step S01.

[0154] Switching from the first cache mode to the second cache mode will now be described. First, the cache control unit 114 sends an interrupt request to the core 115, and upon receiving the request, the core 115 stops the currently running program processing (step S05). Next, the cache control unit 114 performs process A (processing for switching from the first cache mode to the second cache mode) (step S06). For example, when the cache control unit 114 receives a read request from the core 115, it may perform control so that it communicates with the second cache 112. Then, the cache control unit 114 sends an interrupt request to the core 115, and upon receiving the request, the core 115 resumes the stopped program processing (step S07).

[0155] The process A of step S06 will be described (see FIG. 7A). In process A, the cache control unit 114 sets the first cache 111 to an invalid state and the second cache 112 to an valid state (step S21).

[0156] 2, the cache control unit 114 may output a signal MEM1_EN that turns off the switches SW11 to SW13, a signal MEM2_EN that turns on the switches SW15 to SW17, and a signal MEM2_PW that turns on the switch SW18. Also, in FIG. 3, the cache control unit 114 may output a signal MEM1_EN at an L level, a signal MEM2_EN at an H level, and a signal MEM2_PW at an H level. Here, the L level is a potential at which the transistors M11 to M13 are turned off (for example, the potential VSS or a potential lower than the potential VSS). Also, the H level is a potential at which the transistors M15 to M18 are turned on (for example, the potential VDD or a potential higher than the potential VDD).

[0157] As a result, when the cache control unit 114 receives a read request from the core 115 , it exchanges the signals ADDR, DATA, and HIT with the second cache 112 .

[0158] Furthermore, the first cache 111 is no longer involved in the exchange of the signals ADDR, DATA, and HIT. In other words, the first cache 111 is no longer used to execute program processing. Therefore, for example, the cache control unit 114 may stop the supply of power to the first cache 111. Stopping the supply of power to the first cache 111 can reduce the power consumption of the semiconductor device 100.

[0159] 2, the cache control unit 114 may output a signal MEM1_PW that turns off the switch SW14. Alternatively, for example, in FIG. 3, the cache control unit 114 may output an L-level signal MEM1_PW. Here, the L-level signal is a potential (e.g., the potential VSS or a potential lower than the potential VSS) that turns off the transistor M14.

[0160] Alternatively, as another example of a method for stopping the supply of power to the first cache 111, the cache control unit 114 may send an instruction to the power control unit 122 to stop the supply of power to the first cache 111, and the power control unit 122 may stop the supply of power to the first cache 111 by receiving the instruction.

[0161] For example, the cache control unit 114 may stop the supply of a clock signal to the first cache 111. By stopping the supply of a clock signal to the first cache 111, it is possible to reduce the power consumption of the semiconductor device 100.

[0162] As an example of a method for stopping the supply of a clock signal to the first cache 111, the cache control unit 114 may send an instruction to the clock control unit 123 to stop the supply of a clock signal to the first cache 111, and the clock control unit 123 may stop the supply of a clock signal to the first cache 111 by receiving the instruction.

[0163] [Overheat State (Second Cache Mode)] After transitioning to the overheat state and switching to the second cache mode, as long as the overheat state continues, it is determined in step S03 that the system is in the overheat state. Then, in step S04, it is determined that the system is in the second cache mode (the first cache 111 is not valid).

[0164] That is, while the program processing is being executed in an overheated state, the semiconductor device 100 repeats steps S01, S02, S03, and S04 in order.

[0165] [Transition from Overheated State to Normal State (Switching from Second Cache Mode to First Cache Mode)] Continuing execution of program processing in an overheated state can cause the temperature T around or inside the core 115 to drop and become less than a predetermined temperature threshold Tth (temperature T is less than temperature threshold Tth). If the temperature T remains below temperature threshold Tth for a certain period of time, step S03 determines that the state is normal (not overheated). If the state is normal, the cache control unit 114 determines whether the second cache 112 is enabled (step S08). Immediately after transitioning from the overheated state to the normal state, the cache control unit 114 is in the second cache mode (the second cache 112 is enabled), so the cache control unit 114 switches from the second cache mode to the first cache mode (steps S09 to S11). After switching from the second cache mode to the first cache mode, the process returns to step S01.

[0166] Switching from the second cache mode to the first cache mode will now be described. First, the cache control unit 114 sends an interrupt request to the core 115, and upon receiving the request, the core 115 stops the currently running program processing (step S09). Next, the cache control unit 114 performs process B (processing for switching from the second cache mode to the first cache mode) (step S10). For example, the cache control unit 114 may perform control so that, upon receiving a read request from the core 115, it communicates with the first cache 111. Then, the cache control unit 114 sends an interrupt request to the core 115, and upon receiving the request, the core 115 resumes the stopped program processing (step S11).

[0167] The process B of step S10 will now be described (see FIG. 7B). In process B, the cache control unit 114 sets the second cache 112 to an invalid state and the first cache 111 to an valid state (step S31).

[0168] 2, the cache control unit 114 may output a signal MEM1_EN that turns on switches SW11 to SW13, a signal MEM1_PW that turns on switch SW14, and a signal MEM2_EN that turns off switches SW15 to SW17. Also, in FIG. 3, the cache control unit 114 may output a signal MEM1_EN at an H level, a signal MEM1_PW at an H level, and a signal MEM2_EN at an L level. Here, the H level is a potential at which transistors M11 to M14 are turned on (for example, potential VDD or a potential higher than potential VDD). Also, the L level is a potential at which transistors M15 to M17 are turned on (for example, potential VSS or a potential lower than potential VSS).

[0169] As a result, when the cache control unit 114 receives a read request from the core 115 , it exchanges the signals ADDR, DATA, and HIT with the first cache 111 .

[0170] Furthermore, the second cache 112 is no longer involved in the exchange of the signals ADDR, DATA, and HIT. In other words, the second cache 112 is no longer used to execute program processing. Therefore, for example, the cache control unit 114 may stop the supply of power to the second cache 112. Stopping the supply of power to the second cache 112 can reduce the power consumption of the semiconductor device 100.

[0171] 2, the cache control unit 114 may output a signal MEM2_PW that turns off the switch SW18. Alternatively, for example, in FIG. 3, the cache control unit 114 may output an L-level signal MEM2_PW. Here, the L-level signal is a potential (e.g., the potential VSS or a potential lower than the potential VSS) that turns off the transistor M18.

[0172] Alternatively, as another example of a method for stopping the supply of power to the second cache 112, the cache control unit 114 may send an instruction to the power control unit 122 to stop the supply of power to the second cache 112, and the power control unit 122 may stop the supply of power to the second cache 112 by receiving the instruction.

[0173] For example, the cache control unit 114 may stop the supply of a clock signal to the second cache 112. By stopping the supply of a clock signal to the second cache 112, it is possible to reduce the power consumption of the semiconductor device 100.

[0174] As an example of a method for stopping the supply of a clock signal to the second cache 112, the cache control unit 114 may send an instruction to the clock control unit 123 to stop the supply of a clock signal to the second cache 112, and the clock control unit 123 may stop the supply of a clock signal to the second cache 112 by receiving the instruction.

[0175] In this way, by switching between the first cache 111 and the second cache 112 depending on the temperature around or inside the core 115, it is possible to suppress a decrease in operating speed due to an increase in temperature of the semiconductor device 100.

[0176] <Operation Example 2> The operation of the semiconductor device 100 according to one aspect of the present invention is not limited to the above-described operation example. For example, in the flowchart shown in FIG. 6, process A (process of switching from the first cache mode to the second cache mode) is not limited to the flowchart shown in FIG. 7A. FIG. 8A is a flowchart illustrating another example of process A. Furthermore, in the flowchart shown in FIG. 6, process B (process of switching from the second cache mode to the first cache mode) is not limited to the flowchart shown in FIG. 7B. FIG. 8B is a flowchart illustrating another example of process B.

[0177] In the description of FIGS. 8A and 8B below, the same parts as those in FIGS. 7A and 7B may be omitted because the above description can be taken into consideration as appropriate.

[0178] 8A, first, the second cache 112 is set to a valid state (step S41). Next, information stored in the first cache 111 (e.g., data, addresses, attribute information, etc.) is copied to the second cache 112 (step S42). Then, the first cache 111 is set to an invalid state (step S43).

[0179] 2, the cache control unit 114 outputs a signal MEM2_EN that turns on switches SW15 to SW17 and a signal MEM2_PW that turns on switch SW18. This enables the cache control unit 114 to exchange signals ADDR, DATA, and HIT with the second cache.

[0180] Next, in step S42, for example, the cache control unit 114 may control the first cache 111 to read information (e.g., data, addresses, attribute information, etc.) stored in the first cache 111 via the signals ADDR, DATA, and HIT, and to write the read information to the second cache 112.

[0181] 2, the cache control unit 114 may output a signal MEM1_EN that turns off the switches SW11 to SW13. This causes the first cache 111 to not be involved in the exchange of the signals ADDR, DATA, and HIT. The cache control unit 114 may also output a signal EM1_PW that turns off the switch SW14. This stops the supply of power to the first cache 111, thereby reducing the power consumption of the semiconductor device 100.

[0182] 8A is adopted, information (e.g., data, addresses, attribute information, etc.) stored in the first cache 111 at the time the program processing is stopped in step S05 is copied to the second cache 112 in step S06. In other words, when the program processing is resumed in step S07, data for program processing by the core 115 will be stored in the second cache 112. Therefore, after the program processing is resumed, when the cache control unit 114 receives a read request from the core 115, the data can be exchanged with the second cache 112 without reading the data from the memory 141. This allows for an improvement in the operating speed of the semiconductor device 100.

[0183] 8B, first, the first cache 111 is set to a valid state (step S51). Next, information (e.g., data, addresses, attribute information, etc.) stored in the second cache 112 is copied to the first cache 111 (step S52). Then, the second cache 112 is set to an invalid state (step S53).

[0184] 2, the cache control unit 114 outputs a signal MEM1_EN that turns on switches SW11 to SW13 and a signal MEM1_PW that turns on switch SW14. This enables the cache control unit 114 to exchange signals ADDR, DATA, and HIT with the first cache.

[0185] Next, in step S52, for example, the cache control unit 114 may control the second cache 112 to read information (e.g., data, addresses, attribute information, etc.) stored in the second cache 112 from the second cache 112 via the signals ADDR, DATA, and HIT, and to write the read information to the first cache 111.

[0186] 2, the cache control unit 114 may output a signal MEM2_EN that turns off switches SW15 to SW17. This causes the second cache 112 to cease to be involved in the exchange of signals ADDR, DATA, and HIT. The cache control unit 114 may also output a signal EM2_PW that turns off switch SW18. This stops the supply of power to the second cache 112, thereby reducing the power consumption of the semiconductor device 100.

[0187] 8B is adopted, information (e.g., data, addresses, attribute information, etc.) stored in the second cache 112 at the time the program processing is stopped in step S09 is copied to the first cache 111 in step S10. In other words, when the program processing is resumed in step S11, data for program processing by the core 115 is stored in the first cache 111. Therefore, after the program processing is resumed, when the cache control unit 114 receives a read request from the core 115, the data can be exchanged with the first cache 111 without reading the data from the memory 141. This allows for an improvement in the operating speed of the semiconductor device 100.

[0188] The semiconductor device according to one embodiment of the present invention is not limited to the above description of the semiconductor device 100. At least part of the configuration examples, operation examples, and corresponding drawings described in this embodiment can be combined as appropriate with other configuration examples, operation examples, other drawings, and other embodiments described in this specification.

[0189] Second Embodiment In this embodiment, an example of mounting the above-described semiconductor device will be described.

[0190] 9 is a schematic diagram illustrating an example of a semiconductor device 170 according to one embodiment of the present invention. As illustrated in FIG. 9, the semiconductor device 170 includes a substrate 171. The substrate 171 is, for example, a substrate containing silicon. Note that the substrate 171 may also be a substrate containing a compound semiconductor such as silicon carbide or gallium nitride.

[0191] In the schematic diagram shown in Fig. 9, the Z direction is defined to facilitate understanding of the positional relationship between the elements constituting the semiconductor device 170. In Fig. 9, the Z direction is defined as a direction perpendicular or approximately perpendicular to the surface of the substrate 171. In the present embodiment and the like, "approximately perpendicular" refers to a state in which the angle between the two elements in question is 85 degrees or more and 95 degrees or less. In the present embodiment and the like, the Z direction may be referred to as the vertical direction to facilitate understanding.

[0192] A core region 185 and a memory region 181[0] are formed on one surface of the substrate 171. The core region 185 and the memory region 181[0] are regions where Si transistors (transistors containing silicon in the channel formation region) or circuits including Si transistors are provided.

[0193] One or more memory layers (memory layers 182[1] to 182[p] (p is a positive integer)) are stacked vertically over the core region 185. Each of the memory layers 182[1] to 182[p] is a layer in which an OS transistor (a transistor including an oxide semiconductor in a channel formation region) or a circuit including an OS transistor is provided.

[0194] Vias 172 are formed between the substrate 171 and each of the memory layers 182[1] to 182[p].

[0195] The substrate 171 and each of the memory layers 182[1] to 182[p] are electrically connected to each other via vias 172 formed therebetween. That is, the circuits provided on one side of the substrate 171 and the circuits provided on each of the memory layers 182[1] to 182[p] are electrically connected to each other via vias 172 formed therebetween. For example, the circuits provided on one side of the substrate 171 and the circuits provided on the memory layer 182[1] are electrically connected to each other via vias 172 formed between the substrate 171 and the memory layer 182[1]. Furthermore, the circuits provided on the memory layer 182[1] and the circuits provided on the memory layer 182[2] are electrically connected to each other via vias 172 formed between the memory layer 182[1] and the memory layer 182[2].

[0196] That is, the substrate 171 and the memory layers 182[1] to 182[p] are fabricated monolithically.

[0197] One or more dies (die 180[1] to die 180[q] (q is a positive integer)) are arranged stacked vertically above memory region 181[0]. Each of die 180[1] to die 180[q] is, for example, a silicon die.

[0198] In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into dices. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0199] Memory regions 181[1] to 181[q] are formed on one surface of each of the dies 180[1] to 180[q] in a one-to-one correspondence. Each of the memory regions 181[1] to 181[q] is a region where a Si transistor or a circuit including a Si transistor is provided.

[0200] An electrode 173 is formed on one surface of the substrate 171 and each of the dies 180[1] to 180[q] (i.e., on each of the memory regions 181[0] to 181[q]). An electrode 174 is formed on the other surface of each of the dies 180[1] to 180[q]. In each of the dies 180[1] to 180[q], a plug 175 that electrically connects the electrode 173 and the electrode 174 is formed penetrating the die. The plug 175 is, for example, a through silicon via (TSV).

[0201] The substrate 171 and each of the dies 180[1] to 180[q] are electrically connected to each other by joining an electrode 173 formed on one surface of the substrate 171 and each of the dies 180[1] to 180[q-1] to an electrode 174 formed on the other surface of each of the dies 180[1] to 180[q]. In other words, the circuits provided in each of the memory regions 181[0] to 181[q] are electrically connected to each other by joining an electrode 173 formed on one surface of the substrate 171 and each of the dies 180[1] to 180[q-1] to an electrode 174 formed on the other surface of each of the dies 180[1] to 180[q]. For example, by joining an electrode 173 formed on one surface of the substrate 171 and an electrode 174 formed on the other surface of the die 180[1], the circuit provided in the memory region 181[0] and the circuit provided in the memory region 181[1] are electrically connected to each other. Also, by joining an electrode 173 formed on one surface of the die 180[1] and an electrode 174 formed on the other surface of the die 180[2], the circuit provided in the memory region 181[1] and the circuit provided in the memory region 181[2] are electrically connected to each other.

[0202] It is preferable to use the same conductive material for electrodes 173 and 174. Examples of conductive materials for electrodes 173 and 174 include metal films containing elements selected from aluminum, chromium, copper, tantalum, tin, zinc, gold, silver, platinum, titanium, molybdenum, and tungsten, and metal nitride films containing the above elements (e.g., titanium nitride film, molybdenum nitride film, or tungsten nitride film). Copper is particularly preferable as the conductive material for electrodes 173 and 174. This allows for the application of Cu-Cu direct bonding technology (a technology for achieving electrical conductivity by connecting copper (Cu) electrodes together). Microbump bonding technology, in which microbumps are formed on electrodes 173 and 174 to bond them, may also be used.

[0203] For example, there may be cases where the electrode 173 does not need to be formed on the die 180[q].

[0204] Furthermore, for example, memory regions 181[1] to 181[q] may be formed on the other surface of each of the dies 180[1] to 180[q] in a one-to-one correspondence. In this case, for example, the electrode 173 and the plug 175 may not be formed on the die 180[q].

[0205] 9, for example, the substrate 171 and each of the dies 180[1] to 180[q] are arranged so that one surface and the other surface face each other, but this is not limited thereto. For example, at least one of the dies 180[1] to 180[q] may be arranged so that one surface or the other surface faces each other. In this case, for example, the electrodes 173 or the electrodes 174 are joined together to electrically connect them. Also, for example, the electrode 174 and the plug 175 may not be formed on the die 180[q].

[0206] The semiconductor device 170 described in this embodiment is an implementation example of the semiconductor device 100 described in the first embodiment. Therefore, the semiconductor device 170 can be configured such that, for example, a portion (e.g., a memory cell unit) of the first cache 111 included in the semiconductor device 100 is provided in memory regions 181[0] to 181[q], a portion (e.g., a memory cell unit) of the second cache 112 included in the semiconductor device 100 is provided in memory layers 182[1] to 182[p], and the core 115 included in the semiconductor device 100 is provided in a core region 185. Other components included in the semiconductor device 100 (e.g., a cache control unit 114 and a heat detection unit 116) may be provided on the substrate 171, for example.

[0207] That is, the semiconductor device 170 has a configuration in which, for example, the second cache 112 is stacked vertically on the core 115 provided on the substrate 171. This allows the second cache 112 to, for example, increase memory density and shorten signal delay time. The semiconductor device 170 also has a configuration in which, for example, the first cache 111 is provided on the dies 180[1] to 180[q] that are stacked vertically on the substrate 171. This allows the first cache 111 to, for example, increase memory density and shorten signal delay time. These features allow, for example, the semiconductor device 170 to be improved in operating speed and miniaturized.

[0208] Mounting Example 2 The mounting of the semiconductor device 170 according to one embodiment of the present invention is not limited to the above mounting example. Fig. 10 is a schematic diagram illustrating another mounting example of the semiconductor device 170.

[0209] In the description of FIG. 10 to be given later, the same parts as those in FIG. 9 may be omitted because the above description can be taken into consideration as appropriate.

[0210] 10, memory layers 182[1] to 182[p] are formed by stacking in the vertical direction above a core region 185 formed on a substrate 171. Furthermore, dies 180[1] to 180[q], on which memory regions 181[1] to 181[q] are formed, are arranged by stacking in the vertical direction above memory layer 182[p].

[0211] The memory layer 182[p] and the die 180[1] are electrically connected to each other by joining the electrode 173 formed on the memory layer 182[p] with the electrode 174 formed on the other surface of the die 180[1]. That is, the circuit provided in the memory layer 182[p] and the circuit provided in the memory region 181[1] are electrically connected to each other by joining the electrode 173 formed on the memory layer 182[p] with the electrode 174 formed on the other surface of the die 180[1].

[0212] 10 has a configuration in which, for example, the second cache 112 is provided stacked vertically above the core 115 provided on the substrate 171, and the first cache 111 is provided stacked vertically above the second cache 112. This allows the first cache 111 to, for example, increase the memory density and shorten the signal delay time. These features allow, for example, the operating speed of the semiconductor device 170 to be improved and the size to be reduced.

[0213] The memory layers 182[1] to 182[p] in which the second cache 112 is provided can have a function of reducing the influence of heat generated in the core 115 on the first cache 111.

[0214] Note that the semiconductor device according to one embodiment of the present invention is not limited to the above-described semiconductor device. At least part of the configuration examples and operation examples described in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples, operation examples, other drawings, and other embodiments described in this specification.

[0215] (Embodiment 3) In this embodiment, a structure of a transistor applicable to the semiconductor device described in the above embodiment will be described. As an example, a structure in which transistors having different electrical characteristics are stacked will be described. By using this structure, the degree of freedom in designing a semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the degree of integration of a semiconductor device can be increased.

[0216] 11 shows a part of a cross-sectional structure of a semiconductor device. The semiconductor device shown in FIG. 11 includes a transistor 550, a transistor 500, and a capacitor 600. FIG. 12A is a cross-sectional view of the transistor 500 in the channel length direction, FIG. 12B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 12C is a cross-sectional view of the transistor 550 in the channel width direction. For example, the transistor 500 corresponds to the OS transistor described in the above embodiment, and the transistor 550 corresponds to a Si transistor.

[0217] In FIG. 11, the transistor 500 is provided above the transistor 550 , and the capacitor 600 is provided above the transistor 550 and the transistor 500 .

[0218] The transistor 550 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 made of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions.

[0219] 12C , in the transistor 550, the top surface and the side surfaces in the channel width direction of the semiconductor region 313 are covered with a conductor 316 via an insulator 315. By forming the transistor 550 as a Fin type in this manner, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 550. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 550.

[0220] Note that the transistor 550 may be either a p-channel type or an n-channel type.

[0221] The transistor 550 preferably includes a semiconductor such as a silicon-based semiconductor, and preferably includes single-crystal silicon, in the region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as one of the source and drain regions, and the low-resistance region 314b that serves as the other of the source and drain regions. Alternatively, the transistor 550 may be formed of a material containing, for example, Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), or GaAlAs (gallium aluminum arsenide). Alternatively, the transistor 550 may be configured using silicon whose effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 550 may be a high electron mobility transistor (HEMT) using, for example, GaAs and GaAlAs.

[0222] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0223] The conductor 316 functioning as the gate electrode can be a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, or can be a conductive material such as a metal material, an alloy material, or a metal oxide material.

[0224] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0225] The transistor 550 may be formed using, for example, an SOI (Silicon on Insulator) substrate.

[0226] The SOI substrate may be a SIMOX (Separation by Implanted Oxygen) substrate formed by implanting oxygen ions into a mirror-polished wafer and then heating the wafer at a high temperature to form an oxide layer to a certain depth from the surface and eliminate defects that occur in the surface layer. Alternatively, an SOI substrate may be formed using, for example, a Smart Cut method in which a semiconductor substrate is cleaved by utilizing the growth of microvoids formed by hydrogen ion implantation through heat treatment, or an ELTRAN method (registered trademark: Epitaxial Layer Transfer). Note that a transistor formed using a single-crystal substrate has a single-crystal semiconductor in a channel formation region.

[0227] An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order to cover the transistor 550 .

[0228] The insulators 320, 322, 324, and 326 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

[0229] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0230] The insulator 322 may function as a planarizing film that planarizes a step caused by an underlying element such as the transistor 550. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0231] The insulator 324 is preferably a film having a barrier property that prevents diffusion of hydrogen, impurities, or the like from the substrate 311 or the transistor 550 to a region where the transistor 500 is provided.

[0232] As a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. For example, diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 550. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0233] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, in the TDS analysis, the amount of desorption of hydrogen from the insulator 324 is calculated as 1×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. and the amount of desorption converted into hydrogen atoms is 1×10 １６ atoms / cm ２ Below 5 × 10, preferably １５ atoms / cm ２ The following is fine.

[0234] The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0235] Furthermore, insulators 320, 322, 324, and 326 are embedded conductors, such as conductors 328 and 330, which connect to capacitor 600 or transistor 500. Conductors 328 and 330 function as plugs or wiring. Conductors that function as plugs or wiring may be collectively designated by the same reference numeral. In this specification and the like, a wiring and a plug electrically connected to the wiring may be integrated. That is, a portion of a conductor may function as a wiring, and a portion of a conductor may function as a plug.

[0236] The material for each plug or wiring (e.g., conductor 328 or conductor 330) can be, for example, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, as the material for the plug or wiring. Alternatively, it is preferable to form the plug or wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material for the plug or wiring can reduce the wiring resistance.

[0237] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 11 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 550. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0238] Note that, for example, the insulator 350 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer. Therefore, diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0239] Note that, for example, tantalum nitride or the like is preferably used as the conductor having a barrier property against hydrogen. Alternatively, a stack of tantalum nitride and tungsten, which has high conductivity, is preferably used. By using a stack of tantalum nitride and tungsten as the conductor 356, the conductor 356 can suppress diffusion of hydrogen from the transistor 550 while maintaining its conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer of the conductor 356 having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

[0240] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 11 , an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductor 366 can be provided using the same material as the conductors 328 and 330.

[0241] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer. Therefore, diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0242] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 11 , an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulators 370, 372, and 374. The conductor 376 functions as a plug or a wiring. The conductor 376 can be formed using the same material as the conductors 328 and 330.

[0243] Note that, for example, the insulator 370 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer. Therefore, diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0244] A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 11 , an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductor 386 can be provided using the same material as the conductors 328 and 330.

[0245] Note that, for example, the insulator 380 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer. Therefore, diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0246] Although the above description has been given of an example in which four wiring layers similar to the wiring layer including conductor 356 are formed, i.e., a wiring layer including conductor 356, a wiring layer including conductor 366, a wiring layer including conductor 376, and a wiring layer including conductor 386, the semiconductor device according to this embodiment is not limited to this. Three or fewer wiring layers similar to the wiring layer including conductor 356 may be formed, or five or more wiring layers similar to the wiring layer including conductor 356 may be formed.

[0247] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 384. Any of the insulators 510, 512, 514, and 516 is preferably formed using a substance that has a barrier property against, for example, oxygen, hydrogen, and the like.

[0248] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or a region where the transistor 550 is provided to a region where the transistor 500 is provided. Therefore, the insulator 510 and the insulator 514 can be formed using a material similar to that of the insulator 324.

[0249] As a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. For example, diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 550. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0250] As a film having a barrier property against hydrogen, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulators 510 and 514 .

[0251] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen or moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen or moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0252] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulators 512 and 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0253] For example, a conductor 518 and a conductor constituting the transistor 500 (for example, the conductor 503) are embedded in the insulators 510, 512, 514, and 516. Note that the conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be formed using a material similar to that of the conductors 328 and 330.

[0254] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 550 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0255] Above the insulator 516, the transistor 500 is provided.

[0256] As shown in Figures 12A and 12B, transistor 500 has a conductor 503 arranged so as to be embedded in insulator 514 and insulator 516, an insulator 520 arranged on insulator 516 and conductor 503, an insulator 522 arranged on insulator 520, an insulator 524 arranged on insulator 522, an oxide 530a arranged on insulator 524, an oxide 530b arranged on oxide 530a, conductors 542a and 542b arranged apart from each other on oxide 530b, an insulator 580 arranged on conductors 542a and 542b and having an opening formed therein overlapping with conductors 542a and 542b, an insulator 545 arranged on the bottom and side surfaces of the opening, and a conductor 560 arranged on the surface on which insulator 545 is formed.

[0257] 12A and 12B, it is preferable that an insulator 544 be disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. Also, as shown in FIGS. 12A and 12B, it is preferable that the conductor 560 has a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. Also, as shown in FIGS. 12A and 12B, it is preferable that an insulator 574 be disposed on the insulator 580, the conductor 560, and the insulator 545.

[0258] In this specification and the like, the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.

[0259] Note that although the transistor 500 has a structure in which two layers of the oxide 530a and the oxide 530b are stacked in the region where a channel is formed and in the vicinity thereof, one embodiment of the present invention is not limited to this structure. For example, a single layer of the oxide 530b or a stacked structure of three or more layers may be provided in the region where a channel is formed and in the vicinity thereof.

[0260] Although the transistor 500 has a two-layer structure, one embodiment of the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 illustrated in FIGS. 11 and 12A is merely an example and is not limited to this structure. For example, an appropriate transistor may be used depending on the circuit configuration, driving method, or the like.

[0261] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode and drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductor 560 and the conductors 542a and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductor 560 can be formed without providing a margin for alignment. This allows the area occupied by the transistor 500 to be reduced. This allows for miniaturization and high integration of semiconductor devices.

[0262] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0263] Here, the conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0264] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered.

[0265] In this specification, a transistor structure in which a channel formation region is electrically surrounded by the electric field of a first gate electrode is called a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification is different from the Fin structure and the planar structure. On the other hand, the S-channel structure disclosed in this specification can also be considered a type of Fin structure. In this specification, the Fin structure refers to a structure in which the gate electrode is arranged to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By employing the Fin structure and the S-channel structure, a transistor can be obtained that has improved resistance to the short channel effect. In other words, a transistor that is less susceptible to the short channel effect can be obtained.

[0266] By forming the transistor in the S-channel structure, the channel formation region can be electrically surrounded. Note that the S-channel structure electrically surrounds the channel formation region, and therefore, can be said to be substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By forming the transistor in the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the gate insulator can be the entire bulk of the oxide 530. Therefore, the current density flowing through the transistor can be improved, thereby realizing an improvement in the on-state current of the transistor or an improvement in the field-effect mobility of the transistor.

[0267] The conductor 503 has a structure similar to that of the conductor 518, in which the conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is formed further inside. Note that although the transistor 500 shows a structure in which the conductors 503a and 503b are stacked, one embodiment of the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0268] Here, the conductor 503a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, or copper atoms (i.e., the impurities are less likely to permeate through it). Alternatively, the conductor 503a is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (i.e., the oxygen is less likely to permeate through it). Note that in this specification and the like, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities or the oxygen.

[0269] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, which can suppress the conductor 503b from being oxidized and causing a decrease in conductivity.

[0270] Furthermore, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that, although the conductor 503 is illustrated as a stack of the conductors 503a and 503b in this embodiment, the conductor 503 may have a single-layer structure.

[0271] The insulators 520, 522, and 524 function as a second gate insulating film.

[0272] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. The oxygen is easily released from the film by heating. In this specification and the like, oxygen released by heating may be referred to as "excess oxygen." That is, the insulator 524 preferably has a region containing excess oxygen (also referred to as an "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (V Ｏ When hydrogen enters an oxygen vacancy in the oxide 530, the defect (hereinafter referred to as V Ｏ H.) may function as a donor and generate electrons as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated. In one embodiment of the present invention, V in the oxide 530 Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. ＯTo obtain an oxide semiconductor in which H is sufficiently reduced, it is important to remove impurities such as moisture or hydrogen from the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also referred to as "oxygenation treatment"). Ｏ When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0273] Specifically, it is preferable to use an oxide material from which part of oxygen is released by heating as an insulator having an excess oxygen region. The oxide from which oxygen is released by heating is an oxide from which the amount of released oxygen converted into oxygen atoms obtained by TDS (Thermal Desorption Spectroscopy) analysis is 1.0 × 10 １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0 × 10 １９ atoms / cm ３ or more, or 3.0 x 10 ２０ atoms / cm ３ The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0274] Furthermore, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the VoH bond, resulting in dehydrogenation. In other words, in the oxide 530, "V Ｏ The reaction "H → Vo + H" occurs, and dehydrogenation can be achieved. Some of the hydrogen generated at this time is combined with oxygen to form H ２As O, hydrogen may be removed from the oxide 530 or from the insulator near the oxide 530. Also, some of the hydrogen may be gettered to one or both of the conductor 542a and the conductor 542b.

[0275] Furthermore, the microwave treatment is preferably performed using, for example, an apparatus having a power supply for generating high-density plasma or an apparatus having a power supply for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530. The microwave treatment may be performed under a pressure of 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. For example, oxygen and argon are used as gases to be introduced into the microwave treatment apparatus, and the oxygen flow ratio (O ２ / (O ２ +Ar)) is preferably 50% or less, and more preferably 10% or more and 30% or less.

[0276] Furthermore, during the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 450° C., more preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V Ｏ ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0277] By performing oxygen addition treatment on the oxide 530, oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "Vo + O → null" can be promoted. Furthermore, the hydrogen remaining in the oxide 530 reacts with the supplied oxygen, converting the hydrogen into H ２ As a result, hydrogen remaining in the oxide 530 is recombined with the oxygen vacancies to form V. Ｏ The formation of H can be suppressed.

[0278] Furthermore, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (the oxygen is less likely to permeate).

[0279] The insulator 522 preferably has a function of suppressing diffusion of, for example, oxygen or impurities, so that oxygen contained in the oxide 530 does not diffuse toward the insulator 520. Furthermore, reaction of the conductor 503 with oxygen contained in, for example, the insulator 524 or the oxide 530 can be suppressed.

[0280] It is preferable to use a high-dielectric-constant (high-k) material (material with a high relative dielectric constant) for the insulator 522. Examples of the insulator 522 include aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), and strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３ It is preferable to use an insulator containing, for example, BST in a single layer or a multilayer structure. As transistors become smaller and more highly integrated, the thinning of the gate insulating film can cause problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0281] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., the oxygen is less likely to permeate). Examples of the insulator containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 or the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0282] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0283] Furthermore, it is preferable that the insulator 520 be thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable layered structure with a high dielectric constant.

[0284] 12A and 12B , the second gate insulating film has a three-layer structure including the insulators 520, 522, and 524. However, the second gate insulating film may have a single-layer structure, a two-layer structure, or a four- or more-layer structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material and may have a stack structure made of different materials.

[0285] In the transistor 500, a metal oxide functioning as an oxide semiconductor is used for the oxide 530 including the channel formation region. For example, a metal oxide containing indium, M (M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc may be used as the oxide 530.

[0286] The metal oxide functioning as an oxide semiconductor may be formed by a sputtering method or an atomic layer deposition (ALD) method. Note that the metal oxide functioning as an oxide semiconductor will be described in detail in another embodiment.

[0287] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. In this manner, by using a metal oxide with a wide band gap for the oxide 530, the off-state current of the transistor 500 can be reduced.

[0288] By having oxide 530a below oxide 530b, oxide 530 can suppress the diffusion of impurities from components formed below oxide 530a to oxide 530b.

[0289] The oxide 530 preferably has a configuration of multiple oxide layers with different atomic ratios of the metal atoms. Specifically, the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. Furthermore, the atomic ratio of the element M to In in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Furthermore, the atomic ratio of In to M in the metal oxide used for the oxide 530b is preferably larger than the atomic ratio of In to M in the metal oxide used for the oxide 530a.

[0290] The oxide 530a preferably has a conduction band minimum energy higher than that of the oxide 530b, or in other words, the oxide 530a preferably has a lower electron affinity than that of the oxide 530b.

[0291] Here, the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes gradually. In other words, the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes continuously, or the junction has a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0292] Specifically, when the oxide 530a and the oxide 530b have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In—Ga—Zn oxide, an In—Ga—Zn oxide, or a gallium oxide can be used as the oxide 530a.

[0293] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a as described above, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0294] Conductors 542a and 542b, which function as source and drain electrodes, are provided on the oxide 530b. For the conductors 542a and 542b, it is preferable to use, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen.Furthermore, for example, a metal nitride film such as tantalum nitride is preferred because it has barrier properties against hydrogen or oxygen.

[0295] 12A shows the conductors 542a and 542b as single-layer structures, but they may also have a stacked structure of two or more layers. The conductors 542a and 542b may be, for example, stacks of a tantalum nitride film and a tungsten film. The conductors 542a and 542b may also be, for example, stacks of a titanium film and an aluminum film. The conductors 542a and 542b may also be, for example, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film.

[0296] The conductors 542a and 542b may have a three-layer structure in which an aluminum film or a copper film is stacked on a titanium film or a titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, or a three-layer structure in which an aluminum film or a copper film is stacked on a molybdenum film or a molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is further formed thereon, etc. Note that the conductors 542a and 542b may be made of a transparent conductive material containing, for example, indium oxide, tin oxide, or zinc oxide.

[0297] 12A , regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source and drain regions, and the region 543b functions as the other of the source and drain regions. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0298] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Furthermore, a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and a component of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0299] The insulator 544 is provided to cover the conductors 542 a and 542 b and suppresses oxidation of the conductors 542 a and 542 b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0300] The insulator 544 can be, for example, a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be, for example, silicon nitride oxide, silicon nitride, or the like.

[0301] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), as the insulator 544. Hafnium aluminate is particularly preferable because it has higher heat resistance than a hafnium oxide film. Therefore, it is less likely to crystallize during heat treatment in a later process. Note that if the conductors 542a and 542b are made of oxidation-resistant materials or materials whose conductivity does not decrease significantly even when they absorb oxygen, the insulator 544 is not an essential component. The insulator 544 may be designed appropriately depending on the desired transistor characteristics.

[0302] The insulator 544 can prevent impurities such as water or hydrogen contained in the insulator 580 from diffusing into the oxide 530b. The insulator 580 can also prevent excess oxygen from being contained in the conductor 542a and the conductor 542b from being oxidized.

[0303] The insulator 545 functions as a first gate insulating film. Like the insulator 524, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating.

[0304] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies can be used. In particular, silicon oxide or silicon oxynitride is preferable because it is stable against heat.

[0305] By providing an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b. Similar to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 545 is preferably reduced. The thickness of the insulator 545 is preferably 1 nm to 20 nm.

[0306] Furthermore, in order to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion between the insulator 545 and the conductor 560, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. In other words, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0307] Note that the insulator 545 may have a layered structure, similar to the second gate insulating film. As transistors become more miniaturized and highly integrated, thinner gate insulating films can cause problems such as leakage current. Therefore, by forming the insulator 545, which functions as a gate insulating film, with a layered structure of a high-k material and a thermally stable material, it is possible to maintain the physical film thickness of the insulator 545 and reduce the gate potential during operation of the transistor 500. Furthermore, the insulator 545 can have a layered structure that is thermally stable and has a high dielectric constant.

[0308] The conductor 560 functioning as the first gate electrode is shown as a two-layer structure (conductor 560a and conductor 560b) in Figures 12A and 12B, but it may be a single-layer structure or a stacked structure of three or more layers.

[0309] The conductor 560a may be, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (e.g., N ２ O, NO, or NO ２ It is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms or copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). The conductor 560a has the function of suppressing oxygen diffusion, which can suppress the oxidation of the conductor 560b due to the oxygen contained in the insulator 545, thereby preventing a decrease in conductivity. For example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used as the conductive material that has the function of suppressing oxygen diffusion. Furthermore, an oxide semiconductor that can be used for the oxide 530 can be used as the conductor 560a. In this case, the electrical resistance of the conductor 560a can be reduced by forming the conductor 560b by a sputtering method, thereby making the conductor 560a a conductor. This can be called an oxide conductor (OC) electrode.

[0310] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure. For example, the conductor 560b may have a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0311] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. The insulator 580 preferably includes, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or a resin. Silicon oxide or silicon oxynitride is particularly preferred because it is thermally stable. Silicon oxide or silicon oxide having voids is particularly preferred because it allows for easy formation of an excess oxygen region in a later step.

[0312] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0313] The opening of the insulator 580 is formed to overlap the region between the conductor 542 a and the conductor 542 b, so that the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542 a and the conductor 542 b.

[0314] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to ensure that the conductivity of the conductor 560 does not decrease. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0315] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0316] The insulator 574 may be, for example, a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium.

[0317] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as an oxygen source as well as a barrier film against impurities such as hydrogen.

[0318] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. The insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen, similar to the insulator 524, for example.

[0319] Furthermore, conductors 540a and 540b are arranged in openings formed in insulators 581, 574, 580, and 544. Conductor 540a and 540b are arranged opposite each other with conductor 560 interposed therebetween. Conductor 540a and 540b have the same configuration as conductors 546 and 548, which will be described later.

[0320] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably formed using a substance that has a barrier property against oxygen, hydrogen, and the like. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514. The insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0321] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen or moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen or moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0322] An insulator 586 is provided over the insulator 582. The insulator 586 can be made of a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film or a silicon oxynitride film can be used as the insulator 586.

[0323] Furthermore, for example, conductors 546 and 548 are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0324] The conductor 546 and the conductor 548 function as plugs or wirings that connect to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be formed using the same material as the conductor 328 and the conductor 330.

[0325] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator with high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be collectively surrounded by an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, it is preferable to form an opening that reaches the insulator 522 or the insulator 514 and form the insulator with high barrier properties in contact with the insulator 522 or the insulator 514, because this can serve as part of the manufacturing process of the transistor 500. For example, the insulator with high barrier properties against hydrogen or water may be made of a material similar to that of the insulator 522 or the insulator 514.

[0326] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0327] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0328] For example, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, or tungsten nitride film), can be used for the conductor 612 and the conductor 610. Alternatively, for example, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with silicon oxide added can be used for the conductor 612 and the conductor 610.

[0329] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but are not limited to this structure, and the conductor 612 and the conductor 610 may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0330] The conductor 620 is provided to overlap the conductor 610 with the insulator 630 interposed therebetween. The conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. The conductor 620 is preferably formed using a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. When the conductor 620 is formed simultaneously with other components such as other conductors, a low-resistance metal material such as copper or aluminum may be used.

[0331] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be provided using a material similar to that of the insulator 320. The insulator 640 may also function as a planarizing film that covers the uneven shape below it.

[0332] With this structure, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.

[0333] Examples of a substrate that can be used for the semiconductor device of one embodiment of the present invention include a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate (e.g., a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, or a substrate having tungsten foil), a semiconductor substrate (e.g., a single-crystal semiconductor substrate, a polycrystalline semiconductor substrate, or a compound semiconductor substrate), and an SOI (Silicon-on-Insulator) substrate. A plastic substrate having heat resistance that can withstand the treatment temperature of this embodiment may also be used as the substrate. Examples of glass substrates include barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass, and soda-lime glass. Other examples of glass substrates that can be used include crystallized glass.

[0334] In addition, the substrate can be, for example, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of flexible substrates, laminated films, or base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or polytetrafluoroethylene (PTFE). Other examples include synthetic resins such as acrylic. Other examples include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Other examples include polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor deposition film, or paper. In particular, by manufacturing transistors using, for example, a semiconductor substrate, a single-crystal substrate, or an SOI substrate, it is possible to manufacture transistors with small size, high current capacity, and little variation in characteristics, size, or shape. Constructing a circuit using such transistors can reduce the power consumption of the circuit or increase the circuit integration.

[0335] Alternatively, a flexible substrate may be used as the substrate, and one or more of, for example, a transistor, a resistor, and a capacitor may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and one or more of, for example, a transistor, a resistor, and a capacitor. The release layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate and transfer the device to another substrate. In this case, for example, one or more of the transistor, the resistor, and the capacitor can be transferred to a substrate with poor heat resistance or a flexible substrate. Note that the release layer may be, for example, a laminated structure of an inorganic film such as a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on a substrate, or a silicon film containing hydrogen.

[0336] That is, a semiconductor device may be formed on a certain substrate and then transferred to another substrate. Examples of substrates onto which a semiconductor device may be transferred include, in addition to the substrates on which the above-described transistors can be formed, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including, for example, natural fibers (silk, cotton, or hemp), synthetic fibers (nylon, polyurethane, or polyester), or recycled fibers (acetate, cupra, rayon, or recycled polyester)), leather substrates, and rubber substrates. By using these substrates, it is possible to manufacture a flexible semiconductor device or a semiconductor device that is not easily broken. It is also possible to impart heat resistance to the semiconductor device. It is also possible to reduce the weight or thickness of the semiconductor device.

[0337] By providing a semiconductor device over a flexible substrate, an increase in weight can be suppressed and a semiconductor device that is less likely to be damaged can be provided.

[0338] 11 is just an example and is not limited to the structure thereof, and an appropriate transistor may be used depending on, for example, the circuit structure, the driving method, etc. For example, when the semiconductor device is a unipolar circuit including only OS transistors (for example, a circuit including only n-channel transistors or a circuit including only p-channel transistors), the structure of the transistor 550 may be the same as that of the transistor 500.

[0339] The configuration, structure, method, or the like described in this embodiment can be used in appropriate combination with the configuration, structure, method, or the like described in other embodiments.

[0340] Embodiment 4 In this embodiment, cross-sectional structure examples of memory devices including the OS transistors described in the above embodiments, such as DOSRAM and NOSRAM, will be described.

[0341] 13 shows a cross-sectional configuration example when a DOSRAM circuit configuration is used. In FIG. 13, a case where memory layers 700[1] to 700[4] are stacked on a driver circuit layer 701 is illustrated.

[0342] 13 illustrates a transistor 550 included in the driver circuit layer 701. The transistor 550 described in the above embodiment can be applied to the transistor 550. Therefore, the description of the transistor 550 can be referred to as appropriate.

[0343] Note that the transistor 550 illustrated in FIG. 13 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or the driving method.

[0344] For example, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between the drive circuit layer 701 and the memory layer 700, or between the kth memory layer 700 and the (k+1)th memory layer 700. Note that in the present embodiment and the like, the kth memory layer 700 may be referred to as memory layer 700[k], and the k+1th memory layer 700 may be referred to as memory layer 700[k+1]. Here, k is an integer of 1 or greater.

[0345] Furthermore, multiple wiring layers can be provided depending on the design. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as the wiring and a part of the conductor may function as the plug.

[0346] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 550. A conductor 328, for example, is embedded in the insulators 320 and 322. A conductor 330, for example, is embedded in the insulators 324 and 326. The conductors 328 and 330 function as contact plugs or wirings.

[0347] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 320 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0348] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 13 , an insulator 350, an insulator 357, an insulator 352, and an insulator 354 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulator 350, the insulator 357, and the insulator 352. The conductor 356 functions as a contact plug or a wiring.

[0349] The insulator 514 of the memory layer 700[1] is provided on the insulator 354. A conductor 358 is embedded in the insulator 514 and the insulator 354. The conductor 358 functions as a contact plug or a wiring. For example, the bit line BL and the transistor 550 are electrically connected via the conductor 358, the conductor 356, the conductor 330, and the like.

[0350] Fig. 14A shows an example of the cross-sectional structure of the memory layer 700[k]. Fig. 14B shows an equivalent circuit diagram of Fig. 14A. Fig. 14A shows an example in which two memory cells MC are electrically connected to one bit line BL.

[0351] 13, 14A, and 14B includes a transistor M1 and a capacitor C. The transistor M1 can be, for example, the transistor 500 described in the above embodiment. Therefore, the above description of the transistor 500 can be referred to as appropriate.

[0352] Note that in this embodiment, the transistor M1 is a modified example of the transistor 500. Specifically, the transistor M1 differs from the transistor 500 in that the conductors 542a and 542b extend beyond the ends of the metal oxide 531 (the oxides 531a and 531b).

[0353] 13, 14A, and 14B correspond to the memory cells MC shown in Fig. 5D in the above embodiment, for example, and therefore the description of Fig. 5D above can be taken into consideration as appropriate.

[0354] 13 and 14A includes a conductor 156 that functions as one terminal of a capacitance C, an insulator 153 that functions as a dielectric, and a conductor 160 (conductor 160a and conductor 160b) that functions as the other terminal of the capacitance C. The conductor 156 is electrically connected to a portion of the conductor 542b. The conductor 160 is also electrically connected to a wiring PL (not shown in FIG. 14A).

[0355] One of the source and drain of the transistor M1 is electrically connected to a part of the conductor 542b. The other of the source and drain of the transistor M1 is electrically connected to a part of the conductor 542a. The gate of the transistor M1 is electrically connected to the word line WL. A part of the conductor 542a is electrically connected to the bit line BL.

[0356] The capacitor C is formed in an opening provided by removing a portion of the insulator 574, the insulator 580, and the insulator 554. The conductor 156, the insulator 580, and the insulator 554 are formed along the side surfaces of the openings, and therefore are preferably formed by, for example, an ALD method, a CVD method, or the like.

[0357] The conductor 156 and the conductor 160 may be made of a conductor that can be used for the conductor 505 or the conductor 560. For example, titanium nitride formed by an ALD method may be used as the conductor 156. Titanium nitride formed by an ALD method may be used as the conductor 160a, and tungsten formed by a CVD method may be used as the conductor 160b. Note that if the adhesion of tungsten to the insulator 153 is sufficiently high, a single layer film of tungsten formed by a CVD method may be used as the conductor 160.

[0358] It is preferable to use a high-dielectric constant (high-k) material (material with a high relative dielectric constant) for the insulator 153. For example, an oxide, oxynitride, oxynitride, or nitride containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium can be used as the high-dielectric constant insulator. Silicon may also be contained in the above oxide, oxynitride, oxynitride, or nitride. Furthermore, a stack of insulating layers made of the above materials can also be used as the high-dielectric constant insulator.

[0359] Furthermore, examples of high-dielectric-constant insulators that can be used include aluminum oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, oxides containing silicon and zirconium, oxynitrides containing silicon and zirconium, oxides containing hafnium and zirconium, and oxynitrides containing hafnium and zirconium. By using such high-dielectric-constant materials, the insulator 153 can be made thick enough to suppress leakage current and also ensure a sufficient electrostatic capacitance of the capacitance C.

[0360] Furthermore, it is preferable to use a laminate of insulating layers made of the above materials as the insulator 153, and it is preferable to use a laminate structure of a high-dielectric-constant material and a material having a higher dielectric strength than the high-dielectric-constant material. For example, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used as the insulator 153. Alternatively, for example, an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used. Alternatively, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order can be used. By using a laminate of an insulator with a relatively high dielectric strength, such as aluminum oxide, as the insulator 153, the dielectric strength is improved and electrostatic breakdown of the capacitance C can be suppressed.

[0361] Fig. 15 shows an example of a cross-sectional configuration when a circuit configuration of a NOSRAM memory cell is used. Note that Fig. 15 is also a modified example of Fig. 13. Fig. 16A shows an example of a cross-sectional structure of a memory layer 700[k]. Fig. 16B shows an equivalent circuit diagram of Fig. 16A.

[0362] 15, 16A, and 16B correspond to the memory cell MC shown in Fig. 5F in the above embodiment, for example. Therefore, the above description of Fig. 5F can be appropriately referred to.

[0363] 15 and 16A has a transistor M1, a transistor M2, and a transistor M3 on an insulator 514. In addition, a conductor 215 is provided so as to be embedded in an insulator 516 on the insulator 514. The conductor 215 can be formed simultaneously with the conductor 505 using the same material and in the same process.

[0364] 15 and 16A share one island-shaped metal oxide 531. In other words, part of the island-shaped metal oxide 531 functions as a channel formation region for the transistor M2, and another part functions as a channel formation region for the transistor M3. The source of the transistor M2 and the drain of the transistor M3, or the drain of the transistor M2 and the source of the transistor M3, are shared. Therefore, the area occupied by the transistors M2 and M3 is smaller than when the transistors M2 and M3 are provided independently.

[0365] 15 and 16A, an insulator 287 is provided on an insulator 581, and a conductor 161 is embedded in the insulator 287. An insulator 514 of a memory layer 700[k+1] is provided on the insulator 287 and the conductor 161.

[0366] A region where a part of the conductor 161 in the memory layer 700[k] and a part of the conductor 215 in the memory layer 700[k+1] overlap with each other via the insulator 514 functions as a capacitance C. That is, the conductor 161 in the memory layer 700[k] functions as one terminal of the capacitance C, the insulator 514 in the memory layer 700[k+1] functions as a dielectric of the capacitance C, and the conductor 215 in the memory layer 700[k+1] functions as the other terminal of the capacitance C. One of the source and drain of the transistor M1 is electrically connected to the conductor 161 through a contact plug, and the gate of the transistor M2 is electrically connected to the conductor 161 through another contact plug. The conductor 161 functions as a charge retention node FN. The conductor 215 is electrically connected to the wiring PL.

[0367] The other of the source or drain of transistor M1 is electrically connected to bit line WBL. The gate of transistor M1 is electrically connected to word line WWL. The other of the source or drain of transistor M2 is electrically connected to the other of the source or drain of transistor M3 by sharing metal oxide 531. The other of the source or drain of transistor M2 is electrically connected to source line SL (not shown in FIG. 16A ). The other of the source or drain of transistor M3 is electrically connected to bit line RBL. The gate of transistor M3 is electrically connected to word line RWL.

[0368] This embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification and the like.

[0369] Embodiment 5 In this embodiment, an example of a chip including a semiconductor device according to one embodiment of the present invention and an example of a module for an electronic device will be described.

[0370] FIG. 17A is a perspective view showing a cross-sectional structure of a package using a lead frame type interposer.

[0371] 17A , a chip 751 corresponding to a semiconductor device according to one embodiment of the present invention is connected to terminals 752 on an interposer 750 by wire bonding. The terminals 752 are arranged on the surface of the interposer 750 on which the chip 751 is mounted. The chip 751 may be sealed with a mold resin 753, with each terminal 752 being sealed in a state where a portion of the chip 751 is exposed.

[0372] The configuration of an electronic device module in which a package is mounted on a circuit board is shown in FIG. 17B.

[0373] 17B, ​​a package 802 and a battery 804 are mounted on a printed wiring board 801. The printed wiring board 801 is mounted by an FPC 803 on a panel 800 provided with a display element.

[0374] The structure or the like described in this embodiment can be used in appropriate combination with the structure or the like described in other embodiments or the like.

[0375] (Embodiment 6) The semiconductor device according to one embodiment of the present invention can be used in a display device, a personal computer, or an image playback device including a recording medium (typically, a device having a display that can play back a recording medium such as a digital versatile disc (DVD) and display the image). Other examples of electronic devices that can use the semiconductor device according to one embodiment of the present invention include mobile phones, game consoles including portable ones, personal digital assistants, e-book readers, cameras (e.g., video cameras and digital still cameras), goggle displays (head-mounted displays), navigation systems, audio playback devices (e.g., car audio systems and digital audio players), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs), and vending machines. Specific examples of these electronic devices are shown in FIGS. 18A to 18F .

[0376] 18A illustrates a portable game console, which includes, for example, a housing 5001, a housing 5002, a display portion 5003, a display portion 5004, a microphone 5005, a speaker 5006, operation keys 5007, and a stylus 5008. A semiconductor device according to one embodiment of the present invention can be used for various integrated circuits included in the portable game console. Note that although the portable game console illustrated in FIG. 18A includes two display portions, 5003 and 5004, the number of display portions included in the portable game console is not limited to this.

[0377] 18B illustrates a portable information terminal including, for example, a first housing 5601, a second housing 5602, a first display portion 5603, a second display portion 5604, a connection portion 5605, and operation keys 5606. The first display portion 5603 is provided in the first housing 5601, and the second display portion 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected to each other by the connection portion 5605, and the angle between the first housing 5601 and the second housing 5602 can be changed by the connection portion 5605. An image displayed on the first display portion 5603 may be switched depending on the angle between the first housing 5601 and the second housing 5602 at the connection portion 5605. A semiconductor device according to one embodiment of the present invention can be used for various integrated circuits included in the portable information terminal. A display device having a function as a position input device may be used for at least one of the first display portion 5603 and the second display portion 5604. The function as the position input device can be added by providing a touch panel to the display device. Alternatively, the function as the position input device can be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device.

[0378] 18C illustrates a laptop computer including, for example, a housing 5401, a display portion 5402, a keyboard 5403, and a pointing device 5404. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits included in the laptop computer.

[0379] 18D illustrates an electric refrigerator-freezer, which includes, for example, a housing 5301, a refrigerator door 5302, and a freezer door 5303. A semiconductor device according to one embodiment of the present invention can be used for various integrated circuits included in the electric refrigerator-freezer.

[0380] 18E illustrates a video camera including, for example, a first housing 5801, a second housing 5802, a display portion 5803, operation keys 5804, a lens 5805, and a connecting portion 5806. The operation keys 5804 and the lens 5805 are provided in the first housing 5801, and the display portion 5803 is provided in the second housing 5802. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits included in the video camera. The first housing 5801 and the second housing 5802 are connected by the connecting portion 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connecting portion 5806. An image displayed on the display portion 5803 may be switched depending on the angle between the first housing 5801 and the second housing 5802 at the connecting portion 5806.

[0381] 18F illustrates an automobile including, for example, a body 5101, wheels 5102, a dashboard 5103, and a light 5104. A semiconductor device according to one embodiment of the present invention can be used for various integrated circuits included in the automobile.

[0382] The configuration, structure, method, or the like described in this embodiment can be used in appropriate combination with the configuration, structure, method, or the like described in other embodiments.

[0383] 100: semiconductor device, 111: first cache, 112: second cache, 113: cache unit, 114: cache control unit, 115: core, 116: heat detection unit, 117: bus, 121: memory control unit, 122: power supply control unit, 123: clock control unit, 131: temperature sensor, 141: memory, SW11: switch, SW12: switch, SW13: switch, SW14: switch, SW15: switch, SW16: switch, SW17: switch, SW18: switch, ADDR: signal, DATA: signal, HIT: signal, MEM1_EN: signal, ME M2_EN: signal, MEM1_PW: signal, MEM2_PW: signal, VSS: potential, VDD: potential, M11: transistor, M12: transistor, M13: transistor, M14: transistor, M15: transistor, M16: transistor, M17: transistor, M18: transistor, 300: memory device, 21: memory cell unit, 90: memory cell array, MC: memory cell, 22: driver circuit unit, 62: PSW, 63: PSW, 71: peripheral circuit, 72: control circuit, 73: voltage generation circuit, 81: peripheral circuit, 82: row decoder, 83: row driver driver, 84: column decoder, 85: column driver, 87: input circuit, 88: output circuit, 51: driver circuit, 55: sense amplifier, WDA: signal, RDA: signal, BW: signal, CE: signal, GW: signal, CLK: signal, WAKE: signal, PON1: signal, PON2: signal, Din: data, Dout: data, VHM: potential, 91: word line driver circuit, 92: bit line driver circuit, M1: transistor, M2: transistor, M3: transistor, C: capacitance, FN: charge retention node, CL: capacitance line, WL: word line, WWL: word line, RWL: word line, BL: Bit line, WBL: bit line, RBL: bit line, BGL: back gate line, S01: step, S02: step, S03: step, S04: step, S05: step, S06: step, S07: step, S08: step, S09: step, S10: step, S11: step, S21: step, S31: step, S41: step, S42: step, S43: step, S51: step, S52: step, S53: step, 170: semiconductor device, 171: substrate, 180: die, 181: memory region, 182: memory layer,185: core region, 172: via, 173: electrode, 174: electrode, 175: plug, 311: substrate, 500: transistor, 550: transistor, 600: capacitor,

Claims

1. It comprises a first cache, a second cache, a cache control unit, and a core. The aforementioned core has the function of performing program processing, The cache control unit has a function to control the storage of data for program processing in the second cache when the temperature around or inside the core is above a predetermined temperature threshold. The cache control unit has a function to control the storage of data for program processing in the first cache when the temperature around or inside the core is below a predetermined temperature threshold. The first cache in the IV includes a Si transistor, The aforementioned second cache includes an OS transistor, Semiconductor equipment.

2. In claim 1, The device comprises a substrate, a layer on the substrate, and a die on the substrate, The core is provided on the substrate, A portion of the first cache is provided on the die, A portion of the second cache is provided in the layer, The layer is electrically connected to the substrate via vias formed between the substrate and the layer. The die is electrically connected to the substrate by a first electrode formed on the substrate and a second electrode formed on the die being joined together. Semiconductor equipment.

3. In claim 1, The device comprises a substrate, a layer on the substrate, and a die on the layer, The core is provided on the substrate, A portion of the first cache is provided on the die, A portion of the second cache is provided in the layer, The layer is electrically connected to the substrate via vias formed between the substrate and the layer. The die is electrically connected to the layer by a first electrode formed in the layer and a second electrode formed in the die being joined together. Semiconductor equipment.