Semiconductor device and switching power supply

Abstract

A semiconductor device 10 comprises: a first driver 162 for driving an output element M1 which forms a switch output stage SWO; at least a part of a bootstrap circuit BST for generating a boot voltage Vb higher than a switch voltage Vsw outputted from the switch output stage SWO, and supplying the boot voltage Vb to the first driver 162; and a boot voltage detection circuit 1E for detecting that a difference value (Vb-Vsw) between the boot voltage Vb and the switch voltage Vsw has become lower than a lower limit detection value when the output element M1 is in the off-state, and performing charging with the boot voltage Vb. The boot voltage detection circuit 1E performs detection through resistive voltage division of the boot voltage Vb when a rectifier element M2, which forms the switch output stage SWO together with the output element M1, is in the on-state, and performs detection through capacitive voltage division of the boot voltage Vb when the rectifier element M2 is in the off-state.

Description

Semiconductor devices, switching power supplies

[0001] The present disclosure relates to a semiconductor device and a switching power supply using the same.

[0002] Bootstrap circuits are widely used as internal power supply means for driving N-channel output transistors.

[0003] An example of the related prior art is disclosed in Japanese Patent Application Laid-Open No. 2003-222299.

[0004] Japanese Patent Application Laid-Open No. 2018-133916

[0005] However, there is room for improvement in preventing a drop in the boot voltage generated by the bootstrap circuit.

[0006] For example, a semiconductor device disclosed in this specification includes a first driver configured to drive an output element that forms a switch output stage, at least a part of a bootstrap circuit configured to generate a boot voltage higher than a switch voltage output from the switch output stage and supply the generated boot voltage to the first driver, and a boot voltage detection circuit configured to detect when a difference value between the boot voltage and the switch voltage becomes lower than a lower limit detection value when the output element is in an off state, and to charge the boot voltage, wherein the boot voltage detection circuit detects the boot voltage by resistive voltage division when a rectifying element that forms the switch output stage together with the output element is in an on state, and detects the boot voltage by capacitive voltage division when the rectifying element is in an off state.

[0007] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto.

[0008] According to the present disclosure, it is possible to provide a semiconductor device that can prevent a drop in the boot voltage generated in a bootstrap circuit, and a switching power supply using the same.

[0009] FIG. 1 is a diagram showing the overall configuration of a switching power supply. FIG. 2 is a diagram showing a first embodiment (comparative example) of the switching power supply. FIG. 3 is a diagram showing the switching operation of the first embodiment (when Vb is normal). FIG. 4 is a diagram showing the switching operation of the first embodiment (when Vb drops). FIG. 5 is a diagram showing a second embodiment of the switching power supply. FIG. 6 is a diagram showing the switching operation of the second embodiment. FIG. 7 is a diagram showing a third embodiment of the switching power supply. FIG. 8 is a diagram showing the switching operation of the third embodiment. FIG. 9 is a diagram showing a fourth embodiment of the switching power supply. FIG. 10 is a diagram showing the switching operation of the fourth embodiment. FIG. 11 is a diagram showing a fifth embodiment of the switching power supply. FIG. 12 is a diagram showing the switching operation of the fifth embodiment.

[0010] <Switching Power Supply (Overall Configuration)> Figure 1 shows the overall configuration of a switching power supply. In this example configuration, the switching power supply X is a step-down DC / DC converter that steps down an input voltage Vin to generate a desired output voltage Vout. Referring to this diagram, the switching power supply X includes a semiconductor device 10 and various discrete components (capacitors C1 to C6, an inductor L1, and resistors R1 and R2) externally attached thereto.

[0011] The semiconductor device 10 is a main body (a so-called power supply control integrated circuit) that comprehensively controls the operation of the switching power supply X. The semiconductor device 10 has a plurality of external terminals (pins 1 to 16 in the figure) as means for establishing electrical connection with the outside of the device.

[0012] Pins 1 and 2 are power system power supply terminals PVIN to which the input voltage Vin is applied. Pins 3 and 4 are power system ground terminals PGND. Pin 5 is an analog system ground terminal AGND. Pin 6 is a feedback input terminal FB. Pin 7 is a frequency setting terminal FREQ. Pin 8 is a mode setting terminal MODE. Pin 9 is a soft start setting terminal SS. Pins 10, 11, and 12 are switch output terminals SW. Pin 13 is a bootstrap terminal BOOT. Pin 14 is a power good output terminal PGD. Pin 15 is an enable input terminal EN. Pin 16 is an analog system power supply terminal AVIN to which the power supply voltage Vcc is applied.

[0013] Next, the external connections of the semiconductor device 10 will be described. The first terminal of the capacitor C1 is connected to the analog power supply terminal AVIN. The second terminal of the capacitor C1 is connected to a ground terminal (e.g., the analog ground terminal AGND). The first terminal of the capacitor C2 is connected to the power power supply terminal PVIN (= the application terminal of the input voltage Vin). The second terminal of the capacitor C2 is connected to a ground terminal (e.g., the power ground terminal PGND). The first terminal of the capacitor C3 is connected to the bootstrap terminal BOOT. The second terminal of the capacitor C3 and the first terminal of the inductor L1 are all connected to the switch output terminal SW. The second terminal of the inductor L1 and the first terminals of the resistor R1, capacitors C4, and C5 are all connected to the application terminal of the output voltage Vout. The second terminals of the resistor R1 and capacitor C5 and the first terminal of the resistor R2 are all connected to the feedback input terminal FB (= the application terminal of the feedback voltage Vfb). The second terminals of the capacitor C4 and the resistor R2 are both connected to a ground terminal (e.g., the power ground terminal PGND). The first terminal of the capacitor C6 is connected to the soft start setting terminal SS. The second terminal of the capacitor C6 is connected to a ground terminal (e.g., the analog ground terminal AGND).

[0014] 1, the internal configuration of the semiconductor device 10 will be described in detail. The semiconductor device 10 of this configuration example integrates an error amplifier 11, a comparator 12, an on-time setting circuit 13, a ripple generation circuit 14, an adder circuit 15, a drive control circuit 16, a soft-start circuit 17, a reference voltage generation circuit 18, a power-good detection circuit 19, an overheat protection circuit 1A, a low input protection circuit 1B, an overcurrent / short-circuit protection circuit 1C, a zero-crossing detection circuit 1D, a capacitor C7, a diode D1, an output element M1, a synchronous rectifier element M2, and a transistor M3.

[0015] The error amplifier 11 generates an error voltage Vc corresponding to the difference between the lower of a reference voltage Vref and a soft-start voltage Vss input to two non-inverting input terminals (+) and a feedback voltage Vfb input to an inverting input terminal (-). The error voltage Vc rises when the feedback voltage Vfb is lower than the lower of the reference voltage Vref and the soft-start voltage Vss, and falls when the feedback voltage Vfb is higher than the lower of the reference voltage Vref and the soft-start voltage Vss.

[0016] The comparator 12 compares the slope voltage Vslp input to its inverting input terminal (-) with the error voltage Vc input to its non-inverting input terminal (+) to generate a comparison signal Sc. The comparison signal Sc goes high when the slope voltage Vslp is lower than the error voltage Vc, and goes low when the slope voltage Vslp is higher than the error voltage Vc. The comparator 12 may have a hysteresis characteristic.

[0017] The on-time setting circuit 13 generates the switch control signal S0 so as to maintain the output element M1 in the on state for the on-time Ton after the comparison signal Sc rises to a high level. The on-time setting circuit 13 may also have a function of setting the switching frequency fsw in response to a frequency setting signal SFREQ externally input to a frequency setting terminal FREQ.

[0018] The ripple generating circuit 14 generates a ripple voltage Vr that simulates the ripple component of the output voltage Vout in synchronization with the switch control signal S0.

[0019] The adder circuit 15 adds the ripple voltage Vr to the feedback voltage Vfb to generate the slope voltage Vslp.

[0020] The drive control circuit 16 generates gate drive signals G1 and G2 as basic output feedback control using a bottom detection type fixed on-time method according to the switch control signal S0 so that the output voltage Vout matches the desired target value.

[0021] In addition, the drive control circuit 16 has the function of forcibly stopping the switching drive of each of the output element M1 and the synchronous rectification element M2 in response to the overheat protection signal SA, the low input protection signal SB, and the overcurrent / short circuit protection signal SC.

[0022] The drive control circuit 16 also has a function of stopping the switching drive of the output device M1 and the synchronous rectifier device M2 under light load conditions in response to the zero-crossing detection signal SD. For example, when the output device M1 is in the off state and the synchronous rectifier device M2 is in the on state, the drive control circuit 16 may turn off the synchronous rectifier device M2 when the zero-crossing detection signal SD rises to a high level, i.e., when it is detected that the switch voltage Vsw has become higher than a zero-crossing detection value (e.g., PGND).

[0023] Furthermore, the drive control circuit 16 may have a function of setting the operation mode of the semiconductor device 10 in response to a mode setting signal SMODE externally input to a mode setting terminal MODE.

[0024] The soft start circuit 17 generates a soft start voltage Vss that gradually rises after startup of the semiconductor device 10. The time (=soft start time) from when the soft start voltage Vss starts to rise until it exceeds the reference voltage Vref can be adjusted as desired according to the capacitance value of a capacitor C6 externally connected to the soft start setting terminal SS.

[0025] The reference voltage generating circuit 18 generates a predetermined reference voltage Vref (corresponding to the target value of the feedback voltage Vfb, and therefore the target value of the output voltage Vout).

[0026] The power-good detection circuit 19 detects whether the feedback voltage Vfb exceeds a predetermined power-good detection threshold and generates a gate drive signal G3.

[0027] The overheat protection circuit 1A detects whether the junction temperature Tj of the semiconductor device 10 (particularly the output element M1) exceeds a predetermined overheat protection threshold value, and generates an overheat protection signal SA.

[0028] The under voltage locked out (UVLO) circuit 1B detects whether the input voltage Vin exceeds a predetermined under voltage locked out (UVLO) threshold and generates a under voltage locked out (SB). The under voltage locked out (UVLO) circuit 1B is enabled or disabled in response to an enable signal SEN externally input to an enable input terminal EN.

[0029] The overcurrent / short circuit protection circuit 1C monitors the switch voltage Vsw and generates an overcurrent / short circuit protection signal SC.

[0030] When the output element M1 is in the off state and the synchronous rectifier element M2 is in the on state, the zero-crossing detection circuit 1D detects the zero-crossing (reverse flow) of the inductor current IL flowing through the synchronous rectifier element M2 by monitoring the voltage across the synchronous rectifier element M2 (corresponding to the switch voltage Vsw).

[0031] For example, as shown in the figure, the zero-crossing detection circuit 1D may be a comparator with hysteresis that compares a switch voltage Vsw input to a non-inverting input terminal (+) with a ground voltage PGND input to an inverting input terminal (-) to generate a zero-crossing detection signal SD. In this case, the zero-crossing detection signal SD is at a low level when Vsw<PGND and at a high level when Vsw>PGND.

[0032] The capacitor C7 serves as a phase compensation means for preventing the error amplifier 11 from oscillating, and is connected between the output terminal of the error amplifier 11 and a ground terminal (for example, an analog system ground terminal ANGD).

[0033] The anode of the diode D1 is connected to the power supply terminal PVIN. The cathode of the diode D1 is connected to the bootstrap terminal BOOT. The diode D1 connected in this manner forms a bootstrap circuit BST together with the aforementioned capacitor C3. The bootstrap circuit BST generates a boot voltage Vb that is higher than the switch voltage Vsw by the voltage across the capacitor C3, and supplies this to the drive control circuit 16 (particularly the driver 162 described below). Note that a Schottky barrier diode, for example, can be suitably used as the diode D1.

[0034] The output element M1 (for example, an NMOSFET [N-channel type metal oxide semiconductor field effect transistor]) functions as an upper switch of the switch output stage SWO that generates a switch voltage Vsw from the input voltage Vin. The drain of the output element M1 is connected to the power supply terminal PVIN. The source of the output element M1 is connected to the switch output terminal SW. The gate of the output element M1 is connected to an application terminal of a gate drive signal G1. The output element M1 is in an ON state when the gate drive signal G1 is at a high level, and in an OFF state when the gate drive signal G1 is at a low level.

[0035] The synchronous rectifier element M2 (e.g., an NMOSFET) functions as a lower switch of the switch output stage SWO. The drain of the synchronous rectifier element M2 is connected to the switch output terminal SW. The source of the synchronous rectifier element M2 is connected to the power ground terminal PGND. The gate of the synchronous rectifier element M2 is connected to an application terminal of a gate drive signal G2. The synchronous rectifier element M2 is in an ON state when the gate drive signal G2 is at a high level, and in an OFF state when the gate drive signal G2 is at a low level.

[0036] As the rectifying element, instead of the synchronous rectifying element M2, a rectifying diode (for example, a Schottky barrier diode) having a cathode connected to the switch output terminal SW and an anode connected to the power ground terminal PGND may be used.

[0037] The output element M1 and the synchronous rectifier element M2 may be externally attached to the semiconductor device 10. In that case, instead of the switch output terminal SW, an external input terminal for the switch voltage Vsw and external output terminals for the gate drive signals G1 and G2 are required.

[0038] Furthermore, when a high voltage can be applied to the switch output stage SWO, high-voltage elements such as an IGBT (insulated gate bipolar transistor), a SiC device, or a GaN device may be used as the output element M1 and the synchronous rectifier element M2.

[0039] The transistor M3 functions as an open-drain output stage. The drain of the transistor M3 is connected to the power-good output terminal PGD (= the application terminal of the power-good signal SPGD). The source of the transistor M3 is connected to the ground terminal (for example, the analog ground terminal AGND). The gate of the transistor M3 is connected to the application terminal of the gate drive signal G3. The transistor M3 is turned on when the gate drive signal G3 is at a high level, and turned off when the gate drive signal G3 is at a low level.

[0040] <Switching Power Supply (First Embodiment)> Fig. 2 is a diagram showing a first embodiment (corresponding to a comparative example to be compared with the second to fifth embodiments described later) of a switching power supply X. The switching power supply X of this embodiment is based on the overall configuration (Fig. 1) described above, with a modification made to the bootstrap circuit BST.

[0041] Referring to this figure, the bootstrap circuit BST includes a transistor M4 (e.g., a PMOSFET [P-channel type MOSFET]) instead of the aforementioned diode D1. The source of the transistor M4 is connected to the application terminal of the internal power supply voltage Vreg. The drain of the transistor M4 is connected to the application terminal of the boot voltage Vb. The gate of the transistor M4 is connected to the application terminal of the gate drive signal PG. The transistor M4 is turned off when the gate drive signal PG is at a high level, and turned on when the gate drive signal PG is at a low level.

[0042] In the bootstrap circuit BST of this configuration example, the capacitor C3 is built into the semiconductor device 10. This allows for a reduction in the number of discrete components externally attached to the semiconductor device 10. However, the capacitance value of the capacitor C3 is smaller than when the capacitor C3 is externally attached to the semiconductor device 10. Therefore, it is necessary to consider measures to prevent a decrease in the boot voltage Vb (details will be described later).

[0043] In this figure, a controller 161 and drivers 162 and 163 are clearly shown as components of the drive control circuit 16 .

[0044] The controller 161 generates gate control signals S1 and S2 as basic output feedback control using a bottom detection type fixed on-time method according to the switch control signal S0 so that the output voltage Vout matches a desired target value.

[0045] Furthermore, the controller 161 generates a gate drive signal PG as a control signal for the bootstrap circuit BST. The gate drive signal PG is essentially a logically inverted signal of the gate control signal S2. Specifically, the gate drive signal PG is at a low level when the gate control signal S2 is at a high level, and is at a high level when the gate control signal S2 is at a low level. That is, the transistor M4 is in an on state when the synchronous rectifier element M2 is in an on state, and is in an off state when the synchronous rectifier element M2 is in an off state.

[0046] The driver 162 drives the output element M1 by generating a gate drive signal G1 in response to the gate control signal S1. For example, the gate drive signal G1 is at a high level (=Vb) when the gate control signal S1 is at a high level, and is at a low level (=Vsw) when the gate control signal S1 is at a low level. In this way, the driver 162 operates by receiving the boot voltage Vb, so it can reliably turn on the output element M1.

[0047] The driver 163 drives the synchronous rectifier element M2 by generating a gate drive signal G2 in response to the gate control signal S2. For example, the gate drive signal G2 is at a high level (=Vreg) when the gate control signal S2 is at a high level, and is at a low level (=PGND) when the gate control signal S2 is at a low level.

[0048] The switch output stage SWO generates a square-wave switch voltage Vsw that is pulse-driven between the input voltage Vin and the ground voltage PGND by complementarily turning on and off the output element M1 and the synchronous rectifier element M2, which are connected to form a half bridge.

[0049] In this specification, the term "complementary" is used to include cases where the on / off states of the output element M1 and the synchronous rectifier element M2 are completely reversed, as well as cases where a delay is given to the timing of their on / off transitions (i.e., cases where a simultaneous off period is provided).

[0050] The inductor L1 and the capacitor C4 function as an LC filter that rectifies and smoothes the square-wave switch voltage Vsw to generate the output voltage Vout.

[0051] The resistors R1 and R2 function as a feedback voltage generating circuit (voltage dividing circuit) that outputs a feedback voltage Vfb (= a divided voltage of the output voltage Vout) corresponding to the output voltage Vout from a connection node between them. Although not shown in the figure, a speed-up capacitor C5 (see FIG. 1) may be connected in parallel across the resistor R1 to ensure smooth startup of the switching power supply X. Furthermore, if the output voltage Vout is within the input dynamic range of the semiconductor device 10, the resistors R1 and R2 may be omitted, and the output voltage Vout may be directly input to the feedback input terminal FB.

[0052] 3 is a diagram showing the switching operation (when Vb is normal) of the first embodiment, depicting, from top to bottom, the output voltage Vout, the switch voltage Vsw (solid line), the boot voltage Vb (dashed line), and the gate drive signals G1, G2, and PG. Note that this diagram shows the waveforms of the intermittent switching operation under a light load.

[0053] As shown between times t11 and t12, when the gate drive signal G1 is at a high level and the gate drive signal G2 is at a low level, the output device M1 is turned on and the synchronous rectifier device M2 is turned off. Therefore, the inductor current IL flows from the power supply terminal PVIN (the terminal to which the input voltage Vin is applied) through the output device M1 and inductor L1 toward the terminal to which the output voltage Vout is applied. As a result, the output voltage Vout increases. Furthermore, the switch voltage Vsw becomes high (= Vin - IL × Ron(M1), where Ron(M1) is the on-resistance of the output device M1).

[0054] When the gate drive signal G2 is at a low level, the gate drive signal PG is at a high level, turning off the transistor M4 of the bootstrap circuit BST, and the boot voltage Vb is therefore higher than the switch voltage Vsw by the voltage across the capacitor C3.

[0055] On the other hand, as shown from time t13 to t14, when the gate drive signal G1 is at a low level and the gate drive signal G2 is at a high level, the output device M1 is in an OFF state and the synchronous rectifier device M2 is in an ON state. At this time, the inductor L1 continues to pass the inductor current IL in the same direction as before due to the electromotive force induced in the inductor L1. That is, the inductor current IL continues to flow from the power ground terminal PGND through the synchronous rectifier device M2 and inductor L1 toward the application terminal of the output voltage Vout. As a result, the output voltage Vout continues to rise. In addition, the switch voltage Vsw becomes a low level (=PGND-IL×Ron(M2), where Ron(M2) is the ON resistance of the synchronous rectifier device M2).

[0056] When the gate drive signal G2 is at a high level, the gate drive signal PG is at a low level, and the transistor M4 of the bootstrap circuit BST is turned on. As a result, the capacitor C3 is charged by the current flowing from the application terminal of the internal power supply voltage Vreg via the transistor M4, and the boot voltage Vb rises.

[0057] Then, at time t14, the electromotive force of inductor L1 becomes weak, and when the zero crossing (reverse flow) of inductor current IL flowing through synchronous rectifier device M2 is detected, gate drive signal G2 falls from high to low. As a result, both output device M1 and synchronous rectifier device M2 are turned off, and switch output terminal SW is in a high impedance state. At this time, switch voltage Vsw is approximately equal to output voltage Vout.

[0058] When the gate drive signal G2 falls to low level, the gate drive signal PG rises to high level, turning off the transistor M4 of the bootstrap circuit BST. Therefore, during the period when the drive of the switch output stage SWO is stopped (times t14 to t15), the boot voltage Vb is maintained at a voltage value higher than the switch voltage Vsw by the voltage across the capacitor C3.

[0059] However, when Vb+Vf>Vreg (Vf is the forward voltage drop of the body diode associated with the transistor M4), the capacitor C3 is not charged, and the boot voltage Vb decreases due to natural discharge while the drive of the switch output stage SWO is stopped.

[0060] At time t15, when the output voltage Vout (and hence the feedback voltage Vfb) drops to the bottom detection value, the gate drive signal G1 rises to a high level, turning on the output element M1, and as a result, the output voltage Vout starts to rise again.

[0061] As shown in the figure, if the amount of decrease in the boot voltage Vb during the drive stop period of the switch output stage SWO (=time t14 to t15) is small, there will be no problem in the ON transition of the output element M1 at time t15.

[0062] 4 is a diagram showing the switching operation (when Vb drops) of the first embodiment, and similarly to the above-mentioned FIG. 3, from top to bottom, the output voltage Vout, the switch voltage Vsw (solid line), the boot voltage Vb (dashed line), and the gate drive signals G1, G2, and PG are depicted. Note that this diagram also shows the waveforms of the intermittent switching operation under a light load.

[0063] 3, this figure shows behavior when the amount of decrease in the boot voltage Vb during the drive stop period of the switch output stage SWO (times t21 to t22) is relatively large. In this case, when it is detected at time t22 that the output voltage Vout has decreased to the bottom detection value, the voltage across the capacitor C3 (=Vb-Vsw) may be lower than the turn-on threshold of the output device M1. In this situation, the gate drive signal G1 does not rise sufficiently, preventing the output device M1 from turning on.

[0064] If the rising edge of the gate drive signal G1 is not detected, the gate drive signal G2 rises to a high level and the gate drive signal PG falls to a low level, as shown from time t23 to t24. As a result, the capacitor C3 is charged and the boot voltage Vb rises. Therefore, at time t24, the gate drive signal G1 can rise to a high level, and the output element M1 is switched on.

[0065] However, since the series of reboot operations described above is performed in response to the gate drive signal G1 not rising sufficiently, the turn-on timing of the output element M1 is delayed (from time t22 to time t24) compared to the normal timing, causing the output voltage Vout to fall below the bottom detection value.

[0066] Furthermore, if the synchronous rectifier device M2 is turned on when the boot voltage Vb is insufficient, the gate-source voltage of the output device M1 may rise when the switch voltage Vsw drops due to insufficient performance of the driver 162. As a result, not only the synchronous rectifier device M2 but also the output device M1 may be turned on, which may cause an excessively large through current to flow in the switch output stage SWO.

[0067] It is difficult to ensure a sufficient capacitance value of the capacitor C3 when the capacitor C3 is built into the semiconductor device 10. Therefore, the amount of decrease in the boot voltage Vb during the driving stop period of the switch output stage SWO is relatively large, and the above problem is likely to become apparent.

[0068] The above problem also applies to the case where diode rectification is adopted in the switch output stage SWO.

[0069] The following proposes an embodiment that can solve the above problem.

[0070] <Switching Power Supply (Second Embodiment)> Fig. 5 is a diagram showing a second embodiment of the switching power supply X. The switching power supply X of this embodiment is based on the first embodiment (Fig. 2) described above, and further includes a boot voltage detection circuit 1E.

[0071] The boot voltage detection circuit 1E detects that the difference value (Vb-Vsw) between the boot voltage Vb and the switch voltage Vsw becomes lower than the lower limit detection value when the output element M1 is in the off state, and generates a reboot control signal SE to charge the boot voltage Vb.

[0072] The reboot control signal SE becomes low level (= the logical level when BOOTUVLO is not detected) when the difference value (Vb-Vsw) is higher than the lower limit detection value, and becomes high level (= the logical level when BOOTUVLO is detected) when the difference value (Vb-Vsw) is lower than the lower limit detection value.

[0073] During the period when the drive of the switch output stage SWO is stopped, the controller 161 turns on the synchronous rectifier element M2 and the transistor M4 to charge the boot voltage Vb when the reboot control signal SE rises to a high level.

[0074] 6 is a diagram showing the switching operation of the second embodiment, depicting, from top to bottom, the output voltage Vout, the switch voltage Vsw (solid line), the boot voltage Vb (dashed line), the gate drive signals G1, G2, and PG, and the reboot control signal SE. Note that this diagram also shows the waveforms of the intermittent switching operation under a light load.

[0075] As the boot voltage Vb decreases during the drive stop period (G1 = G2 = L) of the switch output stage SWO, the difference between the boot voltage Vb and the switch voltage Vsw (Vb - Vsw) falls below the lower limit detection value at time t31, causing the reboot control signal SE to rise to a high level. At this time, as shown from time t31 to t32, the gate drive signal G2 rises to a high level and the gate drive signal PG falls to a low level. As a result, the capacitor C3 is charged, and the boot voltage Vb rises. Therefore, the boot voltage Vb can be raised sufficiently before the output element M1 has a chance to turn on.

[0076] Between times t31 and t32, the synchronous rectifier device M2 is turned on to charge the capacitor C3, and as in the first embodiment (times t13 and t14 in FIG. 4 ), the output voltage Vout drops. However, unlike the first embodiment ( FIG. 4 ), the rebooting operation is not performed until a problem occurs in the on transition of the output device M1, but rather is performed without delay when the difference (Vb−Vsw) between the boot voltage Vb and the switch voltage Vsw falls below the lower limit detection value. Therefore, compared to the first embodiment ( FIG. 4 ), the on timing of the output device M1 is less likely to be delayed, and the amount of drop in the output voltage Vout is suppressed.

[0077] <Switching Power Supply (Third Embodiment)> Fig. 7 is a diagram showing a third embodiment of the switching power supply X. The switching power supply X of this embodiment is based on the second embodiment (Fig. 5) described above, and further includes a charge pump 1F.

[0078] The charge pump 1F generates a boosted voltage Vcp higher than the input voltage Vin in response to the reboot control signal SE, and applies this to the application terminal of the boot voltage Vb.

[0079] In particular, when the switch output stage SWO employs a diode rectification system, it is desirable to employ this embodiment.

[0080] The charge pump 1F does not always maintain the boot voltage Vb at a voltage value higher than the input voltage Vin, but only needs to have a current capacity sufficient to slightly raise the boot voltage Vb when it drops. Therefore, for example, an existing charge pump provided for the purpose of maintaining the boot voltage Vb when the switch output stage SWO is driven at 100% duty may be used as the charge pump 1F.

[0081] 8 is a diagram showing the switching operation of the third embodiment, and similarly to FIG. 6, from top to bottom, the output voltage Vout, the switch voltage Vsw (solid line), the boot voltage Vb (dashed line), the gate drive signals G1, G2, and PG, and the reboot control signal SE are depicted. Note that this diagram also shows the waveforms of the intermittent switching operation under a light load.

[0082] As the boot voltage Vb drops during the period when the switch output stage SWO is not driven (G1=G2=L), the difference between the boot voltage Vb and the switch voltage Vsw (Vb-Vsw) falls below the lower limit detection value at time t41, causing the reboot control signal SE to rise to a high level. At this time, the charge pump 1F is driven, and as shown from time t41 to t42, the capacitor C3 is charged, causing the boot voltage Vb to rise. Therefore, the boot voltage Vb can be sufficiently raised before the output element M1 has a chance to turn on.

[0083] Note that, from time t41 to t42, unlike the second embodiment (times t31 to t32 in FIG. 6), the synchronous rectifier device M2 is not turned on to charge the capacitor C3, and therefore, it is possible to further suppress the decrease in the output voltage Vout compared to the second embodiment (FIG. 6).

[0084] 9 is a diagram showing a fourth embodiment (corresponding to a general comparative example to be contrasted with the fifth embodiment described later) of a switching power supply X. In the switching power supply X of this embodiment, a boot voltage detection circuit 1E includes a Schmitt buffer E11, a level shifter E12, transistors M11 and M12 (both of which are NMOSFETs, for example), and a resistor R11.

[0085] A first terminal of the resistor R11 and a gate of the transistor M11 are both connected to a terminal to which the boot voltage Vb is applied. A second terminal of the resistor R11 and a drain of the transistor M11 are both connected to an input terminal (=a terminal to which the node voltage S11 is applied) of the Schmitt buffer E11. A source of the transistor M11 is connected to a gate and a drain of the transistor M12. A source of the transistor M12 is connected to a terminal to which the switch voltage Vsw is applied.

[0086] When the difference (Vb-Vsw) between the boot voltage Vb and the switch voltage Vsw is higher than the lower limit detection value 2×Vgs (where Vgs is the on-threshold value of each of the transistors M11 and M12), both transistors M11 and M12 are turned on. Therefore, an internal current I11 flows through a current path from the application terminal of the boot voltage Vb to the application terminal of the switch voltage Vsw via the resistor R11 and the transistors M11 and M12. As a result, the node voltage S11 becomes low level (=Vsw). On the other hand, when the difference (Vb-Vsw) between the boot voltage Vb and the switch voltage Vsw is lower than the lower limit detection value 2×Vgs, both transistors M11 and M12 are turned off. Therefore, the internal current I11 does not flow, and the node voltage S11 becomes high level (=Vb).

[0087] The Schmitt buffer E11 receives the node voltage S11 as an input and outputs a node voltage S12. For example, the node voltage S12 becomes high level (=Vb) when the node voltage S11 is high level (=Vb), and becomes low level (=Vsw) when the node voltage S11 is low level (=Vsw). The Schmitt buffer E11 may have a hysteresis characteristic.

[0088] The level shifter E12 shifts the level of the node voltage S12 to generate the reboot control signal SE. For example, the reboot control signal SE is at a high level (=Vreg) when the node voltage S12 is at a high level (=Vb), and is at a low level (=AGND) when the node voltage S12 is at a low level (=Vsw).

[0089] 10 is a diagram showing the switching operation of the fourth embodiment, and similarly to the above-mentioned FIG. 6, from top to bottom, the output voltage Vout, the switch voltage Vsw (solid line), the boot voltage Vb (dashed line), the gate drive signals G1, G2, and PG, and the reboot control signal SE are depicted. Note that this diagram also shows the waveforms of the intermittent switching operation under a light load.

[0090] In the switching power supply X of this embodiment, while the difference value (Vb-Vsw) between the boot voltage Vb and the switch voltage Vsw is higher than the lower limit detection value, the internal current I11 of the boot voltage detection circuit 1E continues to flow from the application terminal of the boot voltage Vb to the application terminal of the switch voltage Vsw.

[0091] Therefore, the speed at which the boot voltage Vb decreases during the period when the drive of the switch output stage SWO is stopped (=time t51 to t52) increases.

[0092] In the following, a novel embodiment that can solve the above problems will be proposed.

[0093] 11 is a diagram showing a fifth embodiment of a switching power supply X. In the switching power supply X of this embodiment, a boot voltage detection circuit 1E includes voltage divider circuits DIV1 and DIV2, an offset applying circuit E21, and a comparator E22.

[0094] The voltage divider circuit DIV1 divides the boot voltage Vb to generate a divided voltage V21. The voltage division ratio of the voltage divider circuit DIV1 may be 1 / 2. Referring to the figure, the voltage divider circuit DIV1 includes a transistor M21 (corresponding to a first switch, e.g., a PMOSFET), a transistor M22 (corresponding to a second switch, e.g., an NMOSFET), resistors R21 and R22, and capacitors C21 and C22.

[0095] The source of the transistor M21 and the first end of the capacitor C21 are both connected to the end to which the boot voltage Vb is applied. The drain of the transistor M21 is connected to the first end of the resistor R21. The second ends of the resistor R21 and the capacitor C21 and the first ends of the resistor R22 and the capacitor C22 are both connected to the end to which the divided voltage V21 is applied. The second end of the resistor R22 is connected to the drain of the transistor M22. The source of the transistor M22 and the second end of the capacitor C22 are both connected to a ground end (e.g., the analog ground terminal AGND).

[0096] The gate of the transistor M21 is connected to the application terminal of the gate drive signal POFF. Therefore, the transistor M21 is turned on when the gate drive signal POFF is at a low level, and turned off when the gate drive signal POFF is at a high level.

[0097] The gate of the transistor M22 is connected to the application terminal of the gate drive signal NON. Therefore, the transistor M22 is turned on when the gate drive signal NON is at a high level, and turned off when the gate drive signal NON is at a low level.

[0098] The voltage divider circuit DIV2 divides the switch voltage Vsw to generate a divided voltage V22. The voltage division ratio of the voltage divider circuit DIV2 may be 1 / 2. Referring to this figure, the voltage divider circuit DIV2 includes resistors R23 and R24 and capacitors C23 and C24. Note that the capacitors C23 and C24 may be omitted.

[0099] The first terminals of the resistor R23 and the capacitor C23 are both connected to the terminal to which the switch voltage Vsw is applied. The second terminals of the resistor R23 and the capacitor C23 and the first terminals of the resistor R24 ​​and the capacitor C24 are both connected to the terminal to which the divided voltage V22 is applied. The second terminals of the resistor R24 ​​and the capacitor C24 are both connected to the ground terminal (e.g., the analog ground terminal AGND).

[0100] The offset applying circuit E21 offsets the divided voltage V22 and outputs it to the non-inverting input terminal (+) of the comparator E22. Note that the offset applying circuit E21 may also offset the divided voltage V21 and output it to the inverting input terminal (-) of the comparator E22. However, if the offset applied to the divided voltage V22 is positive, the offset applied to the divided voltage V21 will be negative.

[0101] The comparator E22 compares the divided voltage V21 input to its inverting input terminal (−) with the offset divided voltage V22 input to its non-inverting input terminal (+) to generate a reboot control signal SE. The reboot control signal SE goes low when the divided voltage V21 is higher than the offset divided voltage V22, and goes high when the divided voltage V21 is lower than the offset divided voltage V22, for example.

[0102] 12 is a diagram showing the switching operation of the fifth embodiment, depicting, from top to bottom, the output voltage Vout, the switch voltage Vsw (solid line), the boot voltage Vb (dashed line), the gate drive signals G1, G2, PG, NON, and POFF, and the reboot control signal SE. Note that this diagram also shows the waveforms of the intermittent switching operation under a light load.

[0103] As shown from time t61 to t62, when the output device M1 is in the off state (G1=L) and the synchronous rectifier device M2 is in the on state (G2=H), the gate drive signal NON is set to a high level and the gate drive signal POFF is set to a low level. Therefore, both transistors M21 and M22 are in the on state. As a result, the voltage divider circuit DIV1 generates the divided voltage V21 by resistively dividing the boot voltage Vb using resistors R21 and R22. In other words, the period from time t61 to t62 corresponds to the resistive voltage division period of the boot voltage Vb.

[0104] On the other hand, as shown from time t62 to t63, when the output device M1 and the synchronous rectifier device M2 are both in the off state (G1 = G2 = L), the gate drive signal NON is set to low level and the gate drive signal POFF is set to high level. Therefore, both transistors M21 and M22 are in the off state. As a result, the voltage divider circuit DIV1 generates the divided voltage V21 by capacitively dividing the boot voltage Vb using capacitors C21 and C22. In other words, the period from time t62 to t63 corresponds to the capacitive division period of the boot voltage Vb.

[0105] During this capacitive voltage division period (=time t62 to t63), no current path exists inside the voltage divider circuit DIV1 from the application terminal of the boot voltage Vb to the application terminal of the switch voltage Vsw, so it is possible to suppress the rate of decrease in the boot voltage Vb during the drive stop period of the switch output stage SWO (=time t62 to t63).

[0106] If the only goal is to suppress the rate at which the boot voltage Vb drops, the boot voltage Vb may be detected by constantly dividing it by capacitance. However, if such a configuration is adopted, once the voltage division ratio of the voltage divider circuit DIV1 shifts due to noise or the like, there is no way to resolve this.

[0107] On the other hand, as explained above, if the resistive voltage division period (=time t61 to t62) is provided before the capacitive voltage division period (=time t62 to t63), the voltage division ratio of the voltage-divider circuit DIV1 can be reset (refreshed) every time the switch output stage SWO is switched. Therefore, even if the voltage division ratio of the voltage-divider circuit DIV1 becomes distorted due to noise or the like, this can be quickly corrected.

[0108] <Summary> The various embodiments described above will be summarized below.

[0109] For example, a semiconductor device disclosed in this specification includes a first driver configured to drive an output element that forms a switch output stage, at least a part of a bootstrap circuit configured to generate a boot voltage higher than a switch voltage output from the switch output stage and supply the generated boot voltage to the first driver, and a boot voltage detection circuit configured to detect when the output element is in an off state that the difference value between the boot voltage and the switch voltage has become lower than a lower limit detection value and to charge the boot voltage, wherein the boot voltage detection circuit is configured to detect the boot voltage by resistive voltage division when a rectifier element that forms the switch output stage together with the output element is in an on state, and to detect the boot voltage by capacitive voltage division when the rectifier element is in an off state (first configuration).

[0110] In the semiconductor device according to the first configuration, the rectifying element may be a synchronous rectifying element configured to be driven complementarily to the output element (second configuration).

[0111] The semiconductor device according to the second configuration may be configured (third configuration) further including a second driver configured to drive the synchronous rectifier element, and a control circuit configured to complementarily drive the output element and the synchronous rectifier element and to detect that the switch voltage becomes higher than a zero-cross detection value when the output element is in an off state and the synchronous rectifier element is in an on state, and to turn off the synchronous rectifier element.

[0112] In a semiconductor device having the second or third configuration, the boot voltage detection circuit may be configured (fourth configuration) to detect that the difference value between the boot voltage and the switch voltage has become lower than the lower limit detection value and turn on the synchronous rectification element.

[0113] In a semiconductor device having any of the first to fourth configurations, the boot voltage detection circuit may be configured (fifth configuration) to detect that the difference value between the boot voltage and the switch voltage has become lower than the lower limit detection value, and apply a boosted voltage higher than the input voltage input to the switch output stage to the boot voltage application terminal.

[0114] In a semiconductor device according to any one of the first to fifth configurations, the boot voltage detection circuit may be configured (sixth configuration) to include a first voltage divider circuit configured to divide the boot voltage to obtain a first divided voltage, a second voltage divider circuit configured to divide the switch voltage to obtain a second divided voltage, and a comparator configured to compare the first divided voltage with the second divided voltage.

[0115] In addition, in the semiconductor device according to the sixth configuration, the first voltage divider circuit may include a first switch and a second switch, a first resistor and a second resistor, and a first capacitor and a second capacitor, wherein first ends of the first switch and the first capacitor are all connected to the application terminal of the boot voltage, a second end of the first switch is connected to the first end of the first resistor, second ends of the first resistor and the first capacitor and first ends of the second resistor and the second capacitor are all connected to the application terminal of the first divided voltage, a second end of the second resistor is connected to the first end of the second switch, and second ends of the second switch and the second capacitor are all connected to the ground terminal (seventh configuration).

[0116] In the semiconductor device according to the sixth or seventh configuration, the second voltage-dividing circuit may include a third resistor and a fourth resistor, and a third capacitor and a fourth capacitor, each of which has a first terminal connected to an application terminal of the switch voltage, each of which has a second terminal connected to an application terminal of the second divided voltage, and each of which has a second terminal connected to a ground terminal (an eighth configuration).

[0117] In a semiconductor device having any of the sixth to eighth configurations, the boot voltage detection circuit may be configured (ninth configuration) to further include an offset applying circuit configured to offset the first divided voltage or the second divided voltage and output it to the comparator.

[0118] Furthermore, for example, a switching power supply disclosed in this specification includes a semiconductor device having any one of the first to ninth configurations, and is configured to drive the switch output stage to generate a desired output voltage from an input voltage (tenth configuration).

[0119] <Other Modifications> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0120] 10 Semiconductor device (power supply control IC) 11 Error amplifier 12 Comparator 13 On-time setting circuit 14 Ripple generation circuit 15 Adder circuit 16 Drive control circuit 161 Controller 162, 163 Driver 17 Soft start circuit 18 Reference voltage generation circuit 19 Power good detection circuit 1A Overheat protection circuit 1B Low input protection circuit 1C Overcurrent / short circuit protection circuit 1D Zero cross detection circuit 1E Boot voltage detection circuit 1F Charge pump BST Bootstrap circuit C1 to C7, C21 to C24 Capacitor D1 Diode DIV1, DIV2 Voltage divider circuit E11 Schmitt buffer E12 Level shifter E21 Offset applying circuit E22 Comparator L1 Inductor M1 Output element (NMOSFET) M2 Synchronous rectifier element (NMOSFET) M3, M11, M12, M22 Transistors (NMOSFET) M4, M21 Transistors (PMOSFET) R1, R2, R11, R21 to R24 Resistors SWO Switch output stage X Switching power supply

Claims

1. a first driver configured to drive an output element forming a switched output stage; At least a part of a bootstrap circuit configured to generate a boot voltage higher than a switch voltage output from the switch output stage and supply the boot voltage to the first driver; a boot voltage detection circuit configured to detect when a difference between the boot voltage and the switch voltage becomes lower than a lower limit detection value when the output element is in an off state, and to charge the boot voltage; Equipped with The boot voltage detection circuit detects the boot voltage by resistive voltage division when a rectifier element which forms the switch output stage together with the output element is in an on state, and detects the boot voltage by capacitive voltage division when the rectifier element is in an off state.

2. 2. The semiconductor device according to claim 1, wherein said rectifying element is a synchronous rectifying element configured to be driven complementarily to said output element.

3. a second driver configured to drive the synchronous rectification element; a control circuit configured to drive the output element and the synchronous rectification element complementarily, and to detect that the switch voltage becomes higher than a zero-cross detection value when the output element is in an off state and the synchronous rectification element is in an on state, and to turn off the synchronous rectification element; The semiconductor device according to claim 2 , further comprising:

4. 3. The semiconductor device according to claim 2, wherein said boot voltage detection circuit detects that said difference value between said boot voltage and said switch voltage becomes lower than said lower limit detection value, and turns on said synchronous rectification element.

5. 2. The semiconductor device according to claim 1, wherein the boot voltage detection circuit detects that the difference value between the boot voltage and the switch voltage becomes lower than the lower limit detection value and applies a boosted voltage higher than the input voltage input to the switch output stage to the boot voltage application terminal.

6. The boot voltage detection circuit includes: a first voltage divider circuit configured to divide the boot voltage to obtain a first divided voltage; a second voltage divider circuit configured to divide the switch voltage to obtain a second divided voltage; a comparator configured to compare the first divided voltage with the second divided voltage; The semiconductor device according to claim 1 ,

7. the first voltage dividing circuit includes a first switch, a second switch, a first resistor, a second resistor, and a first capacitor, a first terminal of the first switch and a first terminal of the first capacitor are both connected to the boot voltage application terminal; a second terminal of the first switch is connected to a first terminal of the first resistor; a second terminal of each of the first resistor and the first capacitor and a first terminal of each of the second resistor and the second capacitor are connected to an application terminal of a first divided voltage, a second end of the second resistor is connected to a first end of the second switch; The semiconductor device according to claim 6 , wherein the second terminals of the second switch and the second capacitor are both connected to a ground terminal.

8. the second voltage dividing circuit includes a third resistor, a fourth resistor, a third capacitor, and a fourth capacitor; a first terminal of the third resistor and a first terminal of the third capacitor are both connected to the switch voltage application terminal; a second terminal of each of the third resistor and the third capacitor and a first terminal of each of the fourth resistor and the fourth capacitor are connected to an application terminal of a second divided voltage, The semiconductor device according to claim 6 , wherein the second terminals of said fourth resistor and said fourth capacitor are both connected to a ground terminal.

9. 7. The semiconductor device according to claim 6, wherein said boot voltage detection circuit further includes an offset applying circuit configured to offset said first divided voltage or said second divided voltage and output the offset voltage to said comparator.

10. 10. A switching power supply comprising the semiconductor device according to claim 1, which drives the switch output stage to generate a desired output voltage from an input voltage.