Linear regulator, semiconductor device, switching power supply

Abstract

This linear regulator comprises: an N-channel type first transistor M11 configured to be connected between the application end of an input voltage Vin and the application end of a stabilization voltage VREG; an N-channel type second transistor M12 configured to mirror a bias current Ib flowing in itself by forming a current mirror type output stage 201 together with the first transistor M11 and to generate an output current Io flowing through the first transistor M11; a feedback control unit 202 that is configured to control the bias current Ib according to the difference between a feedback voltage VFB according to the stabilization voltage VREG and a prescribed reference voltage VREF; and a load 203 that is configured to draw out a first leakage current ILK1 from a control end common to both the first transistor M11 and the second transistor M12.

Description

Linear regulators, semiconductor devices, switching power supplies

[0001] The present disclosure relates to a linear regulator, a semiconductor device, and a switching power supply.

[0002] Linear regulators are used as a power supply means for various devices.

[0003] An example of the related prior art is disclosed in Japanese Patent Application Laid-Open No. 2003-222299.

[0004] Japanese Patent Application Laid-Open No. 2020-071710

[0005] However, conventional linear regulators have room for improvement in suppressing output leakage current at high temperatures.

[0006] The linear regulator disclosed in this specification includes: an N-channel first transistor configured to be connected between an input voltage application terminal and a stabilizing voltage application terminal; an N-channel second transistor configured to form a current mirror output stage together with the first transistor, thereby mirroring a bias current flowing through the first transistor and generating an output current flowing through the first transistor; a feedback control unit configured to control the bias current in accordance with the difference between a feedback voltage corresponding to the stabilizing voltage and a predetermined reference voltage; and a load configured to draw a first leakage current from a control terminal common to both the first transistor and the second transistor.

[0007] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto.

[0008] According to the present disclosure, it is possible to provide a linear regulator, a semiconductor device, and a switching power supply that can suppress output leakage current at high temperatures.

[0009] FIG. 1 is a diagram showing the overall configuration of a switching power supply. FIG. 2 is a diagram showing the schematic configuration of a linear regulator. FIG. 3 is a diagram showing a first embodiment (comparison example) of a linear regulator. FIG. 4 is a diagram showing a second embodiment of a linear regulator. FIG. 5 is a diagram showing temperature characteristics of a source voltage and a gate voltage. FIG. 6 is a diagram showing temperature characteristics of a circuit current.

[0010] <Switching Power Supply> Figure 1 shows the overall configuration of a switching power supply. The switching power supply X in this configuration example is a step-down DC / DC converter that steps down an input voltage Vin to generate a desired output voltage Vout. Referring to this figure, the switching power supply X includes a semiconductor device 10 and various discrete components (capacitors C1 and C2, an inductor L1, and resistors R1 and R2) externally attached thereto.

[0011] The semiconductor device 10 is a main body (a so-called power supply control IC [integrated circuit]) that comprehensively controls the operation of the switching power supply X. The semiconductor device 10 has a plurality of external terminals (pins 1 to 6 in the figure) as means for establishing electrical connection with the outside of the device.

[0012] Pin 1 is an enable input terminal EN. Pin 2 is a power good output terminal PGD. Pin 3 is a feedback input terminal FB. Pin 4 is a ground terminal GND. Pin 5 is a switch output terminal SW. Pin 6 is a power supply terminal VIN to which an input voltage Vin is applied.

[0013] Next, the external connections of the semiconductor device 10 will be described. A first terminal of the capacitor C1 is connected to the power supply terminal VIN. A second terminal of the capacitor C1 is connected to the ground terminal. A first terminal of the inductor L1 is connected to the switch output terminal SW. A second terminal of the inductor L1 and a first terminal of each of the resistor R1 and the capacitor C2 are all connected to the application terminal of the output voltage Vout. A second terminal of the resistor R1 and a first terminal of the resistor R2 are all connected to the feedback input terminal FB (= the application terminal of the feedback voltage Vfb). A second terminal of each of the capacitor C2 and the resistor R2 is all connected to the ground terminal.

[0014] The inductor L1 and the capacitor C2 function as an LC filter that rectifies and smoothes the square-wave switch voltage Vsw to generate the output voltage Vout.

[0015] The resistors R1 and R2 function as a feedback voltage generating circuit (voltage dividing circuit) that outputs a feedback voltage Vfb (= a divided voltage of the output voltage Vout) corresponding to the output voltage Vout from a connection node between them. Although not shown in the figure, a speed-up capacitor may be connected in parallel across the resistor R1 to ensure smooth startup of the switching power supply X. If the output voltage Vout is within the input dynamic range of the semiconductor device 10, the resistors R1 and R2 may be omitted, and the output voltage Vout may be directly input to the feedback input terminal FB.

[0016] 1 , the internal configuration of the semiconductor device 10 will be described in detail. The semiconductor device 10 of this configuration example integrates an error amplifier 11, a comparator 12, an on-time setting circuit 13, a ripple generation circuit 14, an adder circuit 15, a drive control circuit 16, a soft-start circuit 17, a reference voltage generation circuit 18, a power-good detection circuit 19, a low input protection circuit 1A, an overheat protection circuit 1B, an overvoltage protection circuit 1C, a short-circuit protection circuit 1D, an overcurrent protection circuit 1E, a zero-crossing detection circuit 1F, a linear regulator 20, a capacitor C3, an output element M1, a synchronous rectification element M2, transistors M3 and M4, and a resistor R3.

[0017] The error amplifier 11 generates an error voltage Vc corresponding to the difference between the lower of a reference voltage Vref and a soft-start voltage Vss input to two non-inverting input terminals (+) and a feedback voltage Vfb input to an inverting input terminal (-). The error voltage Vc rises when the feedback voltage Vfb is lower than the lower of the reference voltage Vref and the soft-start voltage Vss, and falls when the feedback voltage Vfb is higher than the lower of the reference voltage Vref and the soft-start voltage Vss.

[0018] The comparator 12 compares the slope voltage Vslp input to its inverting input terminal (-) with the error voltage Vc input to its non-inverting input terminal (+) to generate a comparison signal Sc. The comparison signal Sc goes high when the slope voltage Vslp is lower than the error voltage Vc, and goes low when the slope voltage Vslp is higher than the error voltage Vc. The comparator 12 may have a hysteresis characteristic.

[0019] The ON time setting circuit 13 generates the switch control signal S0 so as to maintain the output element M1 in the ON state for the ON time Ton after the comparison signal Sc rises to a high level.

[0020] The ripple generating circuit 14 generates a ripple voltage Vr that simulates the ripple component of the output voltage Vout in synchronization with the switch control signal S0.

[0021] The adder circuit 15 adds the ripple voltage Vr to the feedback voltage Vfb to generate the slope voltage Vslp.

[0022] The drive control circuit 16 includes a controller 161 and drivers 162 and 163 as its components.

[0023] The controller 161 generates gate control signals S1 and S2 as basic output feedback control using a bottom detection type fixed on-time method according to the switch control signal S0 so that the output voltage Vout matches a desired target value.

[0024] In addition, the controller 161 has the function of forcibly stopping the switching drive of each of the output element M1 and the synchronous rectification element M2 in response to the low input protection signal SA, the overheat protection signal SB, the overvoltage protection signal SC, the short circuit protection signal SD, and the overcurrent protection signal SE.

[0025] The controller 161 also has a function of stopping the switching drive of each of the output element M1 and the synchronous rectifier element M2 under a light load in accordance with the zero-cross detection signal SF. For example, the controller 161 may turn off the synchronous rectifier element M2 when the zero-cross detection signal SF rises to a high level while the output element M1 is in an off state and the synchronous rectifier element M2 is in an on state, i.e., when it is detected that the switch voltage Vsw has become higher than a zero-cross detection value (e.g., GND).

[0026] Furthermore, the controller 161 also has a function of generating a gate drive signal G3 for the transistor M3 in response to an enable signal SEN externally input to the enable input terminal EN.

[0027] The driver 162 drives the output element M1 by generating a gate drive signal G1 in response to the gate control signal S1. For example, the gate drive signal G1 is at a high level when the gate control signal S1 is at a high level, and is at a low level when the gate control signal S1 is at a low level.

[0028] The driver 163 drives the synchronous rectifier element M2 by generating a gate drive signal G2 in response to the gate control signal S2. For example, the gate drive signal G2 is at a high level when the gate control signal S2 is at a high level, and is at a low level when the gate control signal S2 is at a low level.

[0029] The soft start circuit 17 generates a soft start voltage Vss that gradually rises after the semiconductor device 10 starts up.

[0030] The reference voltage generating circuit 18 generates a predetermined reference voltage Vref (which corresponds to the target value of the feedback voltage Vfb, and thus to the target value of the output voltage Vout). The reference voltage generating circuit 18 is switched between enabled and disabled in response to an enable signal SEN externally input to an enable input terminal EN.

[0031] The power-good detection circuit 19 detects whether the feedback voltage Vfb exceeds a predetermined power-good detection threshold and generates a gate drive signal G4.

[0032] The under voltage locked out (UVLO) circuit 1A detects whether the input voltage Vin exceeds a predetermined under voltage locked out (UVLO) threshold and generates an under voltage locked out (SA) signal.

[0033] The overheat protection circuit 1B detects whether the junction temperature Tj of the semiconductor device 10 (particularly the output element M1) exceeds a predetermined overheat protection threshold value and generates an overheat protection signal SB.

[0034] The overvoltage protection circuit 1C detects whether the feedback voltage Vfb exceeds a predetermined overvoltage protection threshold and generates an overvoltage protection signal SC.

[0035] The short-circuit protection circuit 1D monitors the feedback voltage Vfb and generates a short-circuit protection signal SD.

[0036] The overcurrent protection circuit 1E generates an overcurrent protection signal SE by monitoring the switch voltage Vsw.

[0037] When the output element M1 is in the off state and the synchronous rectifier element M2 is in the on state, the zero-crossing detection circuit 1F detects the zero-crossing (reverse flow) of the inductor current IL flowing through the synchronous rectifier element M2 by monitoring the voltage across the synchronous rectifier element M2 (corresponding to the switch voltage Vsw).

[0038] The capacitor C3 serves as a phase compensation means for preventing the error amplifier 11 from oscillating, and is connected between the output terminal of the error amplifier 11 and the ground terminal.

[0039] The output element M1 (for example, an NMOSFET [N-channel type metal oxide semiconductor field effect transistor]) functions as an upper switch of the switch output stage SWO that generates a switch voltage Vsw from the input voltage Vin. The drain of the output element M1 is connected to the power supply terminal VIN. The source of the output element M1 is connected to the switch output terminal SW. The gate of the output element M1 is connected to an application terminal of a gate drive signal G1. The output element M1 is in an ON state when the gate drive signal G1 is at a high level, and in an OFF state when the gate drive signal G1 is at a low level.

[0040] The synchronous rectifier element M2 (e.g., an NMOSFET) functions as a lower switch of the switch output stage SWO. The drain of the synchronous rectifier element M2 is connected to the switch output terminal SW. The source of the synchronous rectifier element M2 is connected to the ground terminal GND. The gate of the synchronous rectifier element M2 is connected to an application terminal of a gate drive signal G2. The synchronous rectifier element M2 is in an ON state when the gate drive signal G2 is at a high level, and in an OFF state when the gate drive signal G2 is at a low level.

[0041] As the rectifying element, instead of the synchronous rectifying element M2, a rectifying diode (for example, a Schottky barrier diode) having a cathode connected to the switch output terminal SW and an anode connected to the ground terminal GND may be used.

[0042] The output element M1 and the synchronous rectifier element M2 may be externally attached to the semiconductor device 10. In that case, instead of the switch output terminal SW, an external input terminal for the switch voltage Vsw and external output terminals for the gate drive signals G1 and G2 are required.

[0043] Furthermore, when a high voltage can be applied to the switch output stage SWO, high-voltage elements such as an IGBT (insulated gate bipolar transistor), a SiC device, or a GaN device may be used as the output element M1 and the synchronous rectifier element M2.

[0044] The switch output stage SWO generates a square-wave switch voltage Vsw that is pulse-driven between the input voltage Vin and the ground voltage PGND by complementarily turning on and off the output element M1 and the synchronous rectifier element M2, which are connected to form a half bridge.

[0045] In this specification, the term "complementary" is used to include cases where the on / off states of the output element M1 and the synchronous rectifier element M2 are completely reversed, as well as cases where a delay is given to the timing of their on / off transitions (i.e., cases where a simultaneous off period is provided).

[0046] A first end of the resistor R3 is connected to the switch output terminal SW. A second end of the resistor R3 is connected to the drain of the transistor M3. A source of the transistor M3 is connected to the ground terminal GND. A gate of the transistor M3 is connected to an application terminal of the gate drive signal G3. The transistor M3 is turned on when the gate drive signal G3 is at a high level, and turned off when the gate drive signal G3 is at a low level. The resistor R3 and the transistor M3 connected in this manner function as a pull-down circuit for fixing the switch output terminal SW to the same potential as the ground terminal GND when the enable signal SEN is at a disable logic level.

[0047] The transistor M4 functions as an open-drain output stage. The drain of the transistor M4 is connected to the power-good output terminal PGD (= the application terminal of the power-good signal SPGD). The source of the transistor M4 is connected to the ground terminal. The gate of the transistor M4 is connected to the application terminal of the gate drive signal G4. The transistor M4 is turned on when the gate drive signal G4 is at a high level, and turned off when the gate drive signal G4 is at a low level.

[0048] The linear regulator 20 generates a regulated voltage VREG by stepping down the input voltage Vin. For example, an LDO (low drop out) regulator can be suitably used as the linear regulator 20. The regulated voltage VREG is used as an internal power supply voltage of the semiconductor device 10, for example.

[0049] 2 is a diagram showing a schematic configuration of the linear regulator 20. The linear regulator 20 of this configuration example includes a stabilized voltage generating circuit 21 and resistors 22 and 23.

[0050] The stabilized voltage generating circuit 21 controls an output stage (not shown) so that a reference voltage VREF input to a non-inverting input terminal (+) and a feedback voltage VFB input to an inverting input terminal (-) coincide with each other, thereby stepping down the input voltage Vin to generate the stabilized voltage VREG. The stabilized voltage generating circuit 21 switches between enable and disable of the bias current generation operation in response to a bias enable signal ENBIAS.

[0051] The resistors 22 and 23 function as a feedback voltage generating circuit (voltage dividing circuit) that outputs a feedback voltage VFB (=divided voltage of the stabilized voltage VREG) according to the stabilized voltage VREG from a connection node therebetween.

[0052] 3 is a diagram showing a first embodiment (corresponding to a comparative example to be compared with a second embodiment described later) of a linear regulator 20. In the linear regulator 20 of this embodiment, the stabilized voltage generating circuit 21 includes, for example, transistors M11 and M12 (e.g., NMOSFETs), transistors M21 to M23 (e.g., NMOSFETs), transistors M24 and M25 (e.g., PMOSFETs), an operational amplifier AMP, current sources CS1 and CS2, and a resistor R4.

[0053] The drain of the transistor M11 is connected to the node to which the input voltage Vin is applied. The gates of the transistors M11 and M12 are both connected to the drain of the transistor M12. The source of the transistor M12 is connected to the first node of the resistor R4. The drain of the transistor M11 and the second node of the resistor R4 are both connected to the node to which the regulated voltage VREG is applied.

[0054] The transistors M11 and M12 and resistor R4 connected in this manner form a current mirror type output stage 201 that generates an output current Io that flows through transistor M11 by mirroring the bias current Ib that flows through transistor M12 with a mirror ratio α (at least the mirror ratio α is 10 times or more).

[0055] The transistor M11 corresponds to a first N-channel transistor connected between the application terminal of the input voltage Vin and the application terminal of the stabilization voltage VREG. The transistor M12 corresponds to a second N-channel transistor configured to form a current mirror output stage 201 together with the transistor M11, thereby mirroring the bias current Ib flowing through the transistor M12 to generate the output current Io flowing through the transistor M11.

[0056] A first terminal of the current source CS1 is connected to the power supply terminal, and a second terminal of the current source CS1 is connected to the drains of the transistors M21 and M23, respectively. The current source CS1 thus connected functions as a first bias current generating circuit configured to generate a first bias current I1.

[0057] The gate of the transistor M23 is connected to the output terminal of the operational amplifier AMP (corresponding to the application terminal of the gate drive signal G23). The source of the transistor M23 is connected to the ground terminal. The operational amplifier AMP generates the gate drive signal G23 in response to the reference voltage VREF input to the inverting input terminal (-) and the feedback voltage VFB input to the non-inverting input terminal (+).

[0058] The transistor M23 and the operational amplifier AMP connected in this manner function as a second bias current generating circuit configured to generate a second bias current I2 (corresponding to the drain current of the transistor M23) according to the difference between the feedback voltage VFB and the reference voltage VREF. The second bias current I2 decreases when the feedback voltage VFB is lower than the reference voltage VREF, and increases when the feedback voltage VFB is higher than the reference voltage VREF.

[0059] The gates of the transistors M21 and M22 are both connected to the drain of the transistor M21. The sources of the transistors M21 and M22 are both connected to the ground terminal. The transistors M21 and M22 connected in this manner function as a first current mirror CM1 configured to generate a fourth bias current I4 flowing through the transistor M22 by mirroring a third bias current I3 (=I1-I2) flowing through the transistor M21 as a differential current obtained by subtracting the second bias current I2 from the first bias current I1, with a mirror ratio β (β≧1).

[0060] The gates of the transistors M24 and M25 are both connected to the drain of the transistor M24. The sources of the transistors M24 and M25 are both connected to the terminal to which the input voltage Vin is applied. The drain of the transistor M25 is connected to the drain of the transistor M12. The transistors M24 and M25 connected in this manner function as a second current mirror CM2 configured to generate a bias current Ib flowing through the transistor M25 by mirroring a fifth bias current I5 flowing through the transistor M24 with a mirror ratio γ (where γ≧1).

[0061] Furthermore, when a current mirror (not shown) is inserted between the drains of the transistors M22 and M24, the fifth bias current I5 becomes δ times (where δ≧1) the fourth bias current I4. In this case, the bias current Ib flowing through the transistor M12 is expressed as (I1−I2)×β×γ×δ.

[0062] The first bias current I1 is a fixed value, and the second bias current I2 is a variable value. Therefore, the bias current Ib decreases as the second bias current I2 increases, and decreases as the second bias current I2 decreases. In other words, the bias current Ib increases when the feedback voltage VFB is lower than the reference voltage VREF, and decreases when the feedback voltage VFB is higher than the reference voltage VREF. The bias current Ib reaches a maximum value Ibmax (= I1 × β × γ × δ) when the second bias current I2 is zero.

[0063] In this way, the current source CS1, the transistors M21 to M25, and the operational amplifier AMP form a feedback control unit 202 configured to control the bias current Ib in accordance with the difference between the feedback voltage VFB corresponding to the stabilization voltage VREG and a predetermined reference voltage VREF.

[0064] A first terminal of the current source CS2 is connected to the application terminal of the regulated voltage VREG. A second terminal of the current source CS2 is connected to the ground terminal. The current source CS2 connected in this manner functions as a sink current generating circuit configured to draw a predetermined sink current Is from the application terminal of the regulated voltage VREG.

[0065] Incidentally, if the transistor M11 forming the output stage 201 is an N-channel type, if the difference between the input voltage Vin and the stabilization voltage VREG is small, it becomes impossible to ensure the gate-source voltage Vgs (=Vg-Vs) of the transistor M11, and it becomes impossible to maintain the transistor M11 in the ON state. As a result, it becomes impossible to set the reduced voltage limit voltage of the semiconductor device 10 (corresponding to the low input protection threshold of the low input protection circuit 1A) low.

[0066] In order to reduce the dissipation limit voltage of the semiconductor device 10, an element with a low on-threshold voltage Vth (a so-called low-Vth element) can be used as the transistor M11. However, low-Vth elements generally have a large output leakage current at high temperatures (= the leakage component of the output current Io that leaks even when the transistor M11 is fully off). Therefore, when using a low-Vth element as the transistor M11, it is desirable to take measures to suppress the output leakage current at high temperatures.

[0067] If the current source CS2 is used to extract the sink current Is from the application terminal of the regulated voltage VREG, the increase in the regulated voltage VREG can be suppressed even if the output leakage current of the transistor M11 increases at high temperatures. However, this configuration does not suppress the output leakage current itself, and therefore cannot eliminate the increase in the circuit current Ic consumed by the linear regulator 20.

[0068] In the following, in view of the above considerations, a second embodiment capable of suppressing output leakage current at high temperatures will be proposed.

[0069] <Linear Regulator (Second Embodiment)> Fig. 4 is a diagram showing a second embodiment of the linear regulator 20. In the linear regulator 20 of this embodiment, the stabilized voltage generating circuit 21 further includes a load 203 and a bias current adjusting unit 204 in addition to the above-mentioned components.

[0070] The load 203 is configured to draw a first leakage current ILK1 from the gate common to both the transistors M11 and M12. Referring to the figure, the load 203 includes a transistor M31 (e.g., an NMOSFET).

[0071] The drain of the transistor M31 is connected to the gates of the transistors M11 and M12. The source and gate of the transistor M31 are both connected to the ground terminal. That is, the transistor M31 is always in a fully off state. The transistor M31 corresponds to an N-channel third transistor configured to have the same leakage current characteristics as the transistor M11.

[0072] According to this configuration, when the first leakage current ILK1 flowing through the transistor M31 increases at high temperatures, the gate-source voltage Vgs of the transistor M11 becomes a negative voltage (= a state in which the gate voltage Vg of the transistor M11 is lower than the source voltage Vs). Therefore, the on-resistance of the transistor M11 is increased, which suppresses an increase in the output leakage current flowing through the transistor M11 and eliminates an increase in the circuit current Ic of the linear regulator 20.

[0073] In particular, under a light load condition, the output current Io flowing through the transistor M11 is reduced, increasing the ratio of the output leakage current to the circuit current Ic of the linear regulator 20. Therefore, by introducing the load 203 to suppress the increase in the output leakage current, it becomes possible to improve the efficiency at high temperatures under a light load condition.

[0074] The bias current adjusting unit 204 is configured to increase the bias current Ib by at least the same amount as the first leakage current ILK1 when the transistor M11 is turned on.

[0075] Referring to this figure, the bias current adjusting section 204 includes a transistor M41 (for example, an NMOSFET) and transistors M42 and M43 (for example, PMOSFETs).

[0076] The drain of the transistor M41 is connected to the drain of the transistor M42. The source and gate of the transistor M41 are both connected to the ground terminal. In other words, the transistor M41 is always in a fully off state. The transistor M41 corresponds to an N-channel fourth transistor configured to have the same leakage current characteristics as the transistor M31 (and therefore the transistor M11).

[0077] The gates of the transistors M42 and M43 are both connected to the drain of the transistor M42. The sources of the transistors M42 and M43 are both connected to the power supply terminal. The drain of the transistor M43 is connected to the drains of the transistors M21 and M23. The transistors M42 and M43 connected in this manner function as a third current mirror CM3 configured to generate a mirror current I6 flowing through the transistor M43 by mirroring the second leakage current ILK2 flowing through the transistor M42 with a mirror ratio ε. The mirror ratio ε depends on the device sizes of the transistors M31 and M41. When the device sizes of the transistors M31 and M41 are the same, ε≧1 / (β×γ×δ). The mirror ratio ε needs to be set to a large value in consideration of variations in the transistors M31 and M41 and variations in the third current mirror CM3.

[0078] In addition, with the introduction of the bias current adjustment unit 204, the third bias current I3 flowing through the transistor M21 of the first current mirror CM1 becomes a differential current (= I1 - I2 + ILK2 × ε) obtained by subtracting the second bias current I2 from the sum current I7 (= I1 + I6) of the mirror current I6 (= ILK2 × ε) of the second leakage current ILK2 and the first bias current I1.

[0079] Therefore, for example, when the feedback voltage VFB is lower than the reference voltage VREF and the transistor M23 is in a fully off state (I2=0), the maximum value Ibmax of the bias current Ib is (I1+ILK2×ε)×β×γ×δ. That is, by introducing the bias current adjustment unit 204, the maximum value Ibmax of the bias current Ib is increased by an additional amount ILK2×β×γ×δ×ε (≧ILK1) according to the second leakage current ILK2.

[0080] According to this configuration, when the first leakage current ILK1 increases at high temperatures, the second leakage current ILK2 also increases in the same manner, thereby increasing the maximum value Ibmax of the bias current Ib. Therefore, with the minimum necessary mirror current I6, it is possible to prevent the first leakage current ILK1 from becoming larger than the maximum value Ibmax of the bias current Ib due to variations in elements, etc. In other words, there is an advantage in that unnecessary current does not flow at temperatures where the first leakage current ILK1 is small.

[0081] Therefore, for example, even if the first bias current I1 is set to an extremely small current value in order to reduce the circuit current Ic of the linear regulator 20, there is no shortage of the bias current Ib necessary to turn on the transistor M11. Therefore, there is no problem in the on transition of the transistor M11, and the output current supply capability of the linear regulator 20 is not impaired.

[0082] On the other hand, when the feedback voltage VFB becomes higher than the reference voltage VREF, the transistor M23 is fully on, and the mirror current I6 corresponding to the second leakage current ILK2 is entirely drawn by the transistor M23, so that the negative bias operation of the gate-source voltage Vgs described above due to the first leakage current ILK1 is not impaired.

[0083] <Temperature Characteristics> Figure 5 is a diagram showing the temperature characteristics of the source voltage Vs (= stabilization voltage VREG) and gate voltage Vg of the transistor M11. Note that the horizontal axis of this figure represents temperature, and the vertical axis of this figure represents voltage. Regarding the gate voltage Vg, the solid line represents the behavior in the second embodiment (Figure 4), and the dashed line represents the behavior in the first embodiment (Figure 3).

[0084] As shown in this figure, in the first embodiment (dashed line), even when the temperature rises, the gate voltage Vg of the transistor M11 only drops to the source voltage Vs. On the other hand, in the second embodiment (solid line), as the temperature rises, the gate voltage Vg of the transistor M11 falls below the source voltage Vs. In other words, at high temperatures, the gate-source voltage Vgs (= Vg - Vs) of the transistor M11 becomes a negative voltage. Therefore, the on-resistance of the transistor M11 is increased, suppressing an increase in the output leakage current flowing through the transistor M11 and eliminating an increase in the circuit current Ic of the linear regulator 20.

[0085] 6 is a diagram showing the temperature characteristics of the circuit current Ic of the linear regulator 20. The horizontal axis of this diagram represents temperature, and the vertical axis of this diagram represents current. The solid line represents the behavior of the second embodiment (FIG. 4), and the dashed line represents the behavior of the first embodiment (FIG. 3).

[0086] As shown in this figure, the second embodiment (solid line) can suppress the circuit current Ic of the linear regulator 20 at high temperatures to a smaller value than the first embodiment (broken line).

[0087] <Summary> The various embodiments described above will be summarized below.

[0088] The linear regulator disclosed in this specification has a configuration (first configuration) including: an N-channel first transistor configured to be connected between an input voltage application terminal and a stabilizing voltage application terminal; an N-channel second transistor configured to form a current mirror output stage together with the first transistor, thereby mirroring a bias current flowing through the first transistor and generating an output current flowing through the first transistor; a feedback control unit configured to control the bias current in accordance with the difference between a feedback voltage corresponding to the stabilizing voltage and a predetermined reference voltage; and a load configured to draw a first leakage current from a control terminal common to both the first transistor and the second transistor.

[0089] In the linear regulator according to the first configuration, the load may be configured (second configuration) to include a third N-channel transistor configured to have the same leakage current characteristics as the first transistor.

[0090] The linear regulator according to the first or second configuration may be configured (third configuration) to further include a bias current adjustment unit configured to increase the bias current by at least the same amount as the first leakage current when the first transistor is turned on.

[0091] In the linear regulator according to the third configuration, the bias current adjusting unit may be configured (fourth configuration) to include a fourth N-channel transistor configured to have the same leakage current characteristics as the load.

[0092] In addition, in a linear regulator having any of the above first to third configurations, the feedback control unit may be configured (fifth configuration) to include a first bias current generation circuit configured to generate a predetermined first bias current, a second bias current generation circuit configured to generate a second bias current corresponding to the difference between the feedback voltage and the reference voltage, and a current mirror configured to mirror a differential current obtained by subtracting the second bias current from the first bias current to generate the bias current.

[0093] Furthermore, in the linear regulator according to the fourth configuration, the feedback control unit may be configured (sixth configuration) to include a first bias current generation circuit configured to generate a predetermined first bias current, a second bias current generation circuit configured to generate a second bias current corresponding to the difference between the feedback voltage and the reference voltage, and a current mirror configured to mirror a difference current obtained by subtracting the second bias current from the sum of a second leakage current or its mirror current flowing through the fourth transistor and the first bias current, thereby generating the bias current.

[0094] The linear regulator according to any one of the first to sixth configurations may be configured (seventh configuration) to further include a sink current generating circuit configured to extract a predetermined sink current from the application terminal of the stabilized voltage.

[0095] In the linear regulator according to any one of the first to seventh configurations, the output stage may have a mirror ratio of 10 or more (eighth configuration).

[0096] Furthermore, for example, the semiconductor device disclosed in this specification has a configuration (ninth configuration) including a linear regulator having any one of the first to eighth configurations.

[0097] Furthermore, for example, a switching power supply disclosed in this specification includes a semiconductor device having the ninth configuration described above, and is configured to drive a switch output stage to generate a desired output voltage from the input voltage (tenth configuration).

[0098] <Other Modifications> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0099] 10 Semiconductor device (power supply control IC) 11 Error amplifier 12 Comparator 13 On-time setting circuit 14 Ripple generation circuit 15 Adder circuit 16 Drive control circuit 161 Controller 162, 163 Driver 17 Soft start circuit 18 Reference voltage generation circuit 19 Power good detection circuit 1A Low input protection circuit 1B Overheat protection circuit 1C Overvoltage protection circuit 1D Short circuit protection circuit 1E Overcurrent protection circuit 1F Zero cross detection circuit 20 Linear regulator 21 Stabilized voltage generation circuit 22, 23 Resistor 201 Output stage 202 Feedback control unit 203 Load 204 Bias current adjustment unit AMP Operational amplifier C1 to C3 Capacitors CS1, CS2 Current source L1 Inductor M1 Output element (NMOSFET) M2 Synchronous rectification element (NMOSFET) M3, M4 Transistor (NMOSFET) M11, M12 Transistor (NMOSFET) M21 to M23 Transistor (NMOSFET) M24, M25 Transistor (PMOSFET) M31 Transistor (NMOSFET) M41 Transistor (NMOSFET) M42, M43 Transistor (PMOSFET) R1 to R4 Resistor SWO Switch output stage X Switching power supply

Claims

1. a first N-channel transistor configured to be connected between an application terminal of the input voltage and an application terminal of the stabilizing voltage; a second N-channel transistor configured to form a current mirror type output stage together with the first transistor, thereby mirroring a bias current flowing through the second N-channel transistor to generate an output current flowing through the first transistor; a feedback control unit configured to control the bias current in response to a difference between a feedback voltage corresponding to the stabilized voltage and a predetermined reference voltage; a load configured to draw a first leakage current from a control terminal common to both the first transistor and the second transistor; A linear regulator comprising:

2. 2. The linear regulator of claim 1, wherein the load includes a third transistor of an N-channel type configured to have the same leakage current characteristics as the first transistor.

3. 2. The linear regulator of claim 1, further comprising a bias current adjustment section configured to increase the bias current by at least the first leakage current when turning on the first transistor.

4. 4. The linear regulator according to claim 3, wherein the bias current adjustment section includes a fourth N-channel transistor configured to have the same leakage current characteristics as the load.

5. The feedback control unit is a first bias current generating circuit configured to generate a first predetermined bias current; a second bias current generating circuit configured to generate a second bias current corresponding to a difference between the feedback voltage and the reference voltage; a current mirror configured to mirror a difference current obtained by subtracting the second bias current from the first bias current to generate the bias current; 2. The linear regulator of claim 1 , comprising:

6. The feedback control unit is a first bias current generating circuit configured to generate a first predetermined bias current; a second bias current generating circuit configured to generate a second bias current corresponding to a difference between the feedback voltage and the reference voltage; a current mirror configured to generate the bias current by mirroring a difference current obtained by subtracting the second bias current from a sum current of a second leakage current or a mirror current thereof flowing through the fourth transistor and the first bias current; 5. The linear regulator of claim 4, comprising:

7. 2. The linear regulator according to claim 1, further comprising a sink current generating circuit configured to draw a predetermined sink current from an application terminal of the regulated voltage.

8. 2. The linear regulator of claim 1, wherein the output stage has a mirror ratio of 10 or greater.

9. A semiconductor device comprising the linear regulator according to any one of claims 1 to 8.

10. 10. A switching power supply comprising the semiconductor device according to claim 9, for driving a switch output stage to generate a desired output voltage from the input voltage.