Electronic circuit and method for testing same

Abstract

Provided is an electronic circuit which has a functional circuit and is capable of preventing a mistaken test mode operation from occurring when used in a shopping market, etc. An electronic circuit according to the present invention is equipped with a functional circuit which has a prescribed function, and a test circuit for testing in order to debug the functional circuit. The electronic circuit is equipped with: an input circuit for decoding an enable signal for switching the electronic circuit to an operational state, and outputting the decoded enable signal to the functional circuit; a test signal generator for producing a trigger signal for a test signal on the basis of a signal change included in the enable signal; and a computing element for computing a NOR operation of the decoded enable signal and the trigger signal, and outputting the signal from the computing results to the test circuit as a test signal for instructing so as to execute said test.

Description

Electronic circuits and their inspection methods

[0001] The present invention relates to an electronic circuit having a functional circuit with a predetermined function, and a method for testing the same.

[0002] It is already known that a test mode is provided for the purpose of shipping tests that are not used by users in the market, or for debugging purposes.

[0003] For example, Patent Document 1 provides an integrated circuit, an electronic circuit board, a DC-DC converter, and a method for testing these circuits that can achieve miniaturization. In the integrated circuit according to this conventional example, when a specific test signal is input to a functional circuit FC, its output terminals SW, E (V ＯＵＴ ) outputs a monitor signal corresponding to the test signal. If the functional circuit is normal, the value of the monitor signal input to the determiner will be the signal expected when the functional circuit is normal, but if it is abnormal, the value will be different from the normal signal. Therefore, by inputting the test signal from the test circuit to the functional circuit, it is possible to test the functional circuit. Since the test signal is input to the test circuit via the power supply terminal Vcc of the functional circuit, an additional terminal for testing is not required, and the device can be made smaller.

[0004] Japanese Patent Application Laid-Open No. 2008-224247

[0005] However, with previous test signal entry circuits, it was not possible to disable the test signal after inspection and retest it, or if the signal was not disabled, there was a problem that the device would mistakenly enter test mode operation in the field, resulting in unexpected behavior.

[0006] SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to provide an electronic circuit having a functional circuit that can prevent the circuit from erroneously entering a test mode when used in the market, and a method for testing the electronic circuit.

[0007] An electronic circuit according to a first aspect of the present invention comprises: a functional circuit having a predetermined function; and a test circuit that performs tests for debugging the functional circuit, and comprises: an input circuit that decodes an enable signal that puts the electronic circuit into an operating state and outputs the decoded enable signal to the functional circuit; a test signal generator that generates a trigger signal for a test signal based on a signal change included in the enable signal; and an arithmetic element that performs a NOR operation on the decoded enable signal and the trigger signal and outputs the signal resulting from the operation to the test circuit as a test signal that instructs the test to be performed.

[0008] An electronic circuit according to a second aspect of the present invention is an electronic circuit comprising: a functional circuit having a predetermined function; and a test circuit that performs tests for debugging the functional circuit, and comprises: a first input circuit that decodes an enable signal that puts the electronic circuit into an operating state and outputs a decoded enable signal to the functional circuit; a second input circuit that decodes a predetermined command signal and outputs a decoded command signal to the functional circuit; a test signal generator that generates a trigger signal for a test signal based on a signal change included in the command signal; and an arithmetic element that performs a NOR operation on the decoded enable signal and the trigger signal and outputs the signal resulting from the operation to the test circuit as a test signal that instructs the test to be performed.

[0009] An electronic circuit according to a third aspect of the present invention is an electronic circuit comprising: a functional circuit having a predetermined function; and a test circuit that performs tests for debugging the functional circuit, and comprises: a first input circuit that decodes an enable signal that puts the electronic circuit into an operating state and outputs a decoded enable signal to the functional circuit; a second input circuit that decodes a predetermined first command signal and outputs a first decoded command signal to the functional circuit; a first test signal generator that generates a first trigger signal for a test signal based on a signal change included in the first command signal; a third input circuit that decodes a predetermined second command signal and outputs a second decoded command signal to the functional circuit; a second test signal generator that generates a second trigger signal for a test signal based on a signal change included in the second command signal; and an arithmetic element that performs a NOR operation on the decoded enable signal, the first trigger signal, and the second trigger signal, and outputs a signal resulting from the operation to the test circuit as a test signal instructing the test to be performed.

[0010] Therefore, the electronic circuit etc. according to the present invention is provided with an arithmetic element that performs a NOR operation between the decoding enable signal or the encoding command signal and the trigger signal, and outputs the signal resulting from the operation to the inspection circuit as a test signal that instructs the execution of the inspection, so that an electronic circuit having the functional circuit can be prevented from mistakenly entering test mode operation when used in the market.

[0011] 14 is a block diagram showing an example of the configuration of an electronic circuit 1 according to embodiment 1. FIG. 15 is a timing chart of each voltage showing the operation of the electronic circuit 1 of FIG. 1. FIG. 16 is a circuit diagram showing an example of the configuration of a test signal generator 13A according to modified example 1. FIG. 17 is a timing chart of each voltage showing the operation of the test signal generator 13A of FIG. 3. FIG. 18 is a circuit diagram showing an example of the configuration of a test signal generator 13B according to modified example 2. FIG. 19 is a timing chart of each voltage showing the operation of the test signal generator 13B of FIG. 5. FIG. 19 is a circuit diagram showing an example of the configuration of a test signal generator 13C according to modified example 3. FIG. 19 is a circuit diagram showing an example of the configuration of a test signal generator 13D according to modified example 4. FIG. 19 is a block diagram showing an example of the configuration of an electronic circuit 1A according to embodiment 2. FIG. 20 is a timing chart of each voltage showing the operation of the electronic circuit 1A of FIG. 9. FIG. 21 is a block diagram showing an example of the configuration of an electronic circuit 1B according to embodiment 3. FIG. 22 is a block diagram showing an example of the configuration of an electronic circuit 1C according to embodiment 4. FIG. 23 is a block diagram showing the configuration of an electronic circuit 101 according to a comparative example. FIG. 24 is a circuit diagram showing the configuration of the test signal generator 13 of FIG. 13. FIG. 25 is a timing chart of each voltage showing the operation of the test signal generator 13 of FIG. 15 is a timing chart of each voltage when noise is superimposed on the ground line in the test signal generator 13 of Fig. 14. FIG. 16 is a timing chart of each voltage when noise is superimposed on the connection line of the terminal T2 in the test signal generator 13 of Fig. 14.

[0012] Hereinafter, embodiments and modifications of the present invention will be described with reference to the drawings, in which the same or similar components are designated by the same reference numerals.

[0013] (Inventor's Knowledge) Patent Document 1 discloses a configuration that allows testing without adding a terminal dedicated to testing, but does not solve the problem of not being able to retest because the terminal is disabled after testing. That is, in the state of "chip enable signal EN = H level" where the functional circuit is operating, no state transition occurs even if the test mode entry condition is met, so malfunctions in actual use can be avoided without disabling the testing function after testing.

[0014] FIG. 13 is a block diagram showing the configuration of an electronic circuit 101 according to a comparative example.

[0015] 13 , an electronic circuit 101 includes terminals T1 and T2, input interfaces 11 and 12, a test signal generator 13, and a functional circuit 10 that performs a predetermined function and incorporates a test circuit 20. The input interface 11 decodes a chip enable signal EN input to the terminal T1 into a chip enable signal ENa, which is a predetermined rising edge signal, and outputs the signal to the functional circuit 10. The input interface 12 decodes a command signal XXX input to the terminal T2 into a command signal XXXa, which is a predetermined rising edge signal, and outputs the signal to the functional circuit 10. The test signal generator 13 outputs an H-level test signal TEST to the functional circuit 10 when the command signal XXX input to the terminal T2 satisfies a predetermined test mode signal condition. In response to the H-level test signal TEST, the test circuit 20 incorporated in the functional circuit 10 performs a predetermined test for debugging the functional circuit 10.

[0016] Fig. 14 is a circuit diagram showing the configuration of the test signal generator 13 of Fig. 13. Fig. 15 is a timing chart of each voltage showing the operation of the test signal generator 13 of Fig. 14. In Fig. 15 and other figures, Vxxx represents the voltage of the command signal XXX.

[0017] 14, the test signal generator 13 is configured to include an N-channel MOS transistor Mtest, a resistor R11, and an inverter INV1. Here, the power supply voltage Vdd is connected to a terminal T2 via the resistor R11 and the drain and source of the MOS transistor Mtest. The gate of the MOS transistor Mtest is grounded, and the MOS transistor Mtest is in an off state. The signal from the drain of the MOS transistor Mtest is inverted by the inverter INV1 and then output as a test signal TEST.

[0018] In the test signal generator 13 configured as above, as shown in FIG. 15, when the voltage at the terminal T2 becomes equal to or lower than the voltage Vgtest which is the threshold voltage of the MOS transistor Mtest, the test signal TEST becomes H level.

[0019] That is, in the circuits of FIGS. 13 and 14, in order to enter the functional circuit 10 into the test mode without adding a dedicated terminal, the entry condition is outside the recommended operating conditions of the terminals used to control the integrated circuit.

[0020] However, when the electronic circuit 101 is used in a switching regulator, the output voltage as well as the power supply voltage and ground voltage may fluctuate due to switching noise, etc., and the entry condition may be met. In addition, noise may be mixed into the voltage of the command signal XXX at the terminal T2, which is an external input.

[0021] 16 is a timing chart of voltages when noise is superimposed on the ground line of the test signal generator 13 of FIG. 14. In FIG. 16 and other figures, Vgnd represents the ground voltage. As is clear from FIG. 16, there are cases where the ground voltage changes and the test signal TEST erroneously goes high.

[0022] Fig. 17 is a timing chart of each voltage when noise is superimposed on the connection line of the terminal T2 in the test signal generator 13 of Fig. 14. As is clear from Fig. 17, there are cases where the voltage of the command signal XXX changes and the test signal TEST becomes H level.

[0023] Normally, the entry state of the test mode is latched, so if the test signal TEST goes to H level even once as shown in FIG. 16 or 17, there is a problem that recovery is not possible unless the functional circuit 10 of the electronic circuit 101 is restarted.

[0024] The present inventors have devised the following embodiment and modifications to solve the above-mentioned problems. The embodiment according to the present invention has the following characteristics when a test mode is implemented for use in shipping tests or debugging: "When the functional circuit 10 is operating and the chip enable signal EN is at H level, the test signal TEST does not transition from L level to H level even if the test mode entry condition is met."

[0025] (First Embodiment) Fig. 1 is a block diagram showing an example of the configuration of an electronic circuit 1 according to a first embodiment. Fig. 2 is a timing chart of each voltage showing the operation of the electronic circuit 1. Here, the test signal generator 13 in Fig. 1 has, for example, the circuit configuration shown in Fig. 14. The electronic circuit 1 in Fig. 1 differs from the electronic circuit 101 in Fig. 13 in the following respects: (1) The test signal from the test signal generator 13 is a trigger signal TRG. (2) The electronic circuit 1 further includes a NOR gate 14, which is an arithmetic element that performs a NOR operation on the enable signal ENa and the trigger signal TRG and outputs the signal resulting from the operation as a test signal TEST to the functional circuit 10.

[0026] 14 and 15, the test signal generator 13 sets the test signal TEST to H level when the voltage at the terminal T2 becomes equal to or lower than the voltage Vgtest, which is the threshold voltage of the MOS transistor Mtest. In response to the H-level test signal TEST, the test circuit 20 built into the functional circuit 10 executes a predetermined test for debugging the functional circuit 10.

[0027] The test mode is not disabled even after the shipping inspection. The input interfaces 11 and 12 are an example of an input circuit that decodes an input signal and outputs a coded signal.

[0028] In the electronic circuit 1 configured as described above, when the enable signal ENa is at H level, the NOR gate 14 prevents the test signal TEST from being output at H level even if the test signal generator 13 outputs an H level trigger signal TRG. That is, as shown in Fig. 2, even if noise is superimposed on the ground voltage or an H level trigger signal TRG is output, the electronic circuit 1 is configured not to output an H level test signal TEST as long as the enable signal ENa is at H level.

[0029] As described above, according to the first embodiment, in the "chip enable signal EN=H level" state in which the functional circuit 10 is operating, even if the test mode entry condition is met, the test signal TEST does not transition from L level to H level, i.e., it is possible to prevent the generation of an H level test signal TEST. Therefore, it is possible to prevent the electronic circuit 1 having the functional circuit from erroneously entering the test mode when used in the market.

[0030] The functional circuit 10 in FIG. 1 and the following figures is, for example, a linear regulator, a switching regulator, a reference voltage generating circuit, a protection circuit for electronic circuits, a memory circuit, a digital processing circuit, or the like.

[0031] (Modification 1) Fig. 3 is a circuit diagram showing an example of the configuration of a test signal generator 13A according to Modification 1. Fig. 4 is a timing chart of each voltage showing the operation of the test signal generator 13A of Fig. 3.

[0032] 3, the test signal generator 13A includes a DC offset voltage source 15 that applies a predetermined offset voltage to the command signal, and a comparator 16. The command signal XXX input to terminal T2 is DC offset in the positive voltage direction by the DC voltage source 15 and then input to the inverting input terminal of the comparator 16. The non-inverting input terminal of the comparator 16 is grounded. The comparator 16 outputs an H-level test signal TEST when the voltage at the inverting input terminal falls below the voltage at the non-inverting input terminal (signal change included in the command signal XXX). That is, as shown in FIG. 4, the comparator 16 outputs an H-level test signal TEST when the voltage Vxxx of the command signal XXX falls below −Voffset.

[0033] According to the first modification configured as described above, in the same manner as in the first embodiment, when the functional circuit 10 is operating and the "chip enable signal EN=H level," the test signal TEST does not transition from L level to H level even if the test mode entry condition is met, i.e., it is possible to prevent the generation of an H level test signal TEST. Therefore, it is possible to prevent the electronic circuit 1 having the functional circuit from erroneously entering the test mode when used in the market.

[0034] (Modification 2) Fig. 5 is a circuit diagram showing an example of the configuration of a test signal generator 13B according to Modification 2. Fig. 6 is a timing chart of each voltage showing the operation of the test signal generator 13B of Fig. 5.

[0035] 5, the test signal generator 13A includes a DC offset voltage source 15 that applies a predetermined offset voltage to the command signal, and a comparator 16. The command signal XXX input to terminal T2 is DC offset in the negative voltage direction by the DC voltage source 15 and then input to the non-inverting input terminal of the comparator 16. The inverting input terminal of the comparator 16 is connected to the power supply voltage Vdd. The comparator 16 outputs an H-level test signal TEST when the voltage at the non-inverting input terminal is equal to or greater than the voltage at the inverting input terminal. That is, as shown in FIG. 6, the comparator 16 outputs an H-level test signal TEST when the voltage Vxxx of the command signal XXX is equal to or greater than (Vdd + Voffset).

[0036] According to the second modification configured as described above, in the same way as in the first embodiment and the first modification, when the functional circuit 10 is operating and the "chip enable signal EN=H level", the test signal TEST does not transition from L level to H level even if the test mode entry condition is met, i.e., it is possible to prevent the generation of an H level test signal TEST. Therefore, it is possible to prevent the electronic circuit 1 having the functional circuit from erroneously entering the test mode when used in the market.

[0037] (Modification 3) Fig. 7 is a circuit diagram showing an example of the configuration of a test signal generator 13C according to Modification 3. In Fig. 7, the test signal generator 13C differs from the test signal generator 13B in Fig. 5 in the following respects: (1) Instead of the offset DC voltage source 15, voltage-dividing resistors R1 and R2 are provided which are connected in series with each other and inserted between the terminal T2 and the ground.

[0038] 7, the voltage of the command signal XXX input to the terminal T2 is divided by the voltage-dividing resistors R1 and R2, and the divided voltage is input to the non-inverting input terminal of the comparator 16. The test signal generator 13C configured as above operates in the same manner as the second modification in FIG. 5, and has the same effects.

[0039] (Modification 4) Fig. 8 is a circuit diagram showing an example of the configuration of a test signal generator 13D according to Modification 4. In Fig. 8, the test signal generator 13D differs from the test signal generator 13C in Fig. 7 in the following respects: (1) The power supply voltage Vdd is divided by voltage-dividing resistors R3 and R4 connected in series with each other, and the divided voltage is input to the inverting input terminal of the comparator 16.

[0040] In FIG. 8, the test signal generator 13D configured as described above operates in the same manner as the third modification example in FIG. 7 and has the same effects as the third modification example in FIG. 7, except that the comparison reference voltage of the comparator 16 is a predetermined voltage lower than the power supply voltage Vdd.

[0041] (Embodiment 2) Fig. 9 is a block diagram showing an example of the configuration of an electronic circuit 1A according to embodiment 2. The electronic circuit 1A of Fig. 9 differs from the electronic circuit 1 of Fig. 1 in the following respects: (1) A delay circuit 17 that delays the input signal by a predetermined delay time Td is inserted between the output terminal of the test signal generator 13 and the input terminal of the NOR gate 14. Here, the delay time Td corresponds to the signal processing time of the input interface 11. The differences will be described below.

[0042] In FIG. 9, the delay circuit 17 delays the trigger signal TRG from the test signal generator 13 by a predetermined delay time Td, and then outputs a delay signal TDLY to the NOR gate 14 .

[0043] Fig. 10 is a timing chart of each voltage showing the operation of the electronic circuit 1A of Fig. 9. As is clear from Fig. 10, a circuit that fixes the test signal TEST to L level when the enable signal ENa is H level has a unique effect of being able to adjust the timing of the delay signal TDLY in consideration of the signal processing time of the input interface 11, etc. Other effects are the same as those of the first embodiment.

[0044] When the signal processing time of the input interface 11 is not taken into consideration, the delay circuit 17 may be omitted.

[0045] (Embodiment 3) Fig. 11 is a block diagram showing an example configuration of an electronic circuit 1B according to embodiment 3. The electronic circuit 1B of Fig. 11 differs from the electronic circuit 1A of Fig. 9 in the following respects: (1) It further includes a terminal T3 that receives another command signal YYY. (2) It further includes an input interface 22 and a test signal generator 23 that are connected to the terminal T3. (3) It includes a NOR gate 14A having three input terminals instead of the NOR gate 14. (4) It includes a delay circuit 17A having a configuration similar to the delay circuit 17, which is inserted between the test signal generator 23 and the NOR gate 14A. The differences will be described below.

[0046] 11, the input interface 22 decodes the command signal YYY input to the terminal T3 into a command signal YYYa, which is a predetermined rising edge signal, and then outputs it to the function circuit 10. Furthermore, the test signal generator 23 outputs an H-level trigger signal TRGA to the function circuit 10 as a delayed signal TDLYA via the delay circuit 17A when the command signal YYY input to the terminal T3 meets a predetermined signal condition for the test mode.

[0047] According to the third embodiment configured as described above, it is possible to generate the test signal TEST in response to the two command signals XXX and YYY, taking into consideration the signal processing time of the input interface 11. Other functions and effects are the same as those of the second embodiment.

[0048] It should be noted that the delay circuits 17 and 17A may be omitted when the signal processing time of the input interface 11 is not taken into consideration. In addition, in the fourth embodiment, the test signal TEST is generated using two trigger signals TRG and TRGA, but the present invention is not limited to this, and the test signal TEST may be generated using, for example, three or more trigger signals.

[0049] 12 is a block diagram showing an example of the configuration of an electronic circuit 1C according to a fourth embodiment. The electronic circuit 1C in FIG. 12 differs from the electronic circuit 1 in FIG. 1 in the following respects: (1) The terminal T2 and the input interface 12 are deleted. (2) The test signal generator 13 generates a trigger signal TRG based on an enable signal EN input to the terminal T1 under predetermined signal conditions (such as those of the first embodiment, the first modification, or the second modification) similar to the command signal XXX, and outputs the trigger signal TRG to the NOR gate 14 via the delay circuit 17 as a delayed signal TDLY.

[0050] According to the fourth embodiment configured as described above, the trigger signal TRG is generated based on the enable signal EN under predetermined signal conditions similar to those of the command signal XXX, so that the command signal XXX and the terminal T2 are not provided, and the enable signal EN serves as the entry condition for the command signal XXX, thereby generating the trigger signal TRG and the test signal TEST. Except for this, the fourth embodiment has the same effects as the first embodiment.

[0051] 12, if the signal processing time of the input interface 11 is not taken into consideration, the delay circuit 17 does not need to be provided. Also, the test signal generators 13 and 23 may be configured with the above-mentioned test signal generators 13A to 13D.

[0052] As described above in detail, the electronic circuit etc. according to the present invention can prevent an electronic circuit having a functional circuit from mistakenly entering a test mode when used by a user in the market.

[0053] 1, 1A to 1C, 101 Electronic circuit 10 Functional circuit 11, 12, 22 Input interface 13, 13A to 13D, 23 Test signal generator 14, 14A NOR gate 15 DC voltage source 16 Comparator 17, 17A Delay circuit 20 Inspection circuit INV1 Inverter Mtest MOS transistor R1 to R11 Resistor T1 to T3 Terminal

Claims

1. 1. An electronic circuit comprising: a functional circuit having a predetermined function; and a test circuit for performing a test for debugging the functional circuit, an input circuit for decoding an enable signal for putting the electronic circuit into an operating state and outputting the decoded enable signal to the functional circuit; a test signal generator that generates a trigger signal for a test signal based on a signal change included in the enable signal; an arithmetic element that performs a NOR operation on the decoding enable signal and the trigger signal, and outputs a signal resulting from the operation to the inspection circuit as a test signal instructing execution of the inspection; An electronic circuit comprising:

2. The electronic circuit further comprises: a delay circuit that is inserted between the test signal generator and the arithmetic element, delaying the trigger signal by a processing time of the input circuit and outputting the delayed trigger signal to the arithmetic element; The electronic circuit of claim 1 .

3. 1. An electronic circuit comprising: a functional circuit having a predetermined function; and a test circuit for performing a test for debugging the functional circuit, a first input circuit for decoding an enable signal for causing the electronic circuit to be in an operational state and outputting a decoded enable signal to the functional circuit; a second input circuit that decodes a predetermined command signal and outputs the decoded command signal to the functional circuit; a test signal generator that generates a trigger signal for a test signal based on a signal change included in the command signal; an arithmetic element that performs a NOR operation on the decoding enable signal and the trigger signal, and outputs a signal resulting from the operation to the inspection circuit as a test signal instructing execution of the inspection; An electronic circuit comprising:

4. The electronic circuit further comprises: a delay circuit that is inserted between the test signal generator and the arithmetic element, delaying the trigger signal by a processing time of the first input circuit and outputting the delayed trigger signal to the arithmetic element; The electronic circuit of claim 3 .

5. 1. An electronic circuit comprising: a functional circuit having a predetermined function; and a test circuit for performing a test for debugging the functional circuit, a first input circuit for decoding an enable signal for causing the electronic circuit to be in an operational state and outputting a decoded enable signal to the functional circuit; a second input circuit that decodes a predetermined first command signal and outputs a first decoded command signal to the functional circuit; a first test signal generator for generating a first trigger signal for a test signal based on a signal change included in the first command signal; a third input circuit that decodes a predetermined second command signal and outputs a second decoded command signal to the functional circuit; a second test signal generator for generating a second trigger signal for a test signal based on a signal change included in the second command signal; an arithmetic element that performs a NOR operation on the decoding enable signal, the first trigger signal, and the second trigger signal, and outputs a signal resulting from the operation to the inspection circuit as a test signal instructing to execute the inspection; An electronic circuit comprising:

6. The electronic circuit further comprises: a first delay circuit that is inserted between the first test signal generator and the arithmetic element, delaying the first trigger signal by a processing time of the first input circuit and outputting the delayed first trigger signal to the arithmetic element; a second delay circuit that is inserted between the second test signal generator and the arithmetic element, delaying the second trigger signal by a processing time of the first input circuit and outputting the delayed second trigger signal to the arithmetic element; 6. The electronic circuit of claim 5, comprising:

7. The test signal generator includes: a series circuit in which a resistor and a grounded-gate MOS transistor are connected in series, the series circuit being connected between a predetermined power supply voltage and an input terminal for the command signal; an inverter that inverts a signal from an output terminal of the MOS transistor and outputs the inverted signal as the trigger signal; An electronic circuit according to any one of claims 3 to 6.

8. The test signal generator includes: a DC voltage source that applies a predetermined offset voltage to a signal input to an input terminal of the command signal; a comparator that compares the signal to which the offset voltage has been applied with a power supply voltage or a ground voltage and outputs a comparison result signal as the trigger signal; The electronic circuit according to any one of claims 3 to 6, comprising:

9. The test signal generator includes: a voltage dividing resistor that divides a signal input to an input terminal of the command signal and outputs a divided voltage; a comparator that compares the divided voltage with a power supply voltage and outputs a comparison result signal as the trigger signal; The electronic circuit according to any one of claims 3 to 6, comprising:

10. The test signal generator includes: a first voltage dividing resistor that divides a power supply voltage and outputs a first divided voltage; a second voltage dividing resistor that divides a signal input to an input terminal of the command signal and outputs a second divided voltage; a comparator that compares the first divided voltage with the second divided voltage and outputs a comparison result signal as the trigger signal; The electronic circuit according to any one of claims 3 to 6, comprising:

11. 1. A method for testing an electronic circuit comprising: a functional circuit having a predetermined function; and a test circuit for performing a test for debugging the functional circuit, comprising: an input circuit for decoding an enable signal for causing the electronic circuit to be in an operational state and outputting a decoded enable signal to the functional circuit; a test signal generator generating a trigger signal for a test signal based on a signal change included in the enable signal; a calculation element performing a NOR operation on the decoding enable signal and the trigger signal, and outputting a signal resulting from the operation to the test circuit as a test signal instructing to execute the test; A method for inspecting an electronic circuit comprising:

12. 1. A method for testing an electronic circuit comprising: a functional circuit having a predetermined function; and a test circuit for performing a test for debugging the functional circuit, comprising: a first input circuit decoding an enable signal for causing the electronic circuit to be in an operational state and outputting a decoded enable signal to the functional circuit; a second input circuit decoding a predetermined command signal and outputting the decoded command signal to the function circuit; a test signal generator generating a trigger signal for a test signal based on a signal change included in the command signal; a calculation element performing a NOR operation on the decoding enable signal and the trigger signal, and outputting a signal resulting from the operation to the test circuit as a test signal instructing to execute the test; A method for inspecting an electronic circuit comprising:

13. 1. A method for testing an electronic circuit comprising: a functional circuit having a predetermined function; and a test circuit for performing a test for debugging the functional circuit, comprising: a first input circuit decoding an enable signal for causing the electronic circuit to be in an operational state and outputting a decoded enable signal to the functional circuit; a second input circuit decoding a predetermined first command signal and outputting a first decoded command signal to the functional circuit; a first test signal generator generating a first trigger signal for a test signal based on a signal change included in the first command signal; a third input circuit decoding a predetermined second command signal and outputting a second decoded command signal to the function circuit; a second test signal generator generating a second trigger signal for a test signal based on a signal change included in the second command signal; a calculation element performing a NOR operation on the decoding enable signal, the first trigger signal, and the second trigger signal, and outputting a signal resulting from the operation to the test circuit as a test signal instructing to execute the test; A method for inspecting an electronic circuit comprising: