Semiconductor device

Abstract

This semiconductor device comprises: a first lead that has a first surface facing the thickness direction; a semiconductor element supported on the first surface; and a plurality of wires each having first and second ends. The semiconductor element has an element main surface facing the thickness direction, and a main surface electrode formed in the element main surface. Each of the wires is joined at the first end to the main surface electrode. The wires include a first wire and a second wire. The second wire crosses over the first wire when viewed in the thickness direction.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Various configurations have been proposed for semiconductor devices including semiconductor elements. Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes a semiconductor element, multiple leads, multiple wires, and a sealing resin. The semiconductor element is mounted on one of the multiple leads. Each of the multiple wires is bonded to the semiconductor element and another lead different from the lead on which the semiconductor element is mounted. The other lead has multiple terminal portions. In a plan view, the other lead is arranged adjacent to the lead on which the semiconductor element is mounted in a certain direction (downward in the plane of the drawing in Figure 3 of Patent Document 1) on the side on which the multiple terminal portions are arranged. The sealing resin covers each portion of the multiple leads, the multiple wires, and the semiconductor element.

[0003] In the conventional semiconductor device described above, efforts are being made to miniaturize semiconductor elements. As the size of semiconductor elements decreases, the area of ​​the semiconductor elements to which wires can be bonded decreases. Therefore, it is necessary to efficiently arrange multiple wires to be bonded to the semiconductor elements while avoiding mutual interference.

[0004] Japanese Patent Application Laid-Open No. 2017-135241

[0005] An object of the present disclosure is to provide a semiconductor device that is improved over conventional devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that is suitable for efficiently arranging multiple wires on a semiconductor element.

[0006] A first aspect of the present disclosure provides a semiconductor device comprising: a first lead having a first surface facing one side in a thickness direction; a semiconductor element supported on the first surface; and a plurality of wires, each having a first end and a second end. The semiconductor element has a main surface facing one side in the thickness direction and a main surface electrode formed on the main surface. Each of the plurality of wires has the first end joined to the main surface electrode. The plurality of wires includes one or more first wires and one or more second wires. At least one of the one or more second wires straddles at least one of the one or more first wires when viewed in the thickness direction.

[0007] According to the above configuration, it is possible to provide a semiconductor device having a structure suitable for efficiently arranging a plurality of wires for a miniaturized semiconductor element.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 2. FIG. 6 is a right side view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 7 is a plan view showing a semiconductor device according to a first modified example of the first embodiment. FIG. 8 is a right side view showing a semiconductor device according to a first modified example of the first embodiment. FIG. 9 is a plan view showing a semiconductor device according to a second modified example of the first embodiment. FIG. 10 is a right side view showing a semiconductor device according to a second modified example of the first embodiment. FIG. 11 is a plan view showing a semiconductor device according to a third modified example of the first embodiment. FIG. 12 is a right side view showing a semiconductor device according to a third modified example of the first embodiment. FIG. 13 is a plan view showing a semiconductor device according to a fourth modified example of the first embodiment. FIG. 14 is a right side view showing a semiconductor device according to a fourth modified example of the first embodiment. Fig. 15 is a plan view showing a semiconductor device according to a fifth modified example of the first embodiment. Fig. 16 is a right side view showing a semiconductor device according to a fifth modified example of the first embodiment. Fig. 17 is a plan view showing a semiconductor device according to a second embodiment of the present disclosure. Fig. 18 is a right side view showing a semiconductor device according to the second embodiment of the present disclosure.

[0010] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0011] The terms "first," "second," "third," etc. in this disclosure are used merely for identification purposes and are not intended to necessarily assign any order to their objects.

[0012] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0013] 1 to 6 show a semiconductor device according to a first embodiment of the present disclosure. A semiconductor device A10 of this embodiment includes a first lead 1, a second lead 2, a third lead 3, a fourth lead 4, a semiconductor element 5, a plurality of wires 6, and a sealing resin 7.

[0014] 1 and 2 are plan views showing the semiconductor device A10. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 2. FIG. 6 is a right side view showing the semiconductor device A10. For ease of understanding, FIG. 2 is a perspective view showing the sealing resin 7. FIG. 6 is a perspective view showing the sealing resin 7, and omits the third lead 3, the fourth lead 4, and some of the multiple wires 6 (third wires 63 and fourth wires 64, which will be described later).

[0015] In the description of the semiconductor device A10, the thickness direction of the semiconductor element 5 is referred to as the "thickness direction z." A direction perpendicular to the thickness direction z is an example of the "first direction" and is referred to as the "first direction x." A direction perpendicular to both the thickness direction z and the first direction x is an example of the "second direction" and is referred to as the "second direction y."

[0016] The first lead 1, the second lead 2, the third lead 3, and the fourth lead 4 are formed, for example, by punching or bending a metal plate (lead frame). The thicknesses of the first lead 1, the second lead 2, the third lead 3, and the fourth lead 4 are not particularly limited and are, for example, approximately 0.1 mm to 2.0 mm. The first lead 1, the second lead 2, the third lead 3, and the fourth lead 4 are made of, for example, copper (Cu) or nickel (Ni), or an alloy thereof. Although detailed illustrations are omitted, most of the first lead 1, the second lead 2, the third lead 3, and the fourth lead 4 are covered, for example, with a plating layer. The material of the plating layer is not particularly limited and is, for example, made of an alloy mainly containing tin (Sn).

[0017] 2, the first lead 1, the second lead 2, the third lead 3, and the fourth lead 4 are spaced apart from one another when viewed in the thickness direction z (in a plan view). The first lead 1 has the largest size when viewed in the thickness direction z.

[0018] As shown in FIGS. 2 to 5 , the first lead 1 has a die pad 11, a first terminal portion 12, and a bent portion 13. The die pad 11 is, for example, rectangular when viewed in the thickness direction z. The die pad 11 has a first surface 11a and a second surface 11b. The first surface 11a faces the z1 side in the thickness direction z, and the second surface 11b faces the opposite side to the first surface 11a (the z2 side in the thickness direction z). The first surface 11a supports the semiconductor element 5. In this embodiment, the entire die pad 11 is covered with the sealing resin 7. The die pad 11 is an example of a "base."

[0019] The first terminal 12 is located on the x1 side in the first direction x with respect to the die pad 11. The first terminal 12 extends on the x1 side in the first direction x. The first terminal 12 is located at the end of the die pad 11 on the y1 side in the second direction y in the second direction y. The first terminal 12 is exposed from the sealing resin 7. The bent portion 13 connects the die pad 11 and the first terminal 12, and has a bent shape when viewed in the second direction y.

[0020] 2, 4, and 6, the second lead 2 has a pad portion 21 and a second terminal portion 22. When viewed in the thickness direction z, the pad portion 21 is located on the x1 side in the first direction x with respect to the die pad 11. The pad portion 21 extends along the second direction y. The second terminal portion 22 is connected to an end of the pad portion 21 on the y2 side in the second direction y and extends on the x1 side in the first direction x. The second terminal portion 22 is exposed from the sealing resin 7. When viewed in the thickness direction z, the second lead 2 is located on the y2 side in the second direction y with respect to the first terminal portion 12.

[0021] 2 , the third lead 3 has a pad portion 31 and a third terminal portion 32. The pad portion 31 is located on the x1 side in the first direction x with respect to the die pad 11 when viewed in the thickness direction z. The third terminal portion 32 is connected to the pad portion 31 and extends on the x1 side in the first direction x. The third terminal portion 32 is exposed from the sealing resin 7. When viewed in the thickness direction z, the third lead 3 is located on the y2 side in the second direction y with respect to the second lead 2. The third lead 3 is located at the end of the die pad 11 on the y2 side in the second direction y in the second direction y.

[0022] 2 , the fourth lead 4 has a pad portion 41 and a fourth terminal portion 42. The pad portion 41 is located on the x1 side in the first direction x with respect to the die pad 11 when viewed in the thickness direction z. The fourth terminal portion 42 is connected to the pad portion 41 and extends on the x1 side in the first direction x. The fourth terminal portion 42 is exposed from the sealing resin 7. When viewed in the thickness direction z, the fourth lead 4 is located on the y2 side in the second direction y with respect to the second lead 2. The fourth lead 4 is located between the second lead 2 and the third lead 3 in the second direction y.

[0023] The semiconductor element 5 is an element that exerts the electrical function of the semiconductor device A10. The type of the semiconductor element 5 is not particularly limited, and in this embodiment, the semiconductor element 5 is configured as a transistor. In the description of the semiconductor device A10, the semiconductor element 5 is a switching element, for example, an n-channel MOSFET, but it may also be a p-channel MOSFET. As shown in FIGS. 2 to 5 , the semiconductor element 5 has an element body 50, a first main surface electrode 51, a second main surface electrode 52, and a back surface electrode 53.

[0024] The element body 50 has a rectangular shape when viewed in the thickness direction z. More specifically, the element body 50 (semiconductor element 5) has an elongated rectangular shape with the second direction y as the longitudinal direction and the first direction x as the lateral direction. The element body 50 has an element main surface 50a and an element back surface 50b. The element main surface 50a and the element back surface 50b face opposite each other in the thickness direction z. The element main surface 50a faces the same side as the first surface 11a of the die pad 11 in the thickness direction z. Therefore, the element back surface 50b faces the first surface 11a.

[0025] The first principal-surface electrode 51 and the second principal-surface electrode 52 are disposed on the element principal surface 50a. The back surface electrode 53 is disposed on the element back surface 50b. The constituent materials of the first principal-surface electrode 51, the second principal-surface electrode 52, and the back surface electrode 53 are not particularly limited, and may be, for example, a Ti / Ni / Au film, a Ti / Ni / Au / Ag film, or a Ti / Ni / Ag film.

[0026] In this embodiment, the first principal surface electrode 51 is disposed in a region from the center of the element principal surface 50a in the second direction y toward the y1 side in the second direction y. The first principal surface electrode 51 is rectangular when viewed in the thickness direction z, and the lengths of each side along the first direction x and the second direction y are approximately the same. In this embodiment, the first principal surface electrode 51 is a source electrode and is an electrode used as an input / output terminal.

[0027] The second principal surface electrode 52 is disposed in a region on the y2 side of the element principal surface 50a in the second direction y. The second principal surface electrode 52 is a gate electrode, and is an electrode through which a gate voltage is applied to the semiconductor element 5 serving as a switching element. In the illustrated example, the area of ​​the first principal surface electrode 51 is significantly larger than the area of ​​the second principal surface electrode 52. However, as the size of the semiconductor element 5 becomes smaller, the area of ​​the first principal surface electrode 51 also becomes smaller, and therefore the ratio of the area of ​​the first principal surface electrode 51 to the area of ​​the second principal surface electrode 52 becomes relatively small (see FIG. 15 described below). The first principal surface electrode 51 and the second principal surface electrode 52 are each an example of a "principal surface electrode."

[0028] The back electrode 53 covers the entire (or almost the entire) surface of the element back surface 50b. The back electrode 53 is a drain electrode, and is an electrode used as an input / output terminal together with the first principal surface electrode 51. The back electrode 53 is electrically joined to the first surface 11a (die pad 11) via a conductive bonding material 59. The conductive bonding material 59 electrically connects the die pad 11 and the back electrode 53. The conductive bonding material 59 is, for example, solder.

[0029] In the above-described configuration of this embodiment, the first terminal portion 12 of the first lead 1 is electrically connected to the back electrode 53 of the semiconductor element 5 via the die pad 11 and the conductive bonding material 59. In this embodiment, the first terminal portion 12 is a drain terminal of the semiconductor device A10.

[0030] In this embodiment, the semiconductor element 5 is relatively small in size compared to the die pad 11. The semiconductor element 5 is disposed on the first surface 11a of the die pad 11 at approximately the center in both the first direction x and the second direction y.

[0031] 2 , each of the plurality of wires 6 is bonded to either the first principal surface electrode 51 or the second principal surface electrode 52 of the semiconductor element 5 and to either the second lead 2, the third lead 3, or the fourth lead 4. The material of each of the plurality of wires 6 is not particularly limited and may include, for example, gold (Au), aluminum, or copper. In this embodiment, the material of each wire 6 includes, for example, aluminum.

[0032] In this embodiment, the plurality of wires 6 includes a plurality of first wires 61 , a second wire 62 , a third wire 63 and a fourth wire 64 .

[0033] Each of the multiple (two in this embodiment) first wires 61 is bonded to the first principal surface electrode 51 and the second lead 2. Each of the multiple first wires 61 has a first end 611 and a second end 612. The first end 611 is bonded to the first principal surface electrode 51. The second end 612 is bonded to the pad portion 21 of the second lead 2. In this embodiment, each of the multiple first wires 61 is bonded to the first principal surface electrode 51 and the pad portion 21 (second lead 2) by wedge bonding.

[0034] In the example shown in Fig. 2, the multiple first wires 61 are arranged at intervals in the second direction y and are arranged parallel to each other when viewed in the thickness direction z. Here, the multiple first wires 61 being parallel to each other includes not only the case where the multiple first wires 61 are parallel to each other, but also the case where the multiple first wires 61 are slightly deviated from parallel due to manufacturing errors, etc. Similarly, the term "parallel" described below also includes the case where the multiple first wires 61 are slightly deviated from parallel due to manufacturing errors, etc. Note that, unlike the example shown in the figure, the multiple first wires 61 may be arranged non-parallel when viewed in the thickness direction z.

[0035] In each first wire 61, the second end 612 is located on the y2 side in the second direction y relative to the first end 611. Furthermore, the first end 611 of each of the two first wires 61 shown in FIG. 2 are located at different positions in the first direction x when viewed in the thickness direction z. The first end 611 of the first wire 61 located on the y1 side in the second direction y is located closer to the x1 side in the first direction x than the first end 611 of the first wire 61 located on the y2 side in the second direction y. The second end 612 of each of the two first wires 61 are located at approximately the same position in the first direction x when viewed in the thickness direction z.

[0036] The second wire 62 is bonded to the first principal surface electrode 51 and the second lead 2. The second wire 62 has a first end 621 and a second end 622. The first end 621 is bonded to the first principal surface electrode 51. The second end 622 is bonded to the pad portion 21 of the second lead 2. In this embodiment, the second wire 62 is bonded to the first principal surface electrode 51 and the pad portion 21 (second lead 2) by wedge bonding.

[0037] The second wire 62 extends generally along the first direction x as viewed in the thickness direction z. The second wire 62 straddles multiple (two) first wires 61 as viewed in the thickness direction z. The first end 621 of the second wire 62 is located on the x2 side in the first direction x relative to the first end 611 of each of the multiple first wires 61 as viewed in the thickness direction z. As shown in FIGS. 2 and 4 , in this embodiment, the second wire 62 overlaps the first end 611 of each of the multiple (two) first wires 61 as viewed in the thickness direction z, and straddles the two first end portions 611. Note that, unlike the example shown in FIG. 2 , even when the multiple first wires 61 are arranged non-parallel, the second wire 62 is arranged to straddle the first end portions 611 of each of the multiple first wires 61 as viewed in the thickness direction z, for example.

[0038] The second end 622 of the second wire 62 is located on the y1 side in the second direction y with respect to the second end 612 of each of the two first wires 61. When viewed in the thickness direction z, the second end 622 is located at approximately the same position in the first direction x as the second end 612 of each of the first wires 61. As shown in Figures 2 and 6 , the second end 612 of each of the two first wires 61 and the second end 622 of the second wire 62 overlap each other when viewed in the second direction y.

[0039] In this embodiment, the second terminal portion 22 of the second lead 2 is electrically connected to the first main surface electrode 51 of the semiconductor element 5 via the pad portion 21, the plurality of first wires 61, and the second wires 62. In this embodiment, the second terminal portion 22 is the source terminal of the semiconductor device A10.

[0040] The third wire 63 is bonded to the second principal surface electrode 52 and the third lead 3. The third wire 63 has a first end 631 and a second end 632. The first end 631 is bonded to the second principal surface electrode 52. The second end 632 is bonded to the pad portion 31 of the third lead 3. In this embodiment, the third terminal portion 32 of the third lead 3 is electrically connected to the second principal surface electrode 52 of the semiconductor element 5 via the pad portion 31 and the third wire 63. In this embodiment, the third terminal portion 32 is a gate terminal of the semiconductor device A10.

[0041] The fourth wire 64 is bonded to the first principal surface electrode 51 and the fourth lead 4. The fourth wire 64 has a first end 641 and a second end 642. The first end 641 is bonded to the first principal surface electrode 51. The second end 642 is bonded to the pad portion 41 of the fourth lead 4. In this embodiment, the fourth terminal portion 42 of the fourth lead 4 is electrically connected to the second principal surface electrode 52 of the semiconductor element 5 via the pad portion 41 and the fourth wire 64. In this embodiment, the fourth terminal portion 42 functions as a source sense terminal. The source sense terminal is a terminal for detecting the potential of the first principal surface electrode 51 (source electrode).

[0042] The sealing resin 7 covers parts of the first lead 1, the second lead 2, the third lead 3, and the fourth lead 4, the semiconductor element 5, and the plurality of wires 6. The sealing resin 7 is made of, for example, black epoxy resin.

[0043] 1 and 3 to 5, the sealing resin 7 has a resin main surface 71, a resin back surface 72, and resin side surfaces 731 to 734. The resin main surface 71 and the resin back surface 72 face opposite sides in the thickness direction z and are spaced apart from each other. The resin main surface 71 faces the z1 side in the thickness direction z, facing the same side as the element main surface 50a and the first surface 11a. The resin back surface 72 faces the z2 side in the thickness direction z, facing the same side as the element back surface 50b and the second surface 11b.

[0044] Each of the resin side surfaces 731 to 734 is connected to the resin main surface 71 and the resin back surface 72 and is sandwiched between the resin main surface 71 and the resin back surface 72 in the thickness direction z. The resin side surface 731 and the resin side surface 732 face opposite each other in the first direction x. The resin side surface 731 faces the x1 side of the first direction x, and the resin side surface 732 faces the x2 side of the first direction x. The resin side surface 733 and the resin side surface 734 face opposite each other in the second direction y. The resin side surface 733 faces the y1 side of the second direction y, and the resin side surface 734 faces the y2 side of the second direction y. As shown in FIG. 1 , a portion of each of the first terminal 12, the second terminal 22, the third terminal 32, and the fourth terminal 42 protrudes from the resin side surface 731. In the illustrated example, the resin side surfaces 731 to 734 are each slightly inclined with respect to the thickness direction z. 1 and 3 to 5 are merely examples. The shape of the sealing resin 7 is not limited to the illustrated shape. In the example shown in FIGS. 3 to 5 in this embodiment, the second surface 11b of the die pad 11 is covered with the sealing resin 7. However, the second surface 11b may be exposed from the resin rear surface 72 of the sealing resin 7 without being covered with the sealing resin 7.

[0045] Next, the operation of this embodiment will be described.

[0046] In the semiconductor device A10, the multiple wires 6 include a first wire 61 and a second wire 62. A first end 611 of the first wire 61 and a first end 621 of the second wire 62 are joined to a first main surface electrode 51 of the semiconductor element 5. The second wire 62 straddles the first wire 61 when viewed in the thickness direction z. With this configuration, it is possible to efficiently arrange the multiple wires 6 (the first wire 61 and the second wire 62) for a semiconductor element 5 that is relatively small in size.

[0047] In this embodiment, the multiple wires 6 include multiple (two) first wires 61, and the second wire 62 straddles the multiple (two) first wires 61 as viewed in the thickness direction z. The first end portions 611 of the multiple (two) first wires 61 are disposed at different positions in the first direction x. The second wire 62 straddles the first end portions 611 of the multiple (two) first wires 61 as viewed in the thickness direction z. With this configuration, the first wires 61 and the second wires 62 can be efficiently arranged in a small space while avoiding interference between the multiple first wires 61 and the second wires 62.

[0048] 2 in this embodiment, the multiple first wires 61 are arranged parallel to each other when viewed in the thickness direction z. The second end portions 612 of the multiple (two) first wires 61 and the second end portions 622 of the second wires 62 overlap each other when viewed in the second direction y. This configuration is preferable for efficiently arranging the multiple first wires 61 and second wires 62 while avoiding interference between the multiple first wires 61 and second wires 62.

[0049] First Modification of First Embodiment: FIGS. 7 and 8 show a semiconductor device A11 according to a first modification of the first embodiment. FIG. 7 is a plan view showing the semiconductor device A11. FIG. 8 is a right side view showing the semiconductor device A11. FIG. 7 shows a view through the sealing resin 7 for ease of understanding. FIG. 8 shows a view through the sealing resin 7 and omits the third lead 3, the fourth lead 4, and some of the wires 6 (the third wire 63 and the fourth wire 64). In the figures following FIG. 7, elements that are the same as or similar to those in the semiconductor device A10 of the above embodiment are given the same reference numerals as in the above embodiment, and descriptions thereof will be omitted as appropriate. Furthermore, the configurations of the various components in each modification can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0050] The semiconductor device A11 of this modification differs from the semiconductor device A10 of the above embodiment in the arrangement of the semiconductor element 5 and the arrangement of the plurality of first wires 61 and second wires 62. In this modification, the semiconductor element 5 is arranged on the first surface 11 a of the die pad 11 closer to the y2 side in the second direction y.

[0051] In the example shown in FIG. 7 , the multiple first wires 61 are arranged at intervals in the second direction y and parallel to each other as viewed in the thickness direction z. In this modification, the second end 612 of each of the multiple (two) first wires 61 is located on the y1 side of the first end 611 in the second direction y. The first end 611 of each of the two first wires 61 shown in FIG. 7 is located at different positions in the first direction x as viewed in the thickness direction z. The first end 611 of the first wire 61 located on the y1 side of the second direction y is located closer to the x2 side of the first direction x than the first end 611 of the first wire 61 located on the y2 side of the second direction y. The second end 612 of each of the two first wires 61 is located at approximately the same position in the first direction x as viewed in the thickness direction z. Unlike the example shown in FIG. 7 , the multiple first wires 61 may be arranged non-parallel as viewed in the thickness direction z.

[0052] The second wire 62 extends generally along the first direction x as viewed in the thickness direction z. The second wire 62 straddles multiple (two) first wires 61 as viewed in the thickness direction z. The first end 621 of the second wire 62 is located on the x2 side in the first direction x relative to the first end 611 of each of the multiple first wires 61 as viewed in the thickness direction z. As shown in FIG. 7 , in this modification, the second wire 62 overlaps the first end 611 of each of the multiple (two) first wires 61 as viewed in the thickness direction z, and straddles the two first end portions 611. Note that, unlike the example shown in FIG. 7 , even when the multiple first wires 61 are arranged non-parallel, the second wire 62 is arranged to straddle the first end 611 of each of the multiple first wires 61 as viewed in the thickness direction z.

[0053] The second end 622 of the second wire 62 is located on the y2 side in the second direction y relative to the second end 612 of each of the two first wires 61. When viewed in the thickness direction z, the second end 622 is located at approximately the same position in the first direction x as the second end 612 of each of the first wires 61. As shown in Figures 7 and 8 , the second end 612 of each of the two first wires 61 and the second end 622 of the second wire 62 overlap each other when viewed in the second direction y.

[0054] In the semiconductor device A11 of this modification, a first end 611 of the first wire 61 and a first end 621 of the second wire 62 are joined to the first main surface electrode 51 of the semiconductor element 5. The second wire 62 straddles the first wire 61 when viewed in the thickness direction z. This configuration makes it possible to efficiently arrange the multiple wires 6 (the first wire 61 and the second wire 62) for the semiconductor element 5, which is relatively small in size.

[0055] The plurality of wires 6 includes a plurality (two) of first wires 61, and the second wire 62 straddles the plurality (two) of first wires 61 as viewed in the thickness direction z. The first end portions 611 of the plurality (two) of first wires 61 are disposed at different positions in the first direction x. The second wire 62 straddles the first end portions 611 of the plurality (two) of first wires 61 as viewed in the thickness direction z. With this configuration, the first wires 61 and the second wires 62 can be efficiently arranged in a small space while avoiding interference between the plurality of first wires 61 and the second wires 62.

[0056] 7 of this modified example, the multiple first wires 61 are arranged parallel to each other when viewed in the thickness direction z. The second end portions 612 of the multiple (two) first wires 61 and the second end portions 622 of the second wires 62 overlap each other when viewed in the second direction y. This configuration is preferable for efficiently arranging the multiple first wires 61 and second wires 62 while avoiding interference between the multiple first wires 61 and second wires 62.

[0057] Second Modification of First Embodiment: Figures 9 and 10 show a semiconductor device A12 according to a second modification of the first embodiment. Figure 9 is a plan view showing the semiconductor device A12. Figure 10 is a right side view showing the semiconductor device A12. For ease of understanding, Figure 9 shows a view transparent to the sealing resin 7. Figure 10 shows a view transparent to the sealing resin 7, and omits the third lead 3, the fourth lead 4, and some of the multiple wires 6 (third wire 63 and fourth wire 64).

[0058] In the semiconductor device A12 of this modification, the multiple wires 6 include multiple second wires 62. In the example shown in Fig. 9, the multiple (two in this modification) second wires 62 are aligned at intervals in the second direction y and are arranged parallel to each other as viewed in the thickness direction z. Unlike the example shown, the multiple second wires 62 may be arranged non-parallel as viewed in the thickness direction z.

[0059] In the example shown in FIG. 9 , the multiple first wires 61 are arranged at intervals in the second direction y and parallel to each other as viewed in the thickness direction z. In each of the multiple (two) first wires 61, the second end 612 is located on the y2 side in the second direction y relative to the first end 611. The first end 611 of the first wire 61 located on the y1 side in the second direction y is located on the x1 side in the first direction x relative to the first end 611 of the first wire 61 located on the y2 side in the second direction y. The second end 612 of each of the two first wires 61 is located at approximately the same position in the first direction x as viewed in the thickness direction z. Note that, unlike the example shown in FIG. 9 , the multiple first wires 61 may be arranged non-parallel as viewed in the thickness direction z.

[0060] Each of the multiple (two) second wires 62 extends generally along the first direction x as viewed in the thickness direction z. Each of the two second wires 62 straddles the multiple (two) first wires 61 as viewed in the thickness direction z. The first end 621 of each second wire 62 is located on the x2 side in the first direction x with respect to the first end 611 of each of the multiple first wires 61 as viewed in the thickness direction z. As shown in FIG. 9 , in this modification, the second wire 62 located on the y1 side in the second direction y overlaps with the first end 611 of the first wire 61 located on the y1 side in the second direction y as viewed in the thickness direction z, and straddles the first end 611.

[0061] The second end 622 of each of the two second wires 62 is located on the y1 side in the second direction y relative to the second end 612 of each of the two first wires 61. When viewed in the thickness direction z, each second end 622 is located at approximately the same position in the first direction x as the second end 612 of each of the first wires 61. As shown in Figures 9 and 10 , the second end 612 of each of the two first wires 61 and the second end 622 of each of the two second wires 62 overlap each other when viewed in the second direction y.

[0062] In the semiconductor device A12 of this modification, a first end 611 of the first wire 61 and a first end 621 of the second wire 62 are joined to the first main surface electrode 51 of the semiconductor element 5. The second wire 62 straddles the first wire 61 when viewed in the thickness direction z. This configuration makes it possible to efficiently arrange the multiple wires 6 (the first wire 61 and the second wire 62) for the semiconductor element 5, which is relatively small in size.

[0063] The multiple wires 6 include multiple (two) first wires 61 and multiple (two) second wires 62. Each of the multiple (two) second wires 62 straddles multiple (two) first wires 61 in the thickness direction z. The first end portions 611 of the multiple (two) first wires 61 are disposed at different positions in the first direction x. One second wire 62 (in this modification, the second wire 62 located on the y1 side in the second direction y) straddles the first end portion 611 of one first wire 61 (the first wire 61 located on the y1 side in the second direction y) in the thickness direction z. This configuration allows the multiple first wires 61 and the multiple second wires 62 to be efficiently arranged in a small space while avoiding interference between them.

[0064] 9 in this modified example, the multiple first wires 61 are arranged parallel to one another when viewed in the thickness direction z. The multiple second wires 62 are arranged parallel to one another when viewed in the thickness direction z. The second end portions 612 of the multiple (two) first wires 61 and the second end portions 622 of the multiple (two) second wires 62 overlap each other when viewed in the second direction y. This configuration is preferable in terms of efficiently arranging the multiple first wires 61 and the multiple second wires 62 while avoiding interference between the multiple first wires 61 and the multiple second wires 62.

[0065] Third Modification of First Embodiment: Figures 11 and 12 show a semiconductor device A13 according to a third modification of the first embodiment. Figure 11 is a plan view showing the semiconductor device A13. Figure 12 is a right side view showing the semiconductor device A13. For ease of understanding, Figure 11 shows a view transparent to the sealing resin 7. Figure 12 shows a view transparent to the sealing resin 7, and omits the third lead 3 and some of the multiple wires 6 (third wires 63).

[0066] In the semiconductor device A13 of this modification, the multiple wires 6 include a plurality of (four) first wires 61 and a plurality of (two) second wires 62. Two sets of three wires 6, each consisting of two first wires 61 and one second wire 62 as shown in the semiconductor device A10 of the above embodiment, are arranged at an interval in the second direction y. Unlike the semiconductor device A10 of the above embodiment, the semiconductor device A13 of this modification does not include a fourth lead 4 or a fourth wire 64. Meanwhile, in the second lead 2, the dimension of the pad portion 21 in the second direction y is increased, and two second terminal portions 22 connected to this pad portion 21 are provided. These two second terminal portions 22 are arranged at an interval in the second direction y. According to this configuration, the cross-sectional area of ​​the path through which the main current flows is increased in the multiple (four) first wires 61 and multiple (two) second wires 62 and the two second terminal portions 22 of the second lead 2 to which they are joined, which is suitable for a large current of the semiconductor device A13. Furthermore, when the cross-sectional area of ​​the main current path is increased, it is expected that heat generated in the semiconductor element 5 can be efficiently released to the outside, thereby improving the reliability of the semiconductor device A13.

[0067] In the semiconductor device A13 of this modification, a first end 611 of the first wire 61 and a first end 621 of the second wire 62 are joined to the first main surface electrode 51 of the semiconductor element 5. The second wire 62 straddles the first wire 61 when viewed in the thickness direction z. This configuration makes it possible to efficiently arrange the multiple wires 6 (the first wire 61 and the second wire 62) for the semiconductor element 5, which is relatively small in size.

[0068] The plurality of wires 6 includes a plurality (four) of first wires 61 and a plurality (two) of second wires 62. One of the two second wires 62 (the second wire 62 located on the y1 side in the second direction y) straddles two first wires 61 (the two first wires 61 located on the y1 side in the second direction y) in the thickness direction z. The first end portions 611 of the two first wires 61 are disposed at different positions in the first direction x. One of the second wires 62 (the second wire 62 located on the y1 side in the second direction y) straddles the first end portions 611 of the two first wires 61 in the thickness direction z. The other of the two second wires 62 (the second wire 62 located on the y2 side in the second direction y) straddles the other two first wires 61 (the two first wires 61 located on the y2 side in the second direction y) in the thickness direction z. The first ends 611 of the other two first wires 61 are disposed at different positions in the first direction x. The other second wire 62 (the second wire 62 located on the y2 side in the second direction y) straddles the first ends 611 of the other two first wires 61 as viewed in the thickness direction z. With this configuration, it is possible to efficiently arrange the first wires 61 and the second wires 62 in a small space while avoiding interference between the multiple first wires 61 and the multiple second wires 62.

[0069] In the example shown in FIG. 11 of this modified example, the multiple first wires 61 are arranged parallel to one another when viewed in the thickness direction z. The second end portions 612 of the multiple (four) first wires 61 and the second end portions 622 of the multiple (two) second wires 62 overlap each other when viewed in the second direction y. This configuration is preferable for efficiently arranging the multiple first wires 61 and the multiple second wires 62 while avoiding interference between the multiple first wires 61 and the multiple second wires 62. Note that, unlike the example shown in FIG. 11 , the multiple first wires 61 may be arranged non-parallel to one another when viewed in the thickness direction z.

[0070] Fourth Modification of First Embodiment: Figures 13 and 14 show a semiconductor device A14 according to a fourth modification of the first embodiment. Figure 13 is a plan view showing the semiconductor device A14. Figure 14 is a right side view showing the semiconductor device A14. For ease of understanding, Figure 13 shows a view transparent to the sealing resin 7. Figure 14 shows a view transparent to the sealing resin 7, and omits the third lead 3 and some of the multiple wires 6 (third wires 63).

[0071] In the semiconductor device A14 of this modification, the multiple wires 6 include a plurality (four) of first wires 61 and a plurality (four) of second wires 62. The semiconductor device A14 is a configuration in which two second wires 62 are added to the semiconductor device A13 of the modification. Each of the two added second wires 62 straddles two first wires 61 in the thickness direction z. Furthermore, like the semiconductor device A13, the semiconductor device A14 of this modification does not include a fourth lead 4 or a fourth wire 64. In the second lead 2, the dimension of the pad portion 21 in the second direction y is increased, and two second terminal portions 22 are provided connected to the pad portion 21. These two second terminal portions 22 are arranged at an interval in the second direction y. The dimension of the semiconductor element 5 (first main surface electrode 51) in the second direction y is increased compared to the semiconductor device A13 of the modification. According to this configuration, the cross-sectional area of ​​the path through which the main current flows is increased in the multiple (four) first wires 61 and multiple (four) second wires 62 and the two second terminal portions 22 of the second lead 2 to which they are joined, which is suitable for a large current of the semiconductor device A14. Furthermore, when the cross-sectional area of ​​the main current path is increased, it is expected that heat generated in the semiconductor element 5 can be efficiently released to the outside, thereby improving the reliability of the semiconductor device A14.

[0072] In the semiconductor device A14 of this modified example, a first end 611 of the first wire 61 and a first end 621 of the second wire 62 are joined to the first main surface electrode 51 of the semiconductor element 5. The second wire 62 straddles the first wire 61 when viewed in the thickness direction z. This configuration makes it possible to efficiently arrange the multiple wires 6 (the first wire 61 and the second wire 62) for the semiconductor element 5, which is relatively small in size.

[0073] The plurality of wires 6 includes a plurality (four) of first wires 61 and a plurality (four) of second wires 62. Two second wires 62 located on the y1 side in the second direction y straddle two first wires 61 (two first wires 61 located on the y1 side in the second direction y) as viewed in the thickness direction z. The first end portions 611 of the two first wires 61 are disposed at different positions in the first direction x. One of the two second wires 62 located on the y1 side in the second direction y (the second wire 62 located on the y1 side in the second direction y) straddles the first end portions 611 of the two first wires 61 as viewed in the thickness direction z. Two second wires 62 located on the y2 side in the second direction y straddle two first wires 61 (two first wires 61 located on the y2 side in the second direction y) as viewed in the thickness direction z. The first ends 611 of the two first wires 61 are disposed at different positions in the first direction x. One of the two second wires 62 located on the y2 side in the second direction y (the second wire 62 located on the y1 side in the second direction y) straddles the first ends 611 of the two first wires 61 as viewed in the thickness direction z. With this configuration, it is possible to efficiently arrange the first wires 61 and the second wires 62 in a small space while avoiding interference between the multiple first wires 61 and the multiple second wires 62.

[0074] In the example shown in FIG. 13 of this modified example, the multiple first wires 61 are arranged parallel to each other when viewed in the thickness direction z. The multiple second wires 62 are arranged parallel to each other when viewed in the thickness direction z. The second end portions 612 of the multiple (four) first wires 61 and the second end portions 622 of the multiple (four) second wires 62 overlap each other when viewed in the second direction y. This configuration is preferable for efficiently arranging the multiple first wires 61 and the multiple second wires 62 while avoiding interference between the multiple first wires 61 and the multiple second wires 62. Note that, unlike the example shown in FIG. 13 , the multiple first wires 61 may be arranged non-parallel to each other when viewed in the thickness direction z, and the multiple second wires 62 may be arranged non-parallel to each other when viewed in the thickness direction z.

[0075] Fifth Modification of First Embodiment: Figures 15 and 16 show a semiconductor device A15 according to a fifth modification of the first embodiment. Figure 15 is a plan view showing the semiconductor device A15. Figure 16 is a right side view showing the semiconductor device A15. For ease of understanding, Figure 15 shows a view transparent to the sealing resin 7. Figure 16 shows a view transparent to the sealing resin 7, and omits the third lead 3, the fourth lead 4, and some of the multiple wires 6 (third wires 63).

[0076] In the semiconductor device A15 of this modification, the size of the semiconductor element 5 is smaller than that of the semiconductor device A10 of the above embodiment. Specifically, the length of the semiconductor element 5 in the second direction y is smaller than that of the semiconductor device A10. Accordingly, the first principal surface electrode 51 has a smaller dimension in the second direction y and an elongated rectangular shape with the first direction x as its longitudinal direction, and the size of the first principal surface electrode 51 is smaller than that of the above embodiment. Furthermore, the multiple wires 6 do not include the fourth wire 64. The fourth lead 4 is not electrically connected to other portions and is a dummy terminal. The multiple wires 6 include multiple (two) first wires 61 and second wires 62, and the arrangement of these first wires 61 and second wires 62 is the same as that of the semiconductor device A10 of the above embodiment.

[0077] In the semiconductor device A15 of this modified example, a first end 611 of the first wire 61 and a first end 621 of the second wire 62 are joined to the first main surface electrode 51 of the semiconductor element 5. The second wire 62 straddles the first wire 61 when viewed in the thickness direction z. This configuration makes it possible to efficiently arrange the multiple wires 6 (the first wire 61 and the second wire 62) for the semiconductor element 5, which is relatively small in size.

[0078] The multiple wires 6 include multiple (two) first wires 61, and the second wire 62 straddles the multiple (two) first wires 61 as viewed in the thickness direction z. The first end 611 of each of the multiple (two) first wires 61 is located at a different position in the first direction x. The second wire 62 straddles the first end 611 of each of the multiple (two) first wires 61 as viewed in the thickness direction z. This configuration allows the multiple first wires 61 and second wires 62 to be efficiently arranged in a narrow space while avoiding interference between the multiple first wires 61 and second wires 62. In the semiconductor device A15 of this modification, the multiple (two) first wires 61 and second wires 62 can be efficiently and appropriately arranged for a smaller-sized semiconductor element 5.

[0079] In the example shown in Fig. 15 of this modified example, the multiple first wires 61 are arranged parallel to each other when viewed in the thickness direction z. The second end portions 612 of the multiple (two) first wires 61 and the second end portions 622 of the second wires 62 overlap each other when viewed in the second direction y. This configuration is preferable for efficiently arranging the multiple first wires 61 and the second wires 62 while avoiding interference between the multiple first wires 61 and the second wires 62. Note that, unlike the example shown in Fig. 15, the multiple first wires 61 may be arranged non-parallel to each other when viewed in the thickness direction z.

[0080] Second Embodiment: Figures 17 and 18 show a semiconductor device A20 according to a second embodiment of the present disclosure. Figure 17 is a plan view showing the semiconductor device A20. Figure 18 is a right side view showing the semiconductor device A20. For ease of understanding, Figure 17 shows a view through the sealing resin 7. Figure 18 shows a view through the sealing resin 7, and omits the third lead 3, the fourth lead 4, and some of the multiple wires 6 (the third wire 63 and the fourth wire 64).

[0081] In the semiconductor device A20 of this embodiment, the multiple wires 6 include multiple (two) first wires 61, second wires 62, third wires 63, and fourth wires 64, similar to the semiconductor device A10, and the arrangement of these first wires 61, second wires 62, third wires 63, and fourth wires 64 is substantially the same as in the semiconductor device A10. On the other hand, in this embodiment, the second end 612 of each first wire 61, the second end 622 of each second wire 62, the second end 632 of each third wire 63, and the second end 642 of each fourth wire 64 are each first bonding portions formed by ball bonding. The first end 611 of each first wire 61, the first end 621 of each second wire 62, the first end 631 of each third wire 63, and the first end 641 of each fourth wire 64 are each second bonding portions.

[0082] The second wire 62 extends generally along the first direction x as viewed in the thickness direction z. The second wire 62 straddles multiple (two) first wires 61 as viewed in the thickness direction z. A first end 621 of the second wire 62 is located on the x2 side in the first direction x with respect to the first end 611 of each of the multiple first wires 61 as viewed in the thickness direction z. As shown in FIG. 17 , in this embodiment, the second wire 62 overlaps with and straddles the first end 611 of the first wire 61 located on the y2 side in the second direction y as viewed in the thickness direction z.

[0083] The second end 622 of the second wire 62 is located on the y2 side in the second direction y with respect to the second end 612 of each of the two first wires 61. When viewed in the thickness direction z, the second end 622 is located at approximately the same position in the first direction x as the second end 612 of each of the first wires 61. As shown in Figures 17 and 18 , the second end 612 of each of the two first wires 61 and the second end 622 of the second wire 62 overlap each other when viewed in the second direction y.

[0084] In the semiconductor device A20 of this embodiment, a first end 611 of the first wire 61 and a first end 621 of the second wire 62 are joined to the first main surface electrode 51 of the semiconductor element 5. The second wire 62 straddles the first wire 61 when viewed in the thickness direction z. This configuration makes it possible to efficiently arrange multiple wires 6 (the first wire 61 and the second wire 62) for a semiconductor element 5 that is relatively small in size.

[0085] The multiple wires 6 include multiple (two) first wires 61, and the second wire 62 straddles the multiple (two) first wires 61 as viewed in the thickness direction z. The first end portions 611 of the multiple (two) first wires 61 are disposed at different positions in the first direction x. The second wire 62 straddles the first end portion 611 of one first wire 61 (the first wire 61 located on the y2 side in the second direction y) as viewed in the thickness direction z. With this configuration, it is possible to efficiently arrange the multiple first wires 61 and the second wires 62 in a small space while avoiding interference between the multiple first wires 61 and the second wires 62.

[0086] In the example shown in Figure 17 of this embodiment, the multiple first wires 61 are arranged parallel to each other when viewed in the thickness direction z. The second end 612 of each of the multiple (two) first wires 61 and the second end 622 of each second wire 62 overlap each other when viewed in the second direction y. This configuration is preferable for efficiently arranging the multiple first wires 61 and the second wires 62 while avoiding interference between the multiple first wires 61 and the second wires 62. Note that, unlike the example shown in Figure 17, the multiple first wires 61 may be arranged non-parallel to each other when viewed in the thickness direction z.

[0087] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways.

[0088] In the above embodiment, a configuration has been described in which a portion of each of the first terminal 12, the second terminal 22, the third terminal 32, and the fourth terminal 42 protrudes in the first direction x from the resin side surface 731 of the sealing resin 7, but the present disclosure is not limited to this. The semiconductor device of the present disclosure may employ a package format in which the terminals do not protrude from the resin side surface of the sealing resin.

[0089] The present disclosure includes the embodiments described in the following appendices.

[0090] Supplementary Note 1. A semiconductor device comprising: a first lead having a first surface facing one side in a thickness direction; a semiconductor element supported on the first surface; and a plurality of wires each having a first end and a second end, wherein the semiconductor element has an element main surface facing one side in the thickness direction and a main surface electrode formed on the element main surface, wherein each of the plurality of wires has the first end joined to the main surface electrode, and the plurality of wires includes one or more first wires and one or more second wires, and at least one of the one or more second wires straddles at least one of the one or more first wires when viewed in the thickness direction. Supplementary Note 2. The semiconductor device according to Supplementary Note 1, wherein at least one of the one or more second wires straddles the first end of at least one of the one or more first wires when viewed in the thickness direction. Supplementary Note 3. The semiconductor device according to Supplementary Note 1 or 2, wherein the plurality of wires includes a plurality of the first wires, and the second wire straddles a plurality of the first wires when viewed in the thickness direction. Supplementary Note 4. The semiconductor device according to Supplementary Note 3, wherein at least one of the one or more second wires straddles the first ends of each of the plurality of first wires when viewed in the thickness direction. Supplementary Note 5. The semiconductor device according to any of Supplements 1 to 4, further comprising one or more second leads arranged on one side of the semiconductor element in a first direction perpendicular to the thickness direction, wherein the one or more first wires include one whose second ends are joined to the one or more second leads. Supplementary Note 6. The semiconductor device according to Supplementary Note 5, wherein the one or more second wires include one whose second ends are joined to the one or more second leads. Supplementary Note 7. The semiconductor device according to Supplementary Note 5 or 6, wherein the plurality of wires include a plurality of the first wires, and the first ends of the plurality of first wires are arranged at different positions in the first direction. Supplementary Note 8. The semiconductor device according to Supplementary Note 7, wherein the plurality of first wires are arranged parallel to each other when viewed in the thickness direction. Supplementary Note 9. The semiconductor device described in Appendix 7 or 8, wherein the second ends of the one or more first wires and the second ends of the one or more second wires overlap each other when viewed in a second direction perpendicular to both the thickness direction and the first direction.Appendix 10. The semiconductor device according to any one of Appendixes 1 to 9, wherein the semiconductor element is a switching element, the main surface electrode has a first main surface electrode that is a source electrode, and the first end of each of the one or more first wires and the first end of each of the one or more second wires are joined to the first main surface electrode. Appendix 11. The semiconductor device according to Appendix 10, wherein the main surface electrode has a second main surface electrode that is a gate electrode, the plurality of wires includes a third wire, and the first end of the third wire is joined to the second main surface electrode. Appendix 12. The semiconductor device according to Appendix 11, further comprising a third lead arranged on one side of the semiconductor element in a first direction orthogonal to the thickness direction, and the second end of the third wire is joined to the third lead. Appendix 13. The semiconductor device according to any one of Appendixes 1 to 12, wherein a constituent material of each of the plurality of wires includes aluminum. Appendix 14. The semiconductor device according to any one of Supplementary Notes 1 to 13, further comprising a sealing resin that covers the plurality of wires, the semiconductor element, and at least a portion of the first lead.Supplementary Note 15. The semiconductor device according to Supplementary Note 14, wherein the first lead includes a base having the first surface and at least a portion of which is covered by the sealing resin, and a first terminal portion that extends in a first direction perpendicular to the thickness direction with respect to the base and is exposed from the sealing resin.

[0091] A10 to A15, A20: semiconductor device 1: first lead 11: die pad (base) 11a: first surface 11b: second surface 12: first terminal portion 13: bent portion 2: second lead 21: pad portion 22: second terminal portion 3: third lead 31: pad portion 32: third terminal portion 4: fourth lead 41: pad portion 42: fourth terminal portion 5: semiconductor element 50: element body 50a: element main surface 50b: element back surface 51: first main surface electrode (main surface electrode) 52: second main surface electrode (main surface electrode) 53: back surface electrode 59: conductive bonding material 6: wire 61: first wire 62: second wire 63: third wire 64: fourth wire 611, 621, 631, 641: first end portion 612, 622, 632, 642: Second end portion 7: Sealing resin 71: Resin main surface 72: Resin back surface 731, 732, 733, 734: Resin side surface x: First direction y: Second direction z: Thickness direction

Claims

1. a first lead having a first surface facing one side in a thickness direction; A semiconductor element supported on the first surface; a plurality of wires, each wire having a first end and a second end; the semiconductor element has an element main surface facing one side in the thickness direction and a main surface electrode formed on the element main surface, Each of the plurality of wires has the first end joined to the principal surface electrode, the plurality of wires includes one or more first wires and one or more second wires; At least one of the one or more second wires straddles at least one of the one or more first wires when viewed in the thickness direction.

2. The semiconductor device according to claim 1 , wherein at least one of the one or more second wires straddles the first end portion of at least one of the one or more first wires when viewed in the thickness direction.

3. the plurality of wires includes a plurality of the first wires, The semiconductor device according to claim 1 , wherein the second wire straddles a plurality of the first wires when viewed in the thickness direction.

4. The semiconductor device according to claim 3 , wherein at least one of the one or more second wires straddles the first ends of each of the plurality of first wires when viewed in the thickness direction.

5. one or more second leads arranged on one side of the semiconductor element in a first direction perpendicular to the thickness direction; The semiconductor device according to claim 1 , wherein the one or more first wires include one in which the second end is joined to the one or more second leads.

6. The semiconductor device according to claim 5 , wherein the one or more second wires include one in which the second end is joined to the one or more second leads.

7. the plurality of wires includes a plurality of the first wires, The semiconductor device according to claim 5 , wherein the first ends of the plurality of first wires are arranged at different positions in the first direction.

8. The semiconductor device according to claim 7 , wherein the first wires are arranged parallel to each other when viewed in the thickness direction.

9. 8. The semiconductor device according to claim 7, wherein the second ends of the one or more first wires and the second ends of the one or more second wires overlap each other when viewed in a second direction perpendicular to both the thickness direction and the first direction.

10. the semiconductor element is a switching element, the principal surface electrode includes a first principal surface electrode which is a source electrode; The semiconductor device according to claim 1 , wherein the first end of each of the one or more first wires and the first end of each of the one or more second wires are joined to the first principal surface electrode.

11. the principal surface electrode has a second principal surface electrode which is a gate electrode, the plurality of wires includes a third wire; The semiconductor device according to claim 10 , wherein the first end of the third wire is joined to the second principal surface electrode.

12. a third lead disposed on one side of the semiconductor element in a first direction perpendicular to the thickness direction; The semiconductor device according to claim 11 , wherein the second end of the third wire is joined to the third lead.

13. The semiconductor device according to claim 1 , wherein a material constituting each of said plurality of wires includes aluminum.

14. The semiconductor device according to claim 1 , further comprising a sealing resin that covers the plurality of wires, the semiconductor element, and at least a portion of the first lead.

15. 15. The semiconductor device of claim 14, wherein the first lead includes a base having the first surface and at least a portion of which is covered by the sealing resin, and a first terminal portion extending in a first direction perpendicular to the thickness direction relative to the base and exposed from the sealing resin.