Semiconductor device

Abstract

A semiconductor device according to the present invention is provided with an element insulating layer and a plurality of semiconductor resistive layers that are provided in the element insulating layer. The semiconductor resistive layers each comprise a resistive back surface, a resistive front surface that is on the reverse side from the resistive back surface, and a resistive lateral surface that connects the resistive back surface and the resistive front surface to each other. The element insulating layer comprises: a first insulating layer; a second insulating layer that is superposed on the first insulating layer and has a higher relative dielectric constant than the first insulating layer; and a third insulating layer that is superposed on the second insulating layer and has a lower relative dielectric constant than the second insulating layer. The semiconductor resistive layers are superposed on the second insulating layer and are provided within the third insulating layer in such a manner that the resistive back surfaces are in contact with the second insulating layer.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Conventionally, devices that detect high voltages using a resistive voltage divider circuit have been known. For example, Patent Document 1 discloses a power supply device that detects the voltage of a battery unit using a voltage detection circuit that includes an A / D converter and a ladder resistor circuit that includes a plurality of series resistors connected in series with each other and a voltage divider resistor that connects a voltage dividing point of the plurality of series resistors to a connection point of a high-voltage battery.

[0003] JP 2010-8227 A

[0004] Meanwhile, development is underway to integrate circuits including multiple resistors, such as ladder resistor circuits in power supply devices, into a single chip. In this case, there is a risk of electric field concentration occurring within the chip, and there is room for improvement in alleviating this electric field concentration.

[0005] A semiconductor device according to one aspect of the present disclosure includes an element insulating layer having a front surface and a back surface opposite to the front surface, and one or more semiconductor resistance layers provided in the element insulating layer, wherein the semiconductor resistance layer includes a resistor back surface facing the back surface in a thickness direction of the element insulating layer, a resistor front surface opposite to the resistor back surface, and a resistor side surface connecting the resistor back surface and the resistor front surface, the element insulating layer includes a first insulating layer, a second insulating layer stacked on the first insulating layer and having a higher dielectric constant than the first insulating layer, and a third insulating layer stacked on the second insulating layer and having a lower dielectric constant than the second insulating layer, and the semiconductor resistance layer is stacked on the second insulating layer and is provided in the third insulating layer with the resistor back surface in contact with the second insulating layer.

[0006] a wiring layer electrically connected to the semiconductor resistance layer in the element insulating layer and disposed opposite the semiconductor resistance layer in a thickness direction of the element insulating layer, the wiring layer including a wiring surface facing the semiconductor resistance layer in the thickness direction of the element insulating layer, a wiring back surface opposite the wiring surface, and a wiring side surface connecting the wiring surface and the wiring back surface, the element insulating layer including a fourth insulating layer, a fifth insulating layer stacked on the fourth insulating layer and having a higher dielectric constant than the fourth insulating layer, and a low-dielectric-constant insulating layer stacked on the fifth insulating layer and having a lower dielectric constant than the fifth insulating layer, the wiring layer being stacked on the fifth insulating layer and being disposed in the low-dielectric-constant insulating layer with the wiring back surface in contact with the fifth insulating layer;

[0007] According to the semiconductor device of the present disclosure, it is possible to alleviate electric field concentration.

[0008] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment. FIG. 2 is a schematic plan view of a first chip and a second chip in the semiconductor device of FIG. 1. FIG. 3 is a schematic plan view of a semiconductor resistance layer in the first chip. FIG. 4 is a schematic cross-sectional view showing the semiconductor resistance layer in the first chip and its periphery. FIG. 5 is an enlarged cross-sectional view of the semiconductor resistance layer in FIG. 4 and its periphery. FIG. 6 is a schematic cross-sectional view showing a wiring layer in the first chip and its periphery. FIG. 7 is a schematic cross-sectional view of the first chip cut along line F7-F7 in FIG. 3. FIG. 8 is a schematic cross-sectional view showing an example of a manufacturing process for a semiconductor device according to the first embodiment. FIG. 9 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 8. FIG. 10 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 9. FIG. 11 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 10. FIG. 12 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 11. FIG. 13 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 12. FIG. 14 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 13. FIG. 15 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 14. FIG. 16 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 15 . FIG. 17 is a schematic cross-sectional view showing a semiconductor resistance layer and its periphery in a first chip for a semiconductor device of a second embodiment. FIG. 18 is a schematic cross-sectional view showing a wiring layer and its periphery in a first chip. FIG. 19 is a schematic cross-sectional view showing a terminal, semiconductor resistance layer, wiring layer, and its periphery in a first chip. FIG. 20 is a schematic cross-sectional view showing a semiconductor resistance layer and its periphery in a first chip for a semiconductor device of a third embodiment. FIG. 21 is a schematic cross-sectional view showing a wiring layer and its periphery in a first chip. FIG. 22 is a schematic cross-sectional view showing a terminal, semiconductor resistance layer, wiring layer, and its periphery in a first chip. FIG. 23 is a schematic cross-sectional view showing a terminal, semiconductor resistance layer, wiring layer, and its periphery in a first chip for a semiconductor device of a modified example. FIG. 24 is a schematic cross-sectional view showing a wiring layer, semiconductor resistance layer, and its periphery in a first chip for a semiconductor device of a modified example.

[0009] Hereinafter, several embodiments of the insulating chip and semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] First Embodiment A semiconductor device 10 according to a first embodiment will be described with reference to Figures 1 to 16. Figures 1 and 2 show a schematic diagram of the overall configuration of the semiconductor device 10, Figure 3 shows a planar structure of a portion of a first chip (described later), and Figures 4 to 7 show a cross-sectional structure of a portion of the first chip. Figures 8 to 16 show an example of a manufacturing process for the semiconductor device 10.

[0012] The term "plan view" used in this disclosure refers to viewing the semiconductor device 10 in the Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in Fig. 4. Furthermore, with respect to the semiconductor device 10 shown in Fig. 4, the +Z direction is defined as up, the -Z direction as down, the +X direction as right, and the -X direction as left. Unless otherwise specified, "plan view" refers to viewing the semiconductor device 10 from above along the Z-axis.

[0013] [Overall Configuration of Semiconductor Device] Fig. 1 schematically shows the overall configuration of a semiconductor device 10 according to a first embodiment. Fig. 2 schematically shows the electrical configuration and electrical connection structure of a first chip 14 and a second chip 15 (described later) of the semiconductor device 10. Note that in Fig. 1, components inside a sealing resin 16 (described later) are shown with solid lines to facilitate understanding of the drawing. In Fig. 2, components inside the first chip 14 and the second chip 15 are shown with solid lines to facilitate understanding of the drawing.

[0014] 1, a semiconductor device 10 includes a frame 11, a die pad 12, a plurality of (seven in the first embodiment) leads 13A to 13G, a first chip 14 mounted on the frame 11, a second chip 15 mounted on the die pad 12, wires W1 to W11, and a sealing resin 16 that seals them. Here, in the first embodiment, the first chip 14 corresponds to an "insulating chip."

[0015] The sealing resin 16 is formed in a flat plate shape. The shape of the sealing resin 16 in a plan view is rectangular. The sealing resin 16 has first to fourth resin side surfaces 16A to 16D. The first resin side surface 16A and the second resin side surface 16B constitute both end surfaces of the sealing resin 16 in the X-axis direction. The first resin side surface 16A constitutes the end surface of the sealing resin 16 in the -X direction, and the second resin side surface 16B constitutes the end surface of the sealing resin 16 in the +X direction. The third resin side surface 16C and the fourth resin side surface 16D constitute both end surfaces of the sealing resin 16 in the Y-axis direction. The third resin side surface 16C constitutes the end surface of the sealing resin 16 in the -Y direction, and the fourth resin side surface 16D constitutes the end surface of the sealing resin 16 in the +Y direction.

[0016] The frame 11 and the die pad 12 are arranged apart from each other in the X-axis direction. That is, the X-axis direction is the arrangement direction of the frame 11 and the die pad 12. The frame 11 is arranged closer to the first resin side surface 16A than the die pad 12. Each of the frame 11, the die pad 12, and the leads 13A to 13G is made of a metal material such as copper (Cu) or aluminum (Al).

[0017] The frame 11 includes a die pad portion 11A and lead portions 11B. In the first embodiment, the die pad portion 11A and lead portions 11B are integrally formed. The die pad portion 11A is a portion on which the first chip 14 is mounted and supports the first chip 14. The die pad portion 11A is disposed closer to the second resin side surface 16B and spaced apart from the first resin side surface 16A. The shape of the die pad portion 11A in plan view is rectangular, with the Y-axis direction as the longitudinal direction and the X-axis direction as the lateral direction. In other words, the die pad portion 11A is formed so that its dimension in the arrangement direction of the frame 11 and the die pad 12 is short.

[0018] The lead portion 11B is connected to a corner portion formed by one of the two end portions of the die pad portion 11A in the Y-axis direction that is closer to the third resin side surface 16C and one of the two end portions of the die pad portion 11A in the X-axis direction that is closer to the first resin side surface 16A. The lead portion 11B extends along the X-axis direction from the die pad portion 11A toward the first resin side surface 16A.

[0019] The die pad 12 is located closer to the second resin side surface 16B than the frame 11, and is spaced apart from the second resin side surface 16B and closer to the first resin side surface 16A. The die pad 12 is the portion on which the second chip 15 is mounted and supports the second chip 15. The shape of the die pad 12 in plan view is rectangular, with the Y-axis direction as the longitudinal direction and the X-axis direction as the lateral direction. In other words, the die pad 12 is formed so that the dimension in the arrangement direction of the frame 11 and the die pad 12 is short.

[0020] The leads 13A to 13G are arranged dispersedly at both ends in the X-axis direction of the sealing resin 16. More specifically, the lead 13A is arranged at the end of the sealing resin 16 on the first resin side surface 16A side. The leads 13B to 13G are each arranged at the end of the sealing resin 16 on the second resin side surface 16B side.

[0021] The lead 13A is arranged closer to the first resin side surface 16A than the die pad portion 11A. The lead 13A is arranged at a distance from the die pad portion 11A in the X-axis direction. The lead 13A is also arranged at a distance from the lead portion 11B in the Y-axis direction. In the first embodiment, the lead 13A is arranged at a position overlapping with the end of the die pad portion 11A on the fourth resin side surface 16D side, of both end portions in the Y-axis direction, of the die pad portion 11A, as viewed from the X-axis direction.

[0022] Each of the leads 13B to 13G is arranged closer to the second resin side surface 16B than the die pad 12. Each of the leads 13B to 13G is arranged at a distance from the die pad 12 in the X-axis direction. The leads 13B to 13G are arranged at a distance from one another in the Y-axis direction. The leads 13B to 13G are arranged from the fourth resin side surface 16D toward the third resin side surface 16C in the order of lead 13B, lead 13C, lead 13D, lead 13E, lead 13F, and lead 13G. As can be seen from FIG. 1 , the distance in the Y-axis direction between the lead 13A and the lead portion 11B is greater than the distance between adjacent leads in the Y-axis direction among the leads 13B to 13G.

[0023] The first chip 14 mounted on the die pad portion 11A of the frame 11 is formed in a flat plate shape. In a plan view, the shape of the first chip 14 is a rectangle with the Y-axis direction as the longitudinal direction and the X-axis direction as the lateral direction. In other words, the first chip 14 is formed so that the dimension in the arrangement direction of the frame 11 and the die pad 12 is short.

[0024] The first chip 14 includes a plurality of terminals P1 to P5. The terminals P1 and P2 are provided on one of both end portions of the first chip 14 in the X-axis direction that is closer to the first resin side surface 16A. The terminal P1 is provided on the first chip 14 near the lead 13A. The terminal P2 is provided on the first chip 14 near the lead portion 11B. The terminals P3 to P5 are provided on one of both end portions of the first chip 14 in the X-axis direction that is closer to the second chip 15. The terminals P3 to P5 are arranged spaced apart from each other in the Y-axis direction.

[0025] The second chip 15 mounted on the die pad 12 is formed in a flat plate shape. In plan view, the shape of the second chip 15 is a rectangle with the Y-axis direction as the longitudinal direction and the X-axis direction as the lateral direction. In other words, the second chip 15 is formed so that the dimension in the arrangement direction of the frame 11 and the die pad 12 is short.

[0026] The second chip 15 includes a plurality of terminals Q1 to Q9. The terminals Q1 to Q3 are provided at one of both ends of the second chip 15 in the X-axis direction that is closer to the first chip 14. The terminals Q1 to Q3 are arranged spaced apart from each other in the Y-axis direction. The terminals Q4 to Q9 are provided at one of both ends of the second chip 15 in the X-axis direction that is closer to the second resin side surface 16B. The terminals Q4 to Q9 are arranged spaced apart from each other in the Y-axis direction.

[0027] Terminal P1 of the first chip 14 is electrically connected to lead 13A by wire W1. Terminal P2 is electrically connected to lead 11B by wire W2. In other words, it can be said that terminal P2 is electrically connected to frame 11. A high voltage generator VT is electrically connected to lead 13A and lead 11B. The high voltage generator VT is, for example, a DC power supply. The positive electrode of the high voltage generator VT is electrically connected to lead 13A, and the negative electrode of the high voltage generator VT is electrically connected to lead 11B.

[0028] Terminals P3 to P5 of the first chip 14 and terminals Q1 to Q3 of the second chip 15 are individually electrically connected by wires W3 to W5. Terminals Q4 to Q9 are individually electrically connected to leads 13B to 13G by wires W6 to W11.

[0029] In the first embodiment, of the terminals P1 to P5, terminals P1 and P2 constitute high-voltage side terminals, and terminals P3 to P5 constitute low-voltage side terminals. In other words, the terminals electrically connected to lead 13A and lead portion 11B constitute high-voltage side terminals, and the terminal electrically connected to second chip 15 constitutes low-voltage side terminals.

[0030] In this way, the die pad portion 11A of the frame 11 electrically connected to the high-voltage generating unit VT constitutes a high-voltage side die pad, and the die pad 12 constitutes a low-voltage side die pad. Therefore, the dielectric strength voltage between the terminals P3 to P5 and the substrate 30 is higher than the dielectric strength voltage between the terminals P1 and P2 and the substrate 30. For example, the dielectric strength voltage between the terminals P3 to P5 and the substrate 30 is about 3850 V DC, and the dielectric strength voltage between the terminals P1 and P2 and the substrate 30 is about 1400 V DC.

[0031] Next, the circuit configurations within the first chip 14 and the second chip 15 will be described. As shown in Fig. 2, the first chip 14 includes first to fourth resistor circuits 14A to 14D for stepping down the high voltage of the high voltage generating unit VT (see Fig. 1). The first resistor circuit 14A has a resistance value RA, the second resistor circuit 14B has a resistance value RB, the third resistor circuit 14C has a resistance value RC, and the fourth resistor circuit 14D has a resistance value RD.

[0032] The resistance value RB is smaller than the resistance value RA. The ratio (RB / RA) of the resistance value RB to the resistance value RA is set in advance. The resistance value RC is smaller than the resistance value RD. The ratio (RC / RD) of the resistance value RC to the resistance value RD is set in advance. The ratio (RB / RA) and the ratio (RC / RD) are set to the same predetermined value (for example, 1 / 999).

[0033] The first to fourth resistor circuits 14A to 14D are connected in series. Each of the first to fourth resistor circuits 14A to 14D has a first end and a second end. The first end of the first resistor circuit 14A is electrically connected to terminal P1, and the second end of the first resistor circuit 14A is electrically connected to the first end of the second resistor circuit 14B. The junction between the first resistor circuit 14A and the second resistor circuit 14B is electrically connected to terminal P3. The second end of the second resistor circuit 14B is electrically connected to the first end of the third resistor circuit 14C. The junction between the second resistor circuit 14B and the third resistor circuit 14C is electrically connected to terminal P4. The second end of the third resistor circuit 14C is electrically connected to the first end of the fourth resistor circuit 14D. The junction between the third resistor circuit 14C and the fourth resistor circuit 14D is electrically connected to terminal P5. The second end of the fourth resistor circuit 14D is electrically connected to terminal P2.

[0034] The second chip 15 includes a voltage detection circuit 15A. The voltage detection circuit 15A includes an operational amplifier. The voltage detection circuit 15A is electrically connected to terminals Q1 to Q3. Terminal Q1 is electrically connected to terminal P3 of the first chip 14 by wire W3, terminal Q2 is electrically connected to terminal P4 of the first chip 14 by wire W4, and terminal Q3 is electrically connected to terminal P5 of the first chip 14 by wire W5. Therefore, the voltage detection circuit 15A detects voltages between the connection point between the first resistor circuit 14A and the second resistor circuit 14B, the connection point between the second resistor circuit 14B and the third resistor circuit 14C, and the connection point between the third resistor circuit 14C and the fourth resistor circuit 14D. Terminals Q4 to Q9 (leads 13B to 13G (see FIG. 1)) are used to supply power supply voltage to the operational amplifier in the second chip 15 and to output an output signal from the voltage detection circuit 15A.

[0035] [Schematic Planar Structure of First Chip] FIG. 3 shows a schematic planar structure of the first chip 14 including the first to fourth resistor circuits 14A to 14D (see FIG. 2) of the first chip 14 described above.

[0036] 3, the first chip 14 includes a plurality of unit semiconductor resistance layers (hereinafter referred to as "semiconductor resistance layers 20"). Each semiconductor resistance layer 20 extends along the X-axis direction. In other words, each semiconductor resistance layer 20 extends in the short-side direction of the first chip 14. The plurality of semiconductor resistance layers 20 are arranged aligned with each other in the X-axis direction and spaced apart from each other in the Y-axis direction. In other words, the plurality of semiconductor resistance layers 20 are arranged spaced apart from each other in the longitudinal direction of the first chip 14.

[0037] The multiple semiconductor resistance layers 20 are used as components of first to fourth resistance circuits 14A to 14D. The multiple semiconductor resistance layers 20 can be divided into multiple resistance regions, first to fourth resistance regions R1 to R4. The first to fourth resistance regions R1 to R4 are arranged in the order of resistance regions R1, R2, R3, and R4 from the +Y direction to the −Y direction. The first resistance region R1 is a region that constitutes the first resistance circuit 14A, the second resistance region R2 is a region that constitutes the second resistance circuit 14B, the third resistance region R3 is a region that constitutes the third resistance circuit 14C, and the fourth resistance region R4 is a region that constitutes the fourth resistance circuit 14D.

[0038] The number of semiconductor resistance layers 20 in each of the first to fourth resistance regions R1 to R4 is set individually. In the first embodiment, the first resistance region R1 and the fourth resistance region R4 have the same number of semiconductor resistance layers 20. The second resistance region R2 and the third resistance region R3 have the same number of semiconductor resistance layers 20. The number of semiconductor resistance layers 20 in the first and fourth resistance regions R1, R4 is greater than the number of semiconductor resistance layers 20 in the second and third resistance regions R2, R3. The number of semiconductor resistance layers 20 in each of the first to fourth resistance regions R1 to R4 is not limited to that in the first embodiment and can be changed as desired.

[0039] More specifically, in the first to fourth resistance regions R1 to R4, the −X direction ends of the semiconductor resistance layers 20 in the odd-numbered rows from the end in the +Y direction are each electrically connected to the −X direction ends of the semiconductor resistance layers 20 in the even-numbered rows adjacent to that semiconductor resistance layer 20 in the −Y direction. Also, the +X direction ends of the semiconductor resistance layers 20 in the even-numbered rows from the end in the +Y direction are electrically connected to the +X direction ends of the semiconductor resistance layers 20 in the odd-numbered rows adjacent to that semiconductor resistance layer 20 in the −Y direction. As a result, all of the semiconductor resistance layers 20 in the first to fourth resistance regions R1 to R4 are connected in series.

[0040] The semiconductor resistance layer 20 in the first row from the end of the first resistance region R1 in the +Y direction and the terminal P1 are connected by a wiring 21. The wiring 21 is connected to the end in the +X direction of the semiconductor resistance layer 20 in the first row from the end of the first resistance region R1 in the +Y direction.

[0041] The semiconductor resistance layer 20 in the first row from the end of the second resistance region R2 in the +Y direction is connected to the terminal P3 by a wiring 22. The wiring 22 is connected to the end in the +X direction of the semiconductor resistance layer 20 in the first row from the end of the second resistance region R2 in the +Y direction.

[0042] The terminal P4 is connected to the semiconductor resistance layer 20 in the first row from the end in the −Y direction of the second resistance region R2 and the semiconductor resistance layer 20 in the first row from the end in the +Y direction of the third resistance region R3 by a wiring 23. The wiring 23 is connected to the +X direction ends of the semiconductor resistance layer 20 in the first row from the end in the −Y direction of the second resistance region R2 and the semiconductor resistance layer 20 in the first row from the end in the +Y direction of the third resistance region R3.

[0043] The semiconductor resistance layer 20 in the first row from the end of the third resistance region R3 in the −Y direction is connected to the terminal P5 by a wiring 24. The wiring 24 is connected to the end in the +X direction of the semiconductor resistance layer 20 in the first row from the end of the third resistance region R3 in the −Y direction.

[0044] The semiconductor resistance layer 20 in the first row from the end of the fourth resistance region R4 in the −Y direction and the terminal P2 are connected by a wiring 25. The wiring 25 is connected to the end in the +X direction of the semiconductor resistance layer 20 in the first row from the end of the fourth resistance region R4 in the −Y direction.

[0045] [Cross-sectional Structure of First Chip] An example of the internal configuration of the first chip 14 will be described with reference to FIGS. 4 to 7. Each of FIGS. 4 to 7 shows the cross-sectional structure of the first chip 14. FIG. 4 shows the cross-sectional structure of a region including four semiconductor resistance layers 20 adjacent in the Y-axis direction in the first resistance region R1, cut along the YZ plane. FIG. 5 shows an enlarged structure of the four semiconductor resistance layers 20 and their surroundings in FIG. 4. FIG. 6 shows the cross-sectional structure of the +X-direction end of a region including four semiconductor resistance layers 20 adjacent in the Y-axis direction in the first resistance region R1, cut along the YZ plane. FIG. 7 shows the cross-sectional structure of the first chip 14 cut along line F7-F7 in FIG. 3.

[0046] As shown in FIG. 4 , the first chip 14 includes a substrate 30 and an element insulating layer 40 formed on the substrate 30. The substrate 30 is formed, for example, of a semiconductor substrate. The thickness of the substrate 30 is, for example, approximately 300 μm. In the first embodiment, the substrate 30 is a semiconductor substrate formed of a material containing Si. Note that a wide bandgap semiconductor or a compound semiconductor may be used as the semiconductor substrate for the substrate 30. Furthermore, instead of a semiconductor substrate, an insulating substrate formed of a material containing glass or a material containing ceramics such as alumina may be used as the substrate 30.

[0047] The wide bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of aluminum nitride (AlN), indium nitride (InN), gallium nitride (GaN), and gallium arsenide (GaAs).

[0048] The element insulating layer 40 has an element front surface 41 and an element back surface 42 that face opposite each other in the Z-axis direction. In the first embodiment, the Z-axis direction corresponds to the "thickness direction of the element insulating layer." The element back surface 42 is in contact with the substrate 30. The element front surface 41 is the surface opposite the substrate 30 in the Z-axis direction.

[0049] Terminals P1 to P5 (see FIG. 3 ) and a passivation film 43 are formed on the element insulating layer 40. The terminals P1 to P5 are formed on the element surface 41 of the element insulating layer 40. The terminals P1 to P5 are made of one or more of Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Au (gold), Ag (silver), Cu (copper), Al (aluminum), Ni (nickel), Pd (palladium), and W (tungsten). In the first embodiment, the terminals P1 to P5 are made of a material containing Al. As an example, FIG. 7 shows a structure in which the terminal P1 is formed on the element surface 41.

[0050] As shown in FIG. 7, terminal P1 is covered with passivation film 43. Meanwhile, passivation film 43 has an opening 43X that exposes terminal P1. Although not shown, passivation film 43 also has openings 43X that expose terminals P2 to P5 shown in FIGS. 1 to 3. Therefore, terminals P1 to P5 include exposed surfaces for connecting wires W1 to W5 (see FIG. 1). In this way, terminals P1 to P5 form electrode pads.

[0051] 4, the passivation film 43 is formed on the element surface 41 of the element insulating layer 40. The passivation film 43 is a surface protection film for the first chip 14, and is formed of a material containing SiN, for example. Note that the material constituting the passivation film 43 can be changed arbitrarily, and may be, for example, SiO ２ The passivation film 43 may also have a laminated structure of a plurality of films, for example, a film formed of a material containing SiN and a film formed of SiO ２ The film may have a laminated structure with a film formed of a material containing the above.

[0052] The element insulating layer 40 includes a substrate-side insulating layer 50 provided on the substrate 30, a wiring-side insulating layer 60 stacked on the substrate-side insulating layer 50, and a resistor-side insulating layer 70 stacked on the wiring-side insulating layer 60.

[0053] The substrate-side insulating layer 50 includes a plurality of first substrate-side insulating layers 51 and a second substrate-side insulating layer 52 formed on the plurality of first substrate-side insulating layers 51. The plurality of first substrate-side insulating layers 51 and the plurality of second substrate-side insulating layers 52 are stacked alternately one by one in the Z-axis direction.

[0054] The first substrate-side insulating layer 51 is formed of a material containing SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), or the like. The first substrate-side insulating layer 51 may be a SiN-based insulating film. In the first embodiment, the first substrate-side insulating layer 51 is formed of a material containing SiN. The first substrate-side insulating layer 51 is, for example, an insulating layer having a different composition from the second substrate-side insulating layer 52 and is a film having an opposite stress to that of the second substrate-side insulating layer 52. The first substrate-side insulating layer 51 may be, for example, a nitride film having tensile stress.

[0055] The second substrate side insulating layer 52 is made of SiO ２ The second substrate-side insulating layer 52 is an oxide film formed of a material containing silicon oxide. The film thickness of the second substrate-side insulating layer 52 is thicker than the film thickness of the first substrate-side insulating layer 51. The first substrate-side insulating layer 51 has a thickness of 50 nm or more and less than 1000 nm. The second substrate-side insulating layer 52 has a thickness of 500 nm or more and 5000 nm or less. In the first embodiment, the first substrate-side insulating layer 51 has a thickness of about 300 nm, and the second substrate-side insulating layer 52 has a thickness of about 2000 nm.

[0056] The reason for alternately stacking the first substrate-side insulating layer 51 and the second substrate-side insulating layer 52 is to form a thick substrate-side insulating layer 50 by controlling warping of the substrate 30 caused by the formation of the second substrate-side insulating layer 52 through the formation of the first substrate-side insulating layer 51. In the first embodiment, the substrate-side insulating layer 50 has a thickness of about 13.5 μm.

[0057] To make the drawings easier to see, the ratio of the film thickness of the first substrate-side insulating layer 51 to the film thickness of the second substrate-side insulating layer 52 in the drawings differs from the actual ratio of the film thickness of the first substrate-side insulating layer 51 to the film thickness of the second substrate-side insulating layer 52. Also, in Fig. 4, the thicknesses of both the first substrate-side insulating layer 51 and the second substrate-side insulating layer 52 are made thicker to clearly show the configurations of the first substrate-side insulating layer 51 and the second substrate-side insulating layer 52. Therefore, the number of layers of the first substrate-side insulating layer 51 and the second substrate-side insulating layer 52 shown in Fig. 4 does not represent the actual number of layers of the first substrate-side insulating layer 51 and the second substrate-side insulating layer 52.

[0058] The resistor-side insulating layer 70 is an insulating layer in which the semiconductor resistance layer 20 is embedded. The resistor-side insulating layer 70 includes a first insulating layer 71, a second insulating layer 72 stacked on the first insulating layer 71, and a third insulating layer 73 stacked on the second insulating layer 72. The semiconductor resistance layer 20 is stacked on the second insulating layer 72 and covered by the third insulating layer 73. Therefore, as shown in FIG. 4 , the multiple semiconductor resistance layers 20 are arranged at the same positions as each other in the Z-axis direction.

[0059] The semiconductor resistance layer 20 is formed in a flat plate shape with its thickness direction in the Z-axis direction. The thickness of the semiconductor resistance layer 20 is thinner than its width (length in the X-axis direction). The semiconductor resistance layer 20 is also thinner than each of the first to third insulating layers 71 to 73. The thickness of the semiconductor resistance layer 20 is, for example, not less than 1 nm and not more than 100 nm. In the first embodiment, the thickness of the semiconductor resistance layer 20 is approximately 2.5 nm. The semiconductor resistance layer 20 is formed of a material containing, for example, CrSi (chromium silicon).

[0060] 5 , the semiconductor resistive layer 20 includes a resistive back surface 27 facing the element back surface 42 of the element insulating layer 40 in the Z-axis direction, a resistive front surface 28 opposite the resistive back surface 27, and a resistive side surface 29 connecting the resistive back surface 27 and the resistive front surface 28. In the first embodiment, both the resistive back surface 27 and the resistive front surface 28 are surfaces along the XY plane. The resistive side surface 29 is a surface that intersects with both the resistive back surface 27 and the resistive front surface 28. In the first embodiment, the resistive side surface 29 is a surface that is perpendicular to both the resistive back surface 27 and the resistive front surface 28.

[0061] The semiconductor resistor layer 20 is provided in the third insulating layer 73 with the resistor back surface 27 in contact with the second insulating layer 72. In other words, the semiconductor resistor layer 20 is sandwiched between the second insulating layer 72 and the third insulating layer 73. Both the resistor front surface 28 and the resistor side surface 29 are in contact with the third insulating layer 73.

[0062] 6 , the wiring-side insulating layer 60 is an insulating layer in which multiple wiring layers 80 are embedded. The wiring-side insulating layer 60 includes a fourth insulating layer 61, a fifth insulating layer 62 stacked on the fourth insulating layer 61, and a sixth insulating layer 63 stacked on the fifth insulating layer 62. The multiple wiring layers 80 are stacked on the fifth insulating layer 62 and covered by the sixth insulating layer 63. In the illustrated example, the multiple wiring layers 80 are arranged at the same positions as each other in the Z direction.

[0063] The wiring layer 80 includes, for example, the wirings 21 to 25 shown in Fig. 3. The wiring layer 80 is embedded in the wiring-side insulating layer 60, and is therefore disposed closer to the substrate 30 (see Fig. 4) in the Z-axis direction than the semiconductor resistor layer 20 embedded in the resistor-side insulating layer 70.

[0064] The wiring layer 80 is formed in a flat plate shape with its thickness direction aligned in the Z-axis direction. The thickness of the wiring layer 80 is thinner than its width (the length in a direction perpendicular to the extension direction of the wiring layer 80 in a plan view). The thickness of the wiring layer 80 is thicker than the thickness of the semiconductor resistance layer 20. In the example shown in FIG. 6 , the thickness of the wiring layer 80 is thicker than the thickness of each of the fifth insulating layer 62 and the sixth insulating layer 63. Meanwhile, the thickness of the wiring layer 80 is thinner than the thickness of the fourth insulating layer 61. The wiring layer 80 is made of one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W, as appropriate. In the first embodiment, the wiring layer 80 is made of a material containing Al.

[0065] In the example shown in FIG. 6 , the wiring layer 80 electrically connects two semiconductor resistance layers 20 adjacent to each other in the Y-axis direction. More specifically, the wiring layer 80 is formed so as to overlap both of the two semiconductor resistance layers 20. Each semiconductor resistance layer 20 and the wiring layer 80 are connected by two vias 90. The vias 90 extend in the Z-axis direction, which is the thickness direction of the element insulating layer 40. More specifically, the vias 90 penetrate the first insulating layer 71, the second insulating layer 72, and the sixth insulating layer 63 in the Z-axis direction, thereby contacting both the semiconductor resistance layer 20 and the wiring layer 80. The vias 90 are made of one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W, as appropriate. In the first embodiment, the vias 90 are made of a material containing W. The number of vias 90 can be changed as desired.

[0066] The wiring layer 80 includes a wiring back surface 81 facing the element back surface 42 (see FIG. 4 ) of the element insulating layer 40 in the Z-axis direction, a wiring front surface 82 opposite the wiring back surface 81, and a wiring side surface 83 connecting the wiring back surface 81 and the wiring front surface 82. In the illustrated example, it can be said that the wiring back surface 81 faces the side opposite the semiconductor resistance layer 20 in the Z-axis direction. In the first embodiment, both the wiring back surface 81 and the wiring front surface 82 are surfaces along the XY plane. The wiring side surface 83 is a surface that intersects with both the wiring back surface 81 and the wiring front surface 82. In the first embodiment, the wiring side surface 83 is a surface that is perpendicular to both the wiring back surface 81 and the wiring front surface 82.

[0067] The wiring layer 80 is provided in the sixth insulating layer 63 with the wiring back surface 81 in contact with the fifth insulating layer 62. In other words, the wiring layer 80 is sandwiched between the fifth insulating layer 62 and the sixth insulating layer 63. Both the wiring front surface 82 and the wiring side surface 83 are in contact with the sixth insulating layer 63.

[0068] 5 , the element insulating layer 40 including the resistor-side insulating layer 70 and the wiring-side insulating layer 60 includes a structure that relieves electric field concentration in the semiconductor resistance layer 20. In one example, the element insulating layer 40 includes a first insulating layer 71, a second insulating layer 72, and a sixth insulating layer 63 as a structure that relieves electric field concentration in the semiconductor resistance layer 20.

[0069] Both the first insulating layer 71 and the second insulating layer 72 are disposed between the semiconductor resistance layer 20 and the wiring layer 80 in the Z-axis direction. The sixth insulating layer 63 is disposed closer to the substrate 30 than both the first insulating layer 71 and the second insulating layer 72. The first insulating layer 71 is stacked on the sixth insulating layer 63. The first insulating layer 71 is in contact with the sixth insulating layer 63.

[0070] The second insulating layer 72 in contact with the semiconductor resistance layer 20 is formed of a material containing, for example, SiN. Therefore, the relative dielectric constant of the second insulating layer 72 is about 7. In the illustrated example, the thickness of the second insulating layer 72 is thinner than both the thickness of the first insulating layer 71 and the thickness of the sixth insulating layer 63.

[0071] The first insulating layer 71 is disposed apart from the semiconductor resistance layer 20 in the Z-axis direction via the second insulating layer 72. The first insulating layer 71 is disposed apart from the wiring layer 80 in the Z-axis direction via the sixth insulating layer 63. The first insulating layer 71 has a lower dielectric constant than the second insulating layer 72. The dielectric constant of the first insulating layer 71 is greater than 3.8 and less than 7. In one example, the dielectric constant of the first insulating layer 71 may be greater than 4 and less than 7. In the first embodiment, the first insulating layer 71 is formed of a material containing SiON. Therefore, the dielectric constant of the first insulating layer 71 is adjusted depending on the concentration of N (nitrogen) in the SiON. The first insulating layer 71 has a thickness thinner than the sixth insulating layer 63.

[0072] The sixth insulating layer 63 is disposed to be spaced apart from the semiconductor resistance layer 20 in the Z-axis direction. The sixth insulating layer 63 has a lower relative dielectric constant than the first insulating layer 71. In the first embodiment, the sixth insulating layer 63 is made of SiO ２ The sixth insulating layer 63 is formed of a material containing . Therefore, the relative dielectric constant of the sixth insulating layer 63 is about 3.8. In this manner, the sixth insulating layer 63 is an insulating layer that alleviates the electric field of the semiconductor resistance layer 20 and covers the wiring layer 80. The thickness of the region of the sixth insulating layer 63 where the wiring layer 80 is not disposed is thicker than the thickness of each of the first insulating layer 71 and the second insulating layer 72. Here, in the first embodiment, the sixth insulating layer 63 corresponds to a "low dielectric constant insulating layer."

[0073] In this way, in the structure that alleviates the electric field concentration on the semiconductor resistance layer 20, the second insulating layer 72, the first insulating layer 71, and the sixth insulating layer 63 are arranged in this order from the semiconductor resistance layer 20 toward the substrate 30. In other words, the structure that alleviates the electric field concentration on the semiconductor resistance layer 20 is configured so that the relative dielectric constant decreases from the semiconductor resistance layer 20 toward the substrate 30.

[0074] Furthermore, the third insulating layer 73 covering the semiconductor resistance layer 20 has a lower dielectric constant than the second insulating layer 72. The third insulating layer 73 may have a lower dielectric constant than the first insulating layer 71. The third insulating layer 73 is made of a material selected from the group consisting of SiON, SiC, and SiO ２ In the first embodiment, the third insulating layer 73 has a lower relative dielectric constant than the first insulating layer 71, and therefore is made of a material containing SiO ２ This improves the insulation between the semiconductor resistance layers 20 adjacent to each other in the Y-axis direction.

[0075] In the illustrated example, the thickness of the third insulating layer 73 is greater than the thickness of the first insulating layer 71, the thickness of the second insulating layer 72, and the thickness of the sixth insulating layer 63. Note that the thicknesses of the first insulating layer 71, the second insulating layer 72, the third insulating layer 73, and the sixth insulating layer 63 can be changed as desired. In one example, the thickness of the first insulating layer 71, the thickness of the second insulating layer 72, and the thickness of the sixth insulating layer 63 may be equal to one another. In another example, the thickness of the first insulating layer 71 and the thickness of the second insulating layer 72 may be equal to one another and thinner than the thickness of the sixth insulating layer 63. In another example, the thickness of the first insulating layer 71 may be thicker than the thickness of the second insulating layer 72. In another example, the thickness of the third insulating layer 73 may be equal to the thickness of the sixth insulating layer 63. In another example, the thickness of the third insulating layer 73 may be thinner than the thickness of the sixth insulating layer 63.

[0076] 6 , the element insulating layer 40, which includes the wiring-side insulating layer 60 and the substrate-side insulating layer 50, includes a structure that alleviates electric field concentration in the wiring layer 80. In one example, the element insulating layer 40 includes a fourth insulating layer 61, a fifth insulating layer 62, and a second substrate-side insulating layer 52 that is the uppermost layer of the substrate-side insulating layer 50, as a structure that alleviates electric field concentration in the wiring layer 80. In the following description, the second substrate-side insulating layer 52 that is the uppermost layer of the substrate-side insulating layer 50 will be referred to as the "seventh insulating layer 52A."

[0077] The fourth insulating layer 61, the fifth insulating layer 62, and the seventh insulating layer 52A are each disposed closer to the substrate 30 (see FIG. 4 ) than the wiring layer 80. It can also be said that the fourth insulating layer 61, the fifth insulating layer 62, and the seventh insulating layer 52A are each disposed on the opposite side of the wiring layer 80 from the semiconductor resistance layer 20 in the Z-axis direction. The fourth insulating layer 61 is stacked on the seventh insulating layer 52A. The fourth insulating layer 61 is in contact with the seventh insulating layer 52A.

[0078] The fifth insulating layer 62 in contact with the wiring layer 80 is formed of a material containing, for example, SiN. Therefore, the relative dielectric constant of the fifth insulating layer 62 is approximately 7. In the illustrated example, the thickness of the fifth insulating layer 62 is equal to the thickness of the fourth insulating layer 61. Here, if the difference between the thicknesses of the fifth insulating layer 62 and the fourth insulating layer 61 is, for example, within 20% of the thickness of the fifth insulating layer 62, it can be said that the thickness of the fifth insulating layer 62 is equal to the thickness of the fourth insulating layer 61. Furthermore, the thickness of the fifth insulating layer 62 is thinner than the thickness of the seventh insulating layer 52A.

[0079] In the illustrated example, the thickness of the fifth insulating layer 62 and the thickness of the fourth insulating layer 61 are both thinner than the thickness of the first insulating layer 71. In addition, the thickness of the fifth insulating layer 62 and the thickness of the fourth insulating layer 61 are both thinner than the thickness of the second insulating layer 72.

[0080] The fourth insulating layer 61 is disposed apart from the wiring layer 80 in the Z-axis direction via the fifth insulating layer 62. The fourth insulating layer 61 has a lower dielectric constant than the fifth insulating layer 62. The dielectric constant of the fourth insulating layer 61 is greater than 3.8 and less than 7. In one example, the dielectric constant of the fourth insulating layer 61 may be greater than 4 and less than 7. In the first embodiment, the fourth insulating layer 61 is formed of a material containing SiON. Therefore, the dielectric constant of the fourth insulating layer 61 is adjusted depending on the concentration of N (nitrogen) in the SiON. The fourth insulating layer 61 has a thickness thinner than that of the seventh insulating layer 52A.

[0081] The seventh insulating layer 52A is disposed to be spaced apart from the wiring layer 80 in the Z-axis direction. The seventh insulating layer 52A has a lower relative dielectric constant than the fourth insulating layer 61. In the first embodiment, the seventh insulating layer 52A is made of SiO ２ The seventh insulating layer 52A is formed of a material containing the compound. Therefore, the relative dielectric constant of the seventh insulating layer 52A is approximately 3.8. The thickness of the seventh insulating layer 52A is greater than both the thickness of the first insulating layer 71 and the thickness of the second insulating layer 72. The thickness of the seventh insulating layer 52A is also greater than the thickness of the sixth insulating layer 63.

[0082] In this way, in the structure that alleviates the electric field concentration on the wiring layer 80, the fifth insulating layer 62, the fourth insulating layer 61, and the seventh insulating layer 52A are arranged in this order from the wiring layer 80 toward the substrate 30. In other words, the structure that alleviates the electric field concentration on the wiring layer 80 is configured so that the relative dielectric constant decreases from the wiring layer 80 toward the substrate 30.

[0083] Furthermore, the sixth insulating layer 63 covering the wiring layer 80 has a lower dielectric constant than the fifth insulating layer 62. The sixth insulating layer 63 may have a lower dielectric constant than the fourth insulating layer 61. The sixth insulating layer 63 is made of a material selected from the group consisting of SiON, SiC, and SiO ２ In the first embodiment, the sixth insulating layer 63 has a lower relative dielectric constant than the fourth insulating layer 61, and therefore is made of a material containing SiO ２ This improves the insulation between the wiring layers 80 adjacent to each other in the Y-axis direction.

[0084] The thicknesses of the fourth insulating layer 61, the fifth insulating layer 62, and the seventh insulating layer 52A can be changed as desired. For example, the thickness of the fourth insulating layer 61 may be thinner than the thickness of the fifth insulating layer 62. For example, the thickness of the fourth insulating layer 61 may be thicker than the thickness of the fifth insulating layer 62. For example, the thicknesses of the fourth insulating layer 61, the fifth insulating layer 62, and the seventh insulating layer 52A may be equal to one another. For example, the thicknesses of the fourth insulating layer 61 and the fifth insulating layer 62 may be equal to one another and thinner than the thickness of the seventh insulating layer 52A. For example, the thickness of the seventh insulating layer 52A may be equal to the thickness of the sixth insulating layer 63. For example, the thickness of the seventh insulating layer 52A may be thinner than the thickness of the sixth insulating layer 63.

[0085] (Terminal Electric Field Relaxation Structure) As shown in FIG. 7 , the element insulating layer 40 includes a structure that relaxes electric field concentration generated at the terminal P1. In one example, the element insulating layer 40 includes a third insulating layer 73, an eighth insulating layer 91, and a ninth insulating layer 92 as a structure that relaxes electric field concentration at the terminal P1. The first chip 14 of the first embodiment includes terminals P1 to P5 shown in FIG. 3 . Terminals P2 to P5 are also formed in the same manner as the terminal P1. In FIG. 7 , the structure that relaxes electric field concentration will be described using the terminal P1.

[0086] The eighth insulating layer 91 is stacked on the third insulating layer 73. The ninth insulating layer 92 is stacked on the eighth insulating layer 91. A terminal P1 is disposed on the ninth insulating layer 92. Both the eighth insulating layer 91 and the ninth insulating layer 92 are disposed to be spaced apart from the semiconductor resistance layer 20 in the Z-axis direction.

[0087] The ninth insulating layer 92 in contact with the terminal P1 is formed of a material containing, for example, SiN. Therefore, the relative dielectric constant of the ninth insulating layer 92 is about 7. In the illustrated example, the thickness of the ninth insulating layer 92 is thinner than the thickness of the eighth insulating layer 91. The thickness of the ninth insulating layer 92 is also thinner than the thickness of the third insulating layer 73.

[0088] In the illustrated example, the thickness of the ninth insulating layer 92 is equal to the thickness of the second insulating layer 72. Here, if the difference between the thicknesses of the ninth insulating layer 92 and the second insulating layer 72 is, for example, within 20% of the thickness of the second insulating layer 72, the thickness of the ninth insulating layer 92 can be said to be equal to the thickness of the second insulating layer 72. The thickness of the ninth insulating layer 92 is thinner than the thickness of the first insulating layer 71. The thickness of the ninth insulating layer 92 is thicker than both the thickness of the fourth insulating layer 61 and the thickness of the fifth insulating layer 62. The thickness of the ninth insulating layer 92 is thinner than the thickness of the sixth insulating layer 63.

[0089] The eighth insulating layer 91 is disposed away from the terminal P1 in the Z-axis direction via the ninth insulating layer 92. The eighth insulating layer 91 has a lower dielectric constant than the ninth insulating layer 92. The dielectric constant of the eighth insulating layer 91 is greater than 3.8 and less than 7. In one example, the dielectric constant of the eighth insulating layer 91 may be greater than 4 and less than 7. In the first embodiment, the eighth insulating layer 91 is formed of a material containing SiON. Therefore, the dielectric constant of the eighth insulating layer 91 is adjusted depending on the concentration of N (nitrogen) in the SiON. In the illustrated example, the eighth insulating layer 91 has a thickness thinner than that of the third insulating layer 73. The thickness of the eighth insulating layer 91 is equal to the thickness of the first insulating layer 71. Here, if the difference between the thicknesses of the eighth insulating layer 91 and the first insulating layer 71 is, for example, within 20% of the thickness of the first insulating layer 71, the thickness of the eighth insulating layer 91 can be said to be equal to the thickness of the first insulating layer 71.

[0090] The third insulating layer 73 is disposed apart from the terminal P1 in the Z-axis direction. As described above, the third insulating layer 73 is made of SiO ２ Since the eighth insulating layer 91 is made of a material containing , it has a lower relative dielectric constant than the eighth insulating layer 91 .

[0091] In this way, in the structure that alleviates the electric field concentration on the terminals P1 to P5, the ninth insulating layer 92, the eighth insulating layer 91, and the third insulating layer 73 are arranged in this order from the terminals P1 to P5 toward the substrate 30. In other words, the structure that alleviates the electric field concentration on the terminals P1 to P5 is configured so that the relative dielectric constant decreases from the terminals P1 to P5 toward the substrate 30.

[0092] The thicknesses of the eighth insulating layer 91, the ninth insulating layer 92, and the third insulating layer 73 can be changed as desired. In one example, the thickness of the eighth insulating layer 91 and the thickness of the ninth insulating layer 92 may be equal to each other. In another example, the thickness of the eighth insulating layer 91 may be thicker than the thickness of the ninth insulating layer 92. In another example, the thickness of the eighth insulating layer 91, the thickness of the ninth insulating layer 92, and the thickness of the third insulating layer 73 may be equal to each other.

[0093] Each of the terminals P1 to P5 and the wiring layer 80 is electrically connected by a via 93. The via 93 extends in the Z-axis direction, which is the thickness direction of the element insulating layer 40. More specifically, as shown in FIG. 7 , the via 93 penetrates the ninth insulating layer 92, the eighth insulating layer 91, the third insulating layer 73, the second insulating layer 72, the first insulating layer 71, and the sixth insulating layer 63 in the Z-axis direction, thereby contacting both the terminal P1 and the wiring layer 80. Note that, although not shown, the connection structure between each of the terminals P2 to P5 and the wiring layer 80 via the via 93 is also similar. The via 93 is formed, for example, from the same material as the via 90.

[0094] 8 to 16, an example of a method for manufacturing the semiconductor device 10 will be described. For convenience, in the following description, components common to the semiconductor device 10 and the semiconductor device 10 will be denoted by the same reference numerals.

[0095] As shown in FIG. 8 , the manufacturing method of the semiconductor device 10 includes a step of preparing a substrate 30 and a step of forming a substrate-side insulating layer 50 on the substrate 30. First, the substrate 30 is prepared. The substrate 30 is, for example, a Si substrate. Subsequently, a step of forming the substrate-side insulating layer 50 on the substrate 30 is performed. In one example, in this step, a second substrate-side insulating layer 52 is formed on the substrate 30, and then the first substrate-side insulating layer 51 and the second substrate-side insulating layer 52 are alternately stacked. The first substrate-side insulating layer 51 and the second substrate-side insulating layer 52 are formed by, for example, chemical vapor deposition (CVD). In the first embodiment, the first substrate-side insulating layer 51 is a SiN film, and the second substrate-side insulating layer 52 is a SiO 2 film. ２The second substrate-side insulating layer 52, which is the uppermost layer of the substrate-side insulating layer 50, constitutes a seventh insulating layer 52A.

[0096] 9 , the method for manufacturing the semiconductor device 10 includes a step of forming a part of the wiring-side insulating layer 60. More specifically, the method for manufacturing the semiconductor device 10 includes a step of forming a fourth insulating layer 61 and a step of forming a fifth insulating layer 62.

[0097] In the step of forming the fourth insulating layer 61, the fourth insulating layer 61 is formed by, for example, CVD so as to be deposited on the second-substrate-side insulating layer 52 that will become the seventh insulating layer 52A. Subsequently, in the step of forming the fifth insulating layer 62, the fifth insulating layer 62 is formed by, for example, CVD so as to be deposited on the fourth insulating layer 61. In the first embodiment, the fourth insulating layer 61 is a SiON film, and the fifth insulating layer 62 is a SiN film.

[0098] 10 , the manufacturing method of the semiconductor device 10 includes a step of forming the wiring layer 80. More specifically, in this step, a metal film (not shown) that is a material film for the wiring layer 80 is formed on the fifth insulating layer 62 over the entire surface of the fifth insulating layer 62, for example, by sputtering. The metal film is made of one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W, as appropriate. Subsequently, the metal film is patterned by, for example, lithography and etching, to form the wiring layer 80.

[0099] 11 , the method for manufacturing the semiconductor device 10 includes a step of forming the remainder of the wiring-side insulating layer 60 and a step of forming a part of the resistor-side insulating layer 70. The step of forming the remainder of the wiring-side insulating layer 60 includes a step of forming the sixth insulating layer 63. In this step, the sixth insulating layer 63 is formed so as to be deposited on the fifth insulating layer 62 and the wiring layer 80 by, for example, CVD. As a result, the wiring layer 80 is covered with the fifth insulating layer 62 and the sixth insulating layer 63. In the first embodiment, the sixth insulating layer 63 is made of SiO ２ It is a membrane.

[0100] The step of forming a part of the resistor-side insulating layer 70 includes a step of forming a first insulating layer 71 and a step of forming a second insulating layer 72. More specifically, in the step of forming the first insulating layer 71, the first insulating layer 71 is formed by, for example, CVD so as to be deposited on the sixth insulating layer 63. In the step of forming the second insulating layer 72, the second insulating layer 72 is formed by, for example, CVD so as to be deposited on the first insulating layer 71. In the first embodiment, the first insulating layer 71 is a SiON film, and the second insulating layer 72 is a SiN film.

[0101] 12 , the manufacturing method of the semiconductor device 10 includes a step of forming a via 90. More specifically, in this step, a via opening 801 is first formed by, for example, etching. The via opening 801 is formed so as to penetrate both the first insulating layer 71 and the second insulating layer 72 in the Z-axis direction and to expose a portion of the wiring layer 80 relative to the sixth insulating layer 63. Next, a metal material is filled in the via opening 801 by, for example, sputtering. The metal material is, for example, one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W, as appropriate. In this way, the via 90 is formed.

[0102] 13 , the manufacturing method of the semiconductor device 10 includes a step of forming the semiconductor resistance layer 20. More specifically, in this step, a resistive material film, which is a material film of the semiconductor resistance layer 20, is first formed on the second insulating layer 72. The resistive material film is formed over the entire surface of the second insulating layer 72. The resistive material film is made of, for example, CrSi. Subsequently, the resistive material film is patterned by, for example, lithography and etching, to form the semiconductor resistance layer 20. As a result, the upper end of the via 90 is connected to the semiconductor resistance layer 20.

[0103] 14 , the method for manufacturing the semiconductor device 10 includes a step of forming the remainder of the resistor-side insulating layer 70, a step of forming an eighth insulating layer 91, and a step of forming a ninth insulating layer 92. The step of forming the remainder of the resistor-side insulating layer 70 includes a step of forming a third insulating layer 73.

[0104] In the step of forming the third insulating layer 73, the third insulating layer 73 is formed by, for example, CVD so as to be deposited on the second insulating layer 72 and the semiconductor resistance layer 20. In the step of forming the eighth insulating layer 91, the eighth insulating layer 91 is formed by, for example, CVD so as to be deposited on the third insulating layer 73. In the step of forming the ninth insulating layer 92, the ninth insulating layer 92 is formed by, for example, CVD so as to be deposited on the eighth insulating layer 91. In the first embodiment, the third insulating layer 73 is made of SiO ２ The eighth insulating layer 91 is a SiON film, and the ninth insulating layer 92 is a SiN film.

[0105] 15 , the manufacturing method of the semiconductor device 10 includes a step of forming a via 93. More specifically, in this step, a via opening 802 is first formed by, for example, etching. The via opening 802 is formed so as to penetrate the ninth insulating layer 92, the eighth insulating layer 91, the third insulating layer 73, the second insulating layer 72, and the first insulating layer 71 in the Z-axis direction and to expose a portion of the wiring layer 80 relative to the sixth insulating layer 63. Next, a metal material is filled in the via opening 802 by, for example, sputtering. The metal material is, for example, one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W, as appropriate. This forms the via 93.

[0106] As shown in FIG. 16 , the manufacturing method for the semiconductor device 10 includes a step of forming terminals P1 to P5. More specifically, in this step, a metal film (not shown) that is the material film for the terminals P1 to P5 is formed on the ninth insulating layer 92 over the entire surface of the ninth insulating layer 92, for example, by sputtering. The metal film is made of one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, Ni, Pd, and W, as appropriate. Subsequently, the terminals P1 to P5 are formed by patterning the metal film, for example, by lithography and etching. Note that, for convenience, FIG. 16 shows only terminal P1 of the terminals P1 to P5.

[0107] Although not shown, the manufacturing method of the semiconductor device 10 includes a step of forming the passivation film 43. More specifically, in this step, a passivation material film, which is a material film for the passivation film 43, is first formed on the ninth insulating layer 92 and the terminals P1 to P5, for example, by CVD. Next, a portion of the passivation material film covering the terminals P1 to P5 is removed, for example, by etching. In other words, a portion of the terminals P1 to P5 is exposed from the passivation material film. The passivation material film is, for example, a SiN film. In this way, the passivation film 43 is formed. Through the above steps, the first chip 14 is formed.

[0108] Although not shown, the manufacturing method of semiconductor device 10 includes the steps of preparing first chip 14 and second chip 15, preparing a lead frame, mounting first chip 14 and second chip 15 on the lead frame, forming wires W1 to W11, forming sealing resin 16, and singulating.

[0109] In the step of preparing a lead frame, a lead frame including a frame 11, a die pad 12, and leads 13A to 13G (see FIG. 1) is prepared. In the step of mounting a first chip 14 and a second chip 15 on the lead frame, the first chip 14 is die-bonded to a die pad portion 11A of the frame 11 (see FIG. 1), and the second chip 15 is die-bonded to the die pad 12.

[0110] In the process of forming the wires W1 to W11, W1 to W11 are formed by a wire bonding device. That is, W1 to W11 are bonding wires. In the process of forming the sealing resin 16, a resin layer that seals the frame 11, die pad 12, leads 13A to 13G, first chip 14, second chip 15, and wires W1 to W11 is formed by, for example, transfer molding. The resin layer is made of, for example, black epoxy resin. Note that the resin layer may also be formed by, for example, compression molding.

[0111] In the singulation process, the lead frame and the resin layer are cut by, for example, dicing, thereby forming the frame 11 and the leads 13A to 13G. Through the above steps, the semiconductor device 10 is manufactured.

[0112] [Effects] The semiconductor device 10 of the first embodiment provides the following effects. (1-1) The semiconductor device 10 includes an element insulating layer 40 having an element front surface 41 and an element back surface 42 opposite the element front surface 41, and a plurality of semiconductor resistance layers 20 provided in the element insulating layer 40. Each semiconductor resistance layer 20 includes a resistor back surface 27 facing the element back surface 42 in the thickness direction (Z-axis direction) of the element insulating layer 40, a resistor front surface 28 opposite the resistor back surface 27, and a resistor side surface 29 connecting the resistor back surface 27 and the resistor front surface 28. The element insulating layer 40 includes a first insulating layer 71, a second insulating layer 72 stacked on the first insulating layer 71 and having a higher dielectric constant than the first insulating layer 71, and a third insulating layer 73 stacked on the second insulating layer 72 and having a lower dielectric constant than the second insulating layer 72. Each semiconductor resistance layer 20 is stacked on the second insulating layer 72. Each semiconductor resistor layer 20 is provided in the third insulating layer 73 with the resistor back surface 27 in contact with the second insulating layer 72 .

[0113] According to this configuration, the resistor back surface 27 of the semiconductor resistor layer 20 is in contact with the second insulating layer 72, which has a higher dielectric constant than the third insulating layer 73, and therefore it is possible to reduce the electric field strength from the resistor back surface 27 toward the element back surface 42 of the element insulating layer 40. Therefore, it is possible to alleviate electric field concentration in the semiconductor resistor layer 20.

[0114] In addition, the dielectric constant decreases in the order from the semiconductor resistance layer 20 to the second insulating layer 72 and the first insulating layer 71. That is, in the direction from the semiconductor resistance layer 20 toward the element back surface 42 of the element insulating layer 40, the dielectric constant gradually decreases with increasing distance from the semiconductor resistance layer 20. This makes it possible to further reduce the electric field strength from the semiconductor resistance layer 20 toward the element back surface 42 of the element insulating layer 40. Therefore, it is possible to further alleviate the electric field concentration in the semiconductor resistance layer 20.

[0115] (1-2) The multiple semiconductor resistance layers 20 are aligned in the thickness direction (Z-axis direction) of the element insulating layer 40 and spaced apart in a direction perpendicular to the thickness direction (Y-axis direction in the first embodiment).

[0116] According to this configuration, a structure for alleviating electric field concentration in each semiconductor resistance layer 20 can be realized by the first insulating layer 71 and the second insulating layer 72 that are common to the multiple semiconductor resistance layers 20. Therefore, compared to a configuration in which the multiple semiconductor resistance layers 20 are provided at different positions in the Z-axis direction, a structure for alleviating electric field concentration in each semiconductor resistance layer 20 can be easily realized.

[0117] (1-3) The semiconductor device 10 includes a wiring layer 80 that is provided on the element back surface 42 side of the element insulating layer 40 with respect to the semiconductor resistance layer 20 and is electrically connected to the semiconductor resistance layer 20. The wiring layer 80 includes a wiring front surface 82 that faces the semiconductor resistance layer 20 in the thickness direction (Z-axis direction) of the element insulating layer 40, a wiring back surface 81 opposite the wiring front surface 82, and a wiring side surface 83 that connects the wiring front surface 82 and the wiring back surface 81. The element insulating layer 40 includes a fourth insulating layer 61 and a fifth insulating layer 62 that is stacked on the fourth insulating layer 61 and has a higher dielectric constant than the fourth insulating layer 61. The wiring layer 80 is stacked on the fifth insulating layer 62, and the wiring back surface 81 is in contact with the fifth insulating layer 62.

[0118] According to this configuration, the wiring back surface 81 of the wiring layer 80 is in contact with the fifth insulating layer 62, which has a higher dielectric constant than the fourth insulating layer 61, and therefore it is possible to reduce the electric field strength from the wiring back surface 81 toward the element back surface 42 of the element insulating layer 40. Therefore, it is possible to alleviate electric field concentration in the wiring layer 80.

[0119] In addition, the dielectric constant decreases in the order from the wiring layer 80 to the fifth insulating layer 62 and the fourth insulating layer 61. That is, in the direction from the wiring layer 80 toward the element back surface 42 of the element insulating layer 40, the dielectric constant gradually decreases with increasing distance from the wiring layer 80. This makes it possible to further reduce the electric field strength from the wiring layer 80 toward the element back surface 42 of the element insulating layer 40. Therefore, it is possible to further alleviate the electric field concentration in the wiring layer 80.

[0120] (1-4) The element insulating layer 40 includes a sixth insulating layer 63 that is provided between the fifth insulating layer 62 and the first insulating layer 71 and has a lower dielectric constant than the fifth insulating layer 62. The first insulating layer 71 is stacked on the sixth insulating layer 63. The sixth insulating layer 63 has a lower dielectric constant than the first insulating layer 71.

[0121] According to this configuration, the dielectric constant decreases in the order of the semiconductor resistance layer 20, the second insulating layer 72, the first insulating layer 71, and the sixth insulating layer 63. That is, in the direction from the semiconductor resistance layer 20 toward the element rear surface 42 of the element insulating layer 40, the dielectric constant gradually decreases with increasing distance from the semiconductor resistance layer 20. This makes it possible to further reduce the electric field strength from the semiconductor resistance layer 20 toward the element rear surface 42 of the element insulating layer 40. Therefore, it is possible to further alleviate the electric field concentration in the semiconductor resistance layer 20.

[0122] (1-5) The element insulating layer 40 includes a seventh insulating layer 52A having a lower dielectric constant than the fourth insulating layer 61. The fourth insulating layer 61 is stacked on the seventh insulating layer 52A. With this configuration, the dielectric constant decreases in the order of the wiring layer 80, the fifth insulating layer 62, the fourth insulating layer 61, and the seventh insulating layer 52A. That is, in the direction from the wiring layer 80 toward the element back surface 42 of the element insulating layer 40, the dielectric constant gradually decreases with increasing distance from the wiring layer 80. This further reduces the electric field strength from the wiring layer 80 toward the element back surface 42 of the element insulating layer 40. Therefore, the electric field concentration in the wiring layer 80 can be further alleviated.

[0123] (1-6) The element insulating layer 40 includes an eighth insulating layer 91 that is stacked on the third insulating layer 73 and has a higher dielectric constant than the third insulating layer 73, and a ninth insulating layer 92 that is stacked on the eighth insulating layer 91 and has a higher dielectric constant than the eighth insulating layer 91. The semiconductor device 10 further includes terminals P1 to P5 that serve as electrode pads formed on the ninth insulating layer 92.

[0124] According to this configuration, the terminals P1 to P5 are in contact with the ninth insulating layer 92, which has a higher dielectric constant than the third insulating layer 73 and the eighth insulating layer 91, and therefore it is possible to reduce the electric field strength from the terminals P1 to P5 toward the element back surface 42 of the element insulating layer 40. Therefore, it is possible to alleviate the electric field concentration at the terminals P1 to P5.

[0125] In addition, the dielectric constant decreases in the order from the terminals P1 to P5 to the ninth insulating layer 92, the eighth insulating layer 91, and the third insulating layer 73. That is, in the direction from the terminals P1 to P5 toward the back surface 42 of the element insulating layer 40, the dielectric constant gradually decreases with increasing distance from the wiring layer 80. This makes it possible to further reduce the electric field strength from the terminals P1 to P5 toward the back surface 42 of the element insulating layer 40. Therefore, it is possible to further alleviate the electric field concentration at the terminals P1 to P5.

[0126] (1-7) The semiconductor device 10 includes an element insulating layer 40, a plurality of semiconductor resistance layers 20 provided in the element insulating layer 40, and a wiring layer 80 electrically connected to the semiconductor resistance layers 20 in the element insulating layer 40 and disposed opposite the semiconductor resistance layers 20 in the thickness direction (Z-axis direction) of the element insulating layer 40. The wiring layer 80 includes a wiring front surface 82 facing the semiconductor resistance layer 20 in the thickness direction of the element insulating layer 40, a wiring back surface 81 opposite the wiring front surface 82, and a wiring side surface 83 connecting the wiring front surface 82 and the wiring back surface 81. The element insulating layer 40 includes a fourth insulating layer 61, a fifth insulating layer 62 stacked on the fourth insulating layer 61 and having a higher dielectric constant than the fourth insulating layer 61, and a sixth insulating layer 63 stacked on the fifth insulating layer 62 and having a lower dielectric constant than the fifth insulating layer 62. The wiring layer 80 is laminated on the fifth insulating layer 62 and is provided in the sixth insulating layer 63 with the wiring back surface 81 in contact with the fifth insulating layer 62 .

[0127] According to this configuration, the wiring back surface 81 of the wiring layer 80 is in contact with the fifth insulating layer 62, which has a higher dielectric constant than the sixth insulating layer 63, and therefore it is possible to reduce the electric field strength from the wiring back surface 81 toward the element back surface 42 of the element insulating layer 40. Therefore, it is possible to alleviate electric field concentration in the wiring layer 80.

[0128] In addition, the dielectric constant decreases in the order from the wiring layer 80 to the fifth insulating layer 62 and the fourth insulating layer 61. That is, in the direction from the wiring layer 80 toward the element back surface 42 of the element insulating layer 40, the dielectric constant gradually decreases with increasing distance from the wiring layer 80. This makes it possible to further reduce the electric field strength from the wiring layer 80 toward the element back surface 42 of the element insulating layer 40. Therefore, it is possible to further alleviate the electric field concentration in the wiring layer 80.

[0129] 17 to 19, a semiconductor device 10 according to a second embodiment will be described. The semiconductor device 10 according to the second embodiment has a different electric field relaxation structure compared to the semiconductor device 10 according to the first embodiment. Differences from the first embodiment will be described in detail below, and components common to the first embodiment will be denoted by the same reference numerals and will not be described again.

[0130] As shown in FIG. 17 , in the semiconductor device 10 of the second embodiment, the element insulating layer 40 includes a front-side insulating layer 100 instead of the wiring-side insulating layer 60 and the resistor-side insulating layer 70 (both see FIG. 5 ). More specifically, the element insulating layer 40 includes a single-layer structure of the first insulating layer 71 instead of the stacked structure of the sixth insulating layer 63 and the first insulating layer 71 (see FIG. 5 ) in the first embodiment. Furthermore, the element insulating layer 40 includes a single-layer structure of the third insulating layer 73 instead of the stacked structure of the third insulating layer 73 and the eighth insulating layer 91 (see FIG. 5 ) in the first embodiment. That is, the front-side insulating layer 100 includes the first insulating layer 71, the second insulating layer 72, the third insulating layer 73, the fourth insulating layer 61, the fifth insulating layer 62, the seventh insulating layer 52A, and the ninth insulating layer 92. It can also be said that the front-side insulating layer 100 includes the resistor-side insulating layer 70. In the second embodiment, the first insulating layer 71 corresponds to a "low dielectric constant insulating layer."

[0131] The electric field relaxation structure of the semiconductor resistance layer 20 of the second embodiment includes a first insulating layer 71 and a second insulating layer 72, but does not include a sixth insulating layer 63. Therefore, in the second embodiment, the first insulating layer 71 is stacked on the fifth insulating layer 62. The first insulating layer 71 is in contact with the fifth insulating layer 62.

[0132] The thickness of the first insulating layer 71 is thicker than that of the first insulating layer 71 in the first embodiment. The thickness of the first insulating layer 71 is thicker than that of the second substrate-side insulating layer 52 (seventh insulating layer 52A). The first insulating layer 71 has a lower dielectric constant than the second insulating layer 72. The dielectric constant of the first insulating layer 71 is greater than 3.8 and less than 7. In one example, the dielectric constant of the first insulating layer 71 may be greater than 4 and less than 7. As in the first embodiment, the first insulating layer 71 is formed of a material containing SiON. Therefore, the dielectric constant of the first insulating layer 71 is adjusted depending on the concentration of N (nitrogen) in the SiON.

[0133] As in the first embodiment, the second insulating layer 72 is an insulating layer in contact with the resistor back surface 27 of the semiconductor resistor layer 20, and is made of a material containing SiN. The thickness of the second insulating layer 72 is the same as in the first embodiment.

[0134] In this way, in the structure that alleviates the electric field concentration on the semiconductor resistance layer 20, the second insulating layer 72 and the first insulating layer 71 are arranged in this order from the semiconductor resistance layer 20 toward the substrate 30. In other words, the structure that alleviates the electric field concentration on the semiconductor resistance layer 20 is configured so that the relative dielectric constant decreases from the semiconductor resistance layer 20 toward the substrate 30.

[0135] Furthermore, the third insulating layer 73 covering the semiconductor resistance layer 20 has a lower dielectric constant than the second insulating layer 72. In the second embodiment, the third insulating layer 73 is formed of a material containing SiON or SiC, unlike the first embodiment. In the second embodiment, the third insulating layer 73 is formed of a material containing SiON, just like the first insulating layer 71. In other words, the third insulating layer 73 and the first insulating layer 71 have the same dielectric constant.

[0136] In the illustrated example, the thickness of the third insulating layer 73 is greater than the thickness of the third insulating layer 73 in the first embodiment. The thickness of the third insulating layer 73 is greater than the thickness of both the first insulating layer 71 and the second insulating layer 72.

[0137] The thicknesses of the first insulating layer 71, the second insulating layer 72, and the third insulating layer 73 can be changed as desired. In one example, the thicknesses of the first insulating layer 71, the second insulating layer 72, and the third insulating layer 73 may be equal to one another. In another example, the thicknesses of the first insulating layer 71 and the second insulating layer 72 may be equal to one another and thinner than the thickness of the third insulating layer 73. In another example, the thickness of the second insulating layer 72 may be thicker than the thickness of the first insulating layer 71.

[0138] 18 , the electric field relaxation structure of the wiring layer 80 of the second embodiment is the same as the electric field relaxation structure of the wiring layer 80 of the first embodiment. That is, the electric field relaxation structure of the wiring layer 80 includes a fourth insulating layer 61, a fifth insulating layer 62, and a seventh insulating layer 52A.

[0139] 19, the semiconductor device 10 of the second embodiment has a single-layer structure of the third insulating layer 73, instead of the stacked structure of the third insulating layer 73 and the eighth insulating layer 91 of the first embodiment (see FIG. 5). Therefore, the electric field relaxation structure of the terminals P1 to P5 of the second embodiment includes the third insulating layer 73 and the ninth insulating layer 92.

[0140] The ninth insulating layer 92 is stacked on the third insulating layer 73. The ninth insulating layer 92 is in contact with the third insulating layer 73. The ninth insulating layer 92 is formed of a material containing SiN, as in the first embodiment. The third insulating layer 73 is formed of a material containing SiON, as in the second embodiment. In other words, the relative dielectric constant of the third insulating layer 73 is lower than the relative dielectric constant of the ninth insulating layer 92.

[0141] In this way, in the structure that alleviates the electric field concentration on the terminals P1 to P5, the ninth insulating layer 92 and the third insulating layer 73 are arranged in this order from the terminals P1 to P5 toward the substrate 30. In other words, the structure that alleviates the electric field concentration on the terminals P1 to P5 is configured so that the relative dielectric constant decreases from the terminals P1 to P5 toward the substrate 30.

[0142] [Effects] According to the semiconductor device 10 of the second embodiment, in addition to the effects (1-1) to (1-3), (1-5), and (1-8) of the first embodiment, the following effects can be obtained.

[0143] (2-1) The semiconductor device 10 includes an element insulating layer 40, a plurality of semiconductor resistance layers 20 provided in the element insulating layer 40, and a wiring layer 80 electrically connected to the semiconductor resistance layers 20 in the element insulating layer 40 and disposed opposite the semiconductor resistance layers 20 in the thickness direction (Z-axis direction) of the element insulating layer 40. The wiring layer 80 includes a wiring front surface 82 facing the semiconductor resistance layer 20 in the thickness direction of the element insulating layer 40, a wiring back surface 81 opposite the wiring front surface 82, and a wiring side surface 83 connecting the wiring front surface 82 and the wiring back surface 81. The element insulating layer 40 includes a fourth insulating layer 61, a fifth insulating layer 62 stacked on the fourth insulating layer 61 and having a higher dielectric constant than the fourth insulating layer 61, and a first insulating layer 71 stacked on the fifth insulating layer 62 and having a lower dielectric constant than the fifth insulating layer 62. The wiring layer 80 is laminated on the fifth insulating layer 62 and is provided in the first insulating layer 71 with the wiring back surface 81 in contact with the fifth insulating layer 62 .

[0144] According to this configuration, the wiring back surface 81 of the wiring layer 80 is in contact with the fifth insulating layer 62, which has a higher dielectric constant than the first insulating layer 71, and therefore it is possible to reduce the electric field strength from the wiring back surface 81 toward the element back surface 42 of the element insulating layer 40. Therefore, it is possible to alleviate electric field concentration in the wiring layer 80.

[0145] In addition, the dielectric constant decreases in the order from the wiring layer 80 to the fifth insulating layer 62 and the fourth insulating layer 61. That is, in the direction from the wiring layer 80 toward the element back surface 42 of the element insulating layer 40, the dielectric constant gradually decreases with increasing distance from the wiring layer 80. This makes it possible to further reduce the electric field strength from the wiring layer 80 toward the element back surface 42 of the element insulating layer 40. Therefore, it is possible to further alleviate the electric field concentration in the wiring layer 80.

[0146] (2-2) The element insulating layer 40 is stacked on the third insulating layer 73 and includes a ninth insulating layer 92 as a high-dielectric-constant insulating layer having a higher dielectric constant than the third insulating layer 73. The semiconductor device 10 further includes terminals P1 to P5 as electrode pads formed on the ninth insulating layer 92.

[0147] According to this configuration, the terminals P1 to P5 are in contact with the ninth insulating layer 92, which has a higher dielectric constant than the third insulating layer 73, and therefore it is possible to reduce the electric field strength from the terminals P1 to P5 toward the element back surface 42 of the element insulating layer 40. Therefore, it is possible to alleviate the electric field concentration at the terminals P1 to P5.

[0148] In addition, the dielectric constant decreases in the order from the terminals P1 to P5 to the ninth insulating layer 92 and the third insulating layer 73. That is, in the direction from the terminals P1 to P5 toward the back surface 42 of the element insulating layer 40, the dielectric constant gradually decreases with increasing distance from the wiring layer 80. This makes it possible to further reduce the electric field strength from the terminals P1 to P5 toward the back surface 42 of the element insulating layer 40. Therefore, it is possible to further alleviate the electric field concentration at the terminals P1 to P5.

[0149] 20 to 22, a semiconductor device 10 according to a third embodiment will be described. The semiconductor device 10 according to the third embodiment has a different electric field relaxation structure compared to the semiconductor device 10 according to the first embodiment. Differences from the first embodiment will be described in detail below, and components common to the first embodiment will be denoted by the same reference numerals and will not be described again.

[0150] As shown in FIG. 20 , in the semiconductor device 10 of the third embodiment, the element insulating layer 40 includes a front-side insulating layer 100 instead of the wiring-side insulating layer 60 and the resistor-side insulating layer 70 (both see FIG. 5 ) of the semiconductor device 10 of the first embodiment. More specifically, the element insulating layer 40 includes a single-layer structure of the first insulating layer 71 instead of the stacked structure of the sixth insulating layer 63 and the first insulating layer 71 (see FIG. 5 ) in the first embodiment. Also, the element insulating layer 40 includes a single-layer structure of the third insulating layer 73 instead of the stacked structure of the third insulating layer 73, the eighth insulating layer 91, and the ninth insulating layer 92 (see FIG. 5 ) in the first embodiment. That is, the front-side insulating layer 100 includes the first insulating layer 71, the second insulating layer 72, the third insulating layer 73, the fourth insulating layer 61, the fifth insulating layer 62, and the seventh insulating layer 52A. It can also be said that the front-side insulating layer 100 includes the resistor-side insulating layer 70. In the third embodiment, the first insulating layer 71 corresponds to a "low dielectric constant insulating layer."

[0151] 20, in the third embodiment, the electric field relaxation structure of the semiconductor resistance layer 20 is the same as the electric field relaxation structure of the semiconductor resistance layer 20 in the second embodiment. As shown in Fig. 21, in the third embodiment, the electric field relaxation structure of the wiring layer 80 is the same as the electric field relaxation structure of the wiring layer 80 in the first and second embodiments.

[0152] 22, in the third embodiment, the electric field relaxation structure of the terminals P1 to P5 is omitted. That is, the semiconductor device 10 of the third embodiment does not include either the eighth insulating layer 91 or the ninth insulating layer 92 (both of which are shown in FIG. 7).

[0153] The terminals P1 to P5 are formed on the third insulating layer 73. The terminals P1 to P5 are in contact with the third insulating layer 73. The third insulating layer 73 is made of SiO 2 as in the first embodiment. ２ The terminals P1 to P5 are formed of a material containing the above-mentioned. As in the first embodiment, the terminals P1 to P5 are covered with a passivation film 43. According to the third embodiment, it is possible to obtain the effects (1-1) to (1-3), (1-5), and (1-8) of the first embodiment and the effect (2-1) of the second embodiment.

[0154] <Modifications> The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0155] In each of the above embodiments, the positional relationship in the Z-axis direction between the semiconductor resistance layer 20 and the wiring layer 80 can be changed as desired. In one example, as shown in Fig. 23, the wiring layer 80 may be disposed closer to the element surface 41 of the element insulating layer 40 than the semiconductor resistance layer 20. In other words, the wiring layer 80 may be disposed between the semiconductor resistance layer 20 and the terminals P1 to P5 in the Z-axis direction.

[0156] As the position of the wiring layer 80 in the Z-axis direction is changed, the positions of the fourth insulating layer 61, the fifth insulating layer 62, and the sixth insulating layer 63 in the Z-axis direction are also changed. As the positions of the fourth insulating layer 61, the fifth insulating layer 62, and the sixth insulating layer 63 in the Z-axis direction are also changed, the positions of the first insulating layer 71, the second insulating layer 72, and the third insulating layer 73 in the Z-axis direction are also changed. In other words, in the illustrated example, the position of the wiring-side insulating layer 60 and the position of the resistor-side insulating layer 70 in the Z-axis direction are swapped.

[0157] More specifically, the fourth insulating layer 61 is stacked on the third insulating layer 73. The fifth insulating layer 62 is stacked on the fourth insulating layer 61. The wiring layer 80 is formed on the fifth insulating layer 62. The sixth insulating layer 63 is stacked on the fifth insulating layer 62 and covers the wiring layer 80. Here, similar to the first embodiment, the fourth insulating layer 61 is formed of a material containing SiON, the fifth insulating layer 62 is formed of a material containing SiN, and the sixth insulating layer 63 is formed of a material containing SiO ２ The material is formed from a material containing

[0158] The first insulating layer 71 is laminated on the seventh insulating layer 52A. The second insulating layer 72 is laminated on the first insulating layer 71. The semiconductor resistance layer 20 is formed on the second insulating layer 72. The third insulating layer 73 is laminated on the second insulating layer 72 and covers the semiconductor resistance layer 20. Here, similar to the first embodiment, the first insulating layer 71 is formed of a material containing SiON, the second insulating layer 72 is formed of a material containing SiN, and the third insulating layer 73 is formed of a material containing SiO ２ The seventh insulating layer 52A is formed of a material containing SiO ２ The material is formed from a material containing

[0159] The via 90 penetrates the fourth insulating layer 61, the fifth insulating layer 62, and the third insulating layer 73 to connect the semiconductor resistance layer 20 to the wiring layer 80. The via 93 penetrates the ninth insulating layer 92, the eighth insulating layer 91, and the sixth insulating layer 63 to connect the wiring layer 80 to the terminals P1 to P5. The material forming the vias 90 and 93 is, for example, the same as that in the first embodiment.

[0160] The structure that alleviates electric field concentration on the wiring layer 80 includes a fifth insulating layer 62, a fourth insulating layer 61, and a third insulating layer 73. In the structure that alleviates electric field concentration on the wiring layer 80, the fifth insulating layer 62, the fourth insulating layer 61, and the third insulating layer 73 are arranged in this order from the wiring layer 80 toward the substrate 30. In other words, the structure that alleviates electric field concentration on the wiring layer 80 is configured so that the relative dielectric constant decreases from the wiring layer 80 toward the substrate 30.

[0161] The structure that alleviates electric field concentration on the semiconductor resistance layer 20 includes a second insulating layer 72, a first insulating layer 71, and a seventh insulating layer 52A. In the structure that alleviates electric field concentration on the semiconductor resistance layer 20, the second insulating layer 72, the first insulating layer 71, and the seventh insulating layer 52A are arranged in this order from the semiconductor resistance layer 20 toward the substrate 30. In other words, the structure that alleviates electric field concentration on the semiconductor resistance layer 20 is configured so that the relative dielectric constant decreases from the semiconductor resistance layer 20 toward the substrate 30.

[0162] An eighth insulating layer 91 is laminated on the sixth insulating layer 63. A ninth insulating layer 92 is laminated on the eighth insulating layer 91. Terminals P1 to P5 are formed on the ninth insulating layer 92. Here, similar to the first embodiment, the eighth insulating layer 91 is formed of a material containing SiON, and the ninth insulating layer 92 is formed of a material containing SiN.

[0163] The structure that alleviates electric field concentration on the terminals P1 to P5 includes a ninth insulating layer 92, an eighth insulating layer 91, and a sixth insulating layer 63. In the structure that alleviates electric field concentration on the terminals P1 to P5, the ninth insulating layer 92, the eighth insulating layer 91, and the sixth insulating layer 63 are arranged in this order from the terminals P1 to P5 toward the substrate 30. In other words, the structure that alleviates electric field concentration on the terminals P1 to P5 is configured so that the relative dielectric constant decreases from the terminals P1 to P5 toward the substrate 30.

[0164] According to this configuration, similarly to the first embodiment, it is possible to reduce the electric field strength of each of the semiconductor resistance layer 20, the wiring layer 80, and the terminals P1 to P5, thereby alleviating electric field concentration within the semiconductor device 10 (first chip 14).

[0165] In each of the above embodiments, the wiring layer 80 may be disposed above the semiconductor resistance layer 20, and the wiring layer 80 may constitute the terminals P1 to P5. In one example, as shown in FIG. 24 , the wiring layer 80 is formed on the element surface 41 of the element insulating layer 40. In other words, the insulating layer including the element surface 41 of the element insulating layer 40 is formed of the fifth insulating layer 62. The fifth insulating layer 62 is stacked on the fourth insulating layer 61. The fourth insulating layer 61 is stacked on the third insulating layer 73. Thus, in the modified example shown in FIG. 24 , both the eighth insulating layer 91 and the ninth insulating layer 92 are omitted from the semiconductor device 10.

[0166] The passivation film 43 covers both the fifth insulating layer 62 and the wiring layer 80. Meanwhile, the passivation film 43 includes openings 43X that expose portions of the wiring layer 80 that form the terminals P1 to P5. In other words, the portions of the wiring layer 80 that are exposed from the passivation film 43 form the terminals P1 to P5.

[0167] The via 90 penetrates the fifth insulating layer 62, the fourth insulating layer 61, and the third insulating layer 73 in the Z-axis direction, thereby connecting the semiconductor resistance layer 20 and the wiring layer 80. The via 90 is formed of, for example, the same material as the via 90 in the first embodiment. In the modified example shown in FIG. 24 , the via 93 is omitted from the semiconductor device 10.

[0168] The first insulating layer 71 is laminated on the seventh insulating layer 52A. The second insulating layer 72 is laminated on the first insulating layer 71. The semiconductor resistance layer 20 is formed on the second insulating layer 72. The third insulating layer 73 is laminated on the second insulating layer 72 and covers the semiconductor resistance layer 20. Here, similar to the first embodiment, the first insulating layer 71 is formed of a material containing SiON, the second insulating layer 72 is formed of a material containing SiN, and the third insulating layer 73 is formed of a material containing SiO ２ The seventh insulating layer 52A is formed of a material containing SiO ２ The material is formed from a material containing

[0169] The structure that alleviates electric field concentration on the wiring layer 80 includes a fifth insulating layer 62, a fourth insulating layer 61, and a third insulating layer 73. In the structure that alleviates electric field concentration on the wiring layer 80, the fifth insulating layer 62, the fourth insulating layer 61, and the third insulating layer 73 are arranged in this order from the wiring layer 80 toward the substrate 30. In other words, the structure that alleviates electric field concentration on the wiring layer 80 is configured so that the relative dielectric constant decreases from the wiring layer 80 toward the substrate 30.

[0170] The structure that alleviates electric field concentration on the semiconductor resistance layer 20 includes a second insulating layer 72, a first insulating layer 71, and a seventh insulating layer 52A. In the structure that alleviates electric field concentration on the semiconductor resistance layer 20, the second insulating layer 72, the first insulating layer 71, and the seventh insulating layer 52A are arranged in this order from the semiconductor resistance layer 20 toward the substrate 30. In other words, the structure that alleviates electric field concentration on the semiconductor resistance layer 20 is configured so that the relative dielectric constant decreases from the semiconductor resistance layer 20 toward the substrate 30.

[0171] According to this configuration, similarly to the first embodiment, it is possible to reduce the electric field strength of each of the semiconductor resistance layer 20 and the wiring layer 80. Therefore, it is possible to alleviate electric field concentration within the semiconductor device 10 (first chip 14).

[0172] In each embodiment, the arrangement of the multiple semiconductor resistance layers 20 can be changed as desired. In one example, the multiple semiconductor resistance layers 20 may be arranged spaced apart from one another in the X-axis direction. In other words, the multiple semiconductor resistance layers 20 may be arranged spaced apart from one another in the short-side direction of the first chip 14. Furthermore, at least one of the multiple semiconductor resistance layers 20 may be arranged at a different position relative to the other semiconductor resistance layers 20 in the thickness direction (Y-axis direction) of the element insulating layer 40.

[0173] In each embodiment, the configuration of the multiple semiconductor resistance layers 20 can be changed as desired. Furthermore, the number of semiconductor resistance layers 20 can be changed as desired. In each embodiment, the configuration of the substrate-side insulating layer 50 can be changed as desired. For example, the first substrate-side insulating layer 51 may be omitted from the substrate-side insulating layer 50. In this case, for example, the substrate-side insulating layer 50 is configured with a stacked structure of a second substrate-side insulating layer 52.

[0174] In each embodiment, the shape of the first chip 14 in a plan view can be arbitrarily changed. In one example, the shape of the first chip 14 in a plan view can be square. As used in this disclosure, the term "on" includes the meanings "on" and "above," unless the context clearly indicates otherwise. Therefore, the expression "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer can be placed directly on the second layer in contact with the second layer, but in other embodiments, the first layer can be placed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first layer and the second layer.

[0175] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0176] <Supplementary Notes> The technical ideas that can be understood from the above-described embodiment and each modified example are described below. Note that, for the purpose of aiding understanding and not intending to limit the scope of the invention, the corresponding reference numerals in the embodiment are shown in parentheses for the configurations described in the Supplementary Notes. The reference numerals are shown as examples to aid understanding, and the components described with each reference numeral should not be limited to the components indicated by the reference numerals.

[0177] [Supplementary Note 1] An element insulating layer (40) having a surface (41) and a back surface (42) opposite to the surface (41), and one or more semiconductor resistance layers (20) provided in the element insulating layer (40), wherein the semiconductor resistance layer (20) includes: a resistor back surface (27) facing the back surface (42) in the thickness direction (Z-axis direction) of the element insulating layer (40); a resistor front surface (28) opposite to the resistor back surface (27); and a resistor side surface (29) connecting the resistor back surface (27) and the resistor front surface (28), wherein the element insulating layer (40) includes: a first insulating layer (71); a second insulating layer (72) stacked on the first insulating layer (71) and having a higher dielectric constant than the first insulating layer (71); and a third insulating layer (73) stacked on the second insulating layer (72) and having a lower dielectric constant than the second insulating layer (72), The semiconductor resistor layer (20) is stacked on the second insulating layer (72), and the resistor back surface (27) is provided in the third insulating layer (73) with the back surface in contact with the second insulating layer (72).

[0178] [Appendix 2] The semiconductor device according to Appendix 1, wherein a plurality of the semiconductor resistance layers (20) are provided and are aligned in the thickness direction (Z-axis direction) of the element insulating layer (40) and spaced apart in the direction (Y-axis direction) perpendicular to the thickness direction (Z-axis direction).

[0179] [Supplementary Note 3] The semiconductor device according to Supplementary Note 1 or 2, further comprising a wiring layer (80) provided on the back surface (42) side of the element insulating layer (40) relative to the semiconductor resistance layer (20), and electrically connected to the semiconductor resistance layer (20).

[0180] [Supplementary Note 4] The semiconductor device according to Supplementary Note 3, wherein the wiring layer (80) includes a wiring surface (82) facing the semiconductor resistance layer (20) in the thickness direction (Z-axis direction) of the element insulating layer (40), a wiring back surface (81) opposite the wiring surface (82), and a wiring side surface (83) connecting the wiring surface (82) and the wiring back surface (81), and the element insulating layer (40) includes a fourth insulating layer (61), and a fifth insulating layer (62) stacked on the fourth insulating layer (61) and having a higher dielectric constant than the fourth insulating layer (61), and the wiring layer (80) is stacked on the fifth insulating layer (62), and the wiring back surface (81) is in contact with the fifth insulating layer (62).

[0181] [Appendix 5] The semiconductor device according to Appendix 4, wherein the element insulating layer (40) includes a sixth insulating layer (63) provided between the fifth insulating layer (62) and the first insulating layer (71) and having a lower dielectric constant than the fifth insulating layer (62), and the wiring layer (80) is provided within the sixth insulating layer (63).

[0182] [Supplementary Note 6] The semiconductor device according to Supplementary Note 4 or 5, wherein the element insulating layer (40) includes a sixth insulating layer (63) provided between the fifth insulating layer (62) and the first insulating layer (71) and having a dielectric constant lower than that of the fifth insulating layer (62), the first insulating layer (71) is stacked on the sixth insulating layer (63), and the sixth insulating layer (63) has a dielectric constant lower than that of the first insulating layer (71).

[0183] [Supplementary Note 7] The semiconductor device according to Supplementary Note 6, wherein the first insulating layer (71) is disposed apart from the wiring layer (80) in the thickness direction (Z-axis direction) of the element insulating layer (40).

[0184] [Appendix 8] The semiconductor device according to any one of Appendices 4 to 7, wherein the first insulating layer (71) is stacked on the fifth insulating layer (62) and has a lower dielectric constant than the fifth insulating layer (62), and the wiring layer (80) is provided within the first insulating layer (71).

[0185] [Appendix 9] The semiconductor device according to any one of appendices 4 to 8, wherein the element insulating layer (40) includes a seventh insulating layer (52A) having a lower dielectric constant than the fourth insulating layer (61), and the fourth insulating layer (61) is stacked on the seventh insulating layer (52A).

[0186] [Supplementary Note 10] The semiconductor device according to any one of Supplementary Notes 1 to 9, wherein the element insulating layer (40) includes an eighth insulating layer (91) stacked on the third insulating layer (73) and having a higher dielectric constant than the third insulating layer (73), and a ninth insulating layer (92) stacked on the eighth insulating layer (91) and having a higher dielectric constant than the eighth insulating layer (91), and further includes electrode pads (P1 to P5) formed on the ninth insulating layer (92).

[0187] [Appendix 11] The semiconductor device according to any one of appendices 1 to 8, wherein the element insulating layer (40) is stacked on the third insulating layer (73) and includes a high dielectric constant insulating layer (92) having a higher dielectric constant than the third insulating layer (37), and further includes electrode pads (P1 to P5) formed on the high dielectric constant insulating layer (92).

[0188] [Appendix 12] The semiconductor device according to any one of appendices 3 to 9, further comprising a via (90) extending in the thickness direction (Z-axis direction) of the element insulating layer (40) and electrically connecting the semiconductor resistance layer (20) and the wiring layer (80).

[0189] [Supplementary Note 13] The semiconductor device according to any one of Supplementary Notes 3 to 9, wherein the semiconductor resistance layer (20) has a thickness thinner than that of the wiring layer (80).

[0190] [Appendix 14] The semiconductor device according to any one of appendices 1 to 13, comprising: a wiring layer (80) provided on the surface (41) of the element insulating layer (40) and electrically connected to the semiconductor resistance layer (20); and a passivation film (43) provided on the surface (41) of the element insulating layer (40) and covering the wiring layer (80) so as to expose a portion of the wiring layer (80).

[0191] [Supplementary Note 15] An element insulating layer (40), one or more semiconductor resistance layers (20) provided in the element insulating layer (40), and a wiring layer (80) electrically connected to the semiconductor resistance layer (20) in the element insulating layer (40) and arranged opposite the semiconductor resistance layer (20) in a thickness direction (Z-axis direction) of the element insulating layer (40), wherein the wiring layer (80) includes: a wiring surface (82) facing the semiconductor resistance layer (20) in the thickness direction (Z-axis direction) of the element insulating layer (40), a wiring back surface (81) opposite to the wiring surface (82), and a wiring side surface (83) connecting the wiring surface (82) and the wiring back surface (81), wherein the element insulating layer (40) includes: a fourth insulating layer (61), and a fifth insulating layer (62) stacked on the fourth insulating layer (61) and having a higher dielectric constant than the fourth insulating layer (61), a low-dielectric-constant insulating layer (63 / 71) stacked on the fifth insulating layer (62) and having a relative dielectric constant lower than that of the fifth insulating layer (62), wherein the wiring layer (80) is stacked on the fifth insulating layer (62) and is provided in the low-dielectric-constant insulating layer (63 / 71) with the wiring back surface (81) in contact with the fifth insulating layer (62).

[0192] [Appendix 16] The semiconductor device according to appendix 15, wherein the element insulating layer (40) further includes a sixth insulating layer (63) having a relative dielectric constant lower than that of the fifth insulating layer (62), and the sixth insulating layer (63) is the low dielectric constant insulating layer stacked on the fifth insulating layer (62).

[0193] [Supplementary Note 17] The semiconductor device according to Supplementary Note 15, wherein the element insulating layer (40) includes a first insulating layer (71) having a lower dielectric constant than the fifth insulating layer (62), and a second insulating layer (72) stacked on the first insulating layer (71) and having a higher dielectric constant than the first insulating layer (71), the semiconductor resistance layer (20) is stacked on the second insulating layer (72), and the first insulating layer (71) is the low dielectric constant insulating layer stacked on the fifth insulating layer (62).

[0194] [Appendix 18] The semiconductor device according to any one of Appendices 15 to 17, wherein the element insulating layer (40) includes a seventh insulating layer (52A) having a lower dielectric constant than the fourth insulating layer (61), and the fourth insulating layer (61) is stacked on the seventh insulating layer (52A).

[0195] [Supplementary Note 19] A semiconductor device (10) comprising: an element insulating layer (40) having a surface (41) and a back surface (42) opposite to the surface (41); one or more semiconductor resistance layers (20) provided in the element insulating layer (40); electrode pads (P1 to P5) provided on the surface (41) of the element insulating layer (40); and a passivation film (43) provided on the surface (41) of the element insulating layer (40) and covering the electrode pads (P1 to P5), wherein the element insulating layer (40) includes: an eighth insulating layer (91); and a ninth insulating layer (92) stacked on the eighth insulating layer (91) and having a higher dielectric constant than the eighth insulating layer (91), and the electrode pads (P1 to P5) are stacked on the ninth insulating layer (92) and are provided in the passivation film (43) in a state of contact with the ninth insulating layer (92).

[0196] [Supplementary Note 20] The semiconductor device according to Supplementary Note 19, comprising: one or more semiconductor resistance layers (20) provided in the element insulating layer (40); and a wiring layer (80) electrically connected to the semiconductor resistance layer (20) in the element insulating layer (40) and arranged opposite the semiconductor resistance layer (20) in the thickness direction (Z-axis direction) of the element insulating layer (40), wherein the electrode pads (P1 to P5) are electrically connected to the semiconductor resistance layer (20) via the wiring layer (80).

[0197] [Appendix 21] The semiconductor device according to appendix 19 or 20, wherein the element insulating layer (40) includes a third insulating layer (73) having a lower dielectric constant than the eighth insulating layer (91), and the eighth insulating layer (91) is stacked on the third insulating layer (73).

[0198] [Appendix 22] The semiconductor device according to any one of Appendices 1 to 4, further comprising a substrate (30), wherein the element insulating layer (40) includes a substrate-side insulating layer (50) provided on the substrate (30), and a surface-side insulating layer (100) stacked on the substrate-side insulating layer (50), wherein the surface-side insulating layer (100) includes the first insulating layer (71), the second insulating layer (72), and the third insulating layer (73).

[0199] [Supplementary Note 23] The semiconductor device according to Supplementary Note 4, further comprising a substrate (30), wherein the element insulating layer (40) includes a substrate-side insulating layer (50) provided on the substrate (30), and a surface-side insulating layer (100) stacked on the substrate-side insulating layer (50), wherein the surface-side insulating layer (100) includes the first insulating layer (71), the second insulating layer (72), the third insulating layer (73), the fourth insulating layer (74), and the fifth insulating layer (75).

[0200] [Appendix 24] The semiconductor device according to any one of Appendices 5 to 7, further comprising a substrate (30), wherein the element insulating layer (40) includes: a substrate-side insulating layer (50) provided on the substrate (30); a wiring-side insulating layer (60) stacked on the substrate-side insulating layer (50); and a resistor-side insulating layer (70) stacked on the wiring-side insulating layer (60), wherein the resistor-side insulating layer (70) includes the first insulating layer (71), the second insulating layer (72), and the third insulating layer (73), and the wiring-side insulating layer (60) includes the fourth insulating layer (61), the fifth insulating layer (62), and the sixth insulating layer (63).

[0201] [Appendix 25] The semiconductor device according to any one of Appendices 22 to 24, wherein the substrate-side insulating layer (50) includes a plurality of first substrate-side insulating layers (51) and a plurality of second substrate-side insulating layers (52), and the plurality of first substrate-side insulating layers (51) and the plurality of second substrate-side insulating layers (52) are alternately stacked one by one.

[0202] [Supplementary Note 26] The first substrate-side insulating layer (51) is formed of a material containing SiN, and the second substrate-side insulating layer (52) is formed of a material containing SiO ２26. The semiconductor device according to claim 25, wherein the semiconductor device is formed from a material comprising:

[0203] [Appendix 27] The semiconductor device according to any one of Appendices 3 to 9, further comprising a substrate (30), wherein the wiring layer (80) is disposed at a distance from the substrate (30) in the thickness direction (Z-axis direction) of the element insulating layer (40).

[0204] [Supplementary Note 28] The first insulating layer (71) is formed of a material containing SiON, the second insulating layer (72) is formed of a material containing SiN, and the third insulating layer (73) is formed of a material containing SiO ２ 15. The semiconductor device according to any one of claims 1 to 14, wherein the semiconductor device is formed from a material comprising:

[0205] [Supplementary Note 29] The semiconductor device according to Supplementary Note 4, wherein the fourth insulating layer (61) is formed of a material containing SiON, and the fifth insulating layer (62) is formed of a material containing SiN.

[0206] [Supplementary Note 30] The fourth insulating layer (61) is formed of a material containing SiON, the fifth insulating layer (62) is formed of a material containing SiN, and the sixth insulating layer (63) is formed of a material containing SiO ２ The semiconductor device according to any one of appendices 5 to 7, wherein the semiconductor device is formed from a material comprising:

[0207] [Supplementary Note 31] The seventh insulating layer (52A) is made of SiO ２ 10. The semiconductor device according to claim 9, wherein the semiconductor device is formed from a material comprising:

[0208] [Supplementary Note 32] The semiconductor device according to Supplementary Note 10, wherein the eighth insulating layer (91) is made of a material containing SiON, and the ninth insulating layer (92) is made of a material containing SiN.

[0209] [Supplementary Note 33] The semiconductor device according to any one of Supplementary Notes 1 to 32, wherein the semiconductor resistance layer (20) contains CrSi.

[0210] [Supplementary Note 34] The semiconductor device according to any one of Supplementary Notes 1 to 14, wherein the first insulating layer (71) has a thickness thinner than the third insulating layer (73).

[0211] [Supplementary Note 35] The semiconductor device according to any one of Supplementary Notes 1 to 14, wherein the second insulating layer (72) has a thickness thinner than the first insulating layer (71).

[0212] [Supplementary Note 36] The semiconductor device according to any one of Supplementary Notes 4 to 8, wherein the fifth insulating layer (62) has a thickness thinner than that of the second insulating layer (72).

[0213] [Supplementary Note 37] The semiconductor device according to any one of Supplementary Notes 4 to 8, wherein the fourth insulating layer (61) has a thickness thinner than that of the second insulating layer (72).

[0214] [Supplementary Note 38] The semiconductor device according to any one of Supplementary Notes 3 to 9, wherein the thickness of the second insulating layer (72) is equal to or less than the thickness of the wiring layer (80).

[0215] [Supplementary Note 39] The semiconductor device according to any one of Supplementary Notes 1 to 14, wherein the second insulating layer (72) has a thickness greater than that of the semiconductor resistance layer (20).

[0216] [Supplementary Note 40] The semiconductor device according to Supplementary Note 6 or 7, wherein the sixth insulating layer (63) has a thickness greater than both the fourth insulating layer (61) and the fifth insulating layer (62).

[0217] [Supplementary Note 41] The semiconductor device according to Supplementary Note 6 or 7, wherein the sixth insulating layer (63) has a thickness greater than that of the first insulating layer (71).

[0218] DESCRIPTION OF SYMBOLS 10...Semiconductor device 11...Frame 11A...First die pad portion 11B...First lead portion 12...Die pad 13A to 13G...Leads 14...First chip 14A to 14D...First to fourth resistor circuits 15...Second chip 15A...Voltage detection circuit 16...Sealing resin 16A to 16D...First to fourth resin side surfaces 20...Semiconductor resistor layer 21 to 25...Wiring 27...Resistor back surface 28...Resistor front surface 29...Resistor side surface 30...Substrate 40...Element insulating layer 41...Element front surface 42...Element back surface 43...Passivation film 43X...Opening 50...Substrate side insulating layer 51...First substrate side insulating layer 52...Second substrate side insulating layer 52A...Seventh insulating layer 60...Wiring side insulating layer 61...Fourth insulating layer 62...Fifth insulating layer 63...Sixth insulating layer 70...Resistor-side insulating layer 71...First insulating layer 72...Second insulating layer 73...Third insulating layer 80...Wiring layer 81...Back surface of wiring 82...Front surface of wiring 83...Side surface of wiring 90...Via 91...Eighth insulating layer 92...Ninth insulating layer 93...Via 100...Front-side insulating layer 801, 802...Openings for vias W1 to W11...Wires P1 to P5...Terminals Q1 to Q9...Terminals

Claims

1. an element insulating layer having a front surface and a back surface opposite to the front surface; one or more semiconductor resistor layers provided within the element insulating layer; Equipped with The semiconductor resistance layer is a resistor back surface facing the back surface in a thickness direction of the element insulating layer; a resistor front surface opposite to the resistor back surface; A resistor side surface connecting the resistor back surface and the resistor front surface; Including, The element insulating layer is A first insulating layer; a second insulating layer laminated on the first insulating layer and having a higher dielectric constant than the first insulating layer; a third insulating layer laminated on the second insulating layer and having a relative dielectric constant lower than that of the second insulating layer; Including, The semiconductor resistor layer is laminated on the second insulating layer, and is provided in the third insulating layer with the resistor back surface in contact with the second insulating layer. Semiconductor device.

2. The semiconductor resistance layers are provided in a plurality, and are aligned in the thickness direction of the element insulating layer and spaced apart in a direction perpendicular to the thickness direction. The semiconductor device according to claim 1 .

3. a wiring layer provided on the back surface side of the element insulating layer with respect to the semiconductor resistance layer and electrically connected to the semiconductor resistance layer; The semiconductor device according to claim 1 .

4. The wiring layer is a wiring surface facing the semiconductor resistance layer in a thickness direction of the element insulating layer; a back surface of the wiring opposite to the front surface of the wiring; A wiring side surface connecting the wiring front surface and the wiring back surface; Including, The element insulating layer is A fourth insulating layer; a fifth insulating layer laminated on the fourth insulating layer and having a higher dielectric constant than the fourth insulating layer; Including, The wiring layer is laminated on the fifth insulating layer, and a back surface of the wiring is in contact with the fifth insulating layer. The semiconductor device according to claim 3 .

5. the element insulating layer includes a sixth insulating layer provided between the fifth insulating layer and the first insulating layer and having a relative dielectric constant lower than that of the fifth insulating layer; The wiring layer is provided in the sixth insulating layer. The semiconductor device according to claim 4.

6. the element insulating layer includes a sixth insulating layer provided between the fifth insulating layer and the first insulating layer and having a relative dielectric constant lower than that of the fifth insulating layer; the first insulating layer is laminated on the sixth insulating layer, The sixth insulating layer has a lower relative dielectric constant than the first insulating layer. The semiconductor device according to claim 4.

7. The first insulating layer is disposed apart from the wiring layer in a thickness direction of the element insulating layer. The semiconductor device according to claim 6.

8. the first insulating layer is stacked on the fifth insulating layer and has a lower dielectric constant than the fifth insulating layer; The wiring layer is provided in the first insulating layer. The semiconductor device according to claim 4.

9. the element insulating layer includes a seventh insulating layer having a relative dielectric constant lower than that of the fourth insulating layer, The fourth insulating layer is laminated on the seventh insulating layer. The semiconductor device according to claim 4.

10. The element insulating layer is an eighth insulating layer laminated on the third insulating layer and having a relative dielectric constant higher than that of the third insulating layer; a ninth insulating layer laminated on the eighth insulating layer and having a higher dielectric constant than the eighth insulating layer; Including, The insulating layer further includes an electrode pad formed on the ninth insulating layer. The semiconductor device according to claim 1 .

11. the element insulating layer is laminated on the third insulating layer and includes a high dielectric constant insulating layer having a relative dielectric constant higher than that of the third insulating layer; The high dielectric constant insulating layer further includes an electrode pad formed on the high dielectric constant insulating layer. The semiconductor device according to claim 1 .

12. a via extending in a thickness direction of the element insulating layer and electrically connecting the semiconductor resistance layer and the wiring layer; The semiconductor device according to claim 3 .

13. The semiconductor resistor layer has a thickness smaller than that of the wiring layer. The semiconductor device according to claim 3 .

14. a wiring layer provided on the surface of the element insulating layer and electrically connected to the semiconductor resistance layer; a passivation film provided on the surface of the element insulating layer and covering the wiring layer so as to expose a portion of the wiring layer. The semiconductor device according to any one of claims 1 to 13.

15. An element insulating layer; one or more semiconductor resistor layers provided within the element insulating layer; a wiring layer that is electrically connected to the semiconductor resistance layer in the element insulating layer and that is disposed opposite the semiconductor resistance layer in a thickness direction of the element insulating layer, The wiring layer is a wiring surface facing the semiconductor resistance layer in a thickness direction of the element insulating layer; a back surface of the wiring opposite to the front surface of the wiring; A wiring side surface connecting the wiring front surface and the wiring back surface; Including, The element insulating layer is A fourth insulating layer; a fifth insulating layer laminated on the fourth insulating layer and having a higher dielectric constant than the fourth insulating layer; a low dielectric constant insulating layer laminated on the fifth insulating layer and having a relative dielectric constant lower than that of the fifth insulating layer; The wiring layer is laminated on the fifth insulating layer, and is provided in the low dielectric constant insulating layer with the back surface of the wiring in contact with the fifth insulating layer. Semiconductor device.

16. the element insulating layer further includes a sixth insulating layer having a relative dielectric constant lower than that of the fifth insulating layer, The sixth insulating layer is the low dielectric constant insulating layer laminated on the fifth insulating layer. The semiconductor device according to claim 15.

17. The element insulating layer is a first insulating layer having a lower dielectric constant than the fifth insulating layer; a second insulating layer laminated on the first insulating layer and having a higher dielectric constant than the first insulating layer; Including, the semiconductor resistance layer is laminated on the second insulating layer, The first insulating layer is the low dielectric constant insulating layer laminated on the fifth insulating layer. The semiconductor device according to claim 15.