Radiation detector, integrated circuit, and radiation detection method

Abstract

This radiation detector comprises a plurality of pixel circuits which are provided corresponding to a plurality of pixels arranged along a predetermined direction, and which each have at least one detection system for reading carriers from the corresponding pixel. The at least one detection system has a counter that counts the number of radiation hits, a first register that holds first data that is a count value from the counter, a second register that holds second data, an adder that generates third data by adding the first data and the second data, and a third register that holds third data. In each of the plurality of pixel circuits, the second data is third data transferred from the third register of the corresponding pixel circuit for a pixel that is adjacent to the corresponding pixel of the pixel circuit.

Description

Radiation detector, integrated circuit, and radiation detection method

[0001] One aspect of the present disclosure relates to a radiation detector, an integrated circuit, and a method of detecting radiation.

[0002] There is known a radiation detector that includes a conversion unit including a plurality of pixels that generate carriers in response to incident radiation, the plurality of pixels being arranged in a predetermined direction, and a plurality of pixel circuits (integrated circuits) that are provided corresponding to the plurality of pixels and read out carriers from the corresponding pixels (see, for example, Patent Documents 1 to 3). In the radiation detector, the plurality of pixel circuits are connected to each other, and each pixel circuit reads out the number of radiation hits counted by a counter in the pixel circuit in the preceding stage and loads it into its own counter. Each pixel circuit then adds up the number of hits newly counted by its own counter to the number of hits loaded from the pixel circuit in the preceding stage. By sequentially performing this operation in each pixel circuit, a time delay integration (TDI) operation is realized.

[0003] Patent No. 4532743 Publication Special Publication No. 2009-540282 Publication Special Publication No. 2014-93616

[0004] However, in the radiation detectors described in Patent Documents 1 to 3, the period required for loading is a period during which the counter is inactive, and during this period the operation of counting the number of radiation hits is stopped. The longer the period during which the counter is inactive, the lower the radiation detection efficiency of the radiation detector.

[0005] An object of one aspect of the present disclosure is to provide a radiation detector, an integrated circuit, and a radiation detection method that improve the efficiency of radiation detection.

[0006] A radiation detector according to one aspect of the present disclosure is [1] "a radiation detector comprising: a conversion unit including a plurality of pixels that generate carriers in response to incident radiation, the plurality of pixels being arranged along a predetermined direction; and a plurality of pixel circuits provided corresponding to each of the plurality of pixels, each having at least one detection system that reads out carriers from the corresponding pixel, wherein the at least one detection system comprises: a comparator that compares a first signal based on an amount of the carriers with a threshold, and outputs a second signal when the first signal exceeds the threshold; a counter that counts the number of the second signals; a first register that holds first data that is a count value by the counter; a second register that holds second data; an adder that generates third data by adding the first data and the second data; and a third register that holds the third data, wherein the second data is the third data transferred from the third register of a pixel circuit provided corresponding to a pixel adjacent to the corresponding pixel in each of the plurality of pixel circuits."

[0007] In the radiation detector described in [1] above, each detection system of a plurality of pixel circuits includes a second register, an adder, and a third register. The second register holds, as second data, third data transferred from a third register in a pixel circuit provided corresponding to a pixel adjacent to the corresponding pixel. The adder generates third data by adding the first data and the second data, which are count values ​​generated by the counter. The third register holds the generated third data. This configuration eliminates the need to write (load) the count value of a preceding pixel circuit to the counter of each pixel circuit. This reduces the counter's non-operating period. This increases the proportion of the counter's operating period in each pixel circuit, i.e., the period during which radiation can be detected, to the total operating period of the pixel circuit. In addition, without the first register, the counter cannot be updated until the count value is stored in a subsequent register (e.g., the third register), causing the counter to stop operating during this period. By providing the first register, this inconvenience is eliminated, thereby further reducing the counter's non-operating period. As described above, according to the radiation detector described in [1] above, it is possible to provide a radiation detector with improved radiation detection efficiency by increasing the proportion of the period during which radiation can be detected in the entire operating period.

[0008] A radiation detector according to one aspect of the present disclosure may be [2] "the radiation detector described in [1] above, wherein the adder includes at least one register from among the first register, the second register, and the third register, and the at least one detection system has other registers from among the first register, the second register, and the third register, other than the at least one register, outside the adder."

[0009] A radiation detector according to one aspect of the present disclosure may be [3] "the radiation detector according to [1] or [2] above, wherein, in each of the plurality of pixel circuits, the area of ​​a first region occupied by an analog circuit including the comparator is larger than the area of ​​a second region occupied by a digital circuit including the counter, the first register, the second register, the adder, and the third register." In the first region, at least one of the size of the elements and the mounting spacing between the elements may be changed to reduce characteristic variations among the elements. According to the radiation detector according to [3], the area of ​​the first region is large, thereby improving the design flexibility of the analog circuit. In addition, according to the radiation detector according to [1] above, a function of transferring third data between pixel circuits (a TDI function in a digital circuit) can be configured relatively easily. Therefore, as in the radiation detector according to [3], the area of ​​the digital circuit can be reduced.

[0010] A radiation detector according to one aspect of the present disclosure may be [4] "the radiation detector according to the above [3], in which the area of ​​the first region occupies half or more of the entire area of ​​each of the plurality of pixel circuits." According to the radiation detector according to [4], the area of ​​the first region is large, which improves the degree of freedom in designing the analog circuit.

[0011] A radiation detector according to one aspect of the present disclosure may be [5] "the radiation detector according to any one of the above [1] to [4], wherein each of the plurality of pixel circuits has a plurality of detection systems as the at least one detection system, and the threshold value of the comparator of the plurality of detection systems is a different value for each of the detection systems." According to the radiation detector described in [5], it is possible to detect the energy level of radiation (amount of generated carriers) separately into a plurality of levels for each detection system.

[0012] A radiation detector according to one aspect of the present disclosure may be [6] "the radiation detector according to the above [5], in which the adders of the plurality of detection systems are individually provided for each of the detection systems." According to the radiation detector according to [6], detection processing can be performed in parallel in the plurality of detection systems. Therefore, the processing speed can be improved.

[0013] A radiation detector according to one aspect of the present disclosure may be [7] "the radiation detector according to the above [5], in which the adder of each of the plurality of detection systems is common to the plurality of detection systems." According to the radiation detector according to [7], the circuit area can be reduced because the adder is common.

[0014] A radiation detector according to one aspect of the present disclosure may be [8] "the radiation detector according to any one of [1] to [7] above, wherein the number of bits of the second register is equal to or greater than the sum of the number of bits of the first register and the number of bits representing the number of the plurality of pixel circuits in binary notation, and the number of bits of the adder is the same as the number of bits of the second register." According to the radiation detector described in [8], the number of bits of the adder matches the number of bits of the second register, so addition processing can be performed in parallel for each bit. This can improve processing speed.

[0015] A radiation detector according to one aspect of the present disclosure may be [9] "the radiation detector according to any one of [1] to [8] above, wherein the number of bits of the second register is equal to or greater than the sum of the number of bits of the first register and the number of bits representing the number of pixel circuits in binary notation, the number of bits of the adder is less than the number of bits of the second register, and the adder repeatedly performs an operation of adding some bits of the first data in the first register and some bits of the second data in the second register corresponding to the some bits, and outputting the result, until all bits of the first data are added." According to the radiation detector described in [9], the number of bits of the adder is less than the number of bits of the second register, so the circuit area can be reduced. Meanwhile, the adder repeatedly performs an operation of adding some bits of the first data and some bits of the second data, and outputting the result, until all bits of the first data are added. This allows addition processing even with a small number of bits.

[0016] A radiation detector according to one aspect of the present disclosure may be

[10] "the radiation detector according to the above [9], wherein the number of bits of the adder is 1 bit, and the adder has a fourth register for holding a carry signal." The radiation detector according to

[10] can reduce the circuit area and can perform carry calculations even if the number of bits of the adder is 1 bit.

[0017] A radiation detector according to one aspect of the present disclosure may be

[11] "the radiation detector according to any one of the above [1] to

[10] , wherein each of the plurality of pixel circuits further comprises a charge sharing countermeasure circuit that, when the carriers generated by the incidence of the radiation are distributed and read out to two or more of the pixel circuits, determines the pixel corresponding to the position on which the radiation is incident and corrects and evaluates the amount of carriers in that pixel, or ignores the incidence of the radiation." The radiation detector described in

[11] can suppress a decrease in energy resolution and image blurring caused by charge sharing.

[0018] A radiation detector according to one aspect of the present disclosure may be

[12] "the radiation detector according to any one of the above [1] to

[11] , wherein the plurality of pixel circuits further have a switching unit for switching between an operation of transferring the third data along the predetermined direction and an operation of transferring the third data along a direction opposite to the predetermined direction." According to the radiation detector described in

[12] , data can be transferred bidirectionally in the plurality of pixel circuits.

[0019] A radiation detector according to one aspect of the present disclosure may be

[13] "the radiation detector according to any one of [1] to

[12] above, wherein each of the plurality of pixel circuits further includes a shaper circuit provided in a stage preceding the comparator, and the shaper circuit reduces the time constant of the first signal." According to the radiation detector described in

[13] , the shaper circuit can increase the response speed of the comparator. This can further shorten the non-operating period of the counter.

[0020] A radiation detector according to one aspect of the present disclosure may be

[14] "the radiation detector according to any one of [1] to

[13] above, wherein the plurality of pixel circuits have a first pixel circuit region and a second pixel circuit region, and the first data is held in the first register at different times in the first pixel circuit region and the second pixel circuit region." According to the radiation detector described in

[14] , the risk of crosstalk can be reduced by the first pixel circuit region and the second pixel circuit region having different times at which the first data is held in the first register.

[0021] A radiation detector according to one aspect of the present disclosure may be

[15] "the radiation detector according to the above

[14] , further including: a power supply that supplies a power supply voltage to each of the plurality of pixel circuits via a power transmission line; and a control unit that transmits a hold signal to each of the plurality of pixel circuits via a signal line, wherein the second pixel circuit area is aligned with the first pixel circuit area along a predetermined direction, and a direction in which the power transmission line branches intersects with both the direction in which the signal line branches and the predetermined direction." According to the radiation detector described in

[15] , both the first pixel circuit area and the second pixel circuit area are present on each of the branched power transmission lines, thereby further reducing the risk of crosstalk.

[0022] An integrated circuit according to one aspect of the present disclosure is

[16] "an integrated circuit comprising: a plurality of pixels that generate carriers in response to incident radiation, the plurality of pixel circuits being provided corresponding to each of the plurality of pixels arranged along a predetermined direction, and each having at least one detection system that reads out carriers from the corresponding pixel, the at least one detection system including: a comparator that compares a first signal based on the amount of carriers with a threshold, and outputs a second signal when the first signal exceeds the threshold; a counter that counts the number of the second signals; a first register that holds first data that is a count value by the counter; a second register that holds second data; an adder that generates third data by adding the first data and the second data; and a third register that holds the third data, the second data being the third data transferred from the third register of the pixel circuit that is provided corresponding to the pixel adjacent to the corresponding pixel in each of the plurality of pixel circuits."

[0023] In the integrated circuit described in

[16] above, each detection system of a plurality of pixel circuits includes a second register, an adder, and a third register. The second register holds, as second data, third data transferred from a third register in a pixel circuit provided corresponding to a pixel adjacent to the corresponding pixel. The adder generates third data by adding the first data and the second data, which are count values ​​of the counter. The third register holds the generated third data. This configuration eliminates the need to write (load) the count value of a preceding pixel circuit to the counter of each pixel circuit. This reduces the counter non-operation period. This increases the proportion of the counter operation period of each pixel circuit, i.e., the period during which radiation can be detected, to the total operation period of the pixel circuit. In addition, without the first register, the counter value cannot be updated until the count value is stored in a subsequent register (e.g., the third register), causing the counter to stop operating during that period. By providing the first register, this inconvenience is eliminated, thereby further reducing the counter non-operation period. As described above, according to the integrated circuit described in

[16] above, by increasing the proportion of the period during which radiation can be detected in the total operating period, it is possible to provide an integrated circuit with improved radiation detection efficiency.

[0024] A radiation detection method according to one aspect of the present disclosure is

[17] "a radiation detection method comprising the steps of generating carriers in a plurality of pixels arranged along a predetermined direction in response to incident radiation; reading out carriers from corresponding pixels in a plurality of pixel circuits provided corresponding to each of the plurality of pixels; comparing a first signal based on the amount of carriers with a threshold and outputting a second signal when the first signal exceeds the threshold; counting the number of the second signals; holding first data, which is a count value obtained by the counting step, in a first register; holding second data in a second register; generating third data by adding the first data and the second data; and holding the third data in a third register, wherein the second data is the third data transferred from the third register of the pixel circuit provided corresponding to the pixel adjacent to the corresponding pixel in each of the plurality of pixel circuits."

[0025] The radiation detection method described in

[17] above includes the steps of: storing third data transferred from a third register in a pixel circuit provided corresponding to a pixel adjacent to the corresponding pixel as second data in the second register; generating third data by adding the first data, which is a count value obtained in the counting step, and the second data; and storing the generated third data in the third register. Here, the counting step is performed by a counter in each pixel circuit. This configuration eliminates the need to write (load) the count value in a preceding pixel circuit to the counter in each pixel circuit. This reduces the counter's non-operating period. This increases the proportion of the counter's operating period in each pixel circuit, i.e., the period during which radiation can be detected, to the total operating period of the pixel circuit. In addition, without the first register, the counter cannot be updated until the count value is stored in a subsequent register (e.g., the third register), causing the counter to stop operating during that period. By providing the first register, this inconvenience is eliminated, thereby further reducing the counter's non-operating period. As described above, according to the radiation detection method described in

[17] above, it is possible to provide a radiation detection method that improves the radiation detection efficiency by increasing the proportion of the period during which radiation can be detected in the entire operating period.

[0026] According to one aspect of the present disclosure, it is possible to provide a radiation detector, an integrated circuit, and a radiation detection method with improved radiation detection efficiency.

[0027] FIG. 1 is a diagram showing the configuration of a radiation detector according to a first embodiment. FIG. 2 is a plan view showing the arrangement of a plurality of pixel electrode units on the back surface of a conversion unit shown in FIG. 1. FIG. 3 is a diagram showing the configuration of each pixel circuit shown in FIG. 1. FIG. 4 is a circuit block diagram of each pixel circuit shown in FIG. 1. FIG. 5 is a diagram showing an example of charge sharing correction. FIG. 6 is an example circuit diagram of a counter shown in FIG. 4. FIG. 7 is a circuit diagram of a pixel circuit shown in FIG. 4. FIG. 8 is a diagram showing a detailed configuration of a pixel circuit shown in FIG. 7. FIG. 9 is a diagram for explaining a TDI operation in the pixel circuit shown in FIG. 7. FIG. 10 is a diagram for explaining a TDI operation in the pixel circuit shown in FIG. 7. FIG. 11 is a diagram for explaining a TDI operation in the pixel circuit shown in FIG. 7. FIG. 12 is a diagram for explaining a TDI operation in the pixel circuit shown in FIG. 7. FIG. 13 is an example circuit diagram of an adder shown in FIG. 7. FIG. 14 is an example circuit diagram of each register shown in FIG. 7. FIG. 15 is a diagram for explaining a radiation detection method using a radiation detector. FIG. 16 is a diagram showing a detailed configuration of a pixel circuit of a pixel circuit according to a second embodiment. FIG. 17 is an example circuit diagram of a selector circuit shown in FIG. 16. FIG. 18 is a diagram for explaining the configuration of input / output terminals of the adder shown in FIG. 16. FIG. 19 is a diagram for explaining a TDI operation in a pixel circuit according to the second embodiment. FIG. 20 is a diagram for explaining a TDI operation in a pixel circuit according to the second embodiment. FIG. 21 is a diagram for explaining a TDI operation in a pixel circuit according to the second embodiment. FIG. 22 is a circuit block diagram of a pixel circuit according to a modified example. FIG. 23 is a circuit diagram of the pixel circuit shown in FIG. 22. FIG. 24 is a circuit diagram of the pixel circuit shown in FIG. 22. FIG. 25 is a diagram for explaining the transfer direction of third data in a pixel circuit according to a modified example. FIG. 26 is a diagram for explaining the transfer direction of third data in a pixel circuit according to a modified example. FIG. 27 is a diagram for explaining the transfer direction of third data in a pixel circuit according to a modified example. FIG. 28 is a diagram for explaining the transfer direction of third data in a pixel circuit according to a modified example. FIG. 29 is a diagram for explaining the transfer direction of the third data in a pixel circuit according to a modified example.FIG. 30 is a diagram showing a detailed configuration of a pixel circuit of a pixel circuit according to a modified example. FIG. 31 is a diagram showing a detailed configuration of a pixel circuit of a pixel circuit according to a modified example. FIG. 32 is a diagram showing an example of a conversion unit, a power supply, and a control unit. (a) to (c) of FIG. 33 are diagrams for explaining a first hold signal, a counter operation signal, and a counter reset signal. FIG. 34 is a diagram showing an example of a plurality of pixel circuits divided into a first pixel circuit area and a second pixel circuit area. (a) to (d) of FIG. 35 are diagrams for explaining a first hold signal and a second hold signal. (a) and (b) of FIG. 36 are diagrams for explaining an example of the first pixel circuit area and the second pixel circuit area. (a) and (b) of FIG. 37 are diagrams for explaining an example of the first pixel circuit area and the second pixel circuit area. (a) and (b) of FIG. 38 are diagrams for explaining an example of the first pixel circuit area and the second pixel circuit area. (a) to (e) of FIG. 39 are diagrams for explaining a first hold signal, a second hold signal, and a third hold signal. FIG. 40 is a diagram for explaining an example of the first pixel circuit region, the second pixel circuit region, and the third pixel circuit region.

[0028] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In each drawing, the same or corresponding parts are denoted by the same reference numerals, and duplicated explanations will be omitted. [First Embodiment]

[0029] 1 is a diagram showing the configuration of a radiation detector 1 according to the first embodiment. As shown in Fig. 1, the radiation detector 1 includes a conversion unit 2, a plurality of pixel electrode units 3, and an integrated circuit 4.

[0030] The conversion section 2 is a bulk or layer-like member that absorbs radiation R to generate carriers. The radiation R is, for example, X-rays, neutron rays, alpha rays, beta rays, or gamma rays. The conversion section 2 is made of, for example, CdTe, CdZnTe, GaAs, InP, TlBr, or HgI. ２ , PbI ２, Si, Ge, and a-Se. The converter 2 extends along a plane intersecting the incident direction of the radiation R. The converter 2 has a front surface 2a and a back surface 2b facing opposite to each other. In one example, the front surface 2a is parallel to the back surface 2b. When viewed from the incident direction of the radiation R, the planar shape of the converter 2 is, for example, rectangular or square. When the planar shape of the converter 2 is rectangular, the length of the long side of the converter 2, or when the planar shape of the converter 2 is square, the length of one side of the converter 2, is, for example, within a range of 1 mm to 500 mm. A bias electrode 21 serving as a common electrode is provided on the front surface 2a so as to cover the entire surface 2a. The radiation R that has passed through the bias electrode 21 is incident on the front surface 2a.

[0031] The pixel electrode units 3 are conductive films provided on the rear surface 2b of the conversion unit 2. The pixel electrode units 3 are, for example, metal films. A high bias voltage is applied between the pixel electrode units 3 and the bias electrode 21 to deplete the conversion unit 2. FIG. 2 is a plan view showing the arrangement of the pixel electrode units 3 on the rear surface 2b of the conversion unit 2. The pixel electrode units 3 are arranged two-dimensionally with M rows and N columns when viewed from the incident direction of the radiation R. M and N are integers of 2 or greater. The two-dimensional arrangement is, for example, a matrix arrangement. Each of the M×N pixel electrode units 3 forms a pixel 2c with M rows and N columns in the conversion unit 2. In other words, the pixels 2c are arranged along the row and column directions in the conversion unit 2. Carriers are generated in the pixels 2c in response to the incident radiation R. Each pixel electrode unit 3 collects the carriers generated in the corresponding pixel 2c. The radiation detector 1 performs a TDI operation to integrate carriers generated in each pixel 2c for each column along a first direction A1 (a predetermined direction) which is the column direction. In the example of Fig. 2, the radiation detector 1 integrates carriers generated in pixel 2c-1, pixel 2c-2, pixel 2c-3, ..., pixel 2c-M.

[0032] Referring again to FIG. 1 , the integrated circuit 4 has a plurality of pixel circuits (M×N pixel circuits) 40 connected to the plurality of pixel electrode units 3, respectively. The integrated circuit 4 is realized by, for example, an ASIC (Application Specific Integrated Circuit) or the like. Each of the plurality of pixel circuits 40 is electrically connected to the plurality of pixel electrode units 3 by bump bonding B1. Each of the plurality of pixel circuits 40 is provided corresponding to a respective one of the plurality of pixels 2c. Each pixel circuit 40 reads carriers from the corresponding pixel 2c. Specifically, each pixel circuit 40 detects carriers collected in the corresponding pixel electrode unit 3. Each pixel circuit 40 counts the number of radiation hits based on the detected carriers.

[0033] FIG. 3 is a diagram showing the configuration of each pixel circuit 40 shown in FIG. 1. When viewed from the direction of incidence of radiation R, the planar shape of each pixel circuit 40 is, for example, a square. The length of one side is, for example, 50 μm to 250 μm. Each pixel circuit 40 is composed of a first region 41 occupied by an analog circuit and a second region 42 occupied by a digital circuit. The area of ​​the first region 41 is larger than the area of ​​the second region 42. The area of ​​the first region 41 is more than half of the entire area of ​​each pixel circuit 40. A pad P is provided in the center of each pixel circuit 40 so as to face each pixel electrode portion 3. The pad P is electrically connected to each pixel electrode portion 3 by bump bonding B1.

[0034] 4 is a circuit block diagram of each pixel circuit 40 shown in FIG. 1. The first region 41 has an amplifier 43, shaper circuits 44a and 44b, a charge sharing countermeasure circuit 45, and a comparator 46. The second region 42 has a counter 47, a pixel circuit 48, and an AND circuit AN. Each pixel circuit 40 has one detection system 49. One detection system 49 includes the comparator 46, the counter 47, the pixel circuit 48, and the AND circuit AN. One detection system 49 reads out carriers from the corresponding pixel 2c and counts the number of hits of radiation R.

[0035] The wiring connections of the circuit blocks of each pixel circuit 40 will be described. The input terminal of the amplifier 43 is connected to a pad P. The output terminal of the amplifier 43 is connected to the input terminal of a shaper circuit 44a and the input terminal of a shaper circuit 44b. The output terminal of the shaper circuit 44a is connected to a charge sharing countermeasure circuit 45. The charge sharing countermeasure circuit 45 is connected to one of the input terminals of an AND circuit AN. The output terminal of the shaper circuit 44b is connected to the inverting input terminal or the non-inverting input terminal of a comparator 46. The output terminal of the comparator 46 is connected to the other of the input terminals of the AND circuit AN. The output terminal of the AND circuit AN is connected to the input terminal of a counter 47. The output terminal of the counter 47 is connected to a pixel circuit 48.

[0036] The amplifier 43 outputs a first pulse signal PS1 (first signal) corresponding to the amount of carriers collected in each pixel electrode 3. The first pulse signal PS1 is, for example, a voltage pulse, and has a voltage value proportional to the amount of carriers. The first pulse signal PS1 has a predetermined time constant and requires a certain rise time to reach a voltage value proportional to the amount of carriers. The rise time is several tens of nanoseconds or less, for example, 10 nanoseconds. The shaper circuits 44a and 44b remove high-frequency and low-frequency components from the first pulse signal PS1. By reducing the time constant of the first pulse signal PS1, the fall time of the first pulse signal PS1 becomes steeper.

[0037] The shaper circuit 44b, the charge sharing countermeasure circuit 45, and the comparator 46 perform charge sharing correction. Fig. 5 is a diagram showing an overview of charge sharing correction. Fig. 5 shows the pixel electrode unit 3e corresponding to the pixel circuit 40 to which it belongs, and the eight pixel electrode units 3a, 3b, 3c, 3d, 3f, 3g, 3h, and 3i surrounding the pixel electrode unit 3e. The charge sharing correction includes energy correction c1 and position correction c2.

[0038] The energy correction c1 will be described using the pixel electrode unit 3e as a reference. First, a copy circuit (not shown) provided downstream of the amplifier 43 copies the first pulse signal PS1 to the pixels (pixel electrodes 3a, 3b, and 3d) adjacent to the pixel electrode unit 3e (copy process c11). Next, the shaper circuit 44b adds the first pulse signal PS1 for four pixels, including the copy signals from the adjacent pixels (pixel electrodes 3f, 3h, and 3i) and the pixel electrode unit 3e, to generate a corrected first pulse signal PS1 (summing process c12). As a result, the shaper circuit 44b corrects the carrier amount by adding the carrier amount collected in the pixel electrode unit 3e corresponding to the pixel circuit 40 to the sum of the carrier amounts collected in the three pixel electrodes 3f, 3h, and 3i adjacent to the pixel electrode unit 3e. The number of pixel electrodes to which the shaper circuit 44b adds the carrier amount is not limited to three. For example, the shaper circuit 44b may correct the amount of carriers by adding the sum of the amounts of carriers collected in the eight pixel electrode units 3a, 3b, 3c, 3d, 3f, 3g, 3h, and 3i adjacent to the pixel electrode unit 3e to the amount of carriers collected in the pixel electrode unit 3e corresponding to the pixel circuit 40 to which the shaper circuit 44b belongs. Alternatively, the shaper circuit 44b may correct the amount of carriers by adding the sum of the amounts of carriers collected in two pixel electrodes (for example, pixel electrode units 3f and 3h) to the amount of carriers collected in the pixel electrode unit 3e corresponding to the pixel circuit 40 to which the shaper circuit 44b belongs.

[0039] Next, the comparator 46 compares the corrected first pulse signal PS1 with a threshold value Th to discriminate the corrected first pulse signal PS1 (discriminate process c13). The corrected first pulse signal PS1 is input from the shaper circuit 44b to one of the inverting and non-inverting input terminals of the comparator 46, and the threshold value Th is input to the other. The comparator 46 compares the corrected first pulse signal PS1 with the threshold value Th. Specifically, if the value of the corrected first pulse signal PS1 is greater than the threshold value Th, the comparator 46 outputs a second pulse signal PS2 (second signal). The second pulse signal PS2 is, for example, a high-level voltage signal. This corresponds to "H" in the discriminate process c13 in FIG. 5. If the value of the first pulse signal PS1 is smaller than the threshold value Th, the comparator 46 does not output the second pulse signal PS2. This corresponds to "L" in the discriminate process c13 in Figure 5. One output of the second pulse signal PS2 can be said to represent one radiation hit. Next, an OR circuit (not shown) provided in the preceding stage of the counter 47 calculates the logical sum of the second pulse signal PS2 of the pixel electrode unit 3e and the second pulse signals PS2 of the pixels (pixel electrodes 3a, 3b, 3d) adjacent to the pixel electrode unit 3e (OR process c14). This OR process c14 is performed to eliminate ambiguity due to the combination of the charge share pattern and the addition set in the summing process c12.

[0040] The position correction c2 will be described using the pixel electrode unit 3e as a reference. When carriers generated by the incidence of radiation R are dispersed and collected among two or more pixel electrode units 3, the charge sharing countermeasure circuit 45 determines the pixel electrode unit 3 that collected the largest number of carriers as the pixel electrode unit 3 corresponding to the position where the radiation R was incident. Specifically, the charge sharing countermeasure circuit 45 copies the first pulse signal PS1 output from the shaper circuit 44a to the adjacent pixels (pixel electrodes 3a, 3b, 3c, 3d, 3f, 3g, 3h, and 3i) and simultaneously compares the copied signals received from the adjacent pixels (pixel electrodes 3a, 3b, 3c, 3d, 3f, 3g, 3h, and 3i) with the first pulse signal PS1 of the pixel electrode unit 3e (comparison process c21). The charge sharing countermeasure circuit 45 then determines whether the pixel electrode unit 3e corresponding to the pixel circuit 40 to which it belongs is the pixel electrode unit 3 corresponding to the position where the radiation R was incident. Specifically, the charge sharing countermeasure circuit 45 determines whether the magnitude of the first pulse signal PS1 of the pixel electrode unit 3e is greater than those of all adjacent pixels (election process c22). If it is determined that the magnitude of the first pulse signal PS1 of the pixel electrode unit 3e is greater than those of all adjacent pixels, the third pulse signal PS3, which is an output signal from the charge sharing countermeasure circuit 45 of the pixel electrode unit 3e, becomes "H". The charge sharing countermeasure circuit 45 can be realized by an electronic circuit including, for example, a logic circuit.

[0041] After the energy correction c1 and the position correction c2, an AND circuit AN provided upstream of the counter 47 calculates the logical product of the ORed second pulse signal PS2 and the third pulse signal PS3 output from the charge sharing countermeasure circuit 45. If the third pulse signal PS3 is "H," the second pulse signal PS2 of the pixel electrode unit 3e becomes active (AND process c3) and is sent to the downstream counter 47. In other words, in the election process c22, if the charge sharing countermeasure circuit 45 determines that the pixel electrode unit 3e corresponding to the pixel circuit 40 to which it belongs is the pixel electrode unit 3 corresponding to the position where radiation R is incident, it enables the output of the comparator 46. On the other hand, if the charge sharing countermeasure circuit 45 determines that the pixel electrode unit 3e corresponding to the pixel circuit 40 to which it belongs is not the pixel electrode unit 3 corresponding to the position where radiation R is incident, it disables the output of the comparator 46. The above-described adding operation of the shaper circuit 44b and the charge sharing countermeasure circuit 45 can be omitted from the pixel circuit 40. In that case, the uncorrected first pulse signal PS1 is input from the shaper circuit 44b to one of the inverting input terminal and the non-inverting input terminal of the comparator 46.

[0042] The counter 47 counts the number of output second pulse signals PS2. In other words, the counter 47 counts the number of radiation hits. The counted value is output to the pixel circuit 48. The counter 47 is, for example, a 4-bit up-counter or down-counter, and in the example of FIG. 6, is configured using four stages of flip-flops F1 to F4. When the counter 47 is an up-counter, the output ( / Q) of the first-stage flip-flop F1 is connected to the input (CLK) of the second-stage flip-flop. Similarly, the output ( / Q) of the second-stage flip-flop F2 is connected to the input (CLK) of the third-stage flip-flop F3. The same is true for the third-stage flip-flop F3 and the fourth-stage flip-flop F4. The output ( / Q) of the first-stage flip-flop F1 switches at the falling edge of CLK. The output ( / Q) of the second-stage flip-flop F2 switches at the falling edge of Q0. The output ( / Q) of the third flip-flop F3 switches at the falling edge of Q1, and the output ( / Q) of the fourth flip-flop F4 switches at the falling edge of Q2.

[0043] FIG. 7 is a circuit diagram of the pixel circuit 48 shown in FIG. 4 . The pixel circuit 48 includes a first register 48 a, a second register 48 b, an adder 48 c, and a third register 48 d. The first register 48 a holds first data D1, which is the count value output from the counter 47. The first data D1 indicates the number of second pulse signals PS2 counted by the counter 47. The wiring between the counter 47 and the first register 48 a is, for example, parallel wiring including the same number of wires as the number of bits of the maximum count value of the counter 47. In this case, the first register 48 a simultaneously holds all bits of the first data D1 at any timing. The wiring between the counter 47 and the first register 48 a may also be serial wiring.

[0044] The second register 48b holds the second data D2. The adder 48c generates the third data D3 by adding the first data D1 and the second data D2. The third register 48d holds the generated third data D3. As a specific means for integrating carriers in the first direction A1 (predetermined direction) shown in FIG. 2 in the multiple pixel circuits 40, the multiple pixel circuits 40 transfer the third data D3 between the pixel circuits 40 corresponding to each pixel 2c. In other words, the TDI operation for integrating carriers generated in each pixel 2c in the first direction A1 is performed by transferring the third data D3 between the pixel circuits 40 corresponding to each pixel 2c. Referring back to FIG. 2, the pixel circuit 40 corresponding to pixel 2c-1 transfers the third data D3 to the pixel circuit 40 corresponding to pixel 2c-2, which is adjacent to pixel 2c-1. The pixel circuit 40 corresponding to pixel 2c-2 then holds the transferred third data D3 as second data D2. Thereafter, the pixel circuit 40 corresponding to pixel 2c-2 adds the first data D1 stored in the first register 48a of the pixel circuit 40 corresponding to pixel 2c-2 to the second data D2. The pixel circuit 40 corresponding to pixel 2c-2 then stores the added value as third data D3 and transfers the third data D3 to the pixel circuit 40 corresponding to pixel 2c-3 adjacent to pixel 2c-2. This operation is repeated up to the pixel circuit 40 corresponding to pixel 2c-M in the last row. Here, the second data D2 is the third data D3 transferred from the third register 48d of the pixel circuit 40 provided in each of the plurality of pixel circuits 40 corresponding to one of the pixels 2c adjacent to the corresponding pixel 2c in the first direction A1 (pixel 2c-1 when viewed from pixel 2c-2 in FIG. 2).

[0045] FIG. 8 is a diagram showing a detailed configuration of the pixel circuit 48 shown in FIG. ０ ~A Ｘ－１ indicates the number of bits in the first register 48a. The number of bits in the first register 48a is X bits, which is the maximum count value of the counter 47. ０ ~B Ｙ＋Ｘ－１ indicates a bit in the second register 48b. ０ ~S Ｙ＋Ｘ－１indicates the bits of the third register 48d. The number of bits of the second register 48b and the third register 48d is X+Y bits. Here, Y is the binary representation of M, which is the number of rows of the plurality of pixel circuits 40. For example, if the number of rows of M is 64, Y=6. X+Y bits is the maximum number of bits required to add the first data D1 of each pixel circuit 40 to the third data D3 (the second data D2 in each pixel circuit 40) transferred from the third register 48d. The number of bits of the adder 48c is X+Y bits, the same number as the number of bits of the second register 48b and the third register 48d. In this embodiment, the adder 48c performs addition processing in parallel for each bit. For example, the adder 48c adds the least significant bit A of the first register 48a to the least significant bit A of the first register 48a. ０ and the least significant bit B of the second register 48b ０ and are added at the least significant bit 0 of the adder 40c, and the sum is input to the least significant bit S of the third register 48d. ０ The adder 40c performs this addition process in parallel for all bits (least significant bit 0 to most significant bit Y+X-1).

[0046] 9 to 12 are diagrams for explaining the TDI operation of the pixel circuit 40 shown in FIG. 7. Because the adder 48c performs parallel addition processing on the first bit through the (X+Y)th bit, the adder 48c is represented as 0 to Y+X-1 in FIGS. 9 to 12. In FIGS. 9 to 12, among the multiple pixel circuits 40, pixel circuits 40-1, 40-2, and 40-3 are arranged in the column direction. The third data D3 of pixel circuit 40-1 is transferred to pixel circuit 40-2, and the third data D3 of pixel circuit 40-2 is transferred to pixel circuit 40-3. The timing for holding the data D1, D2, and D3 of the registers 48a, 48b, and 48d in each pixel circuit 40 can be set arbitrarily. When the data D1, D2, and D3 are held, the outputs of the registers 48a, 48b, and 48d are updated to the data D1, D2, and D3, respectively.

[0047] The operation of each pixel circuit 40 will now be described. This operation is performed simultaneously in pixel circuit 40-1, pixel circuit 40-2, and pixel circuit 40-3. First, as shown in FIG. 9, the first register 48a of each pixel circuit 40 holds the first data D1 and outputs it to the adder 48c. At this time, the second register 48b does not hold the second data D2. The output of the adder 48c is automatically updated when the first data D1 is input. Therefore, at this stage, an invalid value is output from the adder 48c.

[0048] 10, the second register 48b holds the third data D3 transferred from the pixel circuit 40 of the previous row (for example, pixel circuit 40-1 when viewed from pixel circuit 40-2) as the second data D2, and outputs the second data D2 to the adder 48c. The adder 48c outputs the third data D3 obtained by adding the first data D1 and the second data D2. At this time, the third register 48d has not yet held the third data D3. The second register 48b may hold the second data D2 before the first register 48a holds the first data D1.

[0049] Thereafter, as shown in FIG. 11, the third register 48d holds the third data D3 and outputs the third data D3 to the pixel circuit 40 in the next row (for example, the pixel circuit 40-3 when viewed from the pixel circuit 40-2).

[0050] If the first register 48a were not provided, the counter 47 would need to be stopped until the adder 48c adds the first data D1 to the second data D2 and the third data D3 is stored in the third register. Therefore, the first register 48a is provided to extend the counting period of the counter 47. As shown in FIG. 12, if the third register 48d were not provided, when the second register 48b stores the second data D2, the second data D2 would continue to be output as the third data D3 to all subsequent rows of pixel circuits 40. In this case, it would be difficult to add the first data D1 at the appropriate timing using the procedure described above. In other words, the output of the adder 48c changes when the second register 48b stores the second data D2. As a result, the operation of transferring the counted value of the counter 47 to the pixel circuits 40 in subsequent rows cannot be performed simultaneously in all pixel circuits 40, making TDI operation difficult. The same applies if the second register 48b is not provided. Therefore, in order to perform the TDI operation properly, a second register 48b and a third register 48d are provided.

[0051] FIG. 13 is an example circuit diagram of the adder 48c shown in FIG. 7. The adder 48c is a full adder that receives three input signals A, B, and C and performs binary addition. The adder 48c is a composite logic circuit composed of 28 transistors Tr. The output signals are the addition result SUM and a carry signal CARRY for the most significant digit. FIG. 14 is an example circuit diagram of each of the registers 48a, 48b, and 48d shown in FIG. 7. Each of the registers 48a, 48b, and 48d is a D-latch circuit including a clocked inverter In1 and an inverter In2. Each of the registers 48a, 48b, and 48d requires a total of 11 transistors. The input and output of each of the registers 48a, 48b, and 48d are composed of an input signal (D), a latch enable signal (LE), and an output (Q). When the latch enable signal (LE) is low, the previous output (Q) is held. When the latch enable signal (LE) is at a high level, the same logic as the input logic is output.

[0052] FIG. 15 is a diagram illustrating a radiation detection method using the radiation detector 1. The radiation detection method includes steps ST1 to ST12. In step ST1, carriers are generated in a plurality of pixels 2c arranged along a first direction A1 in response to incident radiation R. Next, in step ST2, a plurality of pixel circuits 40 provided corresponding to each of the plurality of pixels 2c read out carriers from the corresponding pixels 2c. Next, in step ST3, a first pulse signal PS1 based on the amount of carriers is compared with a threshold value Th, and a second pulse signal PS2 is output when the first pulse signal PS1 exceeds the threshold value Th. Step ST3 is performed by the comparator 46. Next, in step ST4, the number of second pulse signals PS2 is counted. Step ST4 is performed by the counter 47. Next, in step ST5, first data D1, which is the count value of the counter 47, is stored in the first register 48a. Next, in step ST6, second data D2 is stored in the second register 48b. Step ST6 may be performed before step ST5. Subsequently, in step ST7, the first data D1 and the second data D2 are added together. In step ST7, the first data D1 and the second data D2 are added together to generate third data D3. Step ST7 is performed by the adder 48c. Subsequently, in step ST8, the third data D3 is held in the third register 48d. Here, the second data D2 is the third data D3 transferred from the third register 48d of the pixel circuit 40 provided corresponding to the pixel 2c adjacent to the corresponding pixel 2c in each of the multiple pixel circuits 40. Subsequently, in step ST9, the third data D3 is transferred to the subsequent pixel circuit 40. Subsequently, in step ST10, it is determined whether steps ST1 to ST9 have been completed up to the pixel circuit 40 corresponding to the pixel 2c in the last row. If steps ST1 to ST9 have not been completed up to the pixel circuit 40 corresponding to the pixel 2c in the last row (step ST10; NO), the target pixel 2c is shifted to the next stage (step ST11), and steps ST1 to ST9 are performed again.On the other hand, when steps ST1 to ST9 have been completed up to the pixel circuit 40 corresponding to the pixel 2c in the last row (step ST10; YES), in step ST12, third data D3 is output to the outside of the radiation detector 1. With step ST12, the series of steps in the radiation detection method ends. [Functions and Effects]

[0053] In the radiation detector 1 and the integrated circuit 4, each detection system 49 of a plurality of pixel circuits 40 includes a second register 48b, an adder 48c, and a third register 48d. The second register 48b holds, as second data D2, third data D3 transferred from the third register 48d in the pixel circuit 40 provided corresponding to the pixel 2c adjacent to the corresponding pixel 2c. The adder 48c generates third data D3 by adding the first data D1, which is the count value of the counter 47, to the second data D2. The third register 48d holds the generated third data D3. This configuration eliminates the need to write (load) the count value of the preceding pixel circuit 40 to the counter 47 of each pixel circuit 40. This shortens the non-operating period of the counter 47. This increases the proportion of the operating period of the counter 47 in each pixel circuit 40, i.e., the period during which radiation R can be detected, to the total operating period of the pixel circuit 40. In addition, if the first register 48a is not provided, the count value cannot be updated until it is stored in a subsequent register (for example, the third register 48d), causing the inconvenience of the counter 47 stopping operation during that time. By providing the first register 48a, such an inconvenience does not occur, and the non-operating period of the counter 47 can be further shortened. As described above, the radiation detector 1 can provide a radiation detector 1 and an integrated circuit 4 with improved radiation R detection efficiency by increasing the proportion of the period during which radiation R can be detected in the entire operating period.

[0054] In the radiation detector 1, in each of the multiple pixel circuits 40, the area of ​​the first region 41 occupied by the analog circuit including the comparator 46 is larger than the area of ​​the second region 42 occupied by the digital circuit including the counter 47, the first register 48a, the second register 48b, the adder 48c, and the third register 48d. In the first region 41, at least one of the size of the elements and the mounting spacing between the elements may be changed to reduce characteristic variations among the elements. According to the radiation detector 1, the large area of ​​the first region 41 improves the design flexibility of the analog circuit. Additionally, the function of transferring the third data D3 between the pixel circuits 40 (the TDI function in the digital circuit) can be configured relatively easily. This allows the area of ​​the digital circuit to be reduced.

[0055] In the radiation detector 1, the area of ​​the first region 41 occupies more than half of the overall area of ​​each of the plurality of pixel circuits 40. As a result, the area of ​​the first region 41 is large, which improves the degree of freedom in designing the analog circuit.

[0056] In the radiation detector 1, the number of bits of the second register 48b is the sum X+Y of the number of bits X of the first register 48a and the number of bits Y representing the number of pixel circuits 40 in binary notation, and the number of bits of the adder 48c is the same as the number of bits X+Y of the second register 48b. As a result, since the number of bits X+Y of the adder 48c matches the number of bits X+Y of the second register 48b, addition processing can be performed in parallel for each bit, thereby improving the processing speed.

[0057] In the radiation detector 1, each of the plurality of pixel circuits 40 further includes a charge sharing countermeasure circuit 45 that, when carriers generated by the incidence of radiation R are distributed and read out to two or more pixel circuits 40, identifies the pixel 2c corresponding to the position on which radiation R is incident and corrects and evaluates the amount of carriers in that pixel 2c, or ignores the incidence of radiation R. This makes it possible to suppress the deterioration of energy resolution and blurring of images caused by charge sharing.

[0058] In the radiation detector 1, each of the plurality of pixel circuits 40 further includes shaper circuits 44a, 44b provided in front of the comparator 46, and the shaper circuits 44a, 44b reduce the time constant of the first pulse signal PS1. This enables the shaper circuits 44a, 44b to increase the response speed of the comparator 46, thereby further shortening the non-operating period of the counter 47.

[0059] The radiation detection method using the radiation detector 1 includes step ST6 of storing third data D3 transferred from the third register 48d in the pixel circuit 40 provided corresponding to the pixel 2c adjacent to the corresponding pixel 2c as second data D2 in the second register 48b, step ST7 of generating third data by adding the first data and the second data, which are the count values ​​obtained in step ST4 of counting, and step ST8 of storing the generated third data D3 in the third register 48d. Here, counting step ST4 is performed by the counter 47 of each pixel circuit 40. This configuration eliminates the need to write (load) the count value of the preceding pixel circuit 40 to the counter 47 of each pixel circuit 40. This reduces the non-operating period of the counter 47. This increases the proportion of the operating period of the counter 47 in each pixel circuit 40, i.e., the period during which radiation R can be detected, to the total operating period of the pixel circuit 40. In addition, if the first register 48a is not provided, the count value cannot be updated until it is stored in a subsequent register (for example, the third register 48d), and during that time the operation of the counter 47 stops, which is an inconvenience. By providing the first register 48a, such an inconvenience does not occur, and the non-operating period of the counter 47 can be further shortened. As described above, according to the radiation detection method using the radiation detector 1, it is possible to provide a radiation detection method with improved radiation detection efficiency by increasing the proportion of the period during which radiation can be detected in the total operating period. [Second Embodiment]

[0060] FIG. 16 is a diagram showing the detailed configuration of a pixel circuit 48A of a pixel circuit 40 according to the second embodiment. Only differences from the first embodiment will be described. The pixel circuit 48A has an adder 48e instead of the adder 48c of the first embodiment. The number of bits of the adder 48e is one bit, which is fewer than the number of bits Y of the second register 48b. The adder 48e includes a fourth register 48i for holding a carry signal. The pixel circuit 48A has a plurality of first selector circuits 48f, a plurality of second selector circuits 48g, a plurality of third selector circuits 48h, a plurality of fourth selector circuits 48k, and a plurality of fifth selector circuits 48j. Each of the plurality of first selector circuits 48f corresponds to a respective X bit of the first register 48a. Each of the plurality of second selector circuits 48g and each of the plurality of fifth selector circuits 48j corresponds to a respective X+Y bit of the second register 48b. Each of the plurality of third selector circuits 48h and each of the plurality of fourth selector circuits 48k corresponds to each of the X+Y bits of the third register 48d. The plurality of fourth selector circuits 48k are serially connected to the plurality of fifth selector circuits 48j of the pixel circuits 40 in the next row.

[0061] A bit select signal is input to the plurality of first selector circuits 48f, the plurality of second selector circuits 48g, the plurality of third selector circuits 48h, the plurality of fourth selector circuits 48k, and the plurality of fifth selector circuits 48j. The bit select signal is transmitted, for example, from an external control circuit. Each of the plurality of first selector circuits 48f always receives the first data D1 from the corresponding bit of the first register 48a. When the bit select signal is input, each of the plurality of first selector circuits 48f outputs a part of the bits of the first data D1 from the corresponding bit of the first register 48a to the adder 48e. Specifically, the plurality of first selector circuits 48f selects A ０ ~A Ｘ－１ The least significant bit A ０Each of the second selector circuits 48g always receives the second data D2 from the corresponding bit of the second register 48b. When a bit select signal is input, each of the second selector circuits 48g outputs a part of the bits of the second data D2 from the corresponding bit of the second register 48b to the adder 48e. Specifically, the second selector circuits 48g select the bits of the second data D2 from the corresponding bit of the second register 48b, ０ ~B Ｙ＋Ｘ－１ The least significant bit B ０ The second data D2 is output in order from the first data D1 to the second data D2.

[0062] The adder 48e adds the first data D1 and the second data D2 in order from the least significant bit. In other words, the adder 48e adds some bits of the first data D1 in the first register 48a and some bits of the second data D2 in the second register 48b corresponding to the added bits, and outputs the result, when all bits A of the first data D1 are added. ０ ~A Ｘ－１ This is repeated until the value of all bits A of the first data D1 is added. The carry generated at this time is held in the fourth register 48i and is reflected when the most significant digit is added. ０ ~A Ｘ－１ and B of the second data D2 ０ ~B Ｘ－１ After these are added, the adder 48e adds the carry signal or 0 and the remaining bit B of the second data D2. Ｘ ~B Ｙ＋Ｘ－１ The carry signal here is the most significant bit A of the first data D1. Ｘ－１ and bit B of second data D2 Ｘ－１ After the adder 48e adds the carry signal to the corresponding bit of the second data D2, the adder 48e adds 0 to the most significant bit B of the second data D2. Ｙ＋Ｘ－１ In the second embodiment, even if the data D1, D2, and D3 are held in the registers 48a, 48b, and 48d, the outputs of the registers 48a, 48b, and 48d are not updated and undefined values ​​are output unless the bit to be output is designated by the bit select signal.

[0063] The addition result from the adder 48e is input to each of the plurality of third selector circuits 48h. When a bit select signal is input to each of the plurality of third selector circuits 48h, the addition result is output to the corresponding bit of the third register 48d. As a result, each of the plurality of third registers 48d stores each bit of the third data D3, which is the addition result of the first data D1 and the second data D2. The third data D3 is input to each of the plurality of fourth selector circuits 48k from the corresponding bit of the third register 48d. When a bit select signal is input to each of the plurality of fourth selector circuits 48k, the fourth selector circuits 48k output the bit data of the third data D3 from the corresponding bit of the third register 48d to the pixel circuits 40 of the next row. Specifically, the plurality of fourth selector circuits 48k selects the bit S of the third register 48d. ０ ~S Ｙ＋Ｘ－１ The third data D3 stored in the least significant bit S ０ Output in order from

[0064] Each of the plurality of fifth selector circuits 48j sequentially receives the bits of the third data D3 from the plurality of fourth selector circuits 48k of the pixel circuits 40 in the previous row. A bit select signal is input to each of the plurality of fifth selector circuits 48j at the same timing as the bit select signal to the corresponding fourth selector circuit 48k. When the bit select signal is input, each of the plurality of fifth selector circuits 48j outputs some of the bits of the third data D3 to the corresponding bit of the second register 48b.

[0065] 17 is an example of a circuit diagram of the selector circuits 48f, 48g, 48h, 48k, and 48j shown in FIG. The selector circuits 48f, 48g, 48h, 48k, and 48j are composite logic circuits configured with four transistors Tr. A bit select signal is input to the Sel terminal. Some bits of each data D1, D2, and D3 are input to the In terminal from each register 48a, 48b, and 48d. When the bit select signal is input to the Sel terminal, the selector circuits 48f, 48g, 48h, 48k, and 48j output some bits of each data D1, D2, and D3 from the OUT terminal.

[0066] Here, the number of transistors required for the pixel circuit 48 of the first embodiment ( FIG. 8 ) is compared with the number of transistors required for the pixel circuit 48A of the second embodiment ( FIG. 16 ). To roughly calculate the number of transistors, let us assume that the X bits, which are the maximum count value of the counter 47, are 12 bits, and that the Y bits, which are the binary representation of M, the number of rows of the multiple pixel circuits 40, are 6 bits. The number of transistors required to configure the first register 48a is 132 (number of bits: 12 × number of transistors: 11) in both the pixel circuit 48 of the first embodiment and the pixel circuit 48A of the second embodiment. The number of transistors required to configure the second register 48b and the third register 48d is 198 (number of bits: 18 × number of transistors: 11) in both the pixel circuit 48 of the first embodiment and the pixel circuit 48A of the second embodiment. The number of transistors required to configure the adder 48c of the first embodiment is 504 (number of bits: 18 × number of transistors: 28), and the number of transistors required to configure the adder 48e of the second embodiment is 28 (number of bits: 1 × number of transistors: 28). In the pixel circuit 48A of the second embodiment, 192 transistors (total number of bits: 48 × number of transistors: 4) are required to configure the multiple first selector circuits 48f, the multiple second selector circuits 48g, and the multiple third selector circuits 48h. Furthermore, in the pixel circuit 48A of the second embodiment, 11 transistors (number of bits: 1 × number of transistors: 11) are required to configure the fourth register 48i included in the adder 48e. As a result, the total number of transistors required for the pixel circuit 48 of the first embodiment is 1,032, and the total number of transistors required for the pixel circuit 48A of the second embodiment is 759. The pixel circuit 48A of the second embodiment has about 30% less transistors than the pixel circuit 48 of the first embodiment.

[0067] FIG. 18 is a diagram illustrating the configuration of the input / output terminals of the adder 48e shown in FIG. 16. In the adder 48e, a NOR element N1 is mounted on an input terminal 48e-1 to which the first data D1 is input from the first register 48a. In the adder 48e, a NOR element N2 is mounted on an input terminal 48e-2 to which the second data D2 is input from the second register 48b. The NOR elements N1 and N2 have the function of switching between enable and disable. When an enable signal enb1 is input to the NOR element N1 (the NOR element N1 is enabled), the first data D1 is input to the input terminal 48e-1. On the other hand, when the enable signal enb1 is not input to the NOR element N1 (the NOR element N1 is disabled), '0' is input to the input terminal 48e-1. When the enable signal enb2 is input to the NOR element N2 (the NOR element N2 is enabled), the second data D2 is input to the input terminal 48e-2. On the other hand, when the enable signal enb2 is not input to the NOR element N2 (the NOR element N2 is disabled), '0' is input to the input terminal 48e-2. When both the NOR element N1 and the NOR element N2 are enabled, the third data D3 is output from the output terminal 48e-3 of the adder 48e. However, when only one of the NOR element N1 and the NOR element N2 is enabled, the enabled one of the first data D1 and the second data D2 is output from the output terminal 48e-3. As an alternative to the NOR element N1 and the NOR element N2, another logic circuit may be used that outputs the first data D1 only when the enable signal enb1 is input (input is 1).

[0068] 19 to 21 are diagrams illustrating the TDI operation in a pixel circuit 40 according to the second embodiment. The arrangement of pixel circuits 40-1, 40-2, and 40-3 and the transfer direction of third data D3 are the same as those in the first embodiment. As shown in FIG. 19, first, the first register 48a of each pixel circuit 40 holds the first data D1. At this time, the NOR element N1 is disabled. Therefore, an invalid value is output from the adder 48e. When the NOR element N1 is enabled, the output of the NOR element N1 changes depending on the output of the first register 48a, and an indefinite value is output from the adder 48e. However, if the indefinite value is not held in the third register 48d, there is no risk of the indefinite value being transferred to the subsequent pixel circuit 40, and this does not pose any particular problem.

[0069] 20, the least significant bit of each data D1, D2, D3 is output from each of the registers 48a, 48b, 48d. A specific operation will be described using the pixel circuit 40-1 as an example. When a bit select signal is input, the fourth selector circuit 48k of the pixel circuit 40-1 selects the least significant bit S of the third data D3 from the third register 48d of the pixel circuit 40-1 to the fifth selector circuit 48j of the pixel circuit 40-2. ０ When the bit select signal is input, the fifth selector circuit 48j of the pixel circuit 40-2 outputs the least significant bit S of the third data D3 to the second register 48b of the pixel circuit 40-2. ０ The second register 48b of the pixel circuit 40-2 outputs the least significant bit S of the transferred third data D3. ０ the least significant bit B of the second data D2 ０ Here, the bit select signal is also simultaneously transmitted to the selector circuits 48f and 48g. As a result, when the bit select signal is input, the first selector circuit 48f of the pixel circuit 40-1 transfers the least significant bit A of the first data D1 from the first register 48a of the pixel circuit 40-1 to the adder 48e. ０ When the bit select signal is input, the second selector circuit 48g of the pixel circuit 40-1 outputs the least significant bit B of the second data D2 from the second register 48b of the pixel circuit 40-1 to the adder 48e.０ At this time, the NOR elements N1 and N2 are set to be disabled so that the adder 48e does not operate.

[0070] 21, the NOR element N1 and the NOR element N2 are set to enable, so that the adder 48e adds the least significant bit A of the first data D1 to the least significant bit A of the first data D2. ０ and the least significant bit B of the second data D2 ０ By adding the least significant bit S of the third data D3, ０ The third selector circuit 48h receives the least significant bit S from the adder 48e. ０ When the bit select signal is input, the third selector circuit 48h selects the least significant bit S ０ The third register 48d outputs the least significant bit S of the third data D3. ０ The above process described with reference to FIGS. 19 and 20 holds the least significant bit A of each of the data D1, D2, and D3. ０ , B ０ , S ０ In order, the most significant bit A Ｘ－１ , B Ｙ＋Ｘ－１ , S Ｙ＋Ｘ－１ In this process, the adder 48e repeatedly adds some bits of the first data D1 and some bits of the second data D2 and outputs the result until all bits X of the first data D1 are added. ０ ~A Ｘ－１ and B of the second data D2 ０ ~B Ｘ－１ After these are added, the adder 48e adds the carry signal or 0 and the remaining bit B of the second data D2. Ｘ ~B Ｙ＋Ｘ－１ That is, after the adder 48e adds the carry signal to the corresponding bit of the second data D2, the adder 48e performs the addition of 0 to the most significant bit B of the second data D2. Ｙ＋Ｘ－１ Do this until.

[0071] The pixel circuit 40 according to the second embodiment may also be used as a global shutter in addition to the TDI operation. In this case, the timing for storing the first data D1 in the first register 48a is the same for all pixel circuits 40. For example, when reading out the first data D1 from the pixel circuit 40-1, the NOR element N1 of the adder 48e in the pixel circuit 40-1 is enabled, while the NOR element N2 is disabled. Then, in each of the pixel circuits 40 from the pixel circuit 40-2 in the subsequent row to the pixel circuit 40 in the final row, the NOR element N1 of the adder 48e is disabled, while the NOR element N2 is enabled. As a result, the addition process is not performed in each of the pixel circuits 40 from the pixel circuit 40-2 to the pixel circuit 40 in the final row, and the first data D1 of the pixel circuit 40-1 is transferred sequentially to the pixel circuits 40 in the subsequent rows. Then, the first data D1 of the pixel circuit 40-1 is read out from the pixel circuit 40 in the final row. This operation is repeated from the pixel circuits 40 in the first row to the pixel circuits 40 in the last row. The pixel circuits 40 according to the second embodiment are utilized as a global shutter, thereby enabling the operation of reading out a two-dimensional image. Alternatively, the pixel circuits 40 according to the second embodiment may be utilized as a rolling shutter. In this case, for example, in the above-described global shutter operation, the timing at which the first data D1 is held in the first register 48a is shifted between the pixel circuits 40 by a delay circuit or the like. Specifically, the timing at which the first data D1 is held in the first register 48a in the pixel circuit 40-2 is delayed relative to the timing at which the first data D1 is held in the first register 48a in the pixel circuit 40-1. Similarly, the timing at which the first data D1 is held in the first register 48a in the pixel circuit 40-3 is delayed relative to the timing at which the first data D1 is held in the first register 48a in the pixel circuit 40-2. As a result, the timing at which the first data D1 is read from each pixel circuit 40 gradually shifts along the pixel array direction.

[0072] In the radiation detector 1, the number of bits of the second register 48b is the sum X+Y of the number of bits X of the first register 48a and the number of bits Y representing the number of pixel circuits 40 in binary notation. The number of bits of the adder 48e is smaller than the number of bits X+Y of the second register 48b. The adder 48e repeatedly adds and outputs a portion of the bits of the first data D1 in the first register 48a and a portion of the bits of the second data D2 in the second register 48b corresponding to the added portion of the bits, until all of the bits of the first data D1 are added. This allows the circuit area to be reduced. Meanwhile, the adder 48e repeatedly adds and outputs a portion of the bits of the first data D1 and a portion of the bits of the second data D2 until all of the bits of the first data D1 are added, thereby enabling addition processing even with a small number of bits.

[0073] In the radiation detector 1, the adder 48e has a bit number of 1, and the adder 48e has a fourth register 48i for holding a carry signal. This makes it possible to reduce the circuit area and perform carry calculations even if the adder 48e has a bit number of 1. [Modification]

[0074] The present disclosure is not limited to the above-described embodiments. Each pixel circuit 40 may have multiple detection systems. FIG. 22 is a circuit block diagram of a pixel circuit 40A according to a modified example. Only differences from the first and second embodiments will be described. Each pixel circuit 40A has a first detection system 49a and a second detection system 49b instead of the detection system 49 of the pixel circuit 40. The first detection system 49a includes a first comparator 46a instead of the comparator 46 of the detection system 49. The first detection system 49a includes a first AND circuit ANa instead of the AND circuit AN. The first detection system 49a includes a first counter 47a instead of the counter 47. The second detection system 49b includes a second comparator 46b instead of the comparator 46 of the detection system 49. The second detection system 49b includes a second AND circuit ANb instead of the AND circuit AN. The second detection system 49b includes a second counter 47b instead of the counter 47. The first detection system 49a and the second detection system 49b include common pixel circuits 48B and 48C instead of the pixel circuits 48 and 48A. The output terminal of the shaper circuit 44b is connected to one of the inverting and non-inverting input terminals of the first comparator 46a and one of the inverting and non-inverting input terminals of the second comparator 46b. The charge sharing countermeasure circuit 45 is connected to one of the input terminals of the first AND circuit ANa and one of the input terminals of the second AND circuit ANb. The output terminal of the first comparator 46a is connected to the other of the input terminals of the first AND circuit ANa. The output terminal of the second comparator 46b is connected to the other of the input terminals of the second AND circuit ANb. The output terminal of the first AND circuit ANa is connected to the input terminal of the first counter 47a. The output terminal of the second AND circuit ANb is connected to the input terminal of the second counter 47b. The output terminal of the first counter 47a and the output terminal of the second counter 47b are connected to common pixel circuits 48B and 48C. A first threshold value Th1 is input to the other of the inverting input terminal and the non-inverting input terminal of the first comparator 46a. A second threshold value Th2 is input to the other of the inverting input terminal and the non-inverting input terminal of the second comparator 46b. The second threshold value Th2 may be greater or smaller than the first threshold value Th1, as long as it is different from the first threshold value Th1.

[0075] 23 and 24 are circuit diagrams of the pixel circuits 48B and 48C shown in FIG. 22. FIG. 23 is a circuit diagram of a pixel circuit 48B in which adders 48c-1 and 48c-2 of the first detection system 49a and the second detection system 49b are provided individually for each detection system. As shown in FIG. 23, the first detection system 49a includes a first register 48a-1, a second register 48b-1, an adder 48c-1, and a third register 48d-1 within the pixel circuit 48. The operation of each register 48a-1, 48b-1, and 48d-1 is similar to the operation of each register 48a, 48b, and 48d in the first or second embodiment. The operation of the adder 48c-1 is similar to the operation of the adder 48c in the first embodiment or the adder 48e in the second embodiment. The second detection system 49b includes a first register 48a-2, a second register 48b-2, an adder 48c-2, and a third register 48d-2 within the pixel circuit 48. The operation of the registers 48a-2, 48b-2, and 48d-2 and the adder 48c-2 is similar to the operation of the registers 48a-1, 48b-1, and 48d-1 and the adder 48c-1 of the first detection system 49a. The first detection system 49a counts the number of hits of radiation R based on the comparison result between the first threshold value Th1 and the first pulse signal PS1 using a first counter 47a. The first detection system 49a then sequentially transfers third data D3 (TDI operation) between the corresponding pixel 2c and the pixel circuit 40A provided corresponding to the pixel 2c adjacent to the corresponding pixel 2c in the first direction A1 shown in FIG. 2. The second detection system 49b counts the number of hits of radiation R based on the comparison result between the second threshold value Th2 and the first pulse signal PS1 using the second counter 47b. The second detection system 49b then sequentially transfers the third data D3 (TDI operation) between the pixel circuit 40A provided corresponding to the pixel 2c adjacent to the corresponding pixel 2c in the first direction A1. FIG. 24 is a circuit diagram of a pixel circuit 48C in which the adder 48c of the first detection system 49a and the adder 48c of the second detection system 49b are common to each other. The common adder 48c performs the functions of both the adder 48c-1 and the adder 48c-2 in FIG. 23. The common adder 48c does not simultaneously perform the addition process in the first detection system 49a and the addition process in the second detection system 49b.For example, the common adder 48c does not accept input from the second detection system 49b while performing addition processing in the first detection system 49a.

[0076] According to the radiation detector 1 including the pixel circuits 40A according to the above-described modification, the energy level of radiation R (the amount of generated carriers) can be detected separately for the first detection system 49a and the second detection system 49b. When the adders 48c-1 and 48c-2 for the first detection system 49a and the second detection system 49b are provided individually for each detection system, detection processing can be performed in parallel for the multiple detection systems, thereby improving processing speed. When the adder 48c for the first detection system 49a and the second detection system 49b is shared, the area of ​​each pixel circuit 40 can be reduced. Each pixel circuit 40A is required to have at least one detection system, and may have three or more detection systems.

[0077] In the first and second embodiments, the adders 48c and 48e and the registers 48a, 48b, and 48d are described as independent components. However, the adders 48c and 48e may perform the functions of at least one of the registers 48a, 48b, and 48d. For example, the adders 48c and 48e may have the function of the first register 48a, and may store the first data D1 output from the counter 47. In other words, the adders 48c and 48e may include at least one of the first register 48a that stores the first data D1, the second register 48b that stores the second data D2, and the third register 48d that stores the third data D3. In this case, the detection system 49 includes registers other than at least one of the first register 48a, the second register 48b, and the third register 48d, outside the adders 48c and 48e. Even in the above configuration, the radiation detector 1 and the integrated circuit 4 can exert the same functions and effects as those of the embodiment.

[0078] The conversion unit 2, the plurality of pixel electrode units 3, and the integrated circuit 4 may be formed on the same substrate (monolithic method). Alternatively, the conversion unit 2, the plurality of pixel electrode units 3, and the integrated circuit 4 may each be formed on a different substrate and then joined to each other by bump bonding or the like (hybrid method). The radiation detector 1 may be a direct conversion type that directly converts radiation R into an electrical signal (first pulse signal PS1), or may be an indirect conversion type that further includes a scintillator and performs conversion via the scintillator. The number of bits of the second register 48b and the third register 48d may be greater than X+Y bits.

[0079] FIGS. 25 to 29 are diagrams illustrating the transfer direction of the third data D3 in a pixel circuit 40 according to a modified example. As shown in FIG. 25, the radiation detector 1 may alternate between a first TDI operation and a second TDI operation. The first TDI operation is a TDI operation in which carriers generated in each pixel 2c are transferred to an adjacent pixel 2c along a first direction A1, column by column. The first TDI operation is, for example, an operation in which carriers are transferred from pixel 2c-2 to pixel 2c-3. The second TDI operation is a TDI operation in which carriers are transferred to an adjacent pixel 2c along a second direction A2, which is the opposite direction to the first direction. The second TDI operation is, for example, an operation in which carriers are transferred from pixel 2c-2 to pixel 2c-1. FIGS. 26 and 27 illustrate a pixel circuit 48 of a pixel circuit 40 according to the first embodiment, and FIGS. 28 and 29 illustrate a pixel circuit 48A of a pixel circuit 40 according to the second embodiment. In the first and second embodiments, the pixel circuits 40 may be capable of switching the transfer direction of the third data D3 so that the carrier transfer direction of the pixels 2c switches between the first direction A1 and the second direction A2. The transfer direction of the third data D3 may be switched, for example, by a plurality of changeover switches SW (switching units) equal in number to the number of bits X+Y of the second register 48b and the third register 48d. As shown in FIGS. 26 and 28 , the changeover switches SW may set the transfer direction of the third data D3 so that the carrier transfer direction of the pixels 2c is the first direction A1. Alternatively, as shown in FIGS. 27 and 29 , the changeover switches SW may set the transfer direction of the third data D3 so that the carrier transfer direction of the pixels 2c is the second direction A2. In other words, the multiple changeover switches SW switch between an operation of transferring the third data D3 so that the carrier transfer direction is the first direction A1 and an operation of transferring the third data D3 so that the carrier transfer direction is the second direction A2. The multiple changeover switches SW may switch the transfer direction between the first direction A1 and the second direction A2 at any timing, or may be performed after a predetermined time has elapsed. By providing multiple changeover switches SW, the third data D3 can be transferred in both directions in the multiple pixel circuits 40.26 to 29 show only the pixel circuit 40, this modification can also be applied to the pixel circuit 40A. In that case, the multiple changeover switches SW switch between an operation of transferring the third data D3 so that the carrier transfer direction is the first direction A1 and an operation of transferring the third data D3 so that the carrier transfer direction is the second direction A2 in each of the first detection system 49a and the second detection system 49b.

[0080] FIG. 30 is a diagram showing the detailed configuration of a pixel circuit 48D of a pixel circuit 40 according to a modified example. Only differences from the pixel circuit 48A according to the second embodiment will be described. As shown in FIG. 29 , in the pixel circuit 48D, the third register 48d and the second register 48b of the pixel circuit 40 in the next row may be directly connected in parallel without going through the multiple fourth selector circuits 48k and the multiple fifth selector circuits 48j. In this case, the third data D3 is output directly from each bit of the third register 48d to the corresponding bit of the second register 48b of the pixel circuit 40 in the next row.

[0081] FIG. 31 is a diagram showing a detailed configuration of a pixel circuit 48E of a pixel circuit 40 according to a modified example. Only the differences from the pixel circuit 48A according to the second embodiment will be described. As shown in FIG. 30, in the pixel circuit 48E, the number of bits of the adder 48e is X+1. The adder 48e performs addition processing of the first data D1 and the second data D2 in parallel from 0 bit to X-1 bit. The adder 48e transmits the addition results from 0 bit to X-1 bit to the corresponding bits of the third selector circuit 48h in parallel. All bits A of the first data D1 ０ ~A Ｘ－１ After the addition, the adder 48e adds the carry signal to the remaining bits of the second data D2 at the X+1th bit (Addx) of the adder 48e. The carry signal here refers to the most significant bit A of the first data D1. Ｘ－１ and bit B of second data D2 Ｘ－１ The carry signal is held in the fourth register 48i. The adder 48e adds the most significant bit A of the first data D1 to the most significant bit A of the first data D2. Ｘ－１ and bit B of second data D2 Ｘ－１After the addition of 0 and the second data D2, the most significant bit B of the second data D2 is added. Ｙ＋Ｘ－１ The pixel circuit 48E performs the X+1th bit (Addx) of the adder 48e. In the pixel circuit 48E, because each bit of the first register 48a and bits 0 to X-1 of the adder 48e are connected in parallel, the pixel circuit 48E does not need to include the selector circuit 48f. Similarly, the pixel circuit 48E does not need to include the selector circuit 48g for bits 0 to X-1 and the selector circuit 48h for bits 0 to X-1. The pixel circuit 48E that does not include the above-described selector circuit can achieve a higher processing speed than the pixel circuit 48A according to the second embodiment. The pixel circuit 48E that does not include the above-described selector circuit can achieve a smaller pixel circuit area than the pixel circuit 48 according to the first embodiment.

[0082] In the first embodiment, the second embodiment, and the above-described modified examples, the first data D1 may be held in the first register 48a simultaneously in all of the pixel circuits 40 constituting the plurality of pixel circuits 40. FIG. 32 is a diagram illustrating an example of a conversion unit 2, a power supply 6, and a control unit 5. FIG. 32 illustrates M×N pixel circuits 40. The power supply 6 supplies a power supply voltage PV to each pixel circuit 40 via a power transmission line 61. In the example of FIG. 32 , the power transmission line 61 branches into M rows along the column direction (first direction A1 or second direction A2). The power transmission line 61 branched into M rows is connected to each pixel circuit 40 along the row direction.

[0083] The control unit 5 transmits a first hold signal S1, a counter operation signal C_act, and a counter reset signal C_rst to each pixel circuit 40 via a signal line 51. In the example of FIG. 32 , the signal line 51 branches into N columns along the row direction (a third direction A3 or a fourth direction A4 that is perpendicular to the first direction A1 and the second direction A2). The signal lines 51 branching into the N columns are connected to each pixel circuit 40 along the column direction. The direction in which the power transmission lines 61 branch is the column direction, while the direction in which the signal lines 51 branch is the row direction. In other words, the direction in which the power transmission lines 61 branch intersects with the direction in which the signal lines 51 branch.

[0084] FIG. 33 is a diagram illustrating the first hold signal S1, the counter operation signal C_act, and the counter reset signal C_rst. In the graphs (a) to (c) of FIG. 33, the vertical axis represents voltage, and the horizontal axis represents time. While the counter operation signal C_act shown in (a) of FIG. 33 is at a high level, the counter 47 operates. As shown in (b) of FIG. 33, the counter operation signal C_act falls from a high level to a low level, and after an adjustment time TC has elapsed, the first hold signal S1 rises from a low level to a high level. While the counter operation signal C_act is at a low level, the counter 47 stops. In synchronization with the rising edge of the first hold signal S1, the first data D1 is simultaneously held in the first register 48a in all pixel circuits 40. Thereafter, the first hold signal S1 falls from a high level to a low level, and after an adjustment time TC has elapsed, the counter reset signal C_rst rises from a low level to a high level, resetting the counter 47. Then, the counter reset signal C_rst falls, and after the adjustment time TC has elapsed, the counter operation signal C_act rises from a low level to a high level, causing the counter 47 to operate again. Here, the reason for providing the adjustment time TC will be explained. Parasitic resistance and parasitic capacitance exist in the signal line 51, which may cause delays in signal transmission. In particular, the signal transmission delay may be greater for pixel circuits 40 that are farther from the control unit 5. When a delay in signal transmission occurs, for example, a period occurs in which both the counter operation signal C_act and the first hold signal S1 are high, and during this period, the first data D1 is held in the first register 48a while the counter 47 is operating. The adjustment time TC is adjusted so that the High level periods of each signal do not overlap. In the example of Fig. 33, the adjustment time TC from the falling edge of the counter operating signal C_act to the rising edge of the first hold signal S1, the adjustment time TC from the falling edge of the first hold signal S1 to the rising edge of the counter reset signal C_rst, and the adjustment time TC from the falling edge of the counter reset signal C_rst to the rising edge of the counter operating signal C_act are all the same, but the respective adjustment times may be different.

[0085] The first hold signal S1 is a pulse signal in which one pulse is output in a cycle T. Here, one pulse refers to a waveform in which the voltage value changes from a low level to a high level, remains at the high level for a predetermined period, and then falls from the high level to a low level. The length of one cycle T corresponds to one frame operation. One frame operation is, for example, the operation from when the plurality of pixel circuits 40 hold the first data D1 to when the third data D3 is output from the pixel circuit 40 corresponding to the pixel 2c-M (see FIG. 2) in the last row.

[0086] In the first embodiment, the second embodiment, and the above-described modified examples, the plurality of pixel circuits 40 may be divided into a first pixel circuit region and a second pixel circuit region. The timing at which the first data D1 is held in the first register 48a may differ between the first pixel circuit region and the second pixel circuit region. FIG. 34 is a diagram illustrating an example of a plurality of pixel circuits 40 divided into a first pixel circuit region 401 and a second pixel circuit region 402. As shown in FIG. 34 , the first pixel circuit region 401 and the second pixel circuit region 402 may be arranged in units of one column. The first pixel circuit region 401 and the second pixel circuit region 402 may be arranged alternately along the third direction A3 (row direction). The control unit 5 may output signals via a plurality of signal lines. In the example of FIG. 34 , the signal lines that output signals from the control unit 5 are signal line 51 and signal line 52. The control unit 5 transmits a first hold signal S1, a counter operation signal C_act, and a counter reset signal C_rst to the first pixel circuit region 401 of each pixel circuit 40 via a signal line 51. The control unit 5 transmits a second hold signal S2, a counter operation signal C_act, and a counter reset signal C_rst to the second pixel circuit region 402 of each pixel circuit 40 via a signal line 52. The control unit 5 may output signals via a single signal line. In this case, for example, the single signal line outputting signals from the control unit 5 may be branched into a line transmitting signals to the first pixel circuit region 401 and a line transmitting signals to the second pixel circuit region 402. The control unit 5 may switch between the line transmitting signals to the first pixel circuit region 401 and the line transmitting signals to the second pixel circuit region 402 using a switch circuit disposed between the control unit 5 and the first and second pixel circuit regions 401 and 402. For example, the control unit 5 may switch the switch of the switch circuit depending on the timing of transmitting the first holding signal S1 to the first pixel circuit area 401 and the timing of transmitting the second holding signal S2 to the second pixel circuit area 402.

[0087] FIG. 35 is a diagram for explaining the first hold signal S1 and the second hold signal S2. The operations of the counter actuation signal C_act and the counter reset signal C_rst are the same as those in FIG. 33. The control unit 5 transmits the first hold signal S1 to the first pixel circuit area 401 and transmits the second hold signal S2 to the second pixel circuit area 402. The first hold signal S1 and the second hold signal S2 are both pulse signals in which one pulse is output with a period T1. However, the first hold signal S1 and the second hold signal S2 have different phases. Specifically, as shown in FIG. 35(b), there is a time difference T2 between when the first hold signal S1 rises from a low level to a high level and when the second hold signal S2 rises from a low level to a high level as shown in FIG. 35(c). As a result, after a time difference T2 has elapsed from the timing at which the first data D1 is held in the first register 48a in the first pixel circuit region 401, the first data D1 is held in the first register 48a in the second pixel circuit region 402.

[0088] 36 to 38 are diagrams illustrating other examples of the first pixel circuit region 401 and the second pixel circuit region 402. FIGS. 36 to 38 show M×N pixel circuits 40. As shown in FIG. 36, each of the first pixel circuit region 401 and the second pixel circuit region 402 may be set up in units of multiple columns. As shown in (a) of FIG. 36, the first pixel circuit region 401 and the second pixel circuit region 402 may be set up alternately every few columns along the third direction A3. Alternatively, as shown in (b) of FIG. 36, the first pixel circuit region 401 and the second pixel circuit region 402 may be set up so as to divide the multiple pixel circuits 40 into two along the third direction A3.

[0089] 34 and 36 , the direction in which the power transmission line 61 branches is the column direction, whereas the direction in which the first pixel circuit region 401 and the second pixel circuit region 402 are divided is the row direction. In other words, the direction in which the power transmission line 61 branches intersects with the direction in which the first pixel circuit region 401 and the second pixel circuit region 402 are divided.

[0090] 33 , when the first data D1 is simultaneously stored in the first register 48 a in all pixel circuits 40, the simultaneous operation of a large number of digital circuits temporarily fluctuates the power supply voltage PV, potentially resulting in crosstalk between the pixel circuits 40. By dividing the pixel circuits 40 into a first pixel circuit region 401 and a second pixel circuit region 402 and differentiating the timing at which the first data D1 is stored in the first register 48 a in the first pixel circuit region 401 and the second pixel circuit region 402, the amount of fluctuation in the power supply voltage PV can be reduced, thereby reducing the risk of crosstalk. Furthermore, because the direction in which the power transmission line 61 branches intersects the direction in which the first pixel circuit region 401 and the second pixel circuit region 402 are divided, the first pixel circuit region 401 and the second pixel circuit region 402 coexist on the branched power transmission line 61, further reducing the risk of crosstalk.

[0091] 37(a), the first pixel circuit regions 401 and the second pixel circuit regions 402 may be arranged alternately pixel by pixel along the third direction A3 (row direction) and the first direction A1 (column direction). In other words, the first pixel circuit regions 401 and the second pixel circuit regions 402 may be arranged pixel by pixel in a checkerboard pattern.

[0092] As shown in (b) of FIG. 37 , the first pixel circuit regions 401 and the second pixel circuit regions 402 may be arranged in units of one row. The first pixel circuit regions 401 and the second pixel circuit regions 402 may be arranged alternately along the first direction A1 (column direction). As shown in (a) of FIG. 38 , the first pixel circuit regions 401 and the second pixel circuit regions 402 may be arranged alternately every few columns along the first direction A1. Alternatively, as shown in (b) of FIG. 38 , the first pixel circuit regions 401 and the second pixel circuit regions 402 may be arranged so as to divide the plurality of pixel circuits 40 into two along the first direction A1.

[0093] In the first embodiment, the second embodiment, and the above-described modified examples, the plurality of pixel circuits 40 may be divided into a first pixel circuit area, a second pixel circuit area, and a third pixel circuit area. The first data D1 may be held in the first register 48a at different times in the first pixel circuit area, the second pixel circuit area, and the third pixel circuit area. FIG. 39 is a diagram illustrating the first hold signal S1, the second hold signal S2, and the third hold signal S3. The operations of the counter actuation signal C_act and the counter reset signal C_rst are the same as those in FIG. 33. The control unit 5 transmits the first hold signal S1 to the first pixel circuit area, the second hold signal S2 to the second pixel circuit area, and the third hold signal S3 to the third pixel circuit area. Like the first hold signal S1 and the second hold signal S2, the third hold signal S3 is a pulse signal in which one pulse is output with a period T. However, the first hold signal S1, the second hold signal S2, and the third hold signal S3 have different phases. Specifically, as shown in (b) of Fig. 39, there is a time difference T2 between when the first hold signal S1 rises from a low level to a high level and when the second hold signal S2 rises from a low level to a high level, as shown in (c) of Fig. 39. There is a time difference T2 between when the second hold signal S2 rises from a low level to a high level and when the third hold signal S3 rises from a low level to a high level, as shown in (d) of Fig. 39. As a result, the first data D1 is held in the first register 48a in the second pixel circuit area after the time difference T2 has elapsed since the first data D1 was held in the first register 48a in the first pixel circuit area. Furthermore, after a time difference T2 has elapsed from the timing at which the first data D1 is held in the first register 48a in the second pixel circuit area, the first data D1 is held in the first register 48a in the third pixel circuit area.

[0094] 40 , columns each composed of a first pixel circuit region 401 and a second pixel circuit region 402 and columns each composed of a second pixel circuit region 402 and a third pixel circuit region 403 may be alternately arranged along the third direction A3 (row direction). In a column each composed of a first pixel circuit region 401 and a second pixel circuit region 402, the first pixel circuit region 401 and the second pixel circuit region 402 may be alternately arranged pixel by pixel along the first direction A1 (column direction). In a column each composed of a second pixel circuit region 402 and a third pixel circuit region 403, the second pixel circuit region 402 and the third pixel circuit region 403 may be alternately arranged pixel by pixel along the column direction.

[0095] In the above examples, the configurations have been described in which the pixel circuits 40 are divided into two pixel circuit regions, i.e., the first pixel circuit region 401 and the second pixel circuit region 402, and the configuration in which the pixel circuits 40 are divided into three pixel circuit regions, i.e., the first pixel circuit region 401, the second pixel circuit region 402, and the third pixel circuit region 403. The configuration in which the pixel circuits 40 are divided is not limited to this, and the pixel circuits 40 may be divided into four or more pixel circuit regions. In this case, the timing at which the first data D1 is held in the first register 48a differs from one another in the four or more pixel circuit regions, thereby further reducing the risk of crosstalk. [Note]

[0096] The radiation detector 1 described above includes the first register 48a that holds the first data D1, which is the count value of the counter 47, but it is also possible to omit the first register 48a. That is, the radiation detector comprises: a conversion unit 2 including a plurality of pixels 2c that generate carriers in response to incident radiation R, the plurality of pixels 2c being arranged in a predetermined direction; and a plurality of pixel circuits 40 provided corresponding to the plurality of pixels 2c, each having at least one detection system 49 that reads out carriers from the corresponding pixel 2c, wherein the at least one detection system 49 has: a comparator 46 that compares a first pulse signal PS1 based on the amount of carriers with a threshold value Th, and outputs a second pulse signal PS2 when the first pulse signal PS1 exceeds the threshold value Th; a counter 47 that counts the number of second pulse signals PS2; a second register 48b that holds second data D2; adders 48c, 48e that generate third data D3 by adding the first data D1 and the second data D2, which are the count values ​​of the counter 47; and a third register 48d that holds the third data D3. The second data D2 may be third data D3 transferred from the third register 48d of the pixel circuit 40 provided corresponding to the pixel 2c adjacent to the corresponding pixel 2c in each of the multiple pixel circuits 40. All of the above-described embodiments and modifications can be applied to a radiation detector in which the first register 48a is omitted. For example, this radiation detector may include the pixel circuit 48 according to the first embodiment, and the number of bits of the adder 48c may be X+Y bits, the same as the number of bits of the second register 48b and the third register 48d. Alternatively, this radiation detector may include the pixel circuit 48A according to the second embodiment, and the number of bits of the adder 48e may be 1 bit. This radiation detector may be switchable between a first TDI operation and a second TDI operation. The first TDI operation is a TDI operation in which carriers generated in each pixel 2c are transferred to an adjacent pixel 2c along the first direction A1, column by column. The second TDI operation is a TDI operation in which the radiation detector is moved to the adjacent pixel 2c along a second direction A2 that is the opposite direction to the first direction A1. In addition to the TDI operation, the radiation detector may also be used as a rolling shutter.In this radiation detector, each detection system 49 of a plurality of pixel circuits 40 includes a second register 48b that holds, as second data D2, third data D3 transferred from a third register 48d in a pixel circuit 40 provided corresponding to a pixel 2c adjacent to the corresponding pixel 2c, an adder 48c that generates third data D3 by adding the first data D1 and the second data D2, which are count values ​​by the counter 47, and a third register 48d that holds the generated third data D3. This configuration eliminates the need to write (load) the count value in the preceding pixel circuit 40 to the counter 47 of each pixel circuit 40. This reduces the non-operating period of the counter 47. This increases the proportion of the operating period of the counter 47 in each pixel circuit 40, i.e., the period during which radiation R can be detected, to the total operating period of that pixel circuit 40.

[0097] 1...Radiation detector, 2...Conversion unit, 2c...Pixel, 4...Integrated circuit, 40, 40-1, 40-2, 40-3, 40A...Pixel circuit, 41...First region, 42...Second region, 44a, 44b...Shaper circuit, 45...Charge sharing countermeasure circuit, 46...Comparator, 47...Counter, 48a, 48a-1, 48a-2...First register, 48b, 48b-1, 48b-2...Second register, 48c, 48c-1, 48c-2, 48e...adders, 48d, 48d-1, 48d-2...third register, 48i...fourth register, 49...detection system, 401...first pixel circuit area, 402...second pixel circuit area, 51...signal line, 61...power transmission line, D1...first data, D2...second data, D3...third data, PS1...first pulse signal, PS2...second pulse signal, R...radiation, Th...threshold value.

Claims

1. a conversion unit including a plurality of pixels that generate carriers in response to incident radiation, the plurality of pixels being arranged in a predetermined direction; a plurality of pixel circuits provided corresponding to the plurality of pixels, each pixel circuit having at least one detection system for reading out carriers from the corresponding pixel; The at least one detection system includes: a comparator that compares a first signal based on the amount of carriers with a threshold and outputs a second signal when the first signal exceeds the threshold; a counter that counts the number of the second signals; a first register for holding first data which is a count value of the counter; a second register for holding second data; an adder that generates third data by adding the first data and the second data; a third register for holding the third data; A radiation detector, wherein the second data is the third data transferred from the third register of the pixel circuit provided corresponding to the pixel adjacent to the corresponding pixel in each of the plurality of pixel circuits.

2. the adder includes at least one of the first register, the second register, and the third register; The radiation detector according to claim 1 , wherein the at least one detection system has registers other than the at least one register among the first register, the second register, and the third register, outside the adder.

3. Each of the plurality of pixel circuits further includes a shaper circuit provided in a stage preceding the comparator, The radiation detector according to claim 1 , wherein the shaper circuit reduces a time constant of the first signal.

4. Each of the plurality of pixel circuits further includes a shaper circuit provided in a stage preceding the comparator, The radiation detector according to claim 2 , wherein the shaper circuit reduces a time constant of the first signal.

5. 5. The radiation detector according to claim 1, wherein in each of the plurality of pixel circuits, an area of ​​a first region occupied by an analog circuit including the comparator is larger than an area of ​​a second region occupied by a digital circuit including the counter, the first register, the second register, the adder, and the third register.

6. The radiation detector according to claim 5 , wherein an area of ​​the first region occupies half or more of an entire area of ​​each of the plurality of pixel circuits.

7. each of the plurality of pixel circuits has a plurality of detection systems as the at least one detection system; 5. The radiation detector according to claim 1, wherein the thresholds of the comparators of the plurality of detection systems are different values ​​for each of the detection systems.

8. The radiation detector according to claim 7 , wherein the adders for the plurality of detection systems are provided individually for each of the detection systems.

9. The radiation detector according to claim 7 , wherein the adder for each of the plurality of detection systems is common to the plurality of detection systems.

10. the number of bits of the second register is equal to or greater than the sum of the number of bits of the first register and the number of bits representing the number of the pixel circuits in binary; 5. The radiation detector according to claim 1, wherein the number of bits of the adder is the same as the number of bits of the second register.

11. the number of bits of the second register is equal to or greater than the sum of the number of bits of the first register and the number of bits representing the number of the pixel circuits in binary; the number of bits of the adder is less than the number of bits of the second register; The adder is 5. The radiation detector according to claim 1, further comprising: a step of repeatedly performing an operation of adding together some bits of the first data in the first register and some bits of the second data in the second register corresponding to the some bits and outputting the result until all bits of the first data are added.

12. The number of bits of the adder is 1 bit, The radiation detector of claim 11 , wherein the adder comprises a fourth register for holding a carry signal.

13. Each of the plurality of pixel circuits 5. The radiation detector according to claim 1, further comprising a charge sharing countermeasure circuit that, when the carriers generated by the incidence of the radiation are distributed and read out to two or more of the pixel circuits, determines the pixel corresponding to the position where the radiation is incident and corrects and evaluates the amount of carriers in that pixel, or ignores the incidence of the radiation.

14. 5. The radiation detector according to claim 1, wherein the plurality of pixel circuits further include a switching unit for switching between an operation of transferring the third data along the predetermined direction and an operation of transferring the third data along a direction opposite to the predetermined direction.

15. the plurality of pixel circuits include a first pixel circuit region and a second pixel circuit region; 5. The radiation detector according to claim 1, wherein the first data is held in the first register at different timings in the first pixel circuit area and the second pixel circuit area.

16. a power supply that supplies a power supply voltage to each of the plurality of pixel circuits via a power transmission line; A control unit that transmits a hold signal to each of the plurality of pixel circuits via a signal line, the second pixel circuit region is aligned with the first pixel circuit region along a predetermined direction, The radiation detector according to claim 15 , wherein a direction in which the power transmission lines branch out intersects with a direction in which the signal lines branch out and the predetermined direction.

17. a plurality of pixels that generate carriers in response to incident radiation, the plurality of pixel circuits being provided corresponding to the plurality of pixels that are arranged in a predetermined direction, each pixel circuit having at least one detection system that reads out carriers from the corresponding pixel; The at least one detection system includes: a comparator that compares a first signal based on the amount of carriers with a threshold and outputs a second signal when the first signal exceeds the threshold; a counter that counts the number of the second signals; a first register for holding first data which is a count value of the counter; a second register for holding second data; an adder that generates third data by adding the first data and the second data; a third register for holding the third data; an integrated circuit, wherein the second data is the third data transferred from the third register of the pixel circuit provided corresponding to the pixel adjacent to the corresponding pixel in each of the plurality of pixel circuits.

18. generating carriers in response to incident radiation in a plurality of pixels arranged along a predetermined direction; reading out carriers from the corresponding pixels in a plurality of pixel circuits provided corresponding to the plurality of pixels; comparing a first signal based on the amount of carriers with a threshold, and outputting a second signal when the first signal exceeds the threshold; counting the number of said second signals; storing first data, which is a count value obtained by the counting step, in a first register; storing second data in a second register; generating third data by adding the first data and the second data; storing the third data in a third register; a third register of a pixel circuit provided corresponding to a pixel adjacent to the corresponding pixel in each of the plurality of pixel circuits, the third data being the third data transferred from the third register of the pixel circuit provided corresponding to the pixel adjacent to the corresponding pixel in each of the plurality of pixel circuits.