Signal generation circuit

Abstract

An N tap resistor network circuit (11) is provided with a plurality of first resistors and a plurality of first taps, and generates a control voltage having one of a plurality of predetermined voltage values by selecting one among the plurality of first taps in response to an inputted digital control signal. An M tap resistor network circuit (12) is provided with a plurality of second resistors and a plurality of second taps, and generates a plurality of predetermined reference voltages from the plurality of second taps. A folding circuit (13, 14) generates an output signal having a signal level corresponding to a predetermined phase of a sine wave or a cosine wave on the basis of a difference between the control voltage and the plurality of reference voltages.

Description

signal generation circuit

[0001] The present disclosure relates to a signal generating circuit, a phase shifter, an array antenna device, and a wireless communication device.

[0002] In wireless communication systems beyond the fifth generation mobile communication system (Beyond 5G), the use of high frequency bands such as millimeter waves and terahertz waves is being considered to increase communication capacity. Furthermore, to increase communication capacity, the use of a phased array antenna device to focus a radio wave beam on a communication partner is being considered. The use of a phased array antenna device makes it possible to perform, for example, beamforming (directing a beam in a specific direction), beam steering (directing a beam at a communication partner), and beam tracking (continuously directing a beam at a communication partner that is moving at high speed).

[0003] To realize a phased array antenna device, a phase shifter capable of freely controlling the phase of a local signal is required. For example, Patent Document 1 discloses a vector sum type analog phase shifter used in communication devices and radar devices.

[0004] Japanese Patent Application Laid-Open No. 2003-133906

[0005] Japanese Patent Application Laid-Open No. 2006-129999 discloses a method for synthesizing output signals of four differential variable gain amplifiers by reading gain setting values ​​and bias voltage values ​​from a storage device. However, storing such gain setting values ​​and bias voltage values ​​and processing signals based on the gain setting values ​​and bias voltage values ​​increases the circuit size and power consumption. Therefore, there is a need for a method for shifting the phase of a signal with a smaller circuit size and power consumption than conventional methods.

[0006] The phase shifter may also be required to have a certain tolerance to process, voltage, and temperature variations (PVT variations), may be required to be digitally controllable, and may be required to have a linear control characteristic with respect to the control signal.

[0007] An object of the present disclosure is to provide a signal generation circuit that generates a signal that can be used to control a phase shifter, the signal generation circuit having a smaller circuit size and power consumption than conventional circuits, being tolerant to PVT fluctuations, being digitally controllable, and having linear control characteristics with respect to a control signal. Another object of the present disclosure is to provide a phase shifter, an array antenna device, and a wireless communication device that include such a signal generation circuit.

[0008] A signal generating circuit according to a first aspect of the present disclosure comprises: a first resistor network circuit including a plurality of first resistors and a plurality of first taps, and generating a control voltage having one of a plurality of predetermined voltage values ​​by selecting one of the plurality of first taps in response to an input digital control signal; a second resistor network circuit including a plurality of second resistors and a plurality of second taps, and generating a plurality of predetermined reference voltages from the plurality of second taps; and at least one folding circuit that generates an output signal having a signal level corresponding to a predetermined phase of a sine wave or a cosine wave based on the difference between the control voltage and the plurality of reference voltages.

[0009] According to a signal generation circuit of a second aspect of the present disclosure, in the signal generation circuit of the first aspect, the signal generation circuit includes: a first folding circuit that generates a first output signal having a signal level corresponding to a predetermined phase of a sine wave; and a second folding circuit that generates a second output signal having a signal level corresponding to a predetermined phase of a cosine wave.

[0010] According to a third aspect of the present disclosure, there is provided a signal generation circuit according to the second aspect, wherein the first folding circuit comprises: a first differential amplifier that compares the control voltage with a first reference voltage to generate a first differential output signal; a second differential amplifier that compares the control voltage with a second reference voltage that is higher than the first reference voltage to generate a second differential output signal; and a third differential amplifier that compares the control voltage with a third reference voltage that is higher than the second reference voltage to generate a third differential output signal; and the second folding circuit comprises: a fourth differential amplifier that compares the control voltage with a fourth reference voltage to generate a fourth differential output signal; a fifth differential amplifier that compares the control voltage with a fifth reference voltage that is higher than the fourth reference voltage to generate a fifth differential output signal; and a sixth differential amplifier that compares the control voltage with a sixth reference voltage that is higher than the fifth reference voltage to generate a sixth differential output signal; The first output signal is the sum of the first and third differential output signals and an inverted signal of the second differential output signal, and the second output signal is the sum of the fourth and sixth differential output signals and an inverted signal of the fifth differential output signal.

[0011] According to a fourth aspect of the present disclosure, in the signal generation circuit according to the third aspect, each of the first to sixth differential amplifiers includes a pair of bipolar transistors or a pair of field effect transistors.

[0012] According to a fifth aspect of the present disclosure, in the signal generation circuit according to any one of the first to fourth aspects, the first resistor network circuit further includes a first constant current source connected to the plurality of first resistors.

[0013] According to a sixth aspect of the present disclosure, in the signal generation circuit according to any one of the first to fifth aspects, the first resistor network circuit further includes a voltage dividing resistor connected to an output terminal of the first resistor network circuit.

[0014] According to a seventh aspect of the present disclosure, in the signal generation circuit according to the third aspect, the second resistor network circuit includes voltage dividing resistors that generate the first to sixth reference voltages from a power supply voltage.

[0015] According to the signal generation circuit of the eighth aspect of the present disclosure, in the signal generation circuit of the third aspect, the second resistor network circuit further includes a first voltage dividing resistor that generates the first to third reference voltages from a power supply voltage, and a second voltage dividing resistor that generates the fourth to sixth reference voltages from the power supply voltage.

[0016] According to a signal generation circuit according to a ninth aspect of the present disclosure, in the signal generation circuit according to the third aspect, the second resistor network circuit further includes a first voltage dividing resistor that generates the first to third reference voltages from a first power supply voltage, and a second voltage dividing resistor that generates the fourth to sixth reference voltages from a second power supply voltage.

[0017] According to a signal generation circuit according to a tenth aspect of the present disclosure, in the signal generation circuit according to any one of the first to ninth aspects, the second resistor network circuit further includes a second constant current source connected to the plurality of second resistors.

[0018] According to an eleventh aspect of the present disclosure, in the signal generation circuit according to the first aspect, the first and second resistor network circuits are connected to a common voltage source.

[0019] According to a signal generation circuit according to a twelfth aspect of the present disclosure, in the signal generation circuit according to any one of the first to eleventh aspects, the first and second resistors have the same temperature coefficient.

[0020] According to a thirteenth aspect of the present disclosure, in the signal generation circuit according to any one of the first to twelfth aspects, the first and second resistor network circuits are implemented on a single integrated circuit.

[0021] A phase shifter according to a fourteenth aspect of the present disclosure includes: a signal generating circuit according to one of the second to fourth and seventh to ninth aspects; a quadrature splitter that separates an input signal into an in-phase signal and a quadrature-phase signal; a first multiplier that multiplies the in-phase signal by a second output signal of the signal generating circuit to generate a first multiplied signal; a second multiplier that multiplies the quadrature-phase signal by the first output signal of the signal generating circuit to generate a second multiplied signal; and a combiner that combines the first and second multiplied signals together.

[0022] A phase shifter according to a fifteenth aspect of the present disclosure is the phase shifter according to the fourteenth aspect, further comprising a low-pass filter that reduces signal components having frequencies higher than a predetermined frequency in the first and second output signals of the signal generating circuit.

[0023] An array antenna apparatus according to a sixteenth aspect of the present disclosure includes: a plurality of antenna elements; a plurality of third mixers; and a plurality of phase shifters according to the fourteenth or fifteenth aspect.

[0024] A wireless communication device according to a seventeenth aspect of the present disclosure includes the array antenna device according to the sixteenth aspect and a communication circuit.

[0025] A signal generating circuit according to an eighteenth aspect of the present disclosure comprises: a first resistive network circuit including a plurality of first resistors and a plurality of first taps, and generating a control voltage having one of a plurality of predetermined voltage values ​​by selecting one of the plurality of first taps in response to an input digital control signal; a second resistive network circuit including a plurality of second resistors and a plurality of second taps, and generating a plurality of predetermined reference voltages from the plurality of second taps; at least one folding circuit that generates an output signal having a signal level corresponding to a predetermined phase of a sine wave or a cosine wave based on a difference between the control voltage and the plurality of reference voltages; and a first impedance conversion circuit provided between the first resistive network circuit and the folding circuit, wherein the first impedance conversion circuit has an input impedance higher than the impedance from the first resistive network circuit to the folding circuit and has an output impedance lower than the impedance from the folding circuit to the first resistive network circuit.

[0026] According to a nineteenth aspect of the present disclosure, in the signal generation circuit of the eighteenth aspect, the first impedance conversion circuit includes an emitter follower circuit, a source follower circuit, or a voltage follower circuit.

[0027] According to a signal generation circuit according to a twentieth aspect of the present disclosure, in the signal generation circuit according to the eighteenth aspect, the first impedance conversion circuit includes first and second buffer circuits connected in parallel to each other.

[0028] According to a signal generation circuit according to a twenty-first aspect of the present disclosure, in the signal generation circuit according to the eighteenth aspect, the first impedance conversion circuit includes a first buffer circuit and a second buffer circuit cascade-connected in a subsequent stage of the first buffer circuit.

[0029] According to a signal generation circuit according to a twenty-second aspect of the present disclosure, in the signal generation circuit according to the twenty-first aspect, the first impedance conversion circuit further includes a third buffer circuit connected in parallel to the second buffer circuit.

[0030] According to a signal generation circuit of a 23rd aspect of the present disclosure, in the signal generation circuit of the 18th aspect, the signal generation circuit further includes a second impedance conversion circuit provided between the second resistor network circuit and the folding circuit, and the second impedance conversion circuit has the same characteristics as the first impedance conversion circuit with respect to fluctuations in at least one of the manufacturing process, power supply voltage, and temperature.

[0031] According to a signal generation circuit according to a 24th aspect of the present disclosure, in the signal generation circuit according to one of the 18th to 23rd aspects, the signal generation circuit comprises: a first folding circuit that generates a first output signal having a signal level corresponding to a predetermined phase of a sine wave; and a second folding circuit that generates a second output signal having a signal level corresponding to a predetermined phase of a cosine wave.

[0032] According to a twenty-fifth aspect of the present disclosure, in the signal generation circuit according to one of the eighteenth to twenty-fourth aspects, the first and second resistors have the same temperature coefficient.

[0033] According to a 26th aspect of the present disclosure, in the signal generation circuit according to one of the 18th to 25th aspects, the first and second resistor network circuits are implemented on a single integrated circuit.

[0034] A phase shifter according to a 27th aspect of the present disclosure includes the signal generating circuit according to the 24th aspect; a quadrature splitter that separates an input signal into an in-phase signal and a quadrature-phase signal; a first multiplier that multiplies the in-phase signal by a second output signal of the signal generating circuit to generate a first multiplied signal; a second multiplier that multiplies the quadrature-phase signal by the first output signal of the signal generating circuit to generate a second multiplied signal; and a combiner that combines the first and second multiplied signals together.

[0035] An array antenna apparatus according to a twenty-eighth aspect of the present disclosure includes: a plurality of antenna elements; a plurality of mixers; and a plurality of phase shifters according to the twenty-seventh aspect.

[0036] A wireless communication device according to a twenty-ninth aspect of the present disclosure includes the array antenna device according to the twenty-eighth aspect and a communication circuit.

[0037] According to one aspect of the present disclosure, it is possible to provide a signal generation circuit that has a smaller circuit size and power consumption than conventional circuits, is resistant to PVT fluctuations, is digitally controllable, and has linear control characteristics with respect to a control signal.

[0038] 1 is a block diagram showing the configuration of a phase shifter 1 including a signal generation circuit 10 according to a first embodiment. It is a circuit diagram showing the configuration of the signal generation circuit 10 of FIG. 1. It is a circuit diagram showing an example of the configuration of the differential amplifiers 31 to 33 and 41 to 43 of FIG. 2. It is a circuit diagram showing another example of the configuration of the differential amplifiers 31 to 33 and 41 to 43 of FIG. 2. It is a graph showing the operating characteristics of each of the differential amplifiers 31 to 33 and 41 to 43 of FIG. 2. It is a graph showing the operating characteristics when different reference voltages Vr2 and Vr4 are set for the pair of differential amplifiers 31 and 32 of FIG. 2. It is a graph explaining that a signal having a waveform similar to a sine wave can be generated by the pair of differential amplifiers 31 and 32 of FIG. 2. It is a diagram explaining the relationship between the control voltage Vc(k), the reference voltage Vr, and the output signals Vsin(k) and Vcos(k) of FIG. 1. It is a circuit diagram showing the configuration of an M-tap resistor network circuit 12A of a signal generation circuit according to a first modification of the first embodiment. 17 is a circuit diagram showing the configuration of an M-tap resistive network circuit 12B of a signal generation circuit according to a second modification of the first embodiment. FIG. 18 is a circuit diagram showing the configuration of an N-tap resistive network circuit 11C of a signal generation circuit according to a third modification of the first embodiment. FIG. 19 is a circuit diagram showing the configuration of an M-tap resistive network circuit 12C of a signal generation circuit according to a third modification of the first embodiment. FIG. 20 is a circuit diagram showing the configurations of an N-tap resistive network circuit 11D and an M-tap resistive network circuit 12D of a signal generation circuit according to a fourth modification of the first embodiment. FIG. 21 is a circuit diagram showing the configuration of an N-tap resistive network circuit 11E of a signal generation circuit according to a fifth modification of the first embodiment. FIG. 22 is a block diagram showing the configuration of a phase shifter 1F of a sixth modification of the first embodiment. FIG. 23 is a block diagram showing the configuration of a phase shifter 1G including a signal generation circuit 10G according to the second embodiment. FIG. 24 is a circuit diagram showing the configuration of the signal generation circuit 10G of FIG. 16. FIG. 25 is a diagram for explaining a delay that occurs in the signal generation circuit 10 according to the first embodiment. FIG. 26 is a circuit diagram showing the configuration of the impedance conversion circuit 15 of FIG. 16. FIG. 27 is a circuit diagram showing the configuration of an impedance conversion circuit 15A of a signal generation circuit according to a first modification of the second embodiment. 10A and 10B are circuit diagrams showing the configuration of an impedance conversion circuit 15B of a signal generation circuit according to a second modified example of the second embodiment, and the configuration of an impedance conversion circuit 15C of a signal generation circuit according to a third modified example of the second embodiment.25 is a circuit diagram showing a configuration of an impedance conversion circuit 15D of a signal generation circuit according to a fourth modified example of the second embodiment. FIG. 26 is a circuit diagram showing a configuration of an impedance conversion circuit 15E of a signal generation circuit according to a fifth modified example of the second embodiment. FIG. 27 is a block diagram showing a configuration of a phase shifter 1H including a signal generation circuit 10H according to a sixth modified example of the second embodiment. FIG. 28 is a circuit diagram showing a configuration of the signal generation circuit 10H of FIG. 25. FIG. 29 is a block diagram showing a configuration of a wireless communication device 100 according to a third embodiment.

[0039] Hereinafter, a signal generating circuit, a phase shifter, an array antenna device, and a wireless communication device according to embodiments of the present disclosure will be described with reference to the drawings. The same reference numerals denote the same components throughout the drawings.

[0040] 1 is a block diagram showing the configuration of a phase shifter 1 including a signal generation circuit 10 according to a first embodiment. The phase shifter 1 includes the signal generation circuit 10 and a quadrature modulation circuit 20.

[0041] The signal generating circuit 10 includes an N-tap resistor network circuit 11, an M-tap resistor network circuit 12, and folding circuits 13 and 14. The N-tap resistor network circuit 11 includes a plurality of resistors and a plurality of N taps, and generates a control voltage Vc(k) having one of N predetermined voltage values ​​by selecting one of the N taps in response to an input digital control signal k. The digital control signal k can take any value between 1 and N. The digital control signal k is expressed as log ２ The M-tap resistor network circuit 12 has a size of N bits. The M-tap resistor network circuit 12 includes a plurality of resistors and a plurality of M taps, and generates M predetermined reference voltages Vr1, ..., VrM from the M taps. The folding circuit 13 generates an output signal Vsin(k) having a signal level corresponding to a predetermined phase of a sine wave based on the difference between the control voltage Vc(k) and the plurality of reference voltages Vr1, ..., VrM. The folding circuit 14 generates an output signal Vcos(k) having a signal level corresponding to a predetermined phase of a cosine wave based on the difference between the control voltage Vc(k) and the plurality of reference voltages Vr1, ..., VrM.

[0042] The quadrature modulation circuit 20 includes a quadrature divider 21, multipliers 22 and 23, and a combiner 24. The quadrature divider 21 divides the input original frequency signal Vin into an I-component signal VinI and a Q-component signal VinQ. The multiplier 22 multiplies the I-component signal VinI by a signal Vcos(k) output from the folding circuit 14. The multiplier 23 multiplies the Q-component signal VinQ by a signal Vsin(k) output from the folding circuit 13. When two analog signals are input, each of the multipliers 22 and 23 outputs the product thereof. The multipliers 22 and 23 may be, for example, four-quadrant multipliers or variable gain amplifiers. The combiner 24 combines the output signals of the multipliers 22 and 23 and outputs a phase-shifted frequency signal Vout.

[0043] Here, the operating principle of the quadrature modulation circuit 20 will be explained. The original frequency signal Vin is expressed as Vin = sin(ωt) as a sine wave having an angular frequency ω. Furthermore, the following signals Vsin(k) and Vcos(k) are input from the signal generation circuit 10.

[0044]

[0045] The quadrature divider 21 generates two signals VinI=sin(ωt) and VinQ=cos(ωt) having a phase difference of 90 degrees. Next, multipliers 22 and 23 multiply the signals VinI and VinQ by the signals Vcos(k) and Vsin(k) input from the signal generating circuit 10, respectively. The combiner 24 combines the output signals of the multipliers 22 and 23 and outputs a phase-shifted frequency signal Vout. Therefore, the phase-shifted frequency signal Vout can be expressed as follows:

[0046]

[0047] Comparing the original frequency signal Vin and the phase-shifted frequency signal Vout, it can be seen that the phase shifter 1 generates an output signal having a phase shift proportional to the value of the digital control signal k.

[0048] The signal generating circuit 10 operates as a control circuit for the quadrature modulation circuit 20 and controls the amount of phase shift of the signal Vin by the quadrature modulation circuit 20 .

[0049] FIG. 2 is a circuit diagram showing the configuration of the signal generating circuit 10 of FIG.

[0050] The N-tap resistor network circuit 11 includes a plurality of resistors R10, R11, and R12, a plurality of N taps, and a switch SW. The plurality of resistors R10, R11, and R12 are connected in series between a terminal for a positive power supply voltage Vcc and a terminal for a negative power supply voltage Vee. FIG. 2 shows a case where N=128. Different predetermined voltage values ​​Vc1, ..., Vc128 are generated at the N taps between the resistors R10, R11, and R12. The plurality of resistors R10 have the same resistance value. In this case, the potential differences between the voltage values ​​Vc1, ..., Vc128 are equal. The switch SW selects one of the plurality of N taps in response to a digital control signal k and outputs the corresponding voltage value Vck as the control voltage Vc(k).

[0051] In this disclosure, for simplicity, the control voltage Vc(k) may also be simply referred to as the control voltage Vc.

[0052] The M-tap resistor network circuit 12 includes resistors R21 to R28 and a plurality of M taps. FIG. 2 shows the case where M=6. The resistors R21, R25 to R28 are connected in series between the positive power supply voltage Vcc terminal and the negative power supply voltage Vee terminal, and are a first voltage-dividing resistor that generates reference voltages Vr2, Vr4, and Vr6 from the power supply voltage. The reference voltages Vr2, Vr4, and Vr6 are generated at M / 2 taps between the resistors R25 to R28. The resistors R21 to R24, and R28 are connected in series between the positive power supply voltage Vcc terminal and the negative power supply voltage Vee terminal, and are a second voltage-dividing resistor that generates reference voltages Vr1, Vr3, and Vr5 from the power supply voltage. The reference voltages Vr1, Vr3, and Vr5 are generated at M / 2 taps between the resistors R21 to R24. The resistance values ​​of the resistors R24 and R25 are set equal to each other. The resistance values ​​of resistors R22, R23, R26, and R27 are set to be equal to each other and twice the resistance value of resistors R24 and R25. By setting the resistance values ​​of resistors R22 to R27 in this way, reference voltages Vr1 to Vr6 for simultaneously generating sine waves and cosine waves can be generated.

[0053] In this disclosure, for the sake of simplicity, the reference voltages Vr1 to Vr6 may also be simply referred to as reference voltages Vr.

[0054] The resistors R10, R11, and R12 of the N-tap resistor network circuit 11 and the resistors R21 to R28 of the M-tap resistor network circuit 12 may have the same temperature coefficient.

[0055] The folding circuit 13 includes differential amplifiers 31 to 33 and resistors R31 and R32. The differential amplifier 31 compares the control voltage Vc with a reference voltage Vr2 to generate a first differential output signal. The differential amplifier 32 compares the control voltage Vc with a reference voltage Vr4 that is higher than the reference voltage Vr2 to generate a second differential output signal. The differential amplifier 33 compares the control voltage Vc with a reference voltage Vr6 that is higher than the reference voltage Vr4 to generate a third differential output signal. The output terminals of the differential amplifiers 31 to 33 are connected to the terminal of the power supply voltage Vcc via the resistors R31 and R32. The first output signal Vsin(k) is the sum of the differential output signals of the differential amplifiers 31 and 33 and an inverted signal of the differential output signal of the differential amplifier 32.

[0056] The folding circuit 14 includes differential amplifiers 41 to 43 and resistors R41 and R42. The differential amplifier 41 compares the control voltage Vc with a reference voltage Vr1 to generate a fourth differential output signal. The differential amplifier 42 compares the control voltage Vc with a reference voltage Vr3 higher than the reference voltage Vr1 to generate a fifth differential output signal. The differential amplifier 43 compares the control voltage Vc with a reference voltage Vr5 higher than the reference voltage Vr3 to generate a sixth differential output signal. The output terminals of the differential amplifiers 41 to 43 are connected to the terminal of the power supply voltage Vcc via resistors R41 and R42. The second output signal Vcos(k) is the sum of the differential output signals of the differential amplifiers 41 and 43 and an inverted signal of the differential output signal of the differential amplifier 42.

[0057] The signal generating circuit 10 may be implemented using a plurality of discrete elements or one or more integrated circuits. Furthermore, among the components of the signal generating circuit 10, at least the N-tap resistor network circuit 11 and the M-tap resistor network circuit 12 may be implemented on a single integrated circuit.

[0058] 3 is a circuit diagram showing an example of the configuration of the differential amplifiers 31 to 33 and 41 to 43 shown in FIG. Each of the differential amplifiers 31 to 33 and 41 to 43 includes a pair of bipolar transistors Q1 and Q2, a constant current source 51, and resistors Ra to Rd. A control voltage Vc is applied to the base of the bipolar transistor Q1, and a reference voltage Vr (one of reference voltages Vr1 to Vr6) is applied to the base of the bipolar transistor Q2. An output current Ix flows through output terminals dout1 and dout2 in accordance with the potential difference between the control voltage Vc and the reference voltage Vr.

[0059] Fig. 4 is a circuit diagram showing another example of the configuration of the differential amplifiers 31 to 33 and 41 to 43 of Fig. 2. The folding circuits 13 and 14 may include differential amplifiers 31A to 33A and 41A to 43A of Fig. 4 instead of the differential amplifiers 31 to 33 and 41 to 43 of Fig. 3. Each of the differential amplifiers 31A to 33A and 41A to 43A includes a pair of field effect transistors Q1A and Q2A instead of the bipolar transistors Q1 and Q2 of Fig. 3.

[0060] The differential amplifier may have an emitter feedback resistor or may include a Darlington connection. Furthermore, the folding circuits 13 and 14 may include cascode-connected differential amplifiers or two-stage cascade-connected differential amplifiers.

[0061] 5 is a graph schematically illustrating the operating characteristics of each of the differential amplifiers 31 to 33 and 41 to 43 in FIG. The output current Ix of each differential amplifier 31 to 33 and 41 to 43 fluctuates approximately according to the transmission characteristic (solid line) of a hyperbolic sine function tanh(Vc) relative to the control voltage Vc or the transmission characteristic (dashed line) of its inverted signal. When the control voltage Vc is within a predetermined voltage range Vtran centered on the reference voltage Vr, the output current Ix fluctuates in response to the control voltage Vc. However, when the control voltage Vc is outside the voltage range Vtran, the output current Ix does not substantially fluctuate even when the control voltage Vc changes.

[0062] FIG. 6 is a graph schematically illustrating changes in the operating characteristics when different reference voltages Vr2 and Vr4 are set for the pair of differential amplifiers 31 and 32 in FIG. 2 . The upper, middle, and lower sections of FIG. 6 show the current Isum′, which is the sum of the output currents of the differential amplifiers 31 and 32, with respect to changes in the control voltage Vc. The upper section of FIG. 6 shows the case where reference voltages Vr2 and Vr4 (shown as reference voltages Vr2a and Vr4a) with a large difference are set, the lower section of FIG. 6 shows the case where reference voltages Vr2 and Vr4 (shown as reference voltages Vr2c and Vr4c) with a small difference are set, and the middle section of FIG. 6 shows the case where reference voltages Vr2 and Vr4 (shown as reference voltages Vr2b and Vr4b) with an intermediate difference between them are set. By combining the differential amplifiers 31 and 32, each having a hyperbolic sine function characteristic, the current Isum′ fluctuates with respect to the control voltage Vc, exhibiting a characteristic that combines two hyperbolic sine functions. In the upper and lower figures of Fig. 6, the current Isum' deviates significantly from a sine wave waveform. On the other hand, in the middle figure of Fig. 6, it can be seen that by appropriately setting the difference between the reference voltages Vr2 and Vr4, the current Isum' can be made to closely approximate a sine wave waveform.

[0063] 7 is a graph illustrating that a signal having a waveform similar to a sine wave can be generated by the pair of differential amplifiers 31 and 32 in FIG. 2. Equation f1 shows the transmission characteristic of the differential amplifier 31, and equation f2 shows the transmission characteristic of the differential amplifier 32. Equation f3 shows the combined transmission characteristic of the adjacent differential amplifiers 31 and 32. Equation f4 shows an ideal sine wave. k Ｂ denotes the Boltzmann constant, T denotes temperature, and q denotes elementary charge. The plots of equations f1 to f4 show that the combined transmission characteristics of the differential amplifiers 31 and 32 can be well approximated to a sine wave in the range of control voltage Vc=2.1 to 2.5.

[0064] Similarly, by appropriately setting the difference between reference voltages Vr4 and Vr6, the sum of the output currents of differential amplifiers 32 and 33 can also be made to closely approximate a sine wave waveform. Furthermore, by appropriately setting the difference between reference voltages Vr1 and Vr3, the sum of the output currents of differential amplifiers 41 and 42 can also be made to closely approximate a sine wave waveform. Furthermore, by appropriately setting the difference between reference voltages Vr3 and Vr5, the sum of the output currents of differential amplifiers 42 and 43 can also be made to closely approximate a sine wave waveform.

[0065] The folding circuits 13 and 14 are analog circuits whose output voltages repeatedly increase and decrease multiple times in response to an increase or decrease in the input voltage.

[0066] 8 is a diagram illustrating the relationship between the control voltage Vc(k), reference voltage Vr, and output signals Vsin(k) and Vcos(k) of FIG. 1. The upper part of FIG. 8 shows the voltage values ​​Vc1, ..., Vc128 that the control voltage Vc can take. The middle part of FIG. 8 shows the voltage values ​​Vr1 to Vr6 that the reference voltage Vr can take. The lower part of FIG. 8 shows how the magnitudes of the output signals Vsin(k) and Vcos(k) change depending on the control voltage Vc(k).

[0067] The total phase shift of the phase shifter 1 is ((M-1) / 4)2π radians. For example, when the control voltage Vc varies over the potential difference Vr5-Vr1 (or the potential difference Vr6-Vr2), a phase shift of 2π is brought about in the quadrature modulation circuit 20.

[0068] The upper and lower limits of the control voltage Vc(k) may be set to coincide with the upper and lower limits of the reference voltage Vr (Vc1=Vr1, Vc128=Vr6), respectively. In this case, when the k-th voltage value is selected in the N-tap resistor network circuit 11, the phase shift amount of the phase shifter 1 is expressed by the following equation:

[0069]

[0070] As described above, the parameter M determines the total phase shift amount of the phase shifter 1. If a wide phase shift amount is required, a large M is set when designing the phase shifter 1. Furthermore, the parameter N determines the resolution with which the digital control signal k can be set. If fine resolution is required, a large N is set when designing the phase shifter 1.

[0071] [Effects of the First Embodiment] As described above, the signal generating circuit 10 includes two folding circuits 13 and 14, and an N-tap resistor network circuit 11 and an M-tap resistor network circuit 12 that generate the control voltage Vc and reference voltage Vr used in the folding circuits 13 and 14, respectively. The folding circuits 13 and 14 generate output signals Vsin(k) and Vcos(k), which are sine or cosine waves with predetermined phases and have signal levels corresponding to phases that change in proportion to the value of the digital control signal k. The output signals Vsin(k) and Vcos(k) are applied as DC coefficients to two multipliers 22 and 23 of the quadrature modulation circuit 20. As a result, the phase of the original frequency signal input to the quadrature modulation circuit 20 is shifted by an amount proportional to the digital control signal k, and the signal is output as a phase-shifted frequency signal. According to this embodiment, it is possible to provide a signal generating circuit 10 and a phase shifter 1 that have a smaller circuit scale and power consumption than conventional ones, are resistant to PVT fluctuations, are digitally controllable, and have linear control characteristics with respect to a control signal.

[0072] The phase shifter 1 including the signal generating circuit 10 according to the embodiment has the following advantages compared to the case of referring to data stored in advance in a storage device (for example, using a look-up table) as in Patent Document 1.

[0073] The control circuit can be realized with significantly fewer elements than conventional circuits, allowing for easier and lower-cost circuit design. Furthermore, the chip size can be reduced, enabling a low-cost phase shifter. When the phase shifter 1 is placed in the front-end circuit of a wireless terminal device, both the signal generation circuit 10 and the quadrature modulation circuit 20 are manufactured as high-frequency integrated circuits, enabling a highly integrated analog circuit with a small number of components. However, incorporating digital circuits into high-frequency integrated circuits is technically difficult. To achieve large-scale MIMO (Multiple-Input and Multiple-Output), the number of antenna elements in the array antenna device must be increased. However, when using high-frequency bands such as millimeter waves, the number of antenna elements in the array antenna device cannot be increased due to power consumption considerations. Therefore, a method of transmitting and receiving signals while changing the beam pattern at short time intervals (time-division multiple access massive MIMO or virtual massive MIMO) is being considered. When adopting such a method, the phase shifter must be controlled at high speed, and the signal generation circuit must operate at high speed. Therefore, it is particularly useful in terms of power consumption if the signal generating circuit 10 can be realized using an analog circuit with a small number of components.

[0074] The N-tap resistor network circuit 11 and the M-tap resistor network circuit 12 can be implemented using multiple resistors with the same resistance value, or multiple resistors with a certain resistance value or twice that resistance value. Therefore, when integrated, manufacturing variations can be reduced. Furthermore, if the N-tap resistor network circuit 11 and the M-tap resistor network circuit 12 are implemented using the same type of resistors (e.g., resistors with the same temperature coefficient), the control voltage Vc and the reference voltage Vr shift in the same direction and by the same magnitude in response to fluctuations in power supply voltage and temperature. Because the control voltage Vc and the reference voltage Vr are input to the differential amplifiers 31-33 and 41-43, the high common-mode rejection ratios (CMRRs) of the differential amplifiers cancel out this voltage shift in the same direction.

[0075] High resistance to temperature fluctuations can be achieved by implementing the N-tap resistor network circuit 11 and the M-tap resistor network circuit 12 using resistors with the same temperature coefficient. Also, high resistance to fluctuations in the manufacturing process can be achieved by implementing the N-tap resistor network circuit 11 and the M-tap resistor network circuit 12 on a single integrated circuit.

[0076] As described above, this circuit has high tolerance to variations in the manufacturing process (P), power supply voltage (V), and temperature (T). By being resistant to PVT variations, it is possible to maintain the same performance in a variety of environments.

[0077] When an externally input analog control voltage is used to generate the control voltage Vc instead of the N-tap resistive network circuit 11 as in the present embodiment, the control voltage is generated by a mechanism separate from the M-tap resistive network circuit 12 within the phase shifter, which poses a problem of low resistance to PVT fluctuations. On the other hand, according to the present embodiment, the control voltage Vc and the reference voltage Vr are generated using the N-tap resistive network circuit 11 and the M-tap resistive network circuit 12, i.e., the same type of resistive network circuits, so that high resistance to PVT fluctuations is achieved. Furthermore, according to the present embodiment, the resistance to PVT fluctuations can be further improved by using, for example, the N-tap resistive network circuit 11 and the M-tap resistive network circuit 12 that are integrated with each other.

[0078] The N-tap resistor network circuit 11 and the M-tap resistor network circuit 12 can also be regarded as a digital-to-analog converter or a potentiometer. In addition, the N-tap resistor network circuit 11 and the M-tap resistor network circuit 12 can provide any phase shift amount by freely designing and setting the voltage step width, so they are also collectively called "Vernier resistor networks."

[0079] In conventional phase shifters, changing the phase generally involves a risk of changing the amplitude. To reduce such amplitude changes, it is necessary to digitally correct the amplitude using a variable gain amplifier provided upstream or downstream of the phase shifter. However, digital correction introduces delays. Furthermore, providing an arithmetic circuit for digital correction and / or a ROM for storing digital correction values ​​increases the circuit size, resulting in increased power consumption. In contrast, the signal generation circuit 10 according to the embodiment has linear control characteristics with respect to the control signal, so the amplitude of the output signal is constant and independent of the phase, eliminating the need for digital correction. Therefore, the signal generation circuit 10 according to the embodiment can operate at high speed without delays due to digital correction, and can operate with a smaller circuit size and power consumption than when digital correction is performed.

[0080] Conventional phase shifters that perform digital correction are typically implemented using circuits including several thousand transistors, have a power consumption of several dozen to several tens of mW, and have a transmission loss of less than 3 dB in a temperature range of −40° C. to 85° C. In contrast, the signal generation circuit 10 according to the embodiment is implemented using a circuit including, for example, approximately 30 transistors, has a power consumption of approximately 3 mW, and has a transmission loss of less than 1 dB in a temperature range of −40° C. to 85° C. Therefore, the signal generation circuit 10 according to the embodiment has a smaller circuit size and power consumption than conventional circuits, and is more resistant to temperature fluctuations than conventional circuits.

[0081] [Modification of First Embodiment] Figure 9 is a circuit diagram showing the configuration of an M-tap resistor network circuit 12A of a signal generation circuit according to a first modification of the first embodiment. The M-tap resistor network circuit 12A includes resistors R21A to R27A. The resistors R21A to R27A are voltage-dividing resistors connected in series between a terminal for a positive power supply voltage Vcc and a terminal for a negative power supply voltage Vee. Reference voltages Vr1 to Vr6 are generated at M taps between the resistors R21A to R27A. The M-tap resistor network circuit 12A of Figure 9 allows the use of resistors R22A to R26A having the same resistance value, thereby reducing relative manufacturing errors and simplifying circuit fabrication.

[0082] 10 is a circuit diagram showing the configuration of an M-tap resistor network circuit 12B of a signal generating circuit according to a second modification of the first embodiment. Resistors R21Ba, R22 to R24, and R28Ba are connected in series between the terminal for the positive power supply voltage Vcc1 and the terminal for the negative power supply voltage Vee1, and are voltage-dividing resistors that generate reference voltages Vr1, Vr3, and Vr5 from the power supply voltages. Resistors R21Bb, R25 to R27, and R28Bb are connected in series between the terminal for the positive power supply voltage Vcc2 and the terminal for the negative power supply voltage Vee2, and are voltage-dividing resistors that generate reference voltages Vr2, Vr4, and Vr6 from the power supply voltages. The power supply voltages Vcc1 and Vcc2 are set equal to each other, and the power supply voltages Vee1 and Vee2 are set equal to each other. Voltage-dividing resistor R21Ba. Increasing the mutual isolation between R22 to R24, R28Ba and voltage dividing resistors R21Bb, R25 to R27, R28Bb reduces disturbance caused by signals from the input terminals of folding circuits 13 and 14. The circuit of Figure 10 is effective when the input impedance of folding circuits 13 and 14 is not sufficiently high.

[0083] FIG. 11 is a circuit diagram showing the configuration of an N-tap resistor network circuit 11C of a signal generation circuit according to a third modification of the first embodiment. FIG. 12 is a circuit diagram showing the configuration of an M-tap resistor network circuit 12C of a signal generation circuit according to the third modification of the first embodiment. The N-tap resistor network circuit 11C includes a constant current source 61 instead of the resistor R11 of FIG. 2. The M-tap resistor network circuit 12C includes a constant current source 62 instead of the resistor R21 of FIG. 2. When the N-tap resistor network circuit 11C and the M-tap resistor network circuit 12C are integrated on a single chip, the constant current sources 61 and 62 can be fabricated with small manufacturing variations. Therefore, the configurations of FIGS. 11 and 12 are suitable for integration.

[0084] 13 is a circuit diagram showing the configurations of an N-tap resistive network circuit 11D and an M-tap resistive network circuit 12D of a signal generation circuit according to a fourth modification of the first embodiment. The M-tap resistive network circuit 12D does not include the resistors R21 and R28 shown in FIG. 2, and is further connected to the positive power supply voltage Vcc terminal and the negative power supply voltage Vee terminal via the resistors R11 and R12 of the N-tap resistive network circuit 11D. In other words, the N-tap resistive network circuit 11D and the M-tap resistive network circuit 12D are connected to a common voltage source. This has the effect of preventing a discrepancy between the power supply voltage of the N-tap resistive network circuit 11D and the power supply voltage of the M-tap resistive network circuit 12D.

[0085] 14 is a circuit diagram showing the configuration of an N-tap resistive network circuit 11E of a signal generation circuit according to a fifth modification of the first embodiment. The N-tap resistive network circuit 11E includes resistors R13 and R14 in addition to the components of the N-tap resistive network circuit 11 shown in FIG. 2. The resistors R13 and R14 are connected in series to a terminal for a positive power supply voltage Vcc and a terminal for a negative power supply voltage Vee, and a node between the resistors R13 and R14 is connected to the output terminal of the N-tap resistive network circuit 11E. By including the voltage-dividing resistors R13 and R14, the N-tap resistive network circuit 11E can reduce the impedance of the entire circuit and enable high-speed operation.

[0086] FIG. 15 is a block diagram showing the configuration of a phase shifter 1F according to a sixth modification of the first embodiment. In addition to the components of the phase shifter 1 shown in FIG. 1 , the phase shifter 1F includes low-pass filters (LPFs) 71 and 72 inserted between the signal generation circuit 10 and the quadrature modulation circuit 20. The low-pass filters 71 and 72 reduce signal components having frequencies higher than a predetermined frequency in the output signals Vsin(k) and Vcos(k) of the signal generation circuit 10. In a phased array antenna device using a phase shifter, high-speed control of the phase shifter can result in the generation of spurious frequencies (unwanted waves) in the output signal of the phased array antenna device. Inserting the low-pass filters 71 and 72 between the signal generation circuit 10 and the quadrature modulation circuit 20 enables smooth phase switching of the phase shifter 1F, thereby preventing spurious signals from occurring.

[0087] Second Embodiment In a second embodiment, a signal generating circuit and a phase shifter that can operate at a higher speed than in the first embodiment will be described.

[0088] Fig. 16 is a block diagram showing the configuration of a phase shifter 1G including a signal generation circuit 10G according to a second embodiment. Fig. 17 is a circuit diagram showing the configuration of the signal generation circuit 10G of Fig. 16. The phase shifter 1G includes a signal generation circuit 10G instead of the signal generation circuit 10 of Fig. 1. In addition to the components of the signal generation circuit 10 of Fig. 1, the signal generation circuit 10G includes an impedance conversion circuit 15 provided between the N-tap resistor network circuit 11 and the folding circuits 13 and 14. The impedance conversion circuit 15 has an input impedance higher than the impedance from the N-tap resistor network circuit 11 to the folding circuits 13 and 14, and an output impedance lower than the impedance from the folding circuits 13 and 14 to the N-tap resistor network circuit 11.

[0089] Here, the "impedance from the N-tap resistive network circuit 11 to the folding circuits 13, 14" refers to the impedance seen from the N-tap resistive network circuit 11 to the folding circuits 13, 14 when the N-tap resistive network circuit 11 and the folding circuits 13, 14 are directly connected to each other without passing through the impedance conversion circuit 15. The "impedance from the folding circuits 13, 14 to the N-tap resistive network circuit 11" refers to the impedance seen from the folding circuits 13, 14 to the N-tap resistive network circuit 11 when the N-tap resistive network circuit 11 and the folding circuits 13, 14 are directly connected to each other without passing through the impedance conversion circuit 15.

[0090] The impedance conversion circuit 15 outputs a control voltage Vc′(k) that is the same as or proportional to the control voltage Vc(k) input from the N-tap resistor network circuit 11 .

[0091] FIG. 18 is a diagram illustrating a delay that occurs in the signal generating circuit 10 according to the first embodiment. FIG. 18 shows an equivalent circuit of the N-tap resistor network circuit 11 when the switch SW is connected to a selected one of N taps. R15 represents the combined resistance from the selected tap to the terminal of the positive power supply voltage Vcc, and R16 represents the combined resistance from the selected tap to the terminal of the negative power supply voltage Vee. Differential amplifiers 31-33 and 41-43 are configured similarly to those shown in FIG. 3 . For simplicity, FIG. 18 shows only bipolar transistors Q1 and Q2 of the components of differential amplifiers 31-33 and 41-43 shown in FIG. 3 .

[0092] When each of the differential amplifiers 31-33 and 41-43 includes a bipolar transistor Q1 or Q2, a parasitic capacitance Cbc0 (e.g., several tens of fF) exists between the base and collector of each transistor. In the example of FIG. 2, the folding circuits 13 and 14 include a total of six differential amplifiers 31-33 and 41-43. One of the two input terminals of each of the differential amplifiers 31-33 and 41-43 (i.e., the base of the bipolar transistor Q1) is connected in parallel. Therefore, when the folding circuits 13 and 14 are viewed from the N-tap resistor network circuit 11, it appears that a parasitic capacitance of 6×Cbc0 is connected to the N-tap resistor network circuit 11.

[0093] The resistors R15 and R16 of the N-tap resistor network circuit 11 and the parasitic capacitance 6×Cbc0 of the folding circuits 13 and 14 form an RC circuit, i.e., an integrator circuit, with a predetermined time constant t0. The larger the resistance R15×R16 / (R15+R16) when looking at the N-tap resistor network circuit 11 from the folding circuits 13 and 14, the larger the time constant t0. Furthermore, the larger the parasitic capacitance of the folding circuits 13 and 14, the larger the time constant t0. Generally, when an input voltage Vin is applied to a circuit having a resistance R and a capacitance C, the output voltage Vout of the circuit changes according to Vout=Vin(1−exp(−t / RC)), and the circuit has a time constant RC (seconds). In the signal generating circuit 10 according to the first embodiment, when the digital control signal k is changed to change the phase, the control voltage Vc(k) does not change to the desired value instantaneously, but rather changes asymptotically to the desired value with a slope according to the time constant t0 of the circuit. The larger the time constant t0 of the circuit, the longer it takes for the control voltage Vc(k) to reach the desired value after the digital control signal k is changed.

[0094] When the N-tap resistor network circuit 11 and the folding circuits 13 and 14 are directly connected as in the first embodiment, the time constant t0 of the circuit becomes large for the following reasons, and as a result, the signal generating circuit 10 may not be able to operate at a sufficiently high speed: The parasitic capacitance when looking from the N-tap resistor network circuit 11 at the folding circuits 13 and 14 is relatively large (e.g., 6 x several tens of fF). The impedance when looking from the folding circuits 13 and 14 at the N-tap resistor network circuit 11 is relatively high (e.g., several kΩ).

[0095] The signal generating circuit 10G in FIG. 16 includes the impedance conversion circuit 15 and has the following features.

[0096] Since the N-tap resistor network circuit 11 and the folding circuits 13 and 14 are not directly connected to each other, the resistors R15 and R16 of the N-tap resistor network circuit 11 and the parasitic capacitance 6×Cbc0 of the folding circuits 13 and 14 do not form an RC circuit.

[0097] Because the impedance conversion circuit 15 has a high input impedance, the N-tap resistor network circuit 11 has a time constant t1 that depends on the resistors R15 and R16 and their surrounding capacitances (such as parasitic capacitances). The time constant t1 is substantially unaffected by the parasitic capacitance 6×Cbc0 of the folding circuits 13 and 14. The surrounding capacitance of the N-tap resistor network circuit 11 is expected to be smaller than the parasitic capacitance 6×Cbc0 of the folding circuits 13 and 14. Therefore, the time constant t1 of the N-tap resistor network circuit 11 is smaller than the time constant t0 when the N-tap resistor network circuit 11 and the folding circuits 13 and 14 are directly connected.

[0098] Furthermore, because the impedance conversion circuit 15 has a low output impedance, the folding circuits 13 and 14 have a time constant t2 that depends on the parasitic capacitance 6×Cbc0 and the surrounding resistance. The time constant t2 is substantially unaffected by the resistors R15 and R16 of the N-tap resistor network circuit 11. The resistances around the folding circuits 13 and 14 are expected to be smaller than the resistances of the resistors R15 and R16 of the N-tap resistor network circuit 11. Therefore, the time constant t2 of the folding circuits 13 and 14 is smaller than the time constant t0 when the N-tap resistor network circuit 11 and the folding circuits 13 and 14 are directly connected.

[0099] The time constant t1 of the N-tap resistor network circuit 11 and the time constant t2 of the folding circuits 13 and 14 are set to satisfy t1+t2<t0.

[0100] FIG. 19 is a circuit diagram showing the configuration of the impedance conversion circuit 15 of FIG. 16 . The impedance conversion circuit 15 may be an emitter follower circuit including a bipolar transistor Q101 and a resistor R101. The bipolar transistor Q101 has a parasitic capacitance Cbc1 between its base and collector. The time constant t1 of the N-tap resistor network circuit 11 depends on the resistors R15 and R16 and the parasitic capacitance Cbc1. For example, if Cbc1≈Cbc0, the time constant t1 of the N-tap resistor network circuit 11 is approximately 1 / 6 of the time constant t0 when the N-tap resistor network circuit 11 and the folding circuits 13 and 14 are directly connected. The bipolar transistor Q101 also has a small on-resistance. The time constant t2 of the folding circuits 13 and 14 depends on the parasitic capacitance 6×Cbc0 and the resistance of the impedance conversion circuit 15. When the on-resistance of the bipolar transistor Q101 is smaller than the resistors R15 and R16 of the N-tap resistor network circuit 11, the time constant t2 of the folding circuits 13 and 14 becomes smaller than the time constant t0 when the N-tap resistor network circuit 11 and the folding circuits 13 and 14 are directly connected.

[0101] As described above, the signal generation circuit 10G has a time constant t0 that is smaller than the time constant t0 when the N-tap resistor network circuit 11 and the folding circuits 13 and 14 are directly connected. Therefore, the time required for the control voltage Vc(k) to reach a desired value after the digital control signal k is changed is shortened. Thus, the signal generation circuit 10G according to the second embodiment can operate faster than the signal generation circuit 10 according to the first embodiment. Furthermore, like the signal generation circuit 10 according to the first embodiment, the signal generation circuit 10G according to the second embodiment can provide a signal generation circuit 10G and a phase shifter 1G that have a smaller circuit size and power consumption than conventional circuits, are resistant to PVT fluctuations, are digitally controllable, and have linear control characteristics with respect to the control signal.

[0102] 20 is a circuit diagram showing the configuration of an impedance conversion circuit 15A of a signal generation circuit according to a first modification of Embodiment 2. The impedance conversion circuit 15A may be a source follower circuit including a field effect transistor Q101A and a resistor R101, and having high input impedance and low output impedance.

[0103] 21 is a circuit diagram showing the configuration of an impedance conversion circuit 15B of a signal generation circuit according to a second modification of the second embodiment. The impedance conversion circuit 15B may be a voltage follower circuit that includes an operational amplifier and has high input impedance and low output impedance.

[0104] The signal generating circuit according to the second embodiment is not limited to an emitter follower circuit, a source follower circuit, and a voltage follower circuit, and may include other impedance conversion circuits having high input impedance and low output impedance.

[0105] FIG. 22 is a circuit diagram showing the configuration of an impedance conversion circuit 15C of a signal generation circuit according to a third modification of the second embodiment. In addition to the components of the impedance conversion circuit 15 shown in FIG. 19, the impedance conversion circuit 15C includes a bipolar transistor Q102 and a resistor R102. The bipolar transistor Q101 and the resistor R101 form a "first buffer circuit," and the bipolar transistor Q102 and the resistor R102 form a "second buffer circuit," and these buffer circuits are connected in parallel. When driving the six bipolar transistors Q1 of each of the differential amplifiers 31-33 and 41-43, a single-stage emitter follower circuit such as that shown in FIG. 19 may not be able to supply sufficient base current. On the other hand, by connecting two sets of buffer circuits in parallel as shown in FIG. 22, sufficient base current can be supplied to the bipolar transistor Q1 of each of the differential amplifiers 31-33 and 41-43.

[0106] FIG. 23 is a circuit diagram showing the configuration of an impedance conversion circuit 15D of a signal generation circuit according to a fourth modification of the second embodiment. The impedance conversion circuit 15D includes a bipolar transistor Q111 and a resistor R111 in addition to the components of the impedance conversion circuit 15 shown in FIG. 19 . The bipolar transistor Q101 and the resistor R101 form a “first buffer circuit,” and the bipolar transistor Q111 and the resistor R111 form a “second buffer circuit,” and these buffer circuits are cascade-connected to each other. When two buffer circuits are connected in parallel as shown in FIG. 22 , the N-tap resistor network circuit 11 appears to be connected to a parasitic capacitance 2×Cbc1 that is twice as large as that in the case of FIG. 19 . Therefore, the time constant of the N-tap resistor network circuit 11 is larger than that in the case of FIG. 19 , and the time it takes for the control voltage Vc(k) to reach a desired value after the digital control signal k is changed is longer. On the other hand, as shown in FIG. 23, by cascading two sets of buffer circuits, it is possible to supply a larger base current to the bipolar transistor Q1 of each of the differential amplifiers 31 to 33, 41 to 43 than in the case of FIG. 19 without increasing the time constant of the N-tap resistor network circuit 11.

[0107] FIG. 24 is a circuit diagram showing the configuration of an impedance conversion circuit 15E of a signal generation circuit according to a fifth modification of the second embodiment. The impedance conversion circuit 15E includes a bipolar transistor Q112 and a resistor R112 in addition to the components of the impedance conversion circuit 15D shown in FIG. 23 . The bipolar transistor Q112 and the resistor R112 form a “third buffer circuit,” which is connected in parallel to the second buffer circuit (i.e., the bipolar transistor Q111 and the resistor R111). In the example shown in FIG. 23 , only the second-stage emitter follower circuit drives the six bipolar transistors Q1 of each of the differential amplifiers 31 to 33 and 41 to 43. In this case, it is possible that a sufficient base current cannot be supplied. On the other hand, by connecting the second and third buffer circuits in parallel with each other as shown in FIG. 24 , a sufficient base current can be supplied to the bipolar transistor Q1 of each of the differential amplifiers 31 to 33 and 41 to 43 without increasing the time constant of the N-tap resistor network circuit 11.

[0108] In the examples of FIGS. 22 to 24, the impedance conversion circuit includes a plurality of emitter follower circuits, but the impedance conversion circuit may include a plurality of source follower circuits.

[0109] FIG. 25 is a block diagram showing the configuration of a phase shifter 1H including a signal generation circuit 10H according to a sixth modification of the second embodiment. FIG. 26 is a circuit diagram showing the configuration of the signal generation circuit 10H of FIG. 25. The phase shifter 1H includes the signal generation circuit 10H instead of the signal generation circuit 10 of FIG. 1. In addition to the components of the signal generation circuit 10G of FIGS. 16 to 17, the signal generation circuit 10H includes impedance conversion circuits 16-1 to 16-6 provided between the M-tap resistor network circuit 12 and the folding circuits 13 and 14. Specifically, as shown in FIG. 26, the impedance conversion circuits 16-1 to 16-6 are provided between the taps of the reference voltages Vr2, Vr4, Vr6, Vr1, Vr3, and Vr5 and the corresponding differential amplifiers 31 to 33 and 41 to 43. In FIG. 25, for simplicity, the impedance conversion circuits 16-1 to 16-6 are denoted by the common reference numeral "16." The impedance conversion circuits 16-1 to 16-6 have the same characteristics as the impedance conversion circuit 15 with respect to variations in at least one of the manufacturing process, the power supply voltage, and the temperature.

[0110] The impedance conversion circuits 16-1 to 16-6 output reference voltages Vr1' to Vr6' that are the same as or proportional to the reference voltages Vr1 to Vr6 input from the M-tap resistor network circuit 12, respectively.

[0111] Undesirable voltage shifts in the control voltage Vc'(k) may occur due to fluctuations in the manufacturing process, power supply voltage, or temperature associated with the impedance conversion circuit 15. By providing impedance conversion circuits 16-1 to 16-6 with the same characteristics as those of the impedance conversion circuit 15, the control voltage Vc'(k) and the reference voltages Vr1' to Vr6' shift in the same direction in response to fluctuations in the power supply voltage and temperature. Because the control voltage Vc'(k) and the reference voltages Vr1' to Vr6' are input to differential amplifiers 31 to 33 and 41 to 43, the high common-mode rejection ratios (CMRRs) of the differential amplifiers cancel out this voltage shift in the same direction. Even if absolute errors occur in the voltages generated by the impedance conversion circuits 15 and 16-1 to 16-6, the voltage shift can be reduced if the relative errors between the impedance conversion circuits 15 and 16-1 to 16-6 are small. As described above, the impedance conversion circuit 15H has high resistance to PVT fluctuations by including the impedance conversion circuits 16-1 to 16-6.

[0112] To realize simultaneous connections between multiple transmitters and multiple receivers, the application of a massive MIMO (mMIMO) system using a phased array antenna apparatus including a large number of antenna elements is expected. However, there is a concern that an increase in the number of antenna elements will lead to increased power consumption in high-frequency bands. Therefore, a system has been proposed that achieves functionality equivalent to the mMIMO system by steering beams in multiple directions in a short period of time (e.g., a time period of one symbol or less) even when using a phased array antenna apparatus including a small number of antenna elements. To achieve such beam steering, it is necessary to quickly control a phase shifter so as to rapidly change the phase of signals transmitted and received by each antenna element. Conventionally, phase shifters capable of setting an arbitrary phase include, for example, a digital arithmetic circuit for correcting amplitude changes or a lookup table storing amplitude information, and the operating speed of the phase shifter is limited by the operating speed of the digital arithmetic circuit or the lookup table. According to the second embodiment, the phase shifter can be quickly controlled so as to rapidly change the phase of signals transmitted and received by each antenna element without requiring a digital arithmetic circuit, a lookup table, or the like.

[0113] 27 is a block diagram showing the configuration of a wireless communication device 100 according to a third embodiment. The wireless communication device 100 includes a transmission circuit 101, mixers 102-1 to 102-4, amplifiers 103-1 to 103-4, antenna elements 104-1 to 104-4, a frequency synthesizer 105, a frequency multiplier 106, phase shifters 107-1 to 107-4, frequency multipliers 108-1 to 108-4, and a control circuit 109.

[0114] The transmitting circuit 101 sends a baseband signal containing data to be transmitted to the mixers 102-1 to 102-4.

[0115] Frequency synthesizer 105 generates a high-frequency signal having a predetermined frequency. Frequency multiplier 106 multiplies the frequency of the high-frequency signal generated by frequency synthesizer 105 and sends the multiplied signal to phase shifters 107-1 to 107-4.

[0116] Each of the phase shifters 107-1 to 107-4 has the same configuration as the phase shifter 1 according to the first embodiment or the phase shifters 1G and 1H according to the second embodiment. Digital control signals k1 to k4 are input to each of the phase shifters 107-1 to 107-4 from a control circuit 109. The phase shifters 107-1 to 107-4 change the phase of the high-frequency signal input from the frequency multiplier 106 in accordance with the digital control signals k1 to k4. The control circuit 109 uses the digital control signals k1 to k4 to arbitrarily change the phases of the high-frequency signals independently of each other.

[0117] Frequency multipliers 108-1 to 108-4 multiply the frequencies of the high frequency signals output from phase shifters 107-1 to 107-4 and send the multiplied signals to mixers 102-1 to 102-4.

[0118] Mixers 102-1 to 102-4 modulate the high-frequency signals (radio frequency signals) input from frequency multipliers 108-1 to 108-4 with the baseband signals input from transmission circuit 101. The output signals of mixers 102-1 to 102-4 are amplified by amplifiers 103-1 to 103-4, respectively, and then radiated from antenna elements 104-1 to 104-4, respectively.

[0119] The antenna elements 104-1 to 104-4 operate as a phased array antenna device by changing the phase of the radio frequency signal to be transmitted by the phase shifters 107-1 to 107-4. By changing the phase of the radio frequency signal with high precision using the phase shifters 107-1 to 107-4, the directivity of the antenna device can be further increased.

[0120] 27 shows a wireless communication device 100 including a transmission circuit 101, the phase shifter 1 according to the first embodiment and the phase shifters 1G and 1H according to the second embodiment are similarly applicable to wireless communication devices including a reception circuit. When the wireless communication device includes a reception circuit, the arrival direction may be estimated based on the received signal, or a beam may be directed toward the arrival direction using a phase shifter.

[0121] According to the third embodiment, it is possible to provide a wireless communication device that utilizes high frequency bands such as millimeter waves and terahertz waves.

[0122] Other Embodiments The embodiments and modifications described above may be combined in any manner.

[0123] In another example of FIG. 2, the reference voltages Vr1 to Vr6 for the differential amplifiers 31 to 33 and 41 to 43 are set in the order Vr1<Vr2<Vr3<Vr4<Vr5<Vr6, but they may also be set in another order, for example, Vr2<Vr1<Vr4<Vr3<Vr6<Vr5.

[0124] 1 and other figures illustrate a case in which the signal generation circuit 10 generates both a sine wave and a cosine wave, but the techniques described in this disclosure are also applicable to a case in which only one of a sine wave and a cosine wave is generated. In this case, the signal generation circuit includes only one of the folding circuits 13 and 14. The output signal of the signal generation circuit may be supplied to any circuit that utilizes a signal level corresponding to a predetermined phase of a sine wave or a cosine wave, for example, a direct digital synthesizer that digitally generates a sine wave signal or a cosine wave signal.

[0125] Summary of the Embodiments A signal generating circuit, a phase shifter, an array antenna device, and a wireless communication device according to each aspect of the present disclosure may be expressed as follows.

[0126] A signal generating circuit according to a first aspect of the present disclosure comprises: a first resistor network circuit including a plurality of first resistors and a plurality of first taps, and generating a control voltage having one of a plurality of predetermined voltage values ​​by selecting one of the plurality of first taps in response to an input digital control signal; a second resistor network circuit including a plurality of second resistors and a plurality of second taps, and generating a plurality of predetermined reference voltages from the plurality of second taps; and at least one folding circuit that generates an output signal having a signal level corresponding to a predetermined phase of a sine wave or a cosine wave based on the difference between the control voltage and the plurality of reference voltages.

[0127] According to a signal generation circuit of a second aspect of the present disclosure, in the signal generation circuit of the first aspect, the signal generation circuit includes: a first folding circuit that generates a first output signal having a signal level corresponding to a predetermined phase of a sine wave; and a second folding circuit that generates a second output signal having a signal level corresponding to a predetermined phase of a cosine wave.

[0128] According to a third aspect of the present disclosure, there is provided a signal generation circuit according to the second aspect, wherein the first folding circuit comprises: a first differential amplifier that compares the control voltage with a first reference voltage to generate a first differential output signal; a second differential amplifier that compares the control voltage with a second reference voltage that is higher than the first reference voltage to generate a second differential output signal; and a third differential amplifier that compares the control voltage with a third reference voltage that is higher than the second reference voltage to generate a third differential output signal; and the second folding circuit comprises: a fourth differential amplifier that compares the control voltage with a fourth reference voltage to generate a fourth differential output signal; a fifth differential amplifier that compares the control voltage with a fifth reference voltage that is higher than the fourth reference voltage to generate a fifth differential output signal; and a sixth differential amplifier that compares the control voltage with a sixth reference voltage that is higher than the fifth reference voltage to generate a sixth differential output signal; The first output signal is the sum of the first and third differential output signals and an inverted signal of the second differential output signal, and the second output signal is the sum of the fourth and sixth differential output signals and an inverted signal of the fifth differential output signal.

[0129] According to a fourth aspect of the present disclosure, in the signal generation circuit according to the third aspect, each of the first to sixth differential amplifiers includes a pair of bipolar transistors or a pair of field effect transistors.

[0130] According to a fifth aspect of the present disclosure, in the signal generation circuit according to any one of the first to fourth aspects, the first resistor network circuit further includes a first constant current source connected to the plurality of first resistors.

[0131] According to a sixth aspect of the present disclosure, in the signal generation circuit according to any one of the first to fifth aspects, the first resistor network circuit further includes a voltage dividing resistor connected to an output terminal of the first resistor network circuit.

[0132] According to a seventh aspect of the present disclosure, in the signal generation circuit according to the third aspect, the second resistor network circuit includes voltage dividing resistors that generate the first to sixth reference voltages from a power supply voltage.

[0133] According to the signal generation circuit of the eighth aspect of the present disclosure, in the signal generation circuit of the third aspect, the second resistor network circuit further includes a first voltage dividing resistor that generates the first to third reference voltages from a power supply voltage, and a second voltage dividing resistor that generates the fourth to sixth reference voltages from the power supply voltage.

[0134] According to a signal generation circuit according to a ninth aspect of the present disclosure, in the signal generation circuit according to the third aspect, the second resistor network circuit further includes a first voltage dividing resistor that generates the first to third reference voltages from a first power supply voltage, and a second voltage dividing resistor that generates the fourth to sixth reference voltages from a second power supply voltage.

[0135] According to a signal generation circuit according to a tenth aspect of the present disclosure, in the signal generation circuit according to any one of the first to ninth aspects, the second resistor network circuit further includes a second constant current source connected to the plurality of second resistors.

[0136] According to an eleventh aspect of the present disclosure, in the signal generation circuit according to the first aspect, the first and second resistor network circuits are connected to a common voltage source.

[0137] According to a signal generation circuit according to a twelfth aspect of the present disclosure, in the signal generation circuit according to any one of the first to eleventh aspects, the signal generation circuit further includes a first impedance conversion circuit provided between the first resistive network circuit and the folding circuit, and the first impedance conversion circuit has an input impedance higher than the impedance from the first resistive network circuit to the folding circuit and an output impedance lower than the impedance from the folding circuit to the first resistive network circuit.

[0138] According to a thirteenth aspect of the present disclosure, in the signal generation circuit according to the twelfth aspect, the first impedance conversion circuit includes an emitter follower circuit, a source follower circuit, or a voltage follower circuit.

[0139] According to a signal generation circuit according to a fourteenth aspect of the present disclosure, in the signal generation circuit according to the twelfth or thirteenth aspect, the first impedance conversion circuit includes first and second buffer circuits connected in parallel to each other.

[0140] According to a signal generation circuit according to a fifteenth aspect of the present disclosure, in the signal generation circuit according to the twelfth or thirteenth aspect, the first impedance conversion circuit includes a first buffer circuit and a second buffer circuit cascade-connected in a subsequent stage of the first buffer circuit.

[0141] According to a sixteenth aspect of the present disclosure, in the signal generation circuit of the fifteenth aspect, the first impedance conversion circuit further includes a third buffer circuit connected in parallel to the second buffer circuit.

[0142] According to a signal generation circuit according to a seventeenth aspect of the present disclosure, in the signal generation circuit according to one of the twelfth to sixteenth aspects, the signal generation circuit further includes a second impedance conversion circuit provided between the second resistor network circuit and the folding circuit, and the second impedance conversion circuit has the same characteristics as the first impedance conversion circuit with respect to fluctuations in at least one of the manufacturing process, power supply voltage, and temperature.

[0143] According to an eighteenth aspect of the present disclosure, in the signal generation circuit according to any one of the first to seventeenth aspects, the first and second resistors have the same temperature coefficient.

[0144] According to a signal generation circuit according to a nineteenth aspect of the present disclosure, in the signal generation circuit according to one of the first to eighteenth aspects, the first and second resistor network circuits are implemented on a single integrated circuit.

[0145] A phase shifter according to a twentieth aspect of the present disclosure includes: a signal generating circuit according to the second aspect or a signal generating circuit according to one of the third to nineteenth aspects dependent on the second aspect; a quadrature splitter that separates an input signal into an in-phase signal and a quadrature-phase signal; a first multiplier that multiplies the in-phase signal by a second output signal of the signal generating circuit to generate a first multiplied signal; a second multiplier that multiplies the quadrature-phase signal by the first output signal of the signal generating circuit to generate a second multiplied signal; and a combiner that combines the first and second multiplied signals together.

[0146] A phase shifter according to a twenty-first aspect of the present disclosure is the phase shifter according to the twentieth aspect, further comprising a low-pass filter that reduces signal components having frequencies higher than a predetermined frequency in the first and second output signals of the signal generating circuit.

[0147] An array antenna apparatus according to a twenty-second aspect of the present disclosure includes: a plurality of antenna elements; a plurality of third mixers; and a plurality of phase shifters according to the twentieth or twenty-first aspect.

[0148] A wireless communication device according to a twenty-third aspect of the present disclosure includes the array antenna device according to the twenty-second aspect and a communication circuit.

[0149] A signal generating circuit, a phase shifter, an array antenna device, and a wireless communication device according to an aspect of the present disclosure may be applied to, for example, a base station or a mobile station of a wireless communication system. The signal generating circuit, the phase shifter, the array antenna device, and the wireless communication device according to an aspect of the present disclosure may be applied to, for example, a phase shifter portion of a phased array antenna device that is being considered for use in satellite communications and weather radar.

[0150] 1, 1F to 1H Phase shifter 10, 10G, 10H Signal generation circuit 11, 11C to 11E N-tap resistor network circuit 12, 12A to 12D M-tap resistor network circuit 13, 14 Folding circuit 15, 15A to 15E, 16, 16-1 to 16-6 Impedance conversion circuit 20 Quadrature modulation circuit 21 Quadrature distributor 22, 23 Multiplier 24 Combiner 31 to 33 Differential amplifier 41 to 43 Differential amplifier 51 Constant current source 61, 62 Constant current source 71, 72 Low-pass filter (LPF) 100 Wireless communication device 101 Transmitting circuit 102-1 to 102-4 Mixer 103-1 to 103-4 Amplifier 104-1 to 104-4 Antenna element 105 Frequency synthesizer 106 Frequency multiplier 107-1 to 107-4 Phase shifter 108-1 to 108-4 Frequency multiplier 109 Control circuit R, R10 to R14, R21 to R28, R21A to R27A, R21Ba, R21Bb, R28Ba, R28Bb, R31, R32, R41, R42, R101, R102, R1111, R112, Ra to Rd Resistors Q1, Q2, Q101, Q102, Q111, Q112 Bipolar transistor Q1A, Q2A, Q101A Field effect transistor SW Switch

Claims

1. a first resistor network circuit including a plurality of first resistors and a plurality of first taps, the first resistor network circuit selecting one of the plurality of first taps in response to an input digital control signal to generate a control voltage having one of a plurality of predetermined voltage values; a second resistor network circuit including a plurality of second resistors and a plurality of second taps, the second resistor network circuit generating a plurality of predetermined reference voltages from the plurality of second taps; at least one folding circuit for generating an output signal having a signal level corresponding to a predetermined phase of a sine wave or a cosine wave based on a difference between the control voltage and the plurality of reference voltages; the first and second resistors have the same temperature coefficient; Signal generation circuit.

2. The signal generating circuit includes: a first folding circuit for generating a first output signal having a signal level corresponding to a predetermined phase of the sine wave; a second folding circuit for generating a second output signal having a signal level corresponding to a predetermined phase of the cosine wave.

2. The signal generating circuit according to claim 1.

3. The first folding circuit includes: a first differential amplifier for comparing the control voltage against a first reference voltage to generate a first differential output signal; a second differential amplifier for comparing the control voltage against a second reference voltage, the second reference voltage being higher than the first reference voltage, to generate a second differential output signal; a third differential amplifier for comparing the control voltage to a third reference voltage higher than the second reference voltage to generate a third differential output signal; The second folding circuit includes: a fourth differential amplifier for comparing the control voltage against a fourth reference voltage to generate a fourth differential output signal; a fifth differential amplifier for comparing the control voltage against a fifth reference voltage, the fifth reference voltage being higher than the fourth reference voltage, to generate a fifth differential output signal; a sixth differential amplifier for comparing the control voltage to a sixth reference voltage higher than the fifth reference voltage to generate a sixth differential output signal; the first output signal is a sum of the first and third differential output signals and an inverted signal of the second differential output signal; the second output signal is a sum of the fourth and sixth differential output signals and an inverted signal of the fifth differential output signal.

3. The signal generating circuit according to claim 2.

4. Each of the first to sixth differential amplifiers includes a pair of bipolar transistors or a pair of field effect transistors.

4. The signal generating circuit according to claim 3.

5. the first resistor network circuit further includes a first constant current source connected to the plurality of first resistors; 2. The signal generating circuit according to claim 1.

6. the first resistor network circuit further includes a voltage dividing resistor connected to an output terminal of the first resistor network circuit; 2. The signal generating circuit according to claim 1.

7. the second resistor network circuit includes voltage dividing resistors that generate the first to sixth reference voltages from a power supply voltage; 4. The signal generating circuit according to claim 3.

8. The second resistor network circuit includes: a first voltage dividing resistor that generates the first to third reference voltages from a power supply voltage; a second voltage dividing resistor that generates the fourth to sixth reference voltages from the power supply voltage; 4. The signal generating circuit according to claim 3.

9. The second resistor network circuit includes: a first voltage dividing resistor that generates the first to third reference voltages from a first power supply voltage; a second voltage dividing resistor that generates the fourth to sixth reference voltages from a second power supply voltage; 4. The signal generating circuit according to claim 3.

10. the second resistor network circuit further includes a second constant current source connected to the plurality of second resistors.

2. The signal generating circuit according to claim 1.

11. the first and second resistor network circuits are connected to a common voltage source.

2. The signal generating circuit according to claim 1.

12. the first and second resistor network circuits are implemented on a single integrated circuit; 2. The signal generating circuit according to claim 1.

13. A signal generating circuit according to claim 2; a quadrature splitter that splits an input signal into an in-phase signal and a quadrature signal; a first multiplier that multiplies the in-phase signal by a second output signal of the signal generating circuit to generate a first multiplied signal; a second multiplier that multiplies the first output signal of the signal generating circuit by the quadrature phase signal to generate a second multiplied signal; a combiner for combining the first and second multiplied signals together. Phase shifter.

14. a low-pass filter for reducing signal components having a frequency higher than a predetermined frequency in the first and second output signals of the signal generating circuit; 14. The phase shifter according to claim 13.

15. A plurality of antenna elements; A plurality of mixers; and a plurality of phase shifters according to claim 13. Array antenna device.

16. An array antenna apparatus according to claim 15, and a communication circuit. Wireless communication device.

17. a first resistor network circuit including a plurality of first resistors and a plurality of first taps, the first resistor network circuit selecting one of the plurality of first taps in response to an input digital control signal to generate a control voltage having one of a plurality of predetermined voltage values; a second resistor network circuit including a plurality of second resistors and a plurality of second taps, the second resistor network circuit generating a plurality of predetermined reference voltages from the plurality of second taps; at least one folding circuit for generating an output signal having a signal level corresponding to a predetermined phase of a sine wave or a cosine wave based on a difference between the control voltage and the plurality of reference voltages; a first impedance conversion circuit provided between the first resistor network circuit and the folding circuit; the first impedance conversion circuit has an input impedance higher than an impedance from the first resistor network circuit to the folding circuit, and has an output impedance lower than an impedance from the folding circuit to the first resistor network circuit; the first and second resistors have the same temperature coefficient; Signal generation circuit.

18. the first impedance conversion circuit includes an emitter follower circuit, a source follower circuit, or a voltage follower circuit; 18. The signal generating circuit according to claim 17.

19. the first impedance conversion circuit includes first and second buffer circuits connected in parallel with each other; 18. The signal generating circuit according to claim 17.

20. The first impedance conversion circuit includes: a first buffer circuit; a second buffer circuit cascade-connected to a rear stage of the first buffer circuit; 18. The signal generating circuit according to claim 17.

21. the first impedance conversion circuit further includes a third buffer circuit connected in parallel to the second buffer circuit; 21. The signal generating circuit according to claim 20.

22. the signal generating circuit further includes a second impedance conversion circuit provided between the second resistor network circuit and the folding circuit; the second impedance conversion circuit has the same characteristics as the first impedance conversion circuit with respect to at least one of variations in a manufacturing process, a power supply voltage, and a temperature; 18. The signal generating circuit according to claim 17.

23. The signal generating circuit includes: a first folding circuit for generating a first output signal having a signal level corresponding to a predetermined phase of the sine wave; a second folding circuit for generating a second output signal having a signal level corresponding to a predetermined phase of the cosine wave. A signal generating circuit according to any one of claims 17 to 22.

24. the first and second resistor network circuits are implemented on a single integrated circuit; 18. The signal generating circuit according to claim 17.

25. A signal generating circuit according to claim 23; a quadrature splitter that splits an input signal into an in-phase signal and a quadrature signal; a first multiplier that multiplies the in-phase signal by a second output signal of the signal generating circuit to generate a first multiplied signal; a second multiplier that multiplies the first output signal of the signal generating circuit by the quadrature phase signal to generate a second multiplied signal; a combiner for combining the first and second multiplied signals together. Phase shifter.

26. A plurality of antenna elements; A plurality of mixers; and a plurality of phase shifters according to claim 25. Array antenna device.

27. An array antenna apparatus according to claim 26, and a communication circuit. Wireless communication device.