Semiconductor memory device

Abstract

A semiconductor memory device (1) comprises a memory cell array (2) and a write circuit (3) that has a function of setting a bit line of a memory cell to be written to a low potential and sets a bit line on a low-potential side to a negative potential by means of capacitance in response to a negative-potential boost signal. The memory cell array (2) comprises a first memory bank (21) and a second memory bank (22), each having a plurality of memory cells (MCs). The bit line on the low-potential side is set to the negative potential by using only a first capacitive element (PCAP0) when the write to the first memory bank (21) is executed and by using a first capacitive element (PCAP1) and a second capacitive element (C32) when the write to the second memory bank (22) is executed.

Description

semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device.

[0002] In recent years, as semiconductor processes have become more miniaturized, the voltage required for semiconductor devices has become lower, making stable write operations to static random access memories (SRAMs) problematic. A known conventional technique for solving this problem is the negative bit line write assist technique.

[0003] Patent Document 1 discloses a semiconductor memory device having a multi-bank SRAM divided into multiple banks and an assist circuit commonly connected to the multiple banks. In Patent Document 1, the number of banks is changed when writing to the SRAM to optimize the write assist level (negative potential).

[0004] Japanese Patent Application Laid-Open No. 2021-140848

[0005] In the multi-bank semiconductor memory device described in Patent Document 1, all banks are connected to the capacity provided in the assist circuit at most, and a large capacity must be provided to optimize the write assist level, resulting in a large circuit area.

[0006] Furthermore, in a multi-bank configuration, if the bank sizes are different, i.e., if the number of memory cells connected to each bit line is different, it may be difficult to optimize the write assist level, and normal writing may not be possible.

[0007] The present disclosure aims to achieve an optimal write assist level and normal writing with a small circuit area in a semiconductor memory device with a multi-bank configuration, even if the banks have different sizes.

[0008] In one aspect of the present disclosure, a memory cell array includes a first memory bank and a second memory bank, each having a plurality of memory cells, the plurality of memory cells being connected to corresponding word lines and bit line pairs, and the number of word lines of the first memory bank being fewer than the number of word lines of the second memory bank; and a write circuit having a function of setting one bit line of a bit line pair connected to a memory cell to be written to a low potential, and setting the low-potential side bit line to a negative potential by a capacitance connected to an internal ground line in response to a negative potential boost signal, the capacitances including a first capacitive element and a second capacitive element each connected to the internal ground line, and when writing to a memory cell of the first memory bank, the low-potential side bit line is set to a negative potential by only the first capacitive element, and when writing to a memory cell of the second memory bank, the low-potential side bit line is set to a negative potential by the first capacitive element and the second capacitive element.

[0009] According to this aspect, when writing to memory cells in a first memory bank having a relatively small number of rows, only the first capacitance element is used to set the low-potential side bit line to a negative potential, and when writing to memory cells in a second memory bank having a relatively large number of rows, both the first capacitance element and the second capacitance element are used to set the low-potential side bit line to a negative potential. This ensures an optimal write assist level for write operations to each of the first memory bank and the second memory bank. This allows for normal writing to memory cells to be written to and prevents erroneous writing to memory cells in unselected memory banks.

[0010] According to the present disclosure, in a semiconductor memory device with a multi-bank configuration, even if the banks have different sizes, it is possible to achieve an optimal write assist level and normal writing with a small circuit area.

[0011] A functional block diagram showing an example of the configuration of a semiconductor memory device. A diagram showing an example of the circuit configuration of the memory cell of FIG. 1. A diagram showing an example of the circuit configuration of a write circuit. A timing chart showing an example of the operation of the semiconductor memory device.

[0012] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same reference numerals may be used to refer to signal lines and signals passing through the signal lines.

[0013] Embodiment A semiconductor memory device 1 includes a memory cell array 2 and a read / write circuit 3 .

[0014] —Memory Cell Array— As shown in FIG. 1, the memory cell array 2 includes a first memory bank 21 and a second memory bank 22 .

[0015] The first memory bank 21 includes a plurality of memory cells MC arranged in an array of [number of columns: c (c is a natural number) × number of rows: w-mr (w is a natural number) × number of sets: b (b is a natural number)]. That is, the first memory bank 21 has a configuration in which c columns of memory cells are arranged in b sets in the column direction, and has a total of [c×b] columns and [c×(w-mr)×b] memory cells MC. In addition, in the first memory bank 21, [w-mr] is the number of rows.

[0016] The first memory bank 21 includes a plurality of word lines WL ([w-mr] in FIG. 1) extending in the row direction and a plurality of bit line pairs TBLT (bit lines BLT, NBLT) ([c×b] in FIG. 1) extending in the column direction. Each memory cell MC is connected to a word line WL and a bit line pair TBLT at a position corresponding to its arrangement position.

[0017] The second memory bank 22 includes a plurality of memory cells MC arranged in an array of [c (c is a natural number) × mr (mr is a natural number) × b (b is a natural number) number of sets]. That is, the second memory bank 22 has a configuration in which c columns of memory cells are arranged in the column direction, and b sets of memory cells are arranged in a total of [c × b] columns, and includes [c × mr × b] memory cells MC. In addition, in the second memory bank 22, mr is the number of rows.

[0018] The second memory bank 22 includes a plurality of word lines WL (mr in FIG. 1 ) extending in the row direction and a plurality of bit line pairs TBLB (c×b in FIG. 1 ) extending in the column direction intersecting the row direction. Each memory cell MC is connected to a word line WL and a bit line pair TBLB (bit lines BLB, NBLB) at a position corresponding to its arrangement position.

[0019] 1, the number of word lines in the first memory bank 21 is smaller than the number of word lines in the second memory bank 22. That is, in the example of FIG. 1, the number of memory cells MC has the relationship [mr>(w-mr)], and the number of rows in the first memory bank 21 is smaller than the number of rows in the second memory bank 22. In other words, the load capacitance of the bit line pair TBLT in the first memory bank 21 is smaller than the load capacitance of the bit line pair TBLB in the second memory bank 22.

[0020] In the first memory bank 21 and the second memory bank 22, the word lines WL are connected to a row decoder (not shown). The row decoder activates the word line WL of the row including the memory cell MC to be operated in accordance with a row address specified by a CPU (not shown).

[0021] The bit line pair TBLT of the first memory bank 21 and the bit line pair TBLB of the second memory bank 22 are connected to the read / write circuits 3 provided at the corresponding positions, respectively. The read / write circuits 3 will be described later.

[0022] In the following description, the bit lines BLB and BLT may be referred to simply as "bit line BL" without distinction. Similarly, the bit lines NBLB and NBLT may be referred to simply as "bit line NBL" without distinction, and the bit line pair TBLB and TBLT may be referred to simply as "bit line pair TBL" without distinction.

[0023] Fig. 2 is a circuit diagram showing the internal configuration of the memory cell MC of Fig. 1. In Fig. 2, the memory cell MC includes N-type transistors NA1 and NA2, P-type transistors PL1 and PL2, and N-type transistors ND1 and ND2.

[0024] The gate of the N-type transistor NA1 is connected to the word line WL and the source is connected to the bit line BL. The gate of the N-type transistor NA2 is connected to the word line WL and the source is connected to the bit line NBL. The source of the P-type transistor PL1 is supplied with the power supply voltage VDD and is connected to the drain of the N-type transistor NA1. The gate of the N-type transistor ND1 is connected to the gate of the P-type transistor PL1, the drain is connected to the drain of the P-type transistor PL1, and the source is connected to the ground potential VSS. The gate of the P-type transistor PL2 is connected to the drain of the N-type transistor NA1, the source is supplied with the power supply voltage VDD, and the drain is connected to the drain of the N-type transistor NA2. The gate of the N-type transistor ND2 is connected to the gate of the P-type transistor PL2, the drain is connected to the drain of the P-type transistor PL2, and the source is connected to the ground potential VSS. The connection node between the gate of the P-type transistor PL1 and the gate of the N-type transistor ND1 is connected to the drain of the N-type transistor NA2.

[0025] Here, the P-type transistor PL1 and the N-type transistor ND1 form a first inverter. The P-type transistor PL2 and the N-type transistor ND2 form a second inverter. The input terminal of the first inverter is connected to the output terminal of the second inverter, and the output terminal of the first inverter is connected to the input terminal of the second inverter, thereby forming a latch circuit.

[0026] 1, a read / write circuit 3 is provided between the first memory bank 21 and the second memory bank 22. The read / write circuit 3 is provided for each of c columns of memory cells, and there are b read / write circuits 3 in total.

[0027] The read / write circuit 3 includes a write circuit 30. The write circuit 30 has a first function of setting one bit line (BL or NBL) of the bit line pair TBL connected to the memory cell MC to be written to a low potential, and a second function of setting the bit line (BL or NBL) on the low potential side to a negative potential by a capacitance connected to the internal ground line WGND in response to negative potential boost signals NWACP0 and NWACP1, which will be described later.

[0028] Fig. 3 is a circuit diagram showing an example of the configuration of the write circuit 30. Note that the configuration of the write circuit 30 is not limited to the configuration shown in Fig. 3, and may be another circuit configuration having the above-described first and second functions.

[0029] In the example of Figure 3, the write circuit 30 includes a write circuit for the first memory bank 21 (precharge circuit 31T, write driver 32T, column selection circuit 33T), a write circuit for the second memory bank 22 (precharge circuit 31B, write driver 32B, column selection circuit 33B), and a write assist circuit 36.

[0030] The precharge circuit 31T precharges the bit lines BLT and NBLT with a precharge signal PCGT (hereinafter referred to as the "PCGT signal"), and the precharge circuit 31B precharges the bit lines BLB and NBLB with a precharge signal PCGB (hereinafter referred to as the "PCGB signal").

[0031] The write driver 32T outputs write data WD[x] or NWD[x] (x is an integer equal to or greater than 0) based on a write control signal WRITET (hereinafter referred to as the "WRITET signal"). The write driver 32B outputs write data WD[x] or NWD[x] (x is an integer equal to or greater than 0) based on a write control signal WRITEB (hereinafter referred to as the "WRITEB signal"). NWD[x] is an inverted signal of WD[x]. In the following description, the write data signal WD will be simply referred to as "WD", and the write data signal NWD will be simply referred to as "NWD".

[0032] The column selection circuits 33T and 33B have a function of selecting a column to be written based on a column selection signal CAD[0:c-1].

[0033] The column selection circuit 33T includes a transistor TN0 connected between the bit line BLT and the internal ground line WGND, and transistors TP3 and TN2 that operate the transistor TN0 based on the output of the write driver 32T and a column selection signal CAD[0:c-1].

[0034] The column selection circuit 33B includes a transistor TN10 connected between the bit line BLB and the internal ground line WGND, and transistors TP8 and TN4 that operate the transistor TN10 based on the output of the write driver 32B and a column selection signal CAD[0:c-1].

[0035] In the following description, the column selection signal CAD will be simply referred to as "CAD."

[0036] The write assist circuit 36 ​​has a function of making the bit line on the low potential side negative potential by capacitance in response to negative potential boost signals NWACP0, NWACP1 generated based on the write assist control signal NWTA (hereinafter referred to as the "NWTA signal"). The capacitance includes a first capacitance element PCAP0 that functions when writing to the first memory bank 21, and a second capacitance element PCAP1 that functions when writing to both the first memory bank 21 and the second memory bank 22.

[0037] In this example, the first capacitance element PCAP0 is a MOS capacitance element provided between the negative potential boost signal line NWACP0 and the internal ground line WGND. The negative potential boost signal NWACP0 is a signal that changes in the same manner as the NWTA signal.

[0038] The second capacitance element PCAP1 is a MOS capacitance element provided between the negative potential boost signal line NWACP1 and the internal ground line WGND. The negative potential boost signal NWACP1 is a signal that changes so as to activate the second capacitance element PCAP1 only when the NWTA signal is 'L' and the WRITEB signal is 'H'.

[0039] With the above configuration, when the NWTA control signal changes from 'H' to 'L' during writing to the first memory bank 21, only the first capacitance element PCAP0 discharges the charge so as to set the internal ground line WGND to a negative potential. At this time, the second capacitance element PCAP1 does not function.

[0040] On the other hand, when writing to the second memory bank 22, if the NWTA control signal changes from 'H' to 'L', both the first capacitance element PCAP0 and the second capacitance element PCAP1 discharge charge so as to set the internal ground line WGND to a negative potential.

[0041] As a result, the capacitance value of the first capacitance element PCAP0 can be adjusted so that the bit line BLT or the bit line NBLT has an optimal negative potential when writing to the first memory bank 21. Furthermore, the capacitance value of the second capacitance element PCAP1 can be adjusted so that the bit line BLB or the bit line NBLB has an optimal negative potential when writing to the second memory bank 22, with the capacitance values ​​of the first capacitance element PCAP0 and the second capacitance element PCAP1 added together. That is, the transistors constituting the first capacitance element PCAP0 and the second capacitance element PCAP1 can be optimized according to the number of rows in the first memory bank 21 and the second memory bank 22, respectively. Furthermore, the combined capacitance of the first capacitance element PCAP0 and the second capacitance element PCAP1 is sufficient to optimize the negative potential of the mr row in the second memory bank 22. This allows the semiconductor memory device 1 to have a smaller area.

[0042] 3, PMOS transistors are used as the first capacitance element PCAP0 and the second capacitance element PCAP1, but this is not limiting. For example, NMOS transistors may be used, or other capacitance elements may be applied. Furthermore, in the first capacitance element PCAP0 and the second capacitance element PCAP1, the gate side is connected to the internal ground line WGND, but the source / drain side may also be connected to the internal ground line WGND.

[0043] 3 and 4, a data write operation to the memory cells MC in the semiconductor memory device 1 will be described. In the following write operation, the capacitance values ​​of the first capacitive element PCAP0 and the second capacitive element PCAP1 will be described as being optimized according to the number of rows in each of the first memory bank 21 and the second memory bank 22.

[0044] (Write operation to first memory bank) In this example, we will explain the operation when writing 'L' to BLT[0] of memory cell MC (write target) in the top row of the first memory bank 21 (corresponding to WL[w-1] in Figure 1) and the leftmost column of column c (corresponding to CAD[0] in Figure 3).

[0045] In the initial state, the NWTA signal is 'H', and the WRITET signal, WRITEB signal, PCGT signal, PCGB signal and CAD[0] are 'L'.

[0046] Since the PCGT signal is 'L', both BLT[0] and NBLT[0] are precharged to 'H'. In Fig. 4, BLT[0] is indicated by a thick solid line, and NBLT[0] is indicated by a thin solid line.

[0047] Since the NWTA signal is 'H', the internal ground signal WGND becomes 'L (0 V)' by the transistor TDN0, and the sources / drains of the first capacitance element PCAP0 and the second capacitance element PCAP1 are charged to 'H'. Also, although not shown, WD[0] = 'L' and NWD[0] = 'H' are input as write data.

[0048] First, the control signals WL[w-1], PCGT signal, WRITET signal, and CAD[0] rise from 'L' to 'H'.

[0049] When the WRITE signal rises from 'L' to 'H', the gates of transistors TP13 and TN9 go to 'H'. Since NWD[0] = 'H', the gates of transistors TP3 and TN2 go to 'L'. Also, since CAD[0] = 'H', the source of transistor TP3 is 'H'. Therefore, the gate of transistor TN0 goes to 'H'. Then, since the internal ground signal WGND is 'L (0V)', the bit line BLT[0] falls from 'H' to 'L'.

[0050] Here, the timing of the NWTA signal is adjusted so that it falls from 'H' to 'L' when the bit line BLT[0] has fallen sufficiently to the ground potential VSS. Therefore, after the bit line BLT[0] has fallen to the ground potential VSS, the NWTA signal changes from 'H' to 'L', the transistor TDN0 is turned off, and the internal ground signal WGND is set to a floating state at the ground potential VSS.

[0051] Furthermore, when the NWTA signal changes from 'H' to 'L', the NWACP0 signal changes from 'H' to 'L', the source / drain of the first capacitance element PCAP0 is discharged, and the internal ground signal WGND becomes negative potential. At this time, since the WRITEB signal remains 'L', the NWACP1 signal remains 'H', and the source / drain of the second capacitance element PCAP1 is not discharged.

[0052] As described above, the capacitance value of the first capacitance element PCAP0 is adjusted so that the bit line (here, BLT) of the first memory bank 21 is at an optimum negative potential, so that data is normally written to the memory cells MC to be written to in the first memory bank 21. In addition, erroneous writing to memory cells MC that are not the target of writing can be prevented.

[0053] (Write operation to second memory bank) Next, we will explain the operation when writing 'L' to BLB[0] of memory cell MC (write target) in the bottom row (corresponding to WL[0] in Figure 1) of the second memory bank and in the leftmost column of column c (corresponding to CAD[0] in Figure 3).

[0054] In the initial state, the NWTA signal is 'H', and the WRITET signal, WRITEB signal, PCGT signal, PCGB signal and CAD[0] are 'L'.

[0055] Since the PCGB signal is 'L', both BLB[0] and NBLB[0] are precharged to 'H'. In Fig. 4, BLB[0] is indicated by a thick solid line, and NBLB[0] is indicated by a thin solid line.

[0056] Since the NWTA signal is 'H', the internal ground signal WGND becomes 'L (0 V)' by the transistor TDN0, and the sources / drains of the first capacitance element PCAP0 and the second capacitance element PCAP1 are charged to 'H'. Also, WD[0] = 'L' and NWD[0] = 'H' are input as write data.

[0057] First, the control signals WL[0], PCGB signal, WRITEB signal, and CAD[0] rise from 'L' to 'H'.

[0058] When the WRITEB signal rises from 'L' to 'H', the gates of transistor TP10 and transistor TN6 go to 'H'. Since NWD[0] = 'H', the gates of transistor TP8 and transistor TN4 go to 'L'. Also, since CAD[0] = 'H', the source of transistor TP8 is 'H'. Therefore, the gate of transistor TN10 goes to 'H'. Then, since the internal ground signal WGND is 'L (0V)', the bit line BLB[0] falls from 'H' to 'L'.

[0059] Here, the timing of the NWTA signal is adjusted so that it falls from 'H' to 'L' when the bit line BLB[0] has fallen sufficiently to the ground potential VSS. Therefore, after the bit line BLB[0] has fallen to the ground potential VSS, the NWTA signal changes from 'H' to 'L', the transistor TDN0 is turned off, and the internal ground signal WGND is set to a floating state at the ground potential VSS.

[0060] Furthermore, when the NWTA signal changes from 'H' to 'L', the NWACP0 signal changes from 'H' to 'L', and the source / drain of the first capacitance element PCAP0 is discharged. Also, since the WRITEB signal is 'H', when the NWTA signal changes from 'H' to 'L', the NWACP1 signal also changes from 'H' to 'L', and the source / drain of the second capacitance element PCAP1 is discharged. In other words, the sources / drains of the first capacitance element PCAP0 and the second capacitance element PCAP1 are discharged, and as a result, the internal ground signal WGND becomes a negative potential.

[0061] As described above, the capacitance value of the second capacitance element PCAP1 is adjusted so that the bit line (here, BLB) of the second memory bank 22 is at an optimum negative potential when the capacitance value of the first capacitance element PCAP0 and the capacitance value of the second capacitance element PCAP1 are added together, so that data can be successfully written to the memory cells MC to be written to in the second memory bank 22. In addition, erroneous writing to memory cells MC that are not to be written to can be prevented.

[0062] As described above, according to this embodiment, when writing to memory cells MC in the first memory bank 21, only the first capacitance element PCAP0 is activated to set the low-potential side bit line (BLT in the example of FIG. 4) to a negative potential. Furthermore, when writing to memory cells MC in the second memory bank 22, which has a greater number of rows than the first memory bank 21, both the first capacitance element PCAP0 and the second capacitance element PCAP1 set the low-potential side bit line (BLB in the example of FIG. 4) to a negative potential. This ensures optimal write assist levels for write operations to each of the first memory bank 21 and the second memory bank 22. This allows for normal writing to memory cells MC that are the target of writing, while preventing erroneous writing to memory cells MC that are not the target of writing.

[0063] According to the present disclosure, in a semiconductor memory device with a multi-bank configuration, even if the bank sizes are different, it is possible to achieve an optimal write assist level and normal writing with a small-area circuit, which is extremely useful.

[0064] REFERENCE SIGNS LIST 1 Semiconductor memory device 2 Memory cell array 21 First memory bank 22 Second memory bank 30 Write circuit PCAP0 First capacitance element PCAP1 Second capacitance element WL Word line BL Bit line NBL Bit line TBL Bit line pair NWACP0 Negative potential boost signal NWACP1 Negative potential boost signal

Claims

1. A semiconductor memory device comprising: a memory cell array including a first memory bank and a second memory bank, each having a plurality of memory cells, the plurality of memory cells being connected to corresponding word lines and bit line pairs, the number of word lines of the first memory bank being fewer than the number of word lines of the second memory bank; and a write circuit having the function of setting one bit line of a bit line pair connected to a memory cell to be written to a low potential, and setting the low potential side bit line to a negative potential by a capacitance connected to an internal ground line in response to a negative potential boost signal, the capacitance comprising a first capacitive element and a second capacitive element each connected to the internal ground line, the low potential side bit line being set to a negative potential by only the first capacitive element when writing to a memory cell of the first memory bank, and the low potential side bit line being set to a negative potential by both the first capacitive element and the second capacitive element when writing to a memory cell of the second memory bank.

2. A semiconductor memory device according to claim 1, wherein said write circuit selects a memory cell to be written to based on a column select signal.

3. A semiconductor memory device according to claim 1, wherein the first capacitance element and the second capacitance element are formed of MOS transistors.

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