Transformer chip and signal transmission device

Abstract

In the present invention, a transformer chip includes: an insulating body that is provided on a substrate; an isolation transformer; a first connection electrode and a second connection electrode; a first capacitor; a second capacitor; and a connection portion. The isolation transformer has a first transformer that includes a first coil and a second coil that are arranged with a first insulating layer of the insulating body interposed therebetween, and a second transformer that includes a third coil and a fourth coil that are arranged with the first insulating layer interposed therebetween. The first connection electrode and the second connection electrode are electrically connected to the isolation transformer. The first capacitor is electrically connected to the first connection electrode. The second capacitor is electrically connected to the second connection electrode. The connection portion electrically connects the first capacitor and the second capacitor to the substrate.

Description

Trans chip, signal transmission device

[0001] The present disclosure relates to a transformer chip, a signal transmission device.

[0002] An example of a signal transmission device is an insulated gate driver that applies a gate voltage to the gate of a switching element such as a transistor. An example of an insulated chip used in such a gate driver is a structure including a first coil and a second coil disposed in an element insulating layer opposite each other in the thickness direction of the element insulating layer (see, for example, Patent Document 1).

[0003] JP 2018-78169 A

[0004] However, in the insulating chips described above, there are cases where an improvement in the dielectric strength is required.

[0005] a first transformer including a first coil and a second coil arranged on either side of the first insulating layer and capable of being magnetically coupled in the thickness direction of the first insulating layer; and a second transformer including a third coil and a fourth coil arranged on either side of the first insulating layer and capable of being magnetically coupled in the thickness direction of the first insulating layer, the second transformer being electrically connected to the first transformer; first and second connection electrodes electrically connected to the isolation transformer and used for electrical connection with an external device; a first capacitor electrically connected to the first connection electrode; a second capacitor electrically connected to the second connection electrode and electrically connected in series with the first capacitor; and a connection portion electrically connecting the first capacitor and the second capacitor to the substrate.

[0006] and a third die pad insulated from both the first die pad and the second die pad and having the transformer chip mounted thereon, the third die pad being insulated from both the first die pad and the second die pad and having the transformer chip mounted thereon, wherein the transformer chip is made of a conductive substrate, an insulator provided on the substrate and including a first insulating layer disposed parallel to the substrate, and a third die pad disposed on either side of the first insulating layer and having a magnetic field in a thickness direction of the first insulating layer. an isolation transformer including: a first transformer including a first coil and a second coil arranged to be coupled to each other; and a second transformer including a third coil and a fourth coil arranged on either side of the first insulating layer and arranged to be magnetically coupled to each other in the thickness direction of the first insulating layer, the second transformer being electrically connected to the first transformer; first and second connection electrodes electrically connected to the isolation transformer and used for electrical connection to an external device; a first capacitor electrically connected to the first connection electrode; a second capacitor electrically connected to the second connection electrode and electrically connected in series to the first capacitor; and a connection portion electrically connecting the first capacitor and the second capacitor to the substrate.

[0007] According to the transformer chip and the signal transmission device of one aspect of the present disclosure, it is possible to improve the dielectric strength voltage.

[0008] FIG. 1 is a circuit diagram schematically showing the circuit configuration of a signal transmission device of one embodiment. FIG. 2 is a schematic cross-sectional view of a signal transmission device of one embodiment. FIG. 3 is a schematic plan view of the transformer chip of FIG. 2. FIG. 4 is a schematic plan view of the transformer chip of FIG. 2 at a position different from that of FIG. 3. FIG. 5 is a schematic cross-sectional view of the transformer chip of FIG. 2. FIG. 6 is a schematic cross-sectional view of a signal transmission device of a comparative example. FIG. 7 is a schematic cross-sectional view of a signal transmission device of a modified example. FIG. 8 is a schematic cross-sectional view of a signal transmission device of a modified example. FIG. 9 is a circuit diagram schematically showing the circuit configuration of a signal transmission device of a modified example.

[0009] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and are not used to rank the objects.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] The phrase "at least one" as used herein means "one or more" of the desired options. As an example, the phrase "at least one" as used herein means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used herein means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0012] (Schematic Configuration of Signal Transmission Device) The schematic configuration of a signal transmission device 10 according to one embodiment will be described with reference to Figures 1 and 2. Figure 1 shows a simplified example of the circuit configuration of the signal transmission device 10. Figure 2 shows an example of a schematic cross-sectional structure showing a portion of the internal configuration of the signal transmission device 10. Note that hatched lines are omitted in Figure 2 for convenience.

[0013] As shown in Fig. 1, a signal transmission device 10 is a device that transmits a signal while electrically isolating a primary terminal 11 and a secondary terminal 12. The signal transmission device 10 is, for example, a digital isolator. The signal transmission device 10 includes a signal transmission circuit 10A having a primary circuit 13 electrically connected to the primary terminal 11, a secondary circuit 14 electrically connected to the secondary terminal 12, and a transformer 15 that electrically isolates the primary circuit 13 from the secondary circuit 14. The primary circuit 13 corresponds to the "first circuit," and the secondary circuit 14 corresponds to the "second circuit." The transformer 15 corresponds to the "isolation transformer."

[0014] The primary side circuit 13 is a circuit configured to operate when a first voltage V1 is applied. The secondary side circuit 14 is a circuit configured to operate when a second voltage V2 different from the first voltage V1 is applied. The first voltage V1 and the second voltage V2 are different voltages. For example, the first voltage V1 is higher than the second voltage V2. The first voltage V1 and the second voltage V2 are DC voltages. In this embodiment, the ground of the primary side circuit 13 and the ground of the secondary side circuit 14 are provided independently of each other.

[0015] The primary circuit 13 is electrically connected to, for example, a drive circuit (e.g., a switching circuit) that is to be controlled by the control device via the primary terminal 11. The secondary circuit 14 is electrically connected to, for example, an external control device (not shown) via the secondary terminal 12.

[0016] In the signal transmission circuit 10A, a control signal from the control device is input to a secondary circuit 14 via a secondary terminal 12. An output signal from the secondary circuit 14 is transmitted to a primary circuit 13 via a transformer 15. The signal transmitted to the primary circuit 13 is then output from the primary circuit 13 to a drive circuit via a primary terminal 11.

[0017] As described above, in the signal transmission circuit 10A, the primary circuit 13 and the secondary circuit 14 are electrically insulated from each other by the transformer 15. More specifically, the transformer 15 is configured to restrict the transmission of DC voltage between the primary circuit 13 and the secondary circuit 14 while allowing the transmission of pulse signals.

[0018] That is, the state in which the primary circuit 13 and the secondary circuit 14 are insulated means a state in which the transmission of DC voltage is blocked between the primary circuit 13 and the secondary circuit 14, but the transmission of pulse signals from the primary circuit 13 to the secondary circuit 14 is permitted. In this way, the primary circuit 13 is configured to perform at least one of transmitting and receiving signals with the secondary circuit 14.

[0019] The withstand voltage of the signal transmission device 10 is, for example, 5000 Vrms or more and 15000 Vrms or less. The withstand voltage of the signal transmission device 10 of this embodiment is approximately 10000 Vrms. However, the specific value of the withstand voltage of the signal transmission device 10 is not limited to this and can be any value.

[0020] (Details of the Signal Transmission Device) The signal transmission device 10 of this embodiment has one signal transmission path between the primary circuit 13 and the secondary circuit 14 via the transformer 15. The signal transmission device 10 includes primary signal lines 16A and 16B that connect the primary circuit 13 and the transformer 15, and secondary signal lines 17A and 17B that connect the transformer 15 and the secondary circuit 14. The transformer 15 transmits a first signal from the primary circuit 13 to the secondary circuit 14, while electrically insulating the primary circuit 13 from the secondary circuit 14.

[0021] The transformer 15 has a first transformer 21 and a second transformer 22 connected in series. In this embodiment, the first transformer 21 corresponds to a "first insulating element," and the second transformer 22 corresponds to a "second insulating element." The signal transmission device 10 includes a pair of connecting signal lines 18A, 18B that connect the first transformer 21 and the second transformer 22.

[0022] In this embodiment, the dielectric strength voltage of each of the transformers 21 and 22 is, for example, 2500 Vrms or more and 7500 Vrms or less. Note that the dielectric strength voltage of each of the transformers 21 and 22 may be 2500 Vrms or more and 5700 Vrms or less. However, the specific numerical values ​​of the dielectric strength voltage of each of the transformers 21 and 22 are not limited to these values ​​and can be any values.

[0023] The first transformer 21 has a first coil 23 and a second coil 24 that is electrically insulated from and magnetically coupleable with the first coil 23. The second transformer 22 has a third coil 25 and a fourth coil 26 that is electrically insulated from and magnetically coupleable with the third coil 25.

[0024] The first coil 23 is electrically connected to the primary circuit 13 via primary signal lines 16A and 16B. The second coil 24 is connected to the fourth coil 26 via a pair of connection signal lines 18A and 18B. In one example, the second coil 24 and the fourth coil 26 are connected to each other so as to be electrically floating. A first end of the second coil 24 and a first end of the fourth coil 26 are connected via a connection signal line 18A, and a second end of the second coil 24 and a second end of the fourth coil 26 are connected via a connection signal line 18B. The second coil 24 and the fourth coil 26 serve as relay coils that relay a first signal between the first coil 23 and the third coil 25. The third coil 25 is electrically connected to the secondary circuit 14 via secondary signal lines 17A and 17B.

[0025] (Internal Configuration of Signal Transmission Device) Fig. 2 shows an example of a schematic cross-sectional structure illustrating the internal configuration of a portion of the signal transmission device 10. As shown in Fig. 2, the signal transmission device 10 is a semiconductor device in which multiple semiconductor chips are packaged together. Although not shown, the package format of the signal transmission device 10 is, for example, an SO (Small Outline) type, and in this embodiment, an SOP (Small Outline Package). Note that the package format of the signal transmission device 10 can be changed as desired.

[0026] The signal transmission device 10 includes a first chip 40, a second chip 50, and a transformer chip 60 as multiple semiconductor chips. The signal transmission device 10 also includes a primary die pad 71 on which the first chip 40 is mounted, a secondary die pad 72 on which the second chip 50 is mounted, and an intermediate die pad 73 on which the transformer chip 60 is mounted. The intermediate die pad 73 is insulated from both the primary die pad 71 and the secondary die pad 72. The signal transmission device 10 also includes a sealing resin 90 that seals the die pads 71, 72, and 73 and the chips 40, 50, and 60. Here, in this embodiment, the transformer chip 60 corresponds to an "insulating chip." The primary die pad 71 corresponds to a "first die pad," the secondary die pad 72 corresponds to a "second die pad," and the intermediate die pad 73 corresponds to a "third die pad."

[0027] The sealing resin 90 is made of an electrically insulating material, such as a black epoxy resin, and is formed in the shape of a rectangular plate with its thickness aligned in the z direction.

[0028] The primary die pad 71, the secondary die pad 72, and the intermediate die pad 73 are formed of a conductive material. In this embodiment, the die pads 71, 72, and 73 are formed of a material containing Cu (copper). The die pads 71, 72, and 73 may also be formed of other metal materials such as Al (aluminum). The material constituting the die pads 71, 72, and 73 is not limited to a conductive material. For example, the die pads 71, 72, and 73 may also be formed of a ceramic such as alumina. In other words, the die pads 71, 72, and 73 may also be formed of an electrically insulating material.

[0029] When viewed from the z direction, the primary die pad 71, the intermediate die pad 73, and the secondary die pad 72 are arranged side by side and spaced apart from each other. The primary die pad 71, the intermediate die pad 73, and the secondary die pad 72 are electrically insulated from each other. Therefore, the intermediate die pad 73 is in an electrically floating state with respect to the primary die pad 71 and the secondary die pad 72. When viewed from the z direction, the arrangement direction of the primary die pad 71, the intermediate die pad 73, and the secondary die pad 72 is defined as the x direction. When viewed from the z direction, the direction perpendicular to the x direction is defined as the y direction. Here, the x direction corresponds to the "first direction," and the y direction corresponds to the "second direction."

[0030] The primary-side die pad 71, the intermediate die pad 73, and the secondary-side die pad 72 are formed in a flat plate shape. In this embodiment, the shape of each of the die pads 71, 72, and 73 when viewed from the z direction is rectangular with its short side in the x direction and its long side in the y direction. In this embodiment, the area of ​​the secondary-side die pad 72 when viewed from the z direction is larger than the area of ​​the primary-side die pad 71 when viewed from the z direction. Note that the shapes of each of the die pads 71, 72, and 73 when viewed from the z direction can be changed as desired. In one example, the shape of each of the die pads 71, 72, and 73 when viewed from the z direction may be rectangular with its long side in the x direction and its short side in the y direction.

[0031] In this embodiment, the transformer chip 60 is mounted on the intermediate die pad 73. That is, the first chip 40, the transformer chip 60, and the second chip 50 are mounted on the primary-side die pad 71, the intermediate die pad 73, and the secondary-side die pad 72, respectively, which are electrically insulated from one another. The first chip 40, the transformer chip 60, and the second chip 50 can be said to be arranged apart from one another in the x direction. In this embodiment, the first chip 40, the transformer chip 60, and the second chip 50 are arranged in this order from the primary-side die pad 71 toward the secondary-side die pad 72 in the x direction. In other words, the transformer chip 60 is arranged between the first chip 40 and the second chip 50 in the x direction. In this embodiment, the die pads 71, 72, and 73 are not exposed from the sealing resin 90.

[0032] In order to set the dielectric strength voltage of the signal transmission device 10 to a preset dielectric strength voltage, the die pads 71, 72, and 73 must be spaced apart from one another. In this embodiment, when viewed from the z direction, the distance between the primary die pad 71 and the intermediate die pad 73 in the x direction is equal to the distance between the intermediate die pad 73 and the secondary die pad 72 in the x direction. Therefore, when viewed from the z direction, the distance between the first chip 40 and the transformer chip 60 in the x direction is equal to the distance between the transformer chip 60 and the second chip 50 in the x direction. In other words, the transformer chip 60 is disposed midway between the first chip 40 and the second chip 50.

[0033] (First Chip) The first chip 40 has a rectangular shape having short and long sides when viewed from the z direction. When viewed from the z direction, the first chip 40 is mounted on the primary-side die pad 71 so that the short sides are aligned with the x direction and the long sides are aligned with the y direction.

[0034] The first chip 40 includes a first substrate 43 on which the primary-side circuit 13 is formed. The first substrate 43 is, for example, a semiconductor substrate. An example of a semiconductor substrate is a substrate formed from a material containing Si (silicon). A wiring layer 44 is formed on the first substrate 43. The wiring layer 44 has a plurality of insulating films stacked in the z direction, a metal layer provided between adjacent insulating films in the z direction, and vias that penetrate the insulating films in the z direction and are connected to the metal layer. The metal layer forms the wiring pattern of the first chip 40.

[0035] The first chip 40 has a chip main surface 40S and a chip back surface 40R that face opposite each other in the z direction. The first substrate 43 forms the chip back surface 40R, and the wiring layer 44 forms the chip main surface 40S. The chip back surface 40R faces the primary-side die pad 71. A plurality of first electrode pads 41 and a plurality of second electrode pads 42 are provided on the chip main surface 40S side of the first chip 40. More specifically, each of the electrode pads 41, 42 is provided so as to be exposed from the chip main surface 40S. Each of the electrode pads 41, 42 is electrically connected to the primary-side circuit 13 by the wiring layer 44.

[0036] The multiple first electrode pads 41 are arranged on the chip main surface 40S on the opposite side of the transformer chip 60 with respect to the center of the chip main surface 40S in the x direction. Although not shown, the multiple first electrode pads 41 are arranged spaced apart from each other in the y direction. The multiple second electrode pads 42 are arranged on the chip main surface 40S closer to the transformer chip 60 with respect to the center of the chip main surface 40S in the x direction. Although not shown, the multiple second electrode pads 42 are arranged spaced apart from each other in the y direction.

[0037] The first chip 40 is bonded to the primary die pad 71 by a first bonding material 81. More specifically, the first bonding material 81 is interposed between the chip back surface 40R and the primary die pad 71. The first bonding material 81 bonds the chip back surface 40R to the primary die pad 71. The first bonding material 81 is a conductive bonding material such as solder or Ag (silver) paste. The first bonding material 81 bonds the first substrate 43 of the first chip 40 to the primary die pad 71. This electrically connects the first substrate 43 to the primary die pad 71. Therefore, the primary circuit 13 is electrically connected to the primary die pad 71 via the first bonding material 81. The primary die pad 71 forms the ground of the primary circuit 13.

[0038] (Second Chip) The second chip 50 has a rectangular shape having short and long sides when viewed from the z direction. When viewed from the z direction, the second chip 50 is mounted on the secondary die pad 72 so that the short sides are aligned with the x direction and the long sides are aligned with the y direction.

[0039] The second chip 50 includes a second substrate 53 on which the secondary-side circuit 14 is formed. The second substrate 53 is, for example, a semiconductor substrate. An example of a semiconductor substrate is a Si substrate. A wiring layer 54 is formed on the second substrate 53. The wiring layer 54 has a plurality of insulating films stacked in the z direction, a metal layer provided between adjacent insulating films in the z direction, and vias that penetrate the insulating films in the z direction and are connected to the metal layer. The metal layer forms the wiring pattern of the second chip 50.

[0040] The second chip 50 has a chip main surface 50S and a chip back surface 50R facing opposite directions in the z direction. The second substrate 53 forms the chip back surface 50R, and the wiring layer 54 forms the chip main surface 50S. The chip back surface 50R faces the secondary-side die pad 72. The chip back surface 50R faces the same side as the chip back surface 40R of the first chip 40, and the chip main surface 50S faces the same side as the chip main surface 40S of the first chip 40. A plurality of first electrode pads 51 and a plurality of second electrode pads 52 are provided on the chip main surface 50S side of the second chip 50. More specifically, each of the electrode pads 51 and 52 is provided so as to be exposed from the chip main surface 50S. Each of the electrode pads 51 and 52 is electrically connected to the secondary-side circuit 14, for example, by the wiring layer 54.

[0041] The multiple first electrode pads 51 are arranged on the chip main surface 50S closer to the transformer chip 60 than the center of the chip main surface 50S in the x direction. Although not shown, the multiple first electrode pads 51 are arranged spaced apart from each other in the y direction. The multiple second electrode pads 52 are arranged on the chip main surface 50S on the opposite side of the transformer chip 60 than the center of the chip main surface 50S in the x direction. Although not shown, the multiple second electrode pads 52 are arranged spaced apart from each other in the y direction.

[0042] The second chip 50 is bonded to the secondary die pad 72 by a second bonding material 82. More specifically, the second bonding material 82 is interposed between the chip back surface 50R and the secondary die pad 72. The second bonding material 82 bonds the chip back surface 50R and the secondary die pad 72. The second bonding material 82 is a conductive bonding material such as solder or Ag paste. In this embodiment, the second bonding material 82 is made of the same material as the first bonding material 81. The second bonding material 82 bonds the second substrate 53 of the second chip 50 to the secondary die pad 72. This electrically connects the second substrate 53 to the secondary die pad 72. Therefore, the secondary circuit 14 is electrically connected to the secondary die pad 72 via the second bonding material 82. The secondary die pad 72 forms the ground of the secondary circuit 14.

[0043] (Transformer Chip) The shape of the transformer chip 60 is a rectangle having short and long sides when viewed from the z direction. In this embodiment, when viewed from the z direction, the transformer chip 60 is mounted on the secondary die pad 72 so that the long sides are aligned with the y direction and the short sides are aligned with the x direction.

[0044] The transformer chip 60 includes a third substrate 63. The third substrate 63 is, for example, a semiconductor substrate. An example of a semiconductor substrate is a Si substrate. The transformer chip 60 includes an insulator 64 on the third substrate 63. The transformer chip 60 includes a transformer 15 (first transformer 21, second transformer 22). The transformer chip 60 also includes a first capacitor 31 and a second capacitor 32. The transformer 15, the first capacitor 31, and the second capacitor 32 are embedded in the insulator 64.

[0045] The transformer chip 60 has a chip main surface 60S and a chip back surface 60R that face opposite each other in the z direction. The chip back surface 60R faces the secondary die pad 72. In other words, the chip back surface 60R faces the same side as the chip back surface 50R of the second chip 50, and the chip main surface 60S faces the same side as the chip main surface 50S of the second chip 50.

[0046] The transformer chip 60 includes a plurality of first electrode pads 61 and a plurality of second electrode pads 62. Each of the first electrode pads 61 and each of the second electrode pads 62 is provided on the chip main surface 60S side. More specifically, when viewed from the z direction, each of the electrode pads 61, 62 is provided so as to be exposed from the chip main surface 60S.

[0047] The first electrode pads 61 are arranged on the chip main surface 60S closer to the first chip 40 than the center of the chip main surface 60S in the x direction. The second electrode pads 62 are arranged on the chip main surface 60S closer to the second chip 50 than the center of the chip main surface 60S in the x direction.

[0048] The first transformer 21 and the second transformer 22 of the transformer 15 are connected in series between the first electrode pad 61 and the second electrode pad 62. The first capacitor 31 and the second capacitor 32 are connected in series between the first electrode pad 61 and the second electrode pad 62. The first capacitor 31 and the second capacitor 32 are also electrically connected to a third substrate 63. The first electrode pad 61 corresponds to a "first connection electrode." The second electrode pad 62 corresponds to a "second connection electrode."

[0049] The transformer chip 60 is bonded to the intermediate die pad 73 by a third bonding material 83. More specifically, the third bonding material 83 is interposed between the chip back surface 60R and the intermediate die pad 73. The third bonding material 83 bonds the chip back surface 60R and the intermediate die pad 73. The third bonding material 83 is a conductive bonding material such as solder or Ag (silver) paste. The third bonding material 83 bonds the third substrate 63 of the transformer chip 60 to the intermediate die pad 73. This electrically connects the third substrate 63 and the intermediate die pad 73.

[0050] (Wires) A ​​plurality of wires W1 to W4 are connected to each of the first chip 40, the transformer chip 60, and the second chip 50. Each of the wires W1 to W4 is a bonding wire formed by a wire bonding device, and is made of a conductor such as Au (gold), Al, or Cu.

[0051] The first electrode pads 41 of the first chip 40 are individually connected to a plurality of primary leads (not shown) by a plurality of wires W1. The primary leads are components that constitute the primary terminals 11 in Fig. 1. This electrically connects the primary circuit 13 and the primary terminals 11.

[0052] The primary side lead is formed, for example, from the same material as the primary side die pad 71. The primary side lead and the primary side die pad 71 may be formed integrally. The primary side lead is arranged on the opposite side of the primary side die pad 71 from the secondary side die pad 72 with a gap therebetween, and is formed across the sealing resin 90. In other words, the primary side lead has a portion that protrudes outward from the sealing resin 90. The portion of the primary side lead that protrudes outward from the sealing resin 90 constitutes an external terminal of the signal transmission device 10.

[0053] The second electrode pads 42 of the first chip 40 are individually connected to the first electrode pads 61 of the transformer chip 60 by wires W2, thereby electrically connecting the primary circuit 13 and the first transformer 21. In other words, the wiring layer 44 of the first chip 40, the second electrode pads 42, the wires W2, and the first electrode pads 61 each constitute part of the primary signal lines 16A and 16B (see FIG. 1 ).

[0054] The second electrode pads 62 of the transformer chip 60 are individually connected to the first electrode pads 51 of the second chip 50 by wires W3, thereby electrically connecting the second transformer 22 and the secondary circuit 14. That is, the second electrode pads 62, the wires W3, and the first electrode pads 51 of the second chip 50 each constitute part of the secondary signal lines 17A and 17B (see FIG. 1 ).

[0055] The second electrode pads 52 of the second chip 50 are individually connected to a plurality of secondary leads (not shown) by a plurality of wires W4. The secondary leads are components that constitute the secondary terminals 12 in Fig. 1. This electrically connects the secondary circuit 14 and the secondary terminals 12.

[0056] The secondary-side lead is formed, for example, from the same material as the secondary-side die pad 72. The secondary-side lead and the secondary-side die pad 72 may be formed integrally. The secondary-side lead is disposed on the opposite side of the primary-side die pad 71 from the secondary-side die pad 72 at a distance, and is formed across the sealing resin 90. In other words, the secondary-side lead has a portion that protrudes outward from the sealing resin 90. The portion of the secondary-side lead that protrudes outward from the sealing resin 90 constitutes an external terminal of the signal transmission device 10.

[0057] (Configuration of Transformer Chip) An example of the configuration of the transformer chip 60 will be described with reference to FIGS. 3 to 5. FIG. 3 is a plan view that schematically shows the planar structure of the transformer chip 60. FIG. 4 is a cross-sectional view that schematically shows the cross-sectional structure of the interior of the transformer chip 60 cut along the xy plane. In FIG. 4, hatching lines are omitted to make the drawing easier to read. FIG. 5 is a cross-sectional view that schematically shows the cross-sectional structure of the transformer chip 60. Furthermore, the coils 23, 24, 25, and 26 shown in FIG. 5 are shown only schematically, and therefore do not match the configurations of the coils 23, 24, 25, and 26 shown in FIGS. 3 and 4.

[0058] 3 to 5, the transformer chip 60 is a single-chip version of the transformer 15. In other words, the transformer chip 60 is a dedicated chip for the transformer 15, provided separately from the first chip 40 and the second chip 50.

[0059] The transformer chip 60 includes a chip main surface 60S, a chip back surface 60R, and multiple chip side surfaces 601, 602, 603, and 604. The chip side surfaces 601 to 604 are perpendicular to both the chip main surface 60S and the chip back surface 60R. The chip side surfaces 601 and 602 constitute the end surfaces of the transformer chip 60 in the x direction. The chip side surfaces 603 and 604 constitute the end surfaces of the transformer chip 60 in the y direction. In this embodiment, the chip side surface 601 of the transformer chip 60 faces the first chip 40 shown in FIG. 2, and the chip side surface 602 of the transformer chip 60 faces the second chip 50 shown in FIG. 2. In the following description, the direction from the chip back surface 60R of the transformer chip 60 toward the chip main surface 60S is referred to as "upward," and the direction from the chip main surface 60S toward the chip back surface 60R is referred to as "downward."

[0060] (Substrate, Insulator) As shown in FIGS. 5 to 8, the transformer chip 60 includes a third substrate 63 and an insulator 64 disposed on the third substrate 63 .

[0061] The third substrate 63 has a substrate front surface 63S and a substrate back surface 63R facing opposite to each other in the z direction. The third substrate 63 is formed, for example, by a semiconductor substrate. In this embodiment, the third substrate 63 is a semiconductor substrate formed from a material containing Si. Note that the third substrate 63 may be formed from a wide bandgap semiconductor or a compound semiconductor. Furthermore, instead of a semiconductor substrate, the third substrate 63 may be formed from an insulating substrate formed from a material containing glass or a material containing ceramics such as alumina.

[0062] The wide bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or more. The wide bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0063] The insulator 64 includes a first insulating layer 641, a second insulating layer 642 provided on the first insulating layer 641, and a third insulating layer 643 provided below the first insulating layer 641. The first insulating layer 641 is disposed parallel to the third substrate 63. The first insulating layer 641 and the second insulating layer 642 are in contact with each other. The first insulating layer 641 and the third insulating layer 643 are in contact with each other. The third insulating layer 643 is in contact with the substrate surface 63S of the third substrate 63. In other words, the insulator 64 includes the third insulating layer 643, the first insulating layer 641, and the second insulating layer 642 stacked upward from the substrate surface 63S of the third substrate 63. The upper surface of the second insulating layer 642 constitutes the chip main surface 60S of the transformer chip 60 described above.

[0064] The first insulating layer 641 is formed of a material containing Si, for example. Examples of the material containing Si include SiO. ２ (silicon oxide), SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), etc. The first insulating layer 641 of this embodiment is composed of a plurality of insulating films 641A. Each of the plurality of insulating films 641A is composed of a thin film formed of a material including SiN, SiC, SiCN, etc., and a thin film formed of a material including SiO ２ The insulating films 641A may be formed as a single insulating film without being distinguished from one another.

[0065] The second insulating layer 642 is formed of, for example, a material containing Si. Examples of the material containing Si include SiO. ２ , SiN, SiC, SiCN, etc. The second insulating layer 642 of this embodiment is composed of a plurality of insulating films 642A. Each of the plurality of insulating films 642A is composed of a thin film formed of a material including SiN, SiC, SiCN, etc., and a thin film formed of a material including SiO ２ The second insulating layer 642 may be composed of an interlayer insulating film formed of a material containing polyimide (PI). The multiple insulating films 642A may be formed as a single insulating film without being distinguished from one another. The second insulating layer 642 may include a resin layer. The resin layer may be formed of a material containing polyimide (PI), for example.

[0066] The third insulating layer 643 is formed of, for example, a material containing Si. Examples of the material containing Si include SiO. ２ , SiN, SiC, SiCN, etc. The third insulating layer 643 of this embodiment is composed of a plurality of insulating films 643A. Each of the plurality of insulating films 643A is composed of a thin film formed of a material including SiN, SiC, SiCN, etc., and a thin film formed of a material including SiO ２ The insulating films 643A may be formed as a single insulating film without being distinguished from one another.

[0067] 3 to 5, the transformer chip 60 includes a transformer 15, a first capacitor 31, and a second capacitor 32. The transformer 15 includes a first transformer 21 and a second transformer 22.

[0068] 3 and 4, the first transformer 21 and the second transformer 22 are arranged side by side in the x direction on the insulator 64. Both the first transformer 21 and the second transformer 22 are arranged along the chip side surface 604. In other words, the first transformer 21 and the second transformer 22 are arranged spaced apart from each other in the x direction while being aligned with each other in the y direction. In other words, the first transformer 21 and the second transformer 22 are arranged spaced apart from each other in the arrangement direction of the die pads 71, 73, and 72 shown in FIG. 2.

[0069] The first capacitor 31 and the second capacitor 32 are arranged side by side in the x direction on the insulator 64. Both the first capacitor 31 and the second capacitor 32 are arranged along the chip side surface 603. In other words, the first capacitor 31 and the second capacitor 32 are arranged spaced apart from each other in the x direction while being aligned with each other in the y direction. In other words, the first capacitor 31 and the second capacitor 32 are arranged spaced apart from each other in the arrangement direction of the die pads 71, 73, and 72 shown in FIG. 2 .

[0070] As shown in FIGS. 3 to 5 , the first transformer 21 includes a first coil 23 and a second coil 24. The second transformer 22 includes a third coil 25 and a fourth coil 26. As shown in FIG. 3 , the first coil 23 includes a spiral coil portion 23A, a first end portion 23B extending inward from the inner circumferential end of the coil portion 23A, and a second end portion 23C extending outward from the outer circumferential end of the coil portion 23A. The first end portion 23B and the second end portion 23C of the first coil 23 are electrically connected to the primary circuit 13 shown in FIG. 1 . The first coil 23 is electrically connected to a first electrode pad 61. The first electrode pad 61 includes an electrode pad 61A electrically connected to the first end portion 23B of the first coil 23 and an electrode pad 61B electrically connected to the second end portion 23C of the first coil 23.

[0071] As shown in Fig. 3, the third coil 25 includes a spiral coil portion 25A, a first end portion 25B extending inward from the inner circumferential end of the coil portion 25A, and a second end portion 25C extending outward from the outer circumferential end of the coil portion 25A. The first end portion 25B and the second end portion 25C of the third coil 25 are electrically connected to the secondary circuit 14 shown in Fig. 1. The third coil 25 is electrically connected to a second electrode pad 62. The second electrode pad 62 includes an electrode pad 62A electrically connected to the first end portion 25B of the third coil 25 and an electrode pad 62B electrically connected to the second end portion 25C of the third coil 25.

[0072] 4, the second coil 24 and the fourth coil 26 have spiral coil portions 24A and 26A, respectively. The coil portion 24A of the second coil 24 and the coil portion 26A of the fourth coil 26 are electrically connected to each other by wiring 65C and 65D.

[0073] 5 , the first coil 23 and the second coil 24 are arranged with a first insulating layer 641 sandwiched therebetween. The first coil 23 and the second coil 24 are arranged so as to be magnetically coupled in the thickness direction (z direction) of the first insulating layer 641. The first coil 23 is arranged in a second insulating layer 642 on the first insulating layer 641. The second coil 24 is arranged in a third insulating layer 643 below the first insulating layer 641. In this embodiment, the first coil 23 and the second coil 24 are in contact with the first insulating layer 641.

[0074] The first coil 23 is electrically connected to the first electrode pad 61B by a wiring 65A. Similarly, the third coil 25 is electrically connected to the second electrode pad 62B by a wiring 65B. The first coil 23 is electrically connected to the first electrode pad 61A shown in FIG. 3 by a wiring not shown. Similarly, the fourth coil 26 is electrically connected to the second electrode pad 62A shown in FIG. 3 by a wiring not shown.

[0075] The third coil 25 and the fourth coil 26 are arranged with the first insulating layer 641 sandwiched therebetween. The third coil 25 and the fourth coil 26 are arranged so as to be magnetically coupled in the thickness direction (z direction) of the first insulating layer 641. The third coil 25 is arranged in a second insulating layer 642 on the first insulating layer 641. The fourth coil 26 is arranged in a third insulating layer 643 below the first insulating layer 641. In this embodiment, both the third coil 25 and the fourth coil 26 are in contact with the first insulating layer 641.

[0076] The first coil 23, the second coil 24, the third coil 25, and the fourth coil 26 are made of one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), Au, Ag, Cu, Al, and tungsten (W). In this embodiment, each of the coils 23 to 26 is made of a material containing Cu. The wiring 65A to 65D are made of one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), Au, Ag, Cu, Al, and tungsten (W). In this embodiment, each of the wiring 65A to 65D is made of a material containing Cu.

[0077] 3 to 5 , the first capacitor 31 includes a first electrode plate 33 and a second electrode plate 34. In this embodiment, both the first electrode plate 33 and the second electrode plate 34 are formed in a rectangular shape when viewed from the z direction. Note that both the first electrode plate 33 and the second electrode plate 34 can have any shape when viewed from the z direction, such as a circle, an ellipse, or a polygon. The first electrode plate 33 and the second electrode plate 34 have the same size when viewed from the z direction and are arranged to overlap each other.

[0078] The second capacitor 32 includes a third electrode plate 35 and a fourth electrode plate 36. In this embodiment, both the third electrode plate 35 and the fourth electrode plate 36 are formed in a rectangular shape when viewed from the z direction. The shapes of both the third electrode plate 35 and the fourth electrode plate 36 when viewed from the z direction can be any shape, such as a circle, an ellipse, or a polygon. The third electrode plate 35 and the fourth electrode plate 36 have the same size when viewed from the z direction and are arranged to overlap each other. Furthermore, both the third electrode plate 35 and the fourth electrode plate 36 have the same shape and size as the first electrode plate 33 and the second electrode plate 34 when viewed from the z direction.

[0079] 3 and 5, the first electrode plate 33 of the first capacitor 31 is electrically connected to the first electrode pad 61B by a wiring 66A. The third electrode plate 35 of the second capacitor 32 is electrically connected to the second electrode pad 62B by a wiring 66B. As shown in Fig. 4, the second electrode plate 34 of the first capacitor 31 and the fourth electrode plate 36 of the second capacitor 32 are electrically connected to each other by a wiring 66C. As shown in Fig. 5, they are electrically connected to the third substrate 63 by wirings 66C and 66D.

[0080] The first electrode plate 33, the second electrode plate 34, the third electrode plate 35, and the fourth electrode plate 36 are made of one or more of Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Au, Ag, Cu, Al, and W (tungsten). In this embodiment, each of the electrode plates 33 to 36 is made of a material containing Cu. The wiring 66A to 66D are made of one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W. In this embodiment, each of the wiring 66A to 66D is made of a material containing Cu.

[0081] 5 , the first electrode plate 33 and the second electrode plate 34 of the first capacitor 31 are disposed with a first insulating layer 641 sandwiched therebetween. The first electrode plate 33 and the second electrode plate 34 are disposed so as to be magnetically coupled in the thickness direction of the first insulating layer 641. The first electrode plate 33 is disposed in a second insulating layer 642 on the first insulating layer 641. The second electrode plate 34 is disposed in a third insulating layer 643 below the first insulating layer 641. In this embodiment, the first electrode plate 33 and the second electrode plate 34 are in contact with the first insulating layer 641. The first electrode plate 33 is electrically connected to the first electrode pad 61 by a wiring 66A.

[0082] The third electrode plate 35 and the fourth electrode plate 36 are disposed with a first insulating layer 641 sandwiched therebetween. The third electrode plate 35 and the fourth electrode plate 36 are disposed so as to be magnetically coupled in the thickness direction of the first insulating layer 641. The third electrode plate 35 is disposed in a second insulating layer 642 above the first insulating layer 641. The fourth electrode plate 36 is disposed in a third insulating layer 643 below the first insulating layer 641. In this embodiment, both the third electrode plate 35 and the fourth electrode plate 36 are in contact with the first insulating layer 641. The third electrode plate 35 is electrically connected to the second electrode pad 62 by a wiring 66B.

[0083] The first electrode plate 33 and the second electrode plate 34 have the same size when viewed from the z direction and are arranged to overlap each other. Therefore, the first capacitor 31 has a capacitance value determined by the area of ​​each of the first electrode plate 33 and the second electrode plate 34 when viewed from the z direction and the distance between the first electrode plate 33 and the second electrode plate 34 (thickness T1 of the first insulating layer 641).

[0084] The third electrode plate 35 and the fourth electrode plate 36 have the same size when viewed from the z direction and are arranged to overlap each other. Therefore, the first capacitor 31 has a capacitance value determined by the area of ​​each of the first electrode plate 33 and the second electrode plate 34 when viewed from the z direction and the distance between the first electrode plate 33 and the second electrode plate 34 (thickness T1 of the first insulating layer 641).

[0085] Furthermore, when viewed from the z direction, both the third electrode plate 35 and the fourth electrode plate 36 have the same shape and size as the first electrode plate 33 and the second electrode plate 34. Therefore, the first capacitor 31 and the second capacitor 32 have the same capacitance value.

[0086] Next, an example of the dimensional relationship in the transformer chip 60 will be described with reference to FIG. 5 . The first coil 23 and the fourth coil 26 are disposed at the same position in the thickness direction of the insulator 64. The second coil 24 and the third coil 25 are disposed at the same position in the thickness direction of the insulator 64. The distance D1 between the first coil 23 of the first transformer 21 and the third coil 25 of the second transformer 22 is greater than the distance D2 between the first coil 23 and the second coil 24. The distance D1 between the first coil 23 and the third coil 25 is greater than the distance D3 between the third coil 25 and the fourth coil 26. The distance D1 between the first coil 23 and the third coil 25 is greater than the distance D4 between the third substrate 63 and the second coil 24. The distance D1 between the first coil 23 and the third coil 25 is greater than the distance D5 between the third substrate 63 and the fourth coil 26. The distance D6 between the second coil 24 and the second electrode plate 34 is equal to or greater than the distance D4 between the third substrate 63 and the second coil 24. The distance D7 between the fourth coil 26 and the fourth electrode plate 36 is equal to or greater than the distance D5 between the third substrate 63 and the fourth coil 26.

[0087] (Function) The function of the signal transmission device 10 of this embodiment will be described. Figure 6 is a schematic cross-sectional view showing a signal transmission device 10X including a transformer chip 60X of a comparative example. In the transformer chip 60X and signal transmission device 10X of the comparative example, the same components as those in the transformer chip 60 and signal transmission device 10 of the above embodiment are designated by the same reference numerals.

[0088] The transformer chip 60X of the comparative example does not include the first capacitor 31 and the second capacitor 32, as compared with the transformer chip 60 of the above embodiment. In the signal transmission device 10X shown in FIG. 6 , the transformer chip 60X of the comparative example is mounted on an intermediate die pad 73, similar to the signal transmission device 10 of the above embodiment. The intermediate die pad 73 and the third substrate 63 electrically connected to the intermediate die pad 73 are in a floating state with respect to the first chip 40, the second chip 50, the primary die pad 71, and the secondary die pad 72.

[0089] When the transformer chip 60X of the comparative example is mounted on the primary die pad 71, the potential of the third substrate 63 becomes equal to the potential of the first substrate 43 of the first chip 40 mounted on the primary die pad 71. Therefore, in the transformer chip 60X of the comparative example, the distance between the third substrate 63 and the second transformer 22 (third coil 25) is required depending on the potential difference between the primary circuit 13 and the secondary circuit 14, i.e., the dielectric strength voltage. To increase the dielectric strength voltage of the transformer chip 60X, it is necessary to increase the distance between the third substrate 63 and the second transformer 22 (third coil 25), i.e., to increase the thickness of the insulator 64. The thickness of the insulator 64 affects changes in the manufacturing process (steps) of the transformer chip 60X and warpage of the third substrate 63 (semiconductor wafer) during manufacturing. The thicker the insulator 64, the more steps are required and the greater the warpage. Therefore, there is a limit to how thick the insulator 64 can be. The same problem occurs when the transformer chip 60X of the comparative example is mounted on the secondary die pad 72.

[0090] 6 , the transformer chip 60X is mounted on an intermediate die pad 73 that is electrically isolated from the primary die pad 71 and the secondary die pad 72. The intermediate die pad 73 is in a floating state with respect to the primary die pad 71 and the secondary die pad 72. Therefore, the transformer chip 60X of the comparative example can improve the dielectric strength without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25.

[0091] However, in the transformer chip 60X and signal transmission device 10X of the comparative example, the intermediate die pad 73 and the third substrate 63 are in an electrically floating state. Therefore, the potential of the intermediate die pad 73 may be affected by the potential of the primary die pad 71. In this case, the situation is the same as when the transformer chip 60X of the comparative example is mounted on the primary die pad 71. In other words, the third substrate 63 has the potential of the first chip, which may exceed the dielectric strength voltage of the transformer chip 60X.

[0092] The transformer chip 60 of this embodiment is mounted on an intermediate die pad 73 that is electrically isolated from the primary die pad 71 and the secondary die pad 72. Therefore, similar to the transformer chip 60X of the comparative example shown in Figure 6, the dielectric strength can be improved without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25.

[0093] The transformer chip 60 of this embodiment includes a first capacitor 31 electrically connected to a first electrode pad 61, and a second capacitor 32 electrically connected to a second electrode pad 62 and electrically connected in series with the first capacitor 31. The first capacitor 31 and the second capacitor 32 are electrically connected to a third substrate 63 by wirings 66C and 66D serving as connecting portions.

[0094] The first electrode pad 61 is electrically connected to the first chip 40. The second electrode pad 62 is electrically connected to the second chip 50. Therefore, the potential of the third substrate 63 is between the potential of the first electrode pad 61 and the potential of the second electrode pad 62. In the above embodiment, the capacitance value of the first capacitor 31 and the capacitance value of the second capacitor 32 are equal to each other. Therefore, the potential of the third substrate 63 is an intermediate potential (½) between the potential of the first electrode pad 61 and the potential of the second electrode pad 62. In other words, in this embodiment, the third substrate 63 of the transformer chip 60 is not in a floating state, but is at a potential between the voltages applied to the first electrode pad 61 and the second electrode pad 62.

[0095] 2 , the potential of the third substrate 63 and intermediate die pad 73 of the transformer chip 60 is the potential between the first chip 40 (primary circuit 13) and the second chip 50 (secondary circuit 14) connected to the first electrode pads 61. This makes it less susceptible to the potential of the primary die pad 71 on which the first chip 40, which is on the high-voltage side, is mounted. Therefore, the transformer chip 60 of this embodiment can improve the dielectric strength without increasing the distance between the third substrate 63 and the first coil 23 and third coil 25.

[0096] As described above, this embodiment provides the following advantages: (1) The transformer chip 60 is mounted on the intermediate die pad 73 that is electrically isolated from the primary die pad 71 and the secondary die pad 72. Therefore, the withstand voltage can be improved without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25.

[0097] (2) In the signal transmission device 10, the potential of the third substrate 63 and intermediate die pad 73 of the transformer chip 60 is the potential between the first chip 40 (primary circuit 13) and the second chip 50 (secondary circuit 14) connected to the first electrode pads 61. This makes it less susceptible to the potential of the primary die pad 71 on which the first chip 40, which is on the high-voltage side, is mounted. This allows the transformer chip 60 to improve its dielectric strength without increasing the distance between the third substrate 63 and the first coil 23 and third coil 25.

[0098] (Modifications) The above embodiment can be modified, for example, as follows. The above embodiment and each of the following modifications can be combined with each other as long as no technical contradiction occurs. In the following modifications, parts that are common to the above embodiment will be assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0099] The configuration of the transformer chip 60 of the above embodiment can be modified as needed. In the transformer chip 60A of the signal transmission device 110 shown in FIG. 7 , the first capacitor 31 and the second capacitor 32 are electrically connected to the third substrate 63 via wiring 67A and 67B, respectively. Specifically, the second electrode plate 34 of the first capacitor 31 is electrically connected to the third substrate 63 via wiring 67A. The fourth electrode plate 36 of the second capacitor 32 is electrically connected to the third substrate 63 via wiring 67B. In other words, the first capacitor 31 and the second capacitor 32 are connected to each other via the third substrate 63 and the wiring 67A and 67B. Even in the transformer chip 60A configured in this manner, the potential of the third substrate 63 can be set to an intermediate voltage between the voltages applied to the first electrode pad 61B and the second electrode pad 62B, respectively. This improves the dielectric strength of the transformer chip 60A.

[0100] In the transformer chip 60B of the signal transmission device 112 shown in FIG. 8, first and second electrode pads 61B and 62B, corresponding to the first and second connection electrodes, are disposed on the upper surface 641S of a first insulating layer 641. The first and second electrode pads 61B and 62B are in contact with the first insulating layer 641. The transformer chip 60B also includes a first opposing electrode 68A facing the first electrode pad 61B across the first insulating layer 641, and a second opposing electrode 68B facing the second electrode pad 62B across the first insulating layer 641. The first opposing electrode 68A and the second opposing electrode 68B are electrically connected to each other by a wiring 66C. The wiring 66C is connected to the third substrate 63 by a wiring 66D. The first capacitor 31 is formed by the first electrode pad 61B and the first opposing electrode 68A, sandwiching the first insulating layer 641. The second capacitor 32 is composed of the second electrode pad 62B and the second opposing electrode 68B sandwiching the first insulating layer 641. In the transformer chip 60B configured in this manner, the potential of the third substrate 63 can also be set to an intermediate voltage between the voltages applied to the first electrode pad 61B and the second electrode pad 62B, respectively. This improves the dielectric strength of the transformer chip 60B.

[0101] Multiple transformers may be provided between the primary circuit 13 and the secondary circuit 14. A signal transmission device 114 (signal transmission circuit 114A) shown in FIG. 9 has two transformers 15A and 15B between the primary circuit 13 and the secondary circuit 14. The two transformers 15A and 15B have the same configuration as the transformer 15 of the above embodiment and each include a first transformer 21 and a second transformer 22. These two transformers 15A and 15B are used, for example, to transmit a signal from the secondary circuit 14 to the primary circuit 13. Note that the two transformers 15A and 15B may also be used to transmit a signal from the primary circuit 13 to the secondary circuit 14. Alternatively, the transformer 15A may be used to transmit a signal from the secondary circuit 14 to the primary circuit 13, and the transformer 15B may be used to transmit a signal from the primary circuit 13 to the secondary circuit 14. The two transformers 15A and 15B may be configured as two of the transformer chips 60 of the above embodiment, or as a single transformer chip. Note that three or more transformers may be provided between the primary side circuit 13 and the secondary side circuit 14.

[0102] The term "on" as used in this disclosure includes both the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0103] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0104] (Supplementary Notes) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the Supplementary Notes are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples to aid understanding, and the components described in each Supplementary Note should not be limited to the components indicated by the reference symbols.

[0105] (Supplementary Note 1) An isolation transformer (15) including: a conductive substrate (63); an insulator (64) provided on the substrate (63) and including a first insulating layer (641) arranged parallel to the substrate (63); a first transformer (21) including a first coil (23) and a second coil (24) arranged across the first insulating layer (641) and capable of magnetic coupling in the thickness direction of the first insulating layer (641); and a second transformer (22) including a third coil (25) and a fourth coil (26) arranged across the first insulating layer (641) and capable of magnetic coupling in the thickness direction of the first insulating layer (641), and electrically connected to the first transformer (21); a first connection electrode (61B) and a second connection electrode (62B) electrically connected to the isolation transformer (15) and used for electrical connection with the outside; and a first capacitor (31) electrically connected to the first connection electrode (61B). a second capacitor (32) electrically connected to the second connection electrode (62B) and electrically connected in series with the first capacitor (31); and connection portions (66C, 66D, 67A, 67B) electrically connecting the first capacitor (31) and the second capacitor (32) to the substrate (63).

[0106] (Supplementary Note 2) The transformer chip according to Supplementary Note 1, wherein the first capacitor (31) and the second capacitor (32) are formed to have the same capacitance.

[0107] (Supplementary Note 3) The transformer chip according to Supplementary Note 1 or Supplementary Note 2, wherein the first capacitor (31) includes a first electrode plate (33) provided in the insulator (64) and electrically connected to the first connection electrode (61B), and a second electrode plate (34) provided in the insulator (64) and arranged opposite the first electrode plate (33) via the first insulating layer (641); the second capacitor (32) includes a third electrode plate (35) provided in the insulator (64) and electrically connected to the second connection electrode (62B), and a fourth electrode plate (36) provided in the insulator (64) and arranged opposite the third electrode plate (35) via the first insulating layer (641); and the connection portions (66C, 66D, 67A, 67B) connect the second electrode plate (34) and the fourth electrode plate (36) to the substrate (63).

[0108] (Supplementary Note 4) The transformer chip according to Supplementary Note 1 or Supplementary Note 2, wherein the first capacitor (31) is composed of the first connection electrode (61B) and a first opposing electrode (68A) provided in a position opposite the first connection electrode (61B) via the first insulating layer (641) in the insulator (64), the second capacitor (32) is composed of the second connection electrode (62B) and a second opposing electrode (68B) provided in a position opposite the second connection electrode (62B) via the first insulating layer (641) in the insulator (64), and the connection portions (66C, 66D) connect the first opposing electrode (68A) and the second opposing electrode (68B) to the substrate (63).

[0109] (Appendix 5) A transformer chip described in any one of appendices 1 to 4, wherein the first coil (23) is connected to the first connection electrode (61B), the third coil (25) is connected to the second connection electrode (62B), and the second coil (24) and the fourth coil (26) are connected to each other.

[0110] (Appendix 6) A transformer chip described in any one of Appendixes 1 to 5, wherein the insulator (64) includes a second insulating layer (642) above the first insulating layer (641) and a third insulating layer (643) below the first insulating layer (641), the first coil (23) and the third coil (25) are arranged in the second insulating layer (642), and the second coil (24) and the fourth coil (26) are arranged in the third insulating layer (643).

[0111] (Supplementary Note 7) A semiconductor device includes a first chip (40) including a first circuit (13), a transformer chip (60), a second chip (50) including a second circuit (14) configured to transmit and receive signals to and from the first circuit (13) through the transformer chip (60), a first die pad (71) on which the first chip (40) is mounted, a second die pad (72) on which the second chip (50) is mounted, and a third die pad (73) insulated from both the first die pad (71) and the second die pad (72) and on which the transformer chip (60) is mounted, wherein the transformer chip (60) includes: a conductive substrate (63), and an insulator (64) provided on the substrate (63) and including a first insulating layer (641) arranged parallel to the substrate (63), an isolation transformer (15) having: a first transformer (21) including a first coil (23) and a second coil (24) arranged across the first insulating layer (641) and arranged so as to be magnetically coupled in the thickness direction of the first insulating layer (641); and a second transformer (22) including a third coil (25) and a fourth coil (26) arranged across the first insulating layer (641) and arranged so as to be magnetically coupled in the thickness direction of the first insulating layer (641), and electrically connected to the first transformer (21); a first connection electrode (61B) and a second connection electrode (62B) electrically connected to the isolation transformer (15) and used for electrical connection with the outside; a first capacitor (31) electrically connected to the first connection electrode (61B); and a second capacitor (32) electrically connected to the second connection electrode (62B) and electrically connected in series with the first capacitor (31); a connection portion that electrically connects the first capacitor (31) and the second capacitor (32) to the substrate (63).

[0112] (Supplementary Note 8) The signal transmission device according to Supplementary Note 7, wherein the transformer chip (60) is electrically connected to the third die pad (73) by a conductive bonding material (83).

[0113] (Supplementary Note 9) The signal transmission device according to Supplementary Note 7 or Supplementary Note 8, wherein the first capacitor (31) and the second capacitor (32) are formed to have the same capacitance.

[0114] (Supplementary Note 10) The signal transmission device according to any one of Supplementary Note 7 to Supplementary Note 9, wherein the first capacitor (31) includes a first electrode plate (33) provided in the insulator (64) and electrically connected to the first connection electrode (61B), and a second electrode plate (34) provided in the insulator (64) and arranged opposite the first electrode plate (33) via the first insulating layer (641); the second capacitor (32) includes a third electrode plate (35) provided in the insulator (64) and electrically connected to the second connection electrode (62B), and a fourth electrode plate (36) provided in the insulator (64) and arranged opposite the third electrode plate (35) via the first insulating layer (641); and the connection portion connects the second electrode plate (34) and the fourth electrode plate (36) to the substrate (63).

[0115] (Supplementary Note 11) The signal transmission device according to any one of Supplementary Note 7 to Supplementary Note 9, wherein the first capacitor (31) is composed of the first connection electrode (61B) and a first opposing electrode (68A) provided in a position opposite the first connection electrode (61B) via the first insulating layer (641) in the insulator (64), the second capacitor (32) is composed of the second connection electrode (62B) and a second opposing electrode (68B) provided in a position opposite the second connection electrode (62B) via the first insulating layer (641) in the insulator (64), and the connection portion connects the first opposing electrode (68A) and the second opposing electrode (68B) to the substrate (63).

[0116] (Supplementary Note 12) A signal transmission device described in any one of Supplementary Note 7 to Supplementary Note 11, wherein the first coil (23) is connected to the first connection electrode (61B), the third coil (25) is connected to the second connection electrode (62B), and the second coil (24) and the fourth coil (26) are connected to each other.

[0117] (Supplementary Note 13) A signal transmission device described in any one of Supplementary Note 7 to Supplementary Note 12, wherein the insulator (64) includes a second insulating layer (642) on the first insulating layer (641) and a third insulating layer (643) below the first insulating layer (641), the first coil (23) and the third coil (25) are arranged in the second insulating layer (642), and the second coil (24) and the fourth coil (26) are arranged in the third insulating layer (643).

[0118] (Supplementary Note 14) A first chip (40) including a first circuit (13), a transformer chip (60), a second chip (50) including a second circuit (14) configured to transmit and receive signals to and from the first circuit (13) through the transformer chip (60), a first die pad (71) on which the first chip (40) is mounted, a second die pad (72) on which the second chip (50) is mounted, and a third die pad (73) insulated from both the first die pad (71) and the second die pad (72) and on which the transformer chip (60) is mounted, wherein the transformer chip (60) includes: a conductive substrate (63), and an insulator (64) provided on the substrate (63) and including a first insulating layer (641) arranged parallel to the substrate (63), a first transformer (21) including a first coil (23) and a second coil (24) arranged on either side of the first insulating layer (641) and arranged so as to be magnetically coupled in the thickness direction of the first insulating layer (641); and a second transformer (22) including a third coil (25) and a fourth coil (26) arranged on either side of the first insulating layer (641) and arranged so as to be magnetically coupled in the thickness direction of the first insulating layer (641), and electrically connected to the first transformer (21); and a first connection electrode (61B) and a second connection electrode (62B) electrically connected to the isolation transformer (15) and used for electrical connection with an external device.

[0119] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0120] 10, 110, 112, 114 Signal transmission device 10A, 114A Signal transmission circuit 11 Primary side terminal 12 Secondary side terminal 13 Primary side circuit 14 Secondary side circuit 15, 15A, 15B Transformer 16A, 16B Primary side signal line 17A, 17B Secondary side signal line 18A, 18B Connection signal line 21 First transformer 22 Second transformer 23 First coil 23A Coil section 23B First end 23C Second end 24 Second coil 24A Coil section 25 Third coil 25A Coil section 25B First end 25C Second end 26 Fourth coil 26A Coil section 31 First capacitor 32 Second capacitor 33 First electrode plate 34 Second electrode plate 35 Third electrode plate 36 4th electrode plate 40 First chip 40R Chip back surface 40S Chip main surface 41 First electrode pad 42 Second electrode pad 43 First substrate 44 Wiring layer 50 Second chip 50R Chip back surface 50S Chip main surface 51 First electrode pad 52 Second electrode pad 53 Second substrate 54 Wiring layer 60, 60A, 60B Transformer chip 60R Chip back surface 60S Chip main surface 601 Chip side surface 602 Chip side surface 603 Chip side surface 604 Chip side surface 61, 61A, 61B First electrode pad 62, 62A, 62B Second electrode pad 63 Third substrate 63R Substrate back surface 63S Substrate surface 64 Insulator 641 First insulating layer 641A Insulating film 641S Upper surface 642 Second insulating layer 642A Insulating film 643 Third insulating layer 643A Insulating film 65A to 65D Wiring 66A to 66D Wiring 67A, 67B Wiring 68A First opposing electrode 68B Second opposing electrode 71 Primary side die pad 72 Secondary side die pad 73 Intermediate die pad 81 First bonding material 82 Second bonding material 83 Third bonding material 90 Sealing resin D1 to D7 Distance V1 First voltage V2 Second voltage W1 to W4 Wires

Claims

1. A conductive substrate; an insulator including a first insulating layer disposed on the substrate and parallel to the substrate; an isolation transformer including: a first transformer including a first coil and a second coil arranged to sandwich the first insulating layer and to be magnetically coupled in a thickness direction of the first insulating layer; and a second transformer including a third coil and a fourth coil arranged to sandwich the first insulating layer and to be magnetically coupled in the thickness direction of the first insulating layer, the second transformer being electrically connected to the first transformer; a first connection electrode and a second connection electrode electrically connected to the insulating transformer and used for electrical connection with an external device; a first capacitor electrically connected to the first connection electrode; a second capacitor electrically connected to the second connection electrode and electrically connected in series with the first capacitor; a connection portion electrically connecting the first capacitor and the second capacitor to the substrate; Including, transformer chip.

2. The transformer chip according to claim 1 , wherein the first capacitor and the second capacitor are formed to have the same capacitance.

3. the first capacitor includes a first electrode plate provided in the insulator and electrically connected to the first connection electrode, and a second electrode plate provided in the insulator and arranged to face the first electrode plate with the first insulating layer interposed therebetween; the second capacitor includes a third electrode plate provided in the insulator and electrically connected to the second connection electrode, and a fourth electrode plate provided in the insulator and arranged to face the third electrode plate with the first insulating layer interposed therebetween, the connection portion connects the second electrode plate and the fourth electrode plate to the substrate; The transformer chip according to claim 1 or 2.

4. the first capacitor is configured with the first connection electrode and a first opposing electrode provided in the insulator at a position opposing the first connection electrode with the first insulating layer interposed therebetween, the second capacitor is configured with the second connection electrode and a second opposing electrode provided in the insulator at a position opposite to the second connection electrode with the first insulating layer interposed therebetween, the connection portion connects the first opposing electrode and the second opposing electrode to the substrate; The transformer chip according to claim 1 or 2.

5. the first coil is connected to the first connection electrode; the third coil is connected to the second connection electrode; The second coil and the fourth coil are connected to each other. The transformer chip according to claim 1 .

6. the insulator includes a second insulating layer above the first insulating layer and a third insulating layer below the first insulating layer; the first coil and the third coil are disposed within the second insulating layer; the second coil and the fourth coil are disposed within the third insulating layer. The transformer chip according to claim 1 .

7. a first chip including a first circuit; A transformer chip and a second chip including a second circuit configured to at least one of transmit and receive signals with the first circuit through the transformer chip; a first die pad on which the first chip is mounted; a second die pad on which the second chip is mounted; a third die pad insulated from both the first die pad and the second die pad, and having the transformer chip mounted thereon; The transformer chip is A conductive substrate; an insulator including a first insulating layer disposed on the substrate and parallel to the substrate; an isolation transformer including: a first transformer including a first coil and a second coil arranged to sandwich the first insulating layer and to be magnetically coupled in a thickness direction of the first insulating layer; and a second transformer including a third coil and a fourth coil arranged to sandwich the first insulating layer and to be magnetically coupled in the thickness direction of the first insulating layer, the second transformer being electrically connected to the first transformer; a first connection electrode and a second connection electrode electrically connected to the insulating transformer and used for electrical connection with an external device; a first capacitor electrically connected to the first connection electrode; a second capacitor electrically connected to the second connection electrode and electrically connected in series with the first capacitor; a connection portion electrically connecting the first capacitor and the second capacitor to the substrate; Including, Signal transmission device.

8. The signal transmission device according to claim 7 , wherein the transformer chip is electrically connected to the third die pad by a conductive bonding material.