Element evaluation device

Abstract

This element evaluation device comprises: a target element connected between first and second nodes; a drive switching element connected between the second node and a third node; an inductor connected between a fourth node to which a power supply voltage is applied and the second node; a switching circuit that switches the drive switching element; a voltage generation circuit connected between the first and fourth nodes; and a capacitor connected between the first and third nodes. The voltage generation circuit generates a voltage between the first and fourth nodes, with the first node as a high potential side, when a return current flows that returns to the fourth node via the second node, the first node, and the voltage generation circuit from the fourth node after the drive switching element is turned off.

Description

Element evaluation equipment

[0001] The present disclosure relates to an element evaluation apparatus.

[0002] A sudden change in voltage applied to a semiconductor element can disrupt the normal operation of the semiconductor element or can lead to deterioration of the semiconductor element. For example, the amount of change in the drain-source voltage of a MOSFET over time is generally referred to as dV / dt, and a high dV / dt can disrupt the normal operation of the MOSFET or can lead to deterioration of the MOSFET. The resistance to dV / dt can be evaluated using a double pulse test or the like.

[0003] Japanese Patent Application Laid-Open No. 2019-176078

[0004] Evaluating the tolerance of semiconductor elements to sudden changes in voltage applied to them is important for understanding the characteristics of the semiconductor elements, and is also necessary for properly designing circuits that incorporate those semiconductor elements. It is hoped that technology can be developed to accurately evaluate the tolerance of semiconductor elements (target elements) that are the subject of evaluation.

[0005] An object of the present disclosure is to provide an element evaluation device that contributes to a good evaluation of the resistance of an element to voltage changes.

[0006] The element evaluation device according to the present disclosure comprises: a target element connected between a first node and a second node; a drive switching element connected between the second node and a third node; an inductor connected between the second node and a fourth node to which a power supply voltage is applied; a switching circuit configured to switch the drive switching element; a voltage generation circuit connected between the first node and the fourth node; and a capacitor connected between the first node and the third node, wherein, after the drive switching element switches from an on state to an off state, when a return current flows in a current loop that returns from the fourth node to the fourth node via the second node, the first node, and the voltage generation circuit, the voltage generation circuit sets the first node to a high potential side to generate a voltage between the first node and the fourth node.

[0007] According to the present disclosure, it is possible to provide an element evaluation device that contributes to a good evaluation of the resistance of an element to voltage changes.

[0008] FIG. 1 is a circuit diagram of a reference evaluation device. FIG. 2 is a circuit diagram of an element evaluation device according to a first embodiment of the present disclosure. FIG. 3 is a diagram showing a waveform of a gate signal and a state transition of a transistor receiving the gate signal according to the first embodiment of the present disclosure. FIG. 4 is an explanatory diagram of the operation of the element evaluation device according to the first embodiment of the present disclosure. FIG. 5 is an explanatory diagram of the operation of the element evaluation device according to the first embodiment of the present disclosure. FIG. 6 is an explanatory diagram of the operation of the element evaluation device according to the first embodiment of the present disclosure. FIG. 7 is a schematic external view of a semiconductor component according to the first embodiment of the present disclosure. FIG. 8 is a diagram of a transistor and its peripheral circuit including an equivalent circuit of the semiconductor component according to the first embodiment of the present disclosure. FIG. 9 is a circuit diagram of an element evaluation device according to a second embodiment of the present disclosure. FIG. 10 is a modified circuit diagram based on the element evaluation device of FIG. 2 according to a third embodiment of the present disclosure. FIG. 11 is a modified circuit diagram based on the element evaluation device of FIG. 2 according to the third embodiment of the present disclosure.

[0009] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, the same parts are designated by the same reference numerals, and duplicate descriptions of the same parts will be omitted as a general rule. In this specification, for the sake of simplicity, symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated.

[0010] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductive portion having a reference potential of 0 V (zero volts), or refers to the 0 V potential itself. The reference conductive portion may be formed using a conductor such as metal. The 0 V potential may also be referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a specific reference represents a potential seen from ground. Level refers to the level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level.

[0011] For any transistor configured as a FET (field effect transistor), including a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Also, unless otherwise specified, in any MOSFET, the back gate can be considered shorted to the source. In any transistor configured as a MOSFET, the gate-source voltage refers to the potential of the gate relative to the potential of the source.

[0012] Hereinafter, the on and off states of any transistor may be simply referred to as on and off. For any transistor, switching from the off state to the on state is referred to as turning on, and switching from the on state to the off state is referred to as turning off. Furthermore, for any transistor, the period during which the transistor is in the on state may be referred to as the on period, and the period during which the transistor is in the off state may be referred to as the off period.

[0013] Unless otherwise specified, the connection between a plurality of parts that form a circuit, such as any circuit element, wiring (line), node, etc., may be understood to refer to an electrical connection.

[0014] <<First Embodiment>> A first embodiment of the present disclosure will be described. Prior to describing the configuration of the first embodiment, a reference evaluation device 900 will be described with reference to FIG. 1. FIG. 1 is a circuit diagram of the reference evaluation device 900. The reference evaluation device 900 includes transistors 910 and 920, which are N-channel MOSFETs. A positive power supply voltage is applied to the drain of the transistor 910 from a voltage source VS′. An inductor L901 is inserted between the connection node between the source of the transistor 910 and the drain of the transistor 920 and the positive output terminal of the voltage source VS′. The source of the transistor 920 is connected to ground. A predetermined potential is applied to the gate of the transistor 910 to fix the transistor 910 in an off state. A switching circuit 930 supplies a gate signal to the gate of the transistor 920 to switch the transistor 920.

[0015] During the on period of the transistor 920, energy is stored in the inductor L901 as a result of a current flowing from the voltage source VS' through the inductor L901 and the channel of the transistor 920. When the transistor 920 is subsequently turned off, a reflux current based on the stored energy in the inductor L901 flows in a current loop via the inductor L901 and the parasitic diode of the transistor 910.

[0016] A change occurs in the drain-source voltage of the transistor 910 during the switching process of the transistor 920. A sudden change in the drain-source voltage of the transistor 910 may have an undesirable effect on the transistor 910. In the reference evaluation device 900, the transistor 920 is repeatedly turned on and off, thereby making it possible to evaluate the tolerance of the transistor 910 to changes in the drain-source voltage (dV / dt).

[0017] The reference evaluation device 900 is a type of double-pulse test circuit. It is difficult to obtain a sufficiently high dV / dt with a typical double-pulse test circuit. It is also difficult to increase the switching frequency, with the limit being around 2 kHz (kilohertz).

[0018] 2 shows a circuit diagram of the element evaluation device 1 according to the first embodiment. The element evaluation device 1 includes a voltage source VS, a transistor 10 (target transistor) that is a high-side transistor, a transistor 20 (drive switching element) that is a low-side transistor, a switching circuit 30, a voltage generating circuit 40, the voltage source VS, an inductor L1, capacitors C1 and C2, and a resistor R2.

[0019] Transistors 10 and 20 are N-channel MOSFETs. Transistor 10 is connected between nodes ND1 and ND2, and transistor 20 is connected between nodes ND2 and ND3. More specifically, the drain of transistor 10 is connected to node ND1, the source of transistor 10 and the drain of transistor 20 are commonly connected to node ND2, and the source of transistor 20 is connected to node ND3. Node ND3 is connected to ground and therefore has ground potential. In FIG. 2 , diode 10D represents a parasitic diode added to transistor 10. Parasitic diode 10D has an anode connected to the source of transistor 10 and a cathode connected to the drain of transistor 10.

[0020] 2, a transistor 10 is a semiconductor element for which the dV / dt tolerance is evaluated, and is an example of a target element. In this embodiment, dV / dt refers to the amount of change in voltage between nodes ND1 and ND2 per unit time. When the target element is the transistor 10, the voltage between nodes ND1 and ND2 is the drain-source voltage of the transistor 10. Hereinafter, the dV / dt tolerance of the target element may be referred to as dV / dt tolerance. Note that tolerance may also be read as tolerance.

[0021] The gate of the transistor 10 is connected to a fixed potential end having a predetermined fixed potential (for example, −5 V) via a gate resistor R2. In the element evaluation device 1, the gate potential of the transistor 10 is fixed at this fixed potential, thereby fixing the transistor 10 in an off state. However, the gate resistor R2 can be omitted, and the gate of the transistor 10 may be directly connected to the fixed potential end.

[0022] The switching circuit 30 includes a pulse generator PG and a gate resistor R1. The switching circuit 30 drives the gate of the transistor 20 to switch the transistor 20, i.e., to switch the state of the transistor 20 between an on state and an off state. In the process of switching the transistor 20, a dV / dt exceeding 0 V can be generated.

[0023] The pulse generator PG has a signal output terminal and a reference potential terminal connected to the node ND3 (thus the ground), and outputs a high-level or low-level signal from the signal output terminal. Hereinafter, the signal output from the signal output terminal of the pulse generator PG will be referred to as the gate signal V G The gate signal V G is supplied to the gate of transistor 20. A high-level gate signal V G has a potential higher than the gate threshold voltage of the transistor 20. The low-level gate signal V G has a potential lower than the gate threshold voltage of transistor 20, which is 0 V in this case. G has a high level, the transistor 20 is turned on, and the gate signal V G has a low level, the transistor 20 is in an off state.

[0024] The pulse generator PG generates the gate signal V G The level of the gate signal V is alternately and periodically changed between a high level and a low level. G The waveform of the gate signal V G The frequency of the gate signal V is called the switching frequency. G The frequency of the gate signal V is also the switching frequency of the transistor 20. G In each period of the gate signal V G The length of time during which H The gate signal V G In each period, the length of the on period of the transistor 20 is time t ON If the turn-on delay time and turn-off delay time of the transistor 20 are assumed to be sufficiently short and ignored, then "t H= t ON "

[0025] The signal output terminal of the pulse generator PG is connected to the gate of the transistor 20 via a gate resistor R1. In the element evaluation device 1, the gate resistor R1 may be a variable resistor. By changing the resistance value of the gate resistor R1, the dV / dt of the transistor 20 can be changed.

[0026] The voltage source VS has a positive output terminal connected to node ND4 and a negative output terminal connected to node ND3 (and therefore ground). The voltage source VS outputs a positive power supply voltage VDD from the positive output terminal with the potential of the negative output terminal as a reference. Therefore, the power supply voltage VDD is applied to node ND4. The voltage source VS may be a variable voltage source in which the power supply voltage VDD is variable. In order to obtain a high dV / dt, it is preferable that the power supply voltage VDD be set to 600 V or higher.

[0027] Inductor L1 is connected between nodes ND2 and ND4. More specifically, a first end of inductor L1 is connected to node ND2, and a second end of inductor L1 is connected to node ND4.

[0028] Capacitor C1 is connected between nodes ND1 and ND3. More specifically, a first end of capacitor C1 is connected to node ND1, and a second end of capacitor C1 is connected to node ND3. Capacitor C2 is connected between nodes ND4 and ND3. More specifically, a first end of capacitor C2 is connected to node ND4, and a second end of capacitor C2 is connected to node ND3.

[0029] The voltage generation circuit 40 is connected between nodes ND1 and ND4. The voltage generation circuit 40 is composed of one or more rectifier diodes 41. Each rectifier diode 41 in the voltage generation circuit 40 has a forward direction from node ND1 to node ND4. When the voltage generation circuit 40 is composed of multiple rectifier diodes 41, the multiple rectifier diodes 41 are connected in series with each other between nodes ND1 and ND4. Therefore, for example, when the voltage generation circuit 40 is composed of first to third rectifier diodes 41, the anode of the first rectifier diode 41 is connected to node ND1, the cathode of the first rectifier diode 41 is connected to the anode of the second rectifier diode 41, the cathode of the second rectifier diode 41 is connected to the anode of the third rectifier diode 41, and the cathode of the third rectifier diode 41 is connected to node ND4. When the voltage generating circuit 40 is configured with a single rectifier diode 41, the anode of the single rectifier diode 41 is connected to the node ND1, and the cathode of the single rectifier diode 41 is connected to the node ND4.

[0030] The operation of the element evaluation device 1 will be described. Let us start from the time when the transistor 20 is off. When the transistor 20 is off, as shown in FIG. 4 , a current flows in a current loop LP1 that runs from the node ND4 through the inductor L1, the parasitic diode 10D, and the capacitor C1 to the node ND3, and returns to the node ND4 via the voltage source VS or the capacitor C2. The current in the current loop LP1 charges the capacitor C1. When the voltage across the capacitor C1 is charged to the power supply voltage VDD, the current in the current loop LP1 becomes zero (here, the forward voltage of the parasitic diode 10D is ignored as it is sufficiently smaller than the power supply voltage VDD).

[0031] After that, the high-level gate signal V from the switching circuit 30 G, and transistor 20 turns on. When transistor 20 turns on, the potential of node ND2 drops to substantially 0 V, and as shown in FIG. 5, a current flows in current loop LP2 that flows from node ND4 through inductor L1 and the channel of transistor 20 to node ND3, and returns to node ND4 via voltage source VS or capacitor C2. Energy is stored in inductor L1 due to the current in current loop LP2. The current in current loop LP2 increases as the on-time of transistor 20 increases, and the stored energy in inductor L1 increases as the current in current loop LP2 increases. Hereinafter, the current flowing through inductor L1 from node ND4 toward node ND2 will be referred to as inductor current IL.

[0032] When the transistor 20 is turned on, the capacitance between the nodes ND1 and ND2 is charged based on the voltage across the capacitor C1, and a high dV / dt occurs during the charging process. The capacitance between the nodes ND1 and ND2 is the drain-source capacitance C of the transistor 10. DS In detail, when the transistor 20 is turned on, the output capacitance C OSS is charged, and the output capacitance C of the transistor 10 OSS A high dV / dt occurs during the charging process of the output capacitance C of the transistor 10. OSS is the drain-source capacitance C of the transistor 10 DS and the gate-drain capacitance C of the transistor 10 GD (not shown) and the capacitance C DS and C GD is a parasitic capacitance added to the transistor 10, and is not shown in FIGS. 2 and 5. The capacitance value of the capacitor C1 is the output capacitance C OSS Therefore, when transistor 20 turns on, the stored charge on capacitor C1 causes a capacitance C DS The voltage across the terminals of the transistors rises substantially to the power supply voltage VDD.

[0033] Further, after that, the gate signal V GWhen the signal ND1 switches from high to low, the transistor 20 is turned off. When the transistor 20 is turned off, a freewheeling operation occurs. In the freewheeling operation, as shown in FIG. 6 , an inductor current IL flows in a current loop LP3 that flows from the node ND4 through the inductor L1, the node ND2, the parasitic diode 10D, the node ND1, and the voltage generating circuit 40 and returns to the node ND4, based on the energy stored in the inductor L1. A high dV / dt also occurs when the transistor 20 is turned off.

[0034] The inductor current IL in the current loop LP3 is called a freewheeling current. After the transistor 20 is turned off, the inductor current IL (freewheeling current) flows in the current loop LP3, causing the stored energy in the inductor L1 to decrease. When the stored energy in the inductor L1 becomes zero, the inductor current IL in the current loop LP3 also becomes zero, returning to the state shown in FIG. 4. In freewheeling operation, the voltage generating circuit 40 generates a voltage drop V between the node ND4 on the low potential side and the node ND1 on the high potential side. 40 A voltage drop V 40 corresponds to the product of the total number of rectifier diodes 41 and the forward voltage of each rectifier diode 41.

[0035] Specific numerical examples for the element evaluation device 1 are given below. For example, the power supply voltage VDD is 800 V, the inductance value of the inductor L1 is 50 μH (microhenries), the capacitance value of the capacitor C1 is 0.47 μF (microfarads), and the capacitance value of the capacitor C2 is 10 μF. The voltage drop V during freewheeling operation is 40 is, for example, 30 V. The present disclosure is not limited to these values.

[0036] By evaluating how long a target device can withstand a specific dV / dt when it is subjected to the specific dV / dt, it is possible to determine the tolerance of the target device to the specific dV / dt. Furthermore, by varying the dV / dt in various ways, it is possible to obtain a life curve for the target device (a curve plotting how long the target device can withstand various dV / dts).

[0037] If a sufficiently high dV / dt can be generated, it is possible to evaluate the tolerance of the target device to high dV / dt. Increasing the speed of the transistor 20 is beneficial for achieving a high dV / dt. Therefore, in this embodiment, a SiC-MOSFET is used as the transistor 20. A SiC-MOSFET is a MOSFET formed using silicon carbide (SiC). The transistor 20 may be any type of switching element (driving switching element), but to achieve a high dV / dt, it is preferable to use a MOSFET having a turn-on delay time of 5 ns (nanoseconds) or less as the transistor 20. Furthermore, it is preferable to drive the transistor 20 as a driver source using the switching circuit 30 (the significance of driver source drive will be described later).

[0038] By using a SiC-MOSFET having a turn-on delay time of 5 ns (nanoseconds) or less as the transistor 20 and by driving the transistor 20 as a driver source, it is possible to obtain a dV / dt of 150 kV / μs in the above numerical example. The turn-on delay time of the transistor 20 is the delay time from when a voltage higher than the gate threshold voltage of the transistor 20 is applied to the gate-source voltage of the transistor 20 until the state of the transistor 20 switches from the off state to the on state, and is the time specified in the electrical characteristic specifications of the transistor 20.

[0039] Furthermore, in both the reference evaluation device 900 and the element evaluation device 1, an increase in the switching frequency is required to evaluate the dV / dt tolerance (lifetime curve, etc.) of the target element in a short period of time. In evaluating the dV / dt tolerance of the target element (910) using the reference evaluation device 900, in order to generate the required dV / dt in each switching cycle, after the transistor 920 is turned off, the next turn-on of the transistor 920 must be delayed until the current in the inductor L901 has decayed to zero (the state of the reference evaluation device 900 must be reset). Similarly, in evaluating the dV / dt tolerance of the target element (10) using the element evaluation device 1, in order to generate the required dV / dt in each switching cycle, after the transistor 20 is turned off, the next turn-on of the transistor 20 must be delayed until the inductor current IL has decayed to zero (the state of the element evaluation device 1 must be reset).

[0040] It is worth noting that the element evaluation device 1 is additionally provided with a voltage generation circuit 40 in comparison with the reference evaluation device 900. As described above, the voltage generation circuit 40 generates a voltage drop V 40 (See Figure 6) A voltage drop V 40 The generation of this voltage increases the consumption rate of the stored energy in the inductor L1, and the time it takes for the inductor current IL to decay to zero after the transistor 20 is turned off is shortened. In other words, the time required for the standby state is shorter in the element evaluation device 1 than in the reference evaluation device 900. As a result, it is possible to increase the switching frequency. Specifically, in the above numerical example, a voltage drop V of about 30 V occurs during freewheeling operation. 40 By generating this, it is possible to increase the switching frequency to about 30 kHz.

[0041] However, by providing the voltage generating circuit 40 consisting of the rectifying diode 41, the output capacitance C OSS The charging current to the output capacitance C of the transistor 10 is blocked by the rectifier diode 41. OSS In the element evaluation device 1, a capacitor C1 is provided as the circuit element.

[0042] Required voltage drop V 40 can be obtained, the number of series-connected rectifier diodes 41 in the voltage generating circuit 40 is arbitrary. If diodes having a sufficiently large forward voltage are used as the rectifier diodes 41, the total number of rectifier diodes 41 can be one.

[0043] 7 is a schematic external view of a semiconductor component 120 including the transistor 20. The semiconductor component 120 includes a semiconductor chip 121 on which a MOSFET is formed, a package 122 that is a housing for accommodating the semiconductor chip 121 and is made of resin, and four metal terminals T D , T PS , T DS and T G Metal terminal T D , T PS , T DS , T G are the drain terminal, the power source terminal, the driver source terminal, and the gate terminal, respectively. In particular, the power source terminal may be composed of a plurality of metal terminals.

[0044] The MOSFET formed on the semiconductor chip 121 is an N-channel MOSFET, and corresponds to the transistor 20. FIG. 8 is a diagram of the transistor 20 and its peripheral circuitry, including an equivalent circuit of the semiconductor component 120.

[0045] Two N-type semiconductor regions separated from each other are formed in the semiconductor chip 121, with one N-type semiconductor region being a source region and the other N-type semiconductor region being a drain region. A source electrode is formed on the source region, and a drain electrode is formed on the drain region. The source of the transistor 20 is formed by the source region and source electrode in the semiconductor chip 121, and the drain of the transistor 20 is formed by the drain region and drain electrode in the semiconductor chip 121. A P-type semiconductor region is provided between the source region and drain region in the semiconductor chip 121, and a gate electrode is formed on the P-type semiconductor region via a gate oxide film. The gate electrode in the semiconductor chip 121 forms the gate of the transistor 20.

[0046] The gate electrode of the MOSFET in the semiconductor chip 121 is connected to the gate terminal T G The gate terminal T G is connected to the signal output terminal of the pulse generator PG via a gate resistor R1 outside the semiconductor component 120. G_INT is a resistance component present in the package 122 and is connected to the gate electrode and gate terminal T G represents the resistance component between

[0047] The drain electrode of the MOSFET in the semiconductor chip 121 is connected to the drain terminal T D Drain terminal T D is connected to a node ND2 outside the semiconductor component 120. That is, the drain electrode of the MOSFET in the semiconductor chip 121 is connected to a drain terminal T D is connected to node ND2 via

[0048] The source electrode of the semiconductor chip 121 is connected to the power source terminal T PS Here, the power source terminal T PS contains a relatively large inductance component. PS The inductance component included in the package inductance component L SThe source electrode of the semiconductor chip 121 is referred to as the package inductance component L S power source terminal T PS The current in the current loop LP2 (FIG. 5) flows through the drain terminal T D and power source terminal T PS When the drain current of the transistor 20 changes with the switching of the transistor 20, the package inductance component L S An electromotive force is generated at

[0049] Suppose the power source terminal T PS and gate terminal T G The gate signal V G If the power supply voltage Vcc is supplied to the transistor 20, the switching speed of the transistor 20 will be reduced due to the influence of the electromotive force. PS The driver source terminal T DS The source electrode of the semiconductor chip 121 and the driver source terminal T DS There is a package inductance component L S Therefore, the voltage between the gate electrode and the source electrode for driving the transistor 20 is calculated by subtracting the package inductance component L S Therefore, the switching speed of the transistor 20 can be improved.

[0050] The driver source drive is a drive circuit in which the reference potential terminal of the pulse generator PG is connected to the driver source terminal T DS and the gate terminal T G and driver source terminal T DS Gate signal V G 8, the gate terminal T G and drain terminal T D The package inductance component of the driver source terminal T DS It can be understood that the driver source terminal T DSThe inductance component included in the package inductance component L S is much smaller than

[0051] As described above, in order to generate the necessary dV / dt in each switching cycle in the evaluation of the dV / dt tolerance of the target element (10) by the element evaluation device 1, after the transistor 20 is turned off, it is necessary to wait until the inductor current IL decays to zero before the next turn-on of the transistor 20 (it is necessary to reset the state of the element evaluation device 1). In order to shorten this waiting time, it is advantageous to keep the peak value of the inductor current IL low, and the on-time t of the transistor 20 is ON However, in consideration of the stabilization of the operation of the entire circuit, the on-time t ON On the other hand, if the peak value of the inductor current IL is too large, the amount of heat generated in each rectifier diode 41 may become a problem. ON It is desirable to set the time to 500 ns (nanoseconds) or less.

[0052] For example, the switching circuit 30 may switch the transistor 20 at a switching frequency of 10 kHz (kilohertz) or more. G The frequency is preferably 10 kHz or more, which allows the dV / dt resistance of the target device (10) to be evaluated in a short time.

[0053] Alternatively, the element evaluation device 1 may be provided with a high-side switching circuit (not shown) connected to the gate and source of the transistor 10, and the high-side switching circuit may supply a signal between the gate and source of the transistor 10 to switch the transistor 10. In this case, the high-side switching circuit performs synchronous rectification in cooperation with the switching circuit 30 so that the transistor 10 is turned off when the transistor 20 is on, and turned on when the transistor 20 is off. However, when such synchronous rectification is performed, the decay rate of the inductor current IL due to the current loop LP3 (see FIG. 6) decreases by the amount of the voltage drop across the parasitic diode 10D. Therefore, it is often preferable not to perform the synchronous rectification.

[0054] <<Second Embodiment>> A second embodiment of the present disclosure will be described. The second embodiment and the third embodiment described below are embodiments based on the first embodiment, and for matters not specifically described in the second and third embodiments, the description of the first embodiment also applies to the second and third embodiments unless there is a contradiction. However, when interpreting the description of the second embodiment, the description of the second embodiment may take precedence for matters that contradict between the first and second embodiments (the same applies to the third embodiment described below). As long as there is no contradiction, any two or more of the first to third embodiments may be combined.

[0055] Fig. 9 shows a circuit diagram of an element evaluation device 1A according to the second embodiment. The element evaluation device 1A can be obtained by replacing the voltage generation circuit 40 of the element evaluation device 1 in Fig. 2 with a voltage generation circuit 50. Except for this replacement, the element evaluation device 1A in Fig. 9 has the same configuration as the element evaluation device 1 in Fig. 2.

[0056] The voltage generating circuit 50 is a DC voltage source inserted between the nodes ND4 and ND1. The negative output terminal and the positive output terminal of the DC voltage source serving as the voltage generating circuit 50 are connected to the nodes ND4 and ND1, respectively. The voltage generating circuit 50 generates a predetermined positive voltage V 50Therefore, similar to the voltage generating circuit 40 according to the first embodiment, the voltage generating circuit 50 outputs a voltage V 50 Therefore, the second embodiment can also achieve the same effects and advantages as the first embodiment.

[0057] The DC voltage source for the voltage generation circuit 50 may be any commercially available DC voltage source, but it is necessary to provide a voltage resistance as viewed from the ground that is equal to or greater than the power supply voltage VDD. Alternatively, a floating power supply device may be used for the voltage generation circuit 50.

[0058] Third Embodiment A third embodiment of the present disclosure will be described. The target element is a semiconductor element whose dV / dt tolerance is to be evaluated.

[0059] The target element may be any type of transistor. A transistor serving as the target element is hereinafter referred to as a target transistor. The above-described transistor 10 is an example of the target transistor, and may hereinafter be referred to as the target transistor 10.

[0060] In the first and second embodiments, the target transistor 10 may be formed from any semiconductor material. For example, the target transistor 10 may be a SiC-MOSFET or a MOSFET formed using silicon. The target transistor 10 may also be a superjunction MOSFET. In either case, the target transistor 10 has a drain connected to a node ND1 and a source connected to a node ND2.

[0061] In the first and second embodiments, a first modification may be applied in which an N-channel IGBT 11 is used as the target transistor 10. FIG. 10 shows a circuit diagram of the element evaluation device 1 when the first modification is applied to the first embodiment. The IGBT is an insulated gate bipolar transistor. In the first modification, the collector and emitter of the IGBT 11 are connected to nodes ND1 and ND2, respectively. That is, in the first modification, the voltage between the nodes ND1 and ND2 is the collector-emitter voltage V CE and the voltage V CE The tolerance to changes in the

[0062] A gate voltage for fixing the IGBT 11 in the off state may be applied to the gate of the IGBT 11. When the first modification is adopted, a diode 12 may be added in parallel to the IGBT 11. The anode and cathode of the diode 12 are connected to nodes ND2 and ND1, respectively, and have the same function as the parasitic diode 10D in Fig. 6. That is, in the freewheeling operation of Fig. 6, the inductor current IL (freewheeling current) in the current loop LP3 flows through the diode 12. When the freewheeling operation of Fig. 6 is performed, the IGBT 11 may be turned on.

[0063] The target element may be any type of diode (for example, a fast recovery diode). A diode serving as a target element will hereinafter be referred to as a target diode. That is, in the first and second embodiments, a second modification may be performed in which the target transistor 10 is replaced with a target diode. FIG. 11 shows a circuit diagram of the element evaluation device 1 when the second modification is performed on the first embodiment. In FIG. 11, a diode 13 is the target diode. The anode of the target diode 13 is connected to a node ND2, and the cathode of the target diode 13 is connected to a node ND1. That is, in the second modification, the voltage between the nodes ND1 and ND2 is the cathode-to-anode voltage V KA and the voltage V KA The tolerance to changes in the

[0064] The channel types of the transistors shown in each embodiment are merely examples, and the channel type of any transistor may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0065] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0066] <<Supplementary Notes>> Supplementary notes are provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0067] An element evaluation device (1, 1A) according to one aspect of the present disclosure includes: a target element (10, 11, 13) connected between a first node (ND1) and a second node (ND2); a drive switching element (20) connected between the second node and a third node (ND3); an inductor (L1) connected between the second node and a fourth node (ND4) to which a power supply voltage is applied; a switching circuit (30) configured to switch the drive switching element; a voltage generation circuit (40, 50) connected between the first node and the fourth node; and a capacitor (C1) connected between the first node and the third node, wherein the voltage generation circuit is configured (first configuration) to make the first node a high potential side and generate a voltage between the first node and the fourth node when a return current flows through a current loop (LP3) that returns from the fourth node to the fourth node via the second node, the first node, and the voltage generation circuit after the drive switching element switches from an on state to an off state.

[0068] This allows a satisfactory evaluation (for example, an efficient evaluation) of the tolerance of the target element to changes in voltage applied to the target element (changes in voltage between the first and second nodes).

[0069] In the element evaluation device according to the first configuration, the voltage generation circuit (40) may be configured (second configuration) to include one or more diodes (41) having a forward direction from the first node toward the fourth node.

[0070] In the element evaluation device according to the first configuration, the voltage generating circuit (50) may be a DC voltage source (third configuration).

[0071] In the element evaluation apparatus according to the first to third configurations, the target element may be a target transistor or a target diode (fourth configuration).

[0072] In the element evaluation device according to the first to third configurations, the target element may be a target transistor (10, 11) having a drain or collector connected to the first node and a source or emitter connected to the second node (fifth configuration).

[0073] In the element evaluation device according to the fifth configuration, the target transistor (10) may be a MOSFET having a drain connected to the first node and a source connected to the second node, and the MOSFET may be formed using silicon carbide (sixth configuration).

[0074] In the element evaluation apparatus according to the fifth or sixth configuration, the target transistor may be fixed in an off state (seventh configuration).

[0075] In the element evaluation device according to any of the first to third configurations, the target element may be a target diode (13) having a cathode connected to the first node and an anode connected to the second node (eighth configuration).

[0076] In the element evaluation device according to any one of the first to eighth configurations, the turn-on delay time of the drive switching element may be 5 nanoseconds or less (ninth configuration).

[0077] The reduction in the turn-on delay time of the drive switching element improves the switching speed of the drive switching element. The improvement in the switching speed of the drive switching element makes it possible to evaluate the tolerance of the target element in a state where the rate of change of the voltage applied to the target element is increased. In other words, the tolerance of the target element related to high dV / dt can be evaluated.

[0078] In the element evaluation device according to any one of the first to ninth configurations, the driving switching element comprises a semiconductor chip (121) on which a MOSFET is formed, a package (122) for accommodating the semiconductor chip, and a drain terminal (T D ), power source terminal (T PS ), driver source terminal (T DS ) and the gate terminal (T G ), and a semiconductor component (120) including: a gate electrode of a MOSFET in the semiconductor chip is connected to the gate terminal; a drain electrode of the MOSFET in the semiconductor chip is connected to the second node via the drain terminal; and a source electrode of the MOSFET in the semiconductor chip is connected to a package inductance component (L S ) and is connected to the driver source terminal without passing through the power source terminal, and the switching circuit applies a gate signal (V G ) to switch the drive switching element (tenth configuration).

[0079] The tenth configuration improves the switching speed of the drive switching element. By improving the switching speed of the drive switching element, the tolerance can be evaluated in a state where the rate of change of the voltage applied to the target element is increased. In other words, the tolerance of the target element related to high dV / dt can be evaluated.

[0080] In the element evaluation device according to any one of the first to tenth configurations, the drive switching element may be a MOSFET formed using silicon carbide (eleventh configuration).

[0081] In the element evaluation device according to any one of the first to eleventh configurations, the switching circuit may be configured to switch the drive switching element at a frequency of 10 kHz or more (twelfth configuration).

[0082] By increasing the switching frequency of the drive switching element, it becomes possible to evaluate the above-mentioned durability (life curve, etc.) of the target element in a short time.

[0083] In the element evaluation device according to any of the first to twelfth configurations above, the switching circuit may be configured to switch the drive switching element at a predetermined frequency, and to set the on time of the drive switching element to 500 nanoseconds or less in each period of switching of the drive switching element (a thirteenth configuration).

[0084] The element evaluation apparatus according to any one of the first to thirteenth configurations may be configured (fourteenth configuration) such that the power supply voltage is 600 V or more when viewed from the potential of the third node.

[0085] 900 Reference evaluation device 910, 920 Transistor 930 Switching circuit L901 Inductor VS' Voltage source 1, 1A Element evaluation device 10 Transistor (target transistor) 10D Parasitic diode 11 IGBT 12 Diode 13 Target diode 20 Transistor (drive switching element) 30 Switching circuit 40, 50 Voltage generation circuit 41 Rectifier diode L1 Inductor C1, C2 Capacitor VS Voltage source R1 Gate resistor R2 Resistor PG Pulse generator ND1 to ND4 Node VDD Power supply voltage V G Gate signal LP1 to LP3 Current loop IL Inductor current 120 Semiconductor component 121 Semiconductor chip 122 Package T D Drain terminal T PS Power source terminal T DS Driver source terminal T G Gate terminal L S Package inductance component RG_INT Resistance component

Claims

1. A target element connected between a first node and a second node, A drive switching element connected between the second node and a third node, An inductor connected between a fourth node to which a power supply voltage is applied and the second node, A switching circuit configured to switch the drive switching element, A voltage generation circuit connected between the first node and the fourth node, A capacitor connected between the first node and the third node, and comprising: After the drive switching element switches from the on state to the off state, when a reflux current flows in a current loop that returns from the fourth node to the fourth node via the second node, the first node, and the voltage generation circuit, the voltage generation circuit sets the first node to the high potential side and generates a voltage between the first node and the fourth node , An element evaluation device.

2. The voltage generation circuit includes one or more diodes having a forward direction in the direction from the first node to the fourth node , The element evaluation device according to claim 1.

3. The voltage generation circuit is a DC voltage source , The element evaluation device according to claim 1.

4. The target element is a target transistor or a target diode , The element evaluation device according to any one of claims 1 to 3.

5. The target element is a target transistor, and has a drain or collector connected to the first node, and a source or emitter connected to the second node , The element evaluation device according to any one of claims 1 to 3.

6. The target transistor is a MOSFET having a drain connected to the first node and a source connected to the second node, and the MOSFET is formed using silicon carbide , The element evaluation device according to claim 5.

7. The target transistor is fixed in the off state , The element evaluation device according to claim 5.

8. The target element is a target diode, and has a cathode connected to the first node and an anode connected to the second node , The element evaluation device according to any one of claims 1 to 3.

9. The turn-on delay time of the drive switching element is 5 nanoseconds or less , The element evaluation device according to any one of claims 1 to 3.

10. The drive switching element is A semiconductor chip on which a MOSFET is formed, A package that houses the semiconductor chip, It is composed of a semiconductor component including drain terminals, power source terminals, driver source terminals, and gate terminals exposed from the package. The gate electrode of the MOSFET in the semiconductor chip is connected to the gate terminal. The drain electrode of the MOSFET in the semiconductor chip is connected to the second node via the drain terminal. The source electrode of the MOSFET in the semiconductor chip is connected to the third node via the power source terminal including a package inductance component, and is also connected to the driver source terminal without passing through the power source terminal. The switching circuit switches the drive switching element by supplying a gate signal between the gate terminal and the driver source terminal. The device evaluation apparatus according to any one of claims 1 to 3.

11. The drive switching element is a MOSFET formed using silicon carbide. The device evaluation apparatus according to any one of claims 1 to 3.

12. The switching circuit switches the drive switching element at a frequency of 10 kHz or higher. The device evaluation apparatus according to any one of claims 1 to 3.

13. The switching circuit switches the drive switching element at a predetermined frequency, and sets the on-time of the drive switching element to 500 nanoseconds or less in each cycle of the switching of the drive switching element. The device evaluation apparatus according to any one of claims 1 to 3.

14. The power supply voltage is 600 V or higher when viewed from the potential of the third node. The device evaluation apparatus according to any one of claims 1 to 3.