Semiconductor device

Abstract

A semiconductor device according to the present invention comprises a substrate including a circuit pattern, a semiconductor chip mounted on the circuit pattern and electrically connected to the circuit pattern, a frame body including a wall portion, and a plate-shaped terminal electrically connected to the circuit pattern. The wall portion surrounds the substrate. The terminal includes a first region installed to the wall portion and a second region disposed inside of the frame body, along with the first region. The distance between the inner wall surface of the wall portion and the circuit pattern is 500 μm or less. The second region is directly connected to the circuit pattern.

Description

Semiconductor Devices

[0001] This disclosure relates to a semiconductor device. This application claims priority to Japanese Application No. 2022-162390, filed on October 7, 2022, and incorporates by reference all of the contents of said Japanese application.

[0002] A semiconductor device has been disclosed that includes a substrate having a metal pattern, a case, a resin filled in the case, and a semiconductor element electrically connected to the metal pattern (see, for example, Patent Document 1). In the semiconductor device disclosed in Patent Document 1, the case has a wall portion extending upward and a protrusion connected to the wall portion and protruding toward the center of the substrate. The protrusion has a first surface that is connected to the tip of the protrusion and is a slope that decreases in distance to the substrate as it moves away from the tip of the protrusion, and a second surface that is connected below the first surface and is closer to a top surface of the substrate than the first surface. The metal pattern is located directly below the first surface.

[0003] Japanese Patent Application Laid-Open No. 2020-14025

[0004] A semiconductor device according to the present disclosure includes a substrate having a circuit pattern, a semiconductor chip mounted on the circuit pattern and electrically connected to the circuit pattern, a frame including a wall portion, and a plate-shaped terminal electrically connected to the circuit pattern. The wall portion surrounds the substrate. The terminal includes a first region attached to the wall portion and a second region connected to the first region and disposed inside the frame. The distance between the inner wall surface of the wall portion and the circuit pattern is 500 μm or less. The second region is directly connected to the circuit pattern.

[0005] FIG. 1 is a schematic plan view of a semiconductor device in a first embodiment as viewed in the thickness direction of a substrate. FIG. 2 is a schematic cross-sectional view showing a part of the semiconductor device shown in FIG. 1. FIG. 3 is a schematic cross-sectional view showing an intermediate stage in a manufacturing process of the semiconductor device. FIG. 4 is a schematic cross-sectional view showing an intermediate stage in a manufacturing process of the semiconductor device. FIG. 5 is a schematic cross-sectional view showing an intermediate stage in a manufacturing process of the semiconductor device. FIG. 6 is a schematic perspective view showing a part of a semiconductor device according to a second embodiment.

[0006] [Problem to be Solved by the Present Disclosure] Recently, in semiconductor devices, there has been a demand for miniaturization as well as reduction in inductance.

[0007] Therefore, one object of the present invention is to provide a semiconductor device that can be easily miniaturized and has reduced inductance.

[0008] Effect of the Present Disclosure According to such a semiconductor device, it is easy to achieve miniaturization and reduction in inductance.

[0009] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. A semiconductor device according to the present disclosure includes: (1) a substrate having a circuit pattern; a semiconductor chip mounted on the circuit pattern and electrically connected to the circuit pattern; a frame body including a wall portion; and a plate-shaped terminal electrically connected to the circuit pattern. The wall portion surrounds the substrate. The terminal includes a first region attached to the wall portion and a second region connected to the first region and disposed inside the frame body. The distance between the inner wall surface of the wall portion and the circuit pattern is 500 μm or less. The second region is directly connected to the circuit pattern.

[0010] In this semiconductor device, the distance between the inner wall surface of the wall portion and the circuit pattern is 500 μm or less, and the second region of the terminal is directly connected to the circuit pattern, which simplifies the device configuration and facilitates miniaturization. Furthermore, components such as wires connecting the terminal and the circuit pattern are not required, which eliminates the need for wiring work and reduces inductance. Therefore, this semiconductor device facilitates miniaturization and reduces inductance.

[0011] The semiconductor device according to the present disclosure also includes: (2) a substrate having a circuit pattern; a semiconductor chip mounted on the circuit pattern and electrically connected to the circuit pattern; a frame including a wall; and a plate-shaped terminal electrically connected to the circuit pattern. The wall surrounds the substrate. The terminal includes a third region attached to the wall, a fourth region disposed inside the frame and directly connected to the circuit pattern, and a fifth region disposed between the third and fourth regions. The distance between the inner wall surface of the wall and the circuit pattern is 500 μm or less. There is a gap between the fifth region and the circuit pattern. The fifth region has a through-hole formed therein that penetrates the substrate in the thickness direction.

[0012] In this semiconductor device, the distance between the inner wall surface of the wall portion and the circuit pattern is 500 μm or less, and the fourth region of the terminal is directly connected to the circuit pattern, simplifying the device configuration and facilitating miniaturization. Furthermore, components such as wires connecting the terminal and the circuit pattern are not required, thereby reducing inductance while eliminating wiring work. Therefore, this semiconductor device facilitates miniaturization and reduces inductance. Furthermore, in this semiconductor device, a through-hole is formed in the fifth region, which has a gap between the fifth region and the circuit pattern, penetrating the substrate in the thickness direction. Even if air bubbles are trapped in the gap when the sealant is filled inside the frame, the air bubbles can escape through the through-hole formed in the fifth region during degassing, removing them from the sealant. This prevents air bubbles from accumulating below the terminal, thereby preventing a decrease in the semiconductor device's durability. As a result, this semiconductor device can improve reliability.

[0013] In the above (1) or (2), the distance between the inner wall surface of the wall portion and the circuit pattern may be set to 100 μm or less from the viewpoint of further suppressing the generation of bubbles.

[0014] (3) In the above (1) or (2), the inner wall surface of the wall portion may be in contact with the circuit pattern. This allows the inner wall surface of the wall portion and the circuit pattern to be in close contact with each other, reducing the risk of air bubbles being trapped in the resin between the inner wall surface of the wall portion and the circuit pattern. This further suppresses a decrease in durability and further improves reliability.

[0015] (4) In any of the above (1) to (3), at least one of the second region and the circuit pattern and the fourth region and the circuit pattern may be connected by welding, ultrasonic bonding, a conductive adhesive, or soldering. Such a connection can more reliably connect the second region and the circuit pattern while ensuring electrical conductivity.

[0016] (5) In any of the above (1) to (4), a base plate may be further provided that is in contact with the substrate and to which the frame is attached. Such a base plate is effectively used to fix the frame and also to dissipate heat from the semiconductor chip.

[0017] (6) In any of the above (1) to (5), a sealing material may be further provided to fill the space surrounded by the wall portion. By providing such a sealing material, it is possible to suppress a decrease in the durability of the semiconductor device and to improve reliability.

[0018] (7) In any of the above (1) to (6), the terminal may include a control terminal that controls the operation of the semiconductor chip. This can reduce the inductance of the control terminal.

[0019] (8) In any one of (1) to (6) above, the terminal may include a main terminal that electrically connects the semiconductor device to an external device. This can reduce inductance in the main terminal.

[0020] (9) In any of the above (1) to (8), the outer wall surface of the substrate and the inner wall surface of the wall portion may be in contact with each other. By doing so, the outer wall surface of the substrate can be fitted into the inner wall surface of the wall portion, making it easy to attach the frame to the substrate. Also, the substrate can be more reliably positioned relative to the frame.

[0021] (10) In any of the above (1) to (9), at least one of the first region and the third region may include a portion inserted into the wall portion. This allows the terminal to be pre-fixed to the wall portion of the frame body, thereby more reliably attaching the terminal to the frame body.

[0022] (11) In any of the above (1) to (10), the semiconductor chip may include a SiC transistor chip. This allows such a semiconductor chip to be switched at high speed because it includes SiC (silicon carbide) as a semiconductor layer. Therefore, this is suitable for the semiconductor device of the present disclosure, which is premised on switching a current path.

[0023] (12) In any of the above (1) to (11), the inner wall surface of the wall portion may extend in the thickness direction of the substrate. This reduces the risk of impeding the escape of trapped air bubbles during degassing when a sealant is filled inside the frame. This semiconductor device is highly reliable because it suppresses a decrease in durability.

[0024] [Details of the Embodiments of the Present Disclosure] Next, embodiments of the semiconductor device of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference characters, and description thereof will not be repeated.

[0025] (First Embodiment) A semiconductor device according to a first embodiment of the present disclosure will be described. FIG. 1 is a schematic plan view of the semiconductor device according to the first embodiment as viewed in the thickness direction of the substrate. FIG. 2 is a schematic cross-sectional view showing a portion of the semiconductor device shown in FIG. 1. FIG. 2 is a schematic cross-sectional view taken along the YZ plane. To facilitate understanding, FIG. 2 omits some of the components shown in FIG. 1. Note that in FIG. 1 and subsequent figures, the thickness direction of the substrate is defined as the Z direction.

[0026] 1 and 2, a semiconductor device 11a in the first embodiment includes a base plate 12, a frame body 13, a substrate 15 having a circuit pattern 16, four terminals 19a (main terminal 19a), 19b (main terminal 19b), 19c (main terminal 19c), and 19d (main terminal 19d), four terminals 29a (control terminal 29a), 29b (control terminal 29b), 29c (control terminal 29c), and 29d (control terminal 29d), and six semiconductor chips 21a, 21b, 21c, 21d, 21e, and 21f.

[0027] The base plate 12 is made of metal, such as copper. The base plate 12 is a so-called heat sink, and is used to dissipate heat from the semiconductor chips 21 a, 21 b, 21 c, 21 d, 21 e, and 21 f. When viewed in the thickness direction (Z direction), the external shape of the base plate 12 is a rectangle with long sides extending in the X direction and short sides extending in the Y direction, and the four corners are rounded.

[0028] The substrate 15 having the circuit pattern 16 is disposed on the base plate 12. Specifically, the substrate 15 is disposed on a first surface 12a located in the thickness direction of the base plate 12. The substrate 15 is insulating. The material of the substrate 15 is, for example, Al. ２ O ３ , AlN, Si ３ N ４The thickness direction of the base plate 12 and the thickness direction of the substrate 15 are both the Z direction. When viewed in the thickness direction of the substrate 15, the outer shape of the substrate 15 is a rectangle with the long sides extending in the X direction and the short sides extending in the Y direction. The configuration of the circuit pattern 16 will be described in detail later.

[0029] The frame 13 extends from the first surface 12a of the base plate 12 and surrounds the substrate 15. The frame 13 includes a wall 13a (first wall 13a), a wall 13b (second wall 13b), a wall 13c (third wall 13c), and a wall 13d (fourth wall 13d). The first wall 13a, the second wall 13b, the third wall 13c, and the fourth wall 13d surround the substrate 15. The inner wall surfaces 27 of the first wall 13a, the second wall 13b, the third wall 13c, and the fourth wall 13d extend in the thickness direction of the substrate 15, i.e., the Z direction. The first wall 13a and the second wall 13b are disposed opposite each other in the Y direction. The third wall 13c and the fourth wall 13d are disposed opposite each other in the X direction. The frame 13 is made of, for example, an insulating resin. The frame 13 is fixed to the base plate 12 by, for example, an adhesive. The base plate 12 and the frame 13 form a case 20 included in the semiconductor device 11a. A space 30 inside the case 20 is filled with a resin sealing material 14.

[0030] The circuit pattern 16 is disposed on the substrate 15. The circuit pattern 16 is made of, for example, copper. The circuit pattern 16 includes seven circuit boards 17a, 17b, 17c, 17d, 17e, 17f, and 17g. That is, the circuit pattern 16 is composed of seven circuit boards 17a, 17b, 17c, 17d, 17e, 17f, and 17g disposed on the substrate 15. The circuit board 17a has a strip shape extending in the X direction and is disposed in contact with the first wall portion 13a. The circuit board 17b is disposed closer to the second wall portion 13b than the circuit board 17a and includes a strip-shaped portion that is longer in the X direction. The circuit board 17b also has a portion that contacts the first wall portion 13a. Circuit board 17c has a strip-like shape that is long in the X direction and is disposed in contact with third wall portion 13c. The configuration of circuit board 17d will be described later. Circuit board 17e has a strip-like portion that is long in the X direction and has a portion that contacts third wall portion 13c. Circuit board 17f includes a strip-like portion that is long in the X direction. Circuit board 17f also has a portion that contacts second wall portion 13b. Circuit board 17g has a strip-like shape that extends in the X direction and is disposed in contact with second wall portion 13b. Circuit boards 17a, 17b, 17c, 17d, 17e, 17f, and 17g are disposed with intervals between each other.

[0031] Circuit board 17d includes a strip-shaped first portion 18a extending in the X direction, a strip-shaped second portion 18b also extending in the X direction, and a strip-shaped third portion 18c extending in the Y direction and connecting first portion 18a and second portion 18b. First portion 18a and second portion 18b are spaced apart in the Y direction. Circuit board 17c is disposed between first portion 18a and circuit board 17b in the Y direction. Circuit board 17e is disposed between first portion 18a and second portion 18b in the Y direction. Third portion 18c is in contact with fourth wall portion 13d.

[0032] Each of main terminals 19a, 19b, 19c, and 19d is plate-shaped and made of metal. In this embodiment, main terminal 19a is a P terminal, main terminals 19b and 19c are O terminals, and main terminal 19d is an N terminal. Each of main terminals 19a, 19b, 19c, and 19d has a bent strip-like shape. In this embodiment, main terminals 19a, 19b, 19c, and 19d are formed, for example, by bending a strip-shaped copper plate. Main terminals 19a and 19d are attached to the third wall portion 13c with a gap in the Y direction, and main terminals 19b and 19c are attached to the fourth wall portion 13d with a gap in the Y direction. Main terminals 19a, 19b, 19c, and 19d ensure electrical connection of semiconductor device 11a to the outside. Each of the main terminals 19a, 19b, 19c, and 19d has a portion that is exposed from the inner wall surface 27 of the frame body 13 toward the space 30 inside the case 20. These portions are used to electrically connect the respective wires that serve as connecting members.

[0033] The main terminal 19a includes a first region 31a attached to the third wall portion 13c and a second region 32a disposed inside the frame body 13. In this embodiment, the first region 31a is embedded in the third wall portion 13c. The main terminal 19b includes a first region 31b attached to the fourth wall portion 13d and a second region 32b disposed inside the frame body 13. In this embodiment, the first region 31b is embedded in the fourth wall portion 13d. The main terminal 19c includes a first region 31c attached to the fourth wall portion 13d and a second region 32c disposed inside the frame body 13. In this embodiment, the first region 31c is embedded in the fourth wall portion 13d. The main terminal 19d includes a first region 31d attached to the third wall portion 13c and a second region 32d disposed inside the frame body 13. In this embodiment, the first region 31d is embedded in the third wall portion 13c. The main terminals 19a, 19b, 19c, and 19d are each inserted into the frame body 13. That is, the main terminals 19a, 19b, 19c, and 19d are attached to the frame body 13 by insert molding.

[0034] The semiconductor chip 21a, the semiconductor chip 21b, the semiconductor chip 21c, the semiconductor chip 21d, the semiconductor chip 21e, and the semiconductor chip 21f each include SiC as a semiconductor layer. The semiconductor chip 21a, the semiconductor chip 21b, the semiconductor chip 21c, the semiconductor chip 21d, the semiconductor chip 21e, and the semiconductor chip 21f are each SiC transistor chips. In this embodiment, the semiconductor chip 21a, the semiconductor chip 21b, the semiconductor chip 21c, the semiconductor chip 21d, the semiconductor chip 21e, and the semiconductor chip 21f are each, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). The semiconductor chip 21a, the semiconductor chip 21b, and the semiconductor chip 21c are each arranged on the circuit board 17c with a gap in the X direction. The semiconductor chip 21a, the semiconductor chip 21b, and the semiconductor chip 21c are each electrically connected to the circuit board 17c by, for example, solder or the like. The semiconductor chips 21d, 21e, and 21f are arranged on the second portion 18b of the circuit board 17d at intervals in the X direction. The semiconductor chips 21d, 21e, and 21f are electrically connected to the circuit board 17d by, for example, solder or the like.

[0035] The control terminals 29a, 29b, 29c, and 29d are also plate-shaped and made of metal. In this embodiment, the control terminal 29a is a gate terminal, the control terminal 29b is a source sense terminal, the control terminal 29c is a gate terminal, and the control terminal 29d is a source sense terminal. The control terminals 29a, 29b, 29c, and 29d each have a bent strip-like shape. In this embodiment, the control terminals 29a, 29b, 29c, and 29d are each formed by bending a strip-shaped copper plate, for example. The control terminals 29a and 29b are attached to the first wall portion 13a with a gap in the X direction, and the control terminals 29c and 29d are attached to the second wall portion 13b with a gap in the X direction. The semiconductor device 11a controls the operations of six semiconductor chips 21a, 21b, 21c, 21d, 21e, and 21f by means of control terminals 29a, 29b, 29c, and 29d. The control terminals 29a, 29b, 29c, and 29d each have a portion that is exposed from the inner wall surface 27 of the frame 13 toward the space 30 inside the case 20. These portions are used to electrically connect the respective wires that serve as connecting members.

[0036] Each control terminal 29a includes a first region 33a attached to the first wall portion 13a and a second region 34a disposed inside the frame body 13. Similarly, each control terminal 29b includes a first region attached to the first wall portion 13a and a second region disposed inside the frame body 13. Each control terminal 29c and control terminal 29d also includes a first region attached to the second wall portion 13b and a second region disposed inside the frame body 13. Each of control terminals 29a, 29b, 29c, and 29d is inserted into the frame body 13. That is, each of control terminals 29a, 29b, 29c, and 29d is attached to the frame body 13 by insert molding.

[0037] The gate pad of semiconductor chip 21a and circuit board 17b are electrically connected by wire 22a. The source pad of semiconductor chip 21a and circuit board 17a are electrically connected by wire 23a. The source pad of semiconductor chip 21a and first portion 18a of circuit board 17d are electrically connected by multiple wires 24a. The gate pad of semiconductor chip 21b and circuit board 17b are electrically connected by wire 22b. The source pad of semiconductor chip 21b and circuit board 17a are electrically connected by wire 23b. The source pad of semiconductor chip 21b and first portion 18a of circuit board 17d are electrically connected by multiple wires 24b. The gate pad of semiconductor chip 21c and circuit board 17b are electrically connected by wire 22c. The source pad of semiconductor chip 21c and circuit board 17a are electrically connected by wire 23c. The source pad of semiconductor chip 21c and first portion 18a of circuit board 17d are electrically connected by multiple wires 24c. The gate pad of semiconductor chip 21d and circuit board 17f are electrically connected by wire 22d. The source pad of semiconductor chip 21d and circuit board 17g are electrically connected by wire 23d. The source pad of semiconductor chip 21d and circuit board 17e are electrically connected by multiple wires 24d. The gate pad of semiconductor chip 21e and circuit board 17f are electrically connected by wire 22e. The source pad of semiconductor chip 21e and circuit board 17g are electrically connected by wire 23e. The source pad of semiconductor chip 21d and circuit board 17e are electrically connected by multiple wires 24e. The gate pad of semiconductor chip 21f and circuit board 17f are electrically connected by wire 22f. The source pad of semiconductor chip 21f and circuit board 17g are electrically connected by wire 23f. The source pad of semiconductor chip 21f and circuit board 17e are electrically connected by multiple wires 24f.

[0038] Here, the distance D between the inner wall surface 27 of the wall portion 13a (first wall portion 13a) and the circuit pattern 16 is 500 μm or less. The distance D is the distance in the Y direction. In this embodiment, the distance between the inner wall surface 27 of the first wall portion 13a and the circuit pattern 16 is 0 μm. In other words, the inner wall surface 27 of the first wall portion 13a and the circuit pattern 16 are in contact with each other.

[0039] Furthermore, the second region 34a of the control terminal 29a is directly connected to the circuit pattern 16. Specifically, the second region 34a and the circuit board 17b of the circuit pattern 16 are directly connected by ultrasonic bonding. Similarly, the control terminals 29b, 29c, 29d, the main terminals 19a, 19b, 19c, and 19d are each directly connected to the circuit pattern 16 by ultrasonic bonding.

[0040] The flow of current can be briefly explained as follows: When semiconductor chip 21a, semiconductor chip 21b, and semiconductor chip 21c are turned on by control via control terminals 29a, 29b, 29c, and 29d, the electrical connection between main terminal 19a and main terminal 19b is on, and the electrical connection between main terminal 19c and main terminal 19d is off, current flows from main terminal 19a to circuit board 17c of circuit pattern 16, flows to semiconductor chip 21a, semiconductor chip 21b, and semiconductor chip 21c that are in the on state, flows to wires 24a, 24b, and 24c, flows to first portion 18a of circuit board 17d of circuit pattern 16, third portion 18c of circuit board 17d of circuit pattern 16, and main terminal 19b. At this time, no current flows through the second portion 18b of the circuit board 17d of the circuit pattern 16 on which the semiconductor chips 21d, 21e, and 21f, which are in the OFF state, are mounted.

[0041] Next, when semiconductor chips 21d, 21e, and 21f are turned on by control via control terminals 29a, 29b, 29c, and 29d, and the electrical connection between main terminal 19c and main terminal 19d is on and the electrical connection between main terminal 19a and main terminal 19b is off, current flows from main terminal 19c to third portion 18c and second portion 18b of circuit board 17d of circuit pattern 16, to semiconductor chips 21d, 21e, and 21f that are on, to wires 24d, 24e, and 24f, to circuit board 17e of circuit pattern 16, and to main terminal 19d. At this time, no current flows through first portion 18a of circuit board 17d of circuit pattern 16, which carries semiconductor chips 21a, 21b, and 21c that are off.

[0042] Here, a brief description of the manufacturing method of the semiconductor device 11a is given. FIGS. 3, 4, and 5 are each schematic cross-sectional views showing intermediate stages in the manufacturing process of the semiconductor device 11a. First, as shown in FIG. 3, a substrate 15 having a circuit pattern 16 is bonded to a base plate 12 using an adhesive (not shown). Next, as shown in FIG. 4, a semiconductor chip 21a is soldered onto the circuit pattern 16. At this time, the drain pad of the semiconductor chip 21a is electrically connected to the circuit pattern 16. Then, as shown in FIG. 5, wire bonding is performed using a bond tool to electrically connect each component via wire. Next, a frame 13 to which control terminals 29a and other components are attached by insert molding is bonded to the base plate 12 using an adhesive. Next, the second region 34a of the control terminal 29a is ultrasonically bonded to the circuit pattern 16. In this way, the control terminal 29a is directly connected to the circuit pattern 16. Then, as shown in FIG. 2, the space 30 formed by the base plate 12 and the frame 13 is filled with a sealant 14 to seal the space. In this manner, the semiconductor device 11a is manufactured.

[0043] In this semiconductor device 11a, the distance D between the inner wall surfaces 27 of the walls 13a, 13b, 13c, and 13d and the circuit pattern 16 is 500 μm or less, and the second regions 32a, 32b, 32c, 32d, and 34a of the control terminals 29a, 29b, 29c, and 29d are directly connected to the circuit pattern 16, simplifying the device configuration and facilitating miniaturization. Furthermore, wires and other components connecting the control terminals 29a, 29b, 29c, and 29d to the circuit pattern 16 are not required, eliminating the need for wiring and reducing inductance. Therefore, this semiconductor device 11a facilitates miniaturization and reduces inductance.

[0044] In this embodiment, the inner wall surface 27 of the wall portion 13a is in contact with the circuit pattern 16. This allows the inner wall surface 27 of the wall portion 13a and the circuit pattern 16 to be in close contact with each other, thereby reducing the risk of resin containing air bubbles being disposed between the inner wall surface 27 of the wall portion 13a and the circuit pattern 16. This further suppresses a decrease in durability, thereby further improving reliability.

[0045] In this embodiment, the second region 34a and the circuit pattern 16 are connected by ultrasonic bonding, which makes it possible to more reliably connect the second region 34a and the circuit pattern 16 while ensuring electrical conductivity.

[0046] In this embodiment, a base plate 12 is provided so as to be in contact with the substrate 15 and to which the frame body 13 is attached. Such a base plate 12 is effectively used to fix the frame body 13 and is also effectively used to dissipate heat from the semiconductor chip 21 a and the like.

[0047] In this embodiment, the space surrounded by the wall portions 13 a, 13 b, 13 c, and 13 d is filled with a sealing material 14. By providing such a sealing material 14, it is possible to suppress a decrease in the durability of the semiconductor device 11 a, and to improve reliability.

[0048] In this embodiment, the terminals include control terminals 29a, 29b, 29c, and 29d that control the operations of semiconductor chip 21a, semiconductor chip 21b, semiconductor chip 21c, semiconductor chip 21d, semiconductor chip 21e, and semiconductor chip 21f. Therefore, it is possible to reduce the inductance at control terminals 29a, 29b, 29c, and 29d.

[0049] In this embodiment, the terminals include main terminals 19a, 19b, 19c, and 19d that electrically connect the semiconductor device 11a to the outside, thereby reducing the inductance of the main terminals 19a, 19b, 19c, and 19d.

[0050] In this embodiment, the outer wall surface of the substrate 15 contacts the inner wall surfaces 27 of the walls 13a, 13b, 13c, and 13d. Therefore, the outer wall surface of the substrate 15 is fitted into the inner wall surfaces 27 of the walls 13a, 13b, 13c, and 13d, making it easy to attach the frame 13 to the substrate 15. Furthermore, the positioning of the substrate 15 relative to the frame 13 can be more reliably performed.

[0051] In this embodiment, the first regions 31 a, 31 b, 31 c, and 31 d include portions inserted into the walls 13 a, 13 b, 13 c, and 13 d. Therefore, the main terminals 19 a, 19 b, 19 c, 19 d, and the control terminals 29 a, 29 b, 29 c, and 29 d can be fixed in advance to the walls 13 a, 13 b, 13 c, and 13 d of the frame 13, so that the main terminals 19 a, 19 b, 19 c, 19 d, and the control terminals 29 a, 29 b, 29 c, and 29 d can be attached to the frame 13 more reliably.

[0052] In this embodiment, the inner wall surfaces 27 of the walls 13a, 13b, 13c, and 13d extend in the thickness direction of the substrate 15. This reduces the risk of impeding the escape of trapped air bubbles during degassing when the sealant 14 is filled inside the frame 13. This semiconductor device 11a is highly reliable as it prevents a decrease in durability.

[0053] (Embodiment 2) Another embodiment, embodiment 2, will now be described. Fig. 6 is a schematic perspective view showing a part of a semiconductor device according to embodiment 2. The semiconductor device according to embodiment 2 basically has the same configuration as embodiment 1 and achieves the same effects. However, the semiconductor device according to embodiment 2 differs from embodiment 1 in the configuration of the terminals.

[0054] Referring to FIG. 6 , the semiconductor device 11b of the second embodiment includes a plate-shaped terminal 41 electrically connected to the circuit pattern. The terminal 41 includes a third region 43a attached to the wall 13a, a fourth region 44a disposed inside the frame and directly connected to the circuit pattern, specifically, a circuit board 17b included in the circuit pattern, and a fifth region 45a disposed between the third region 43a and the fourth region 44a. The inner wall surface of the wall 13a extends in the thickness direction of the substrate. The distance between the inner wall surface of the wall 13a and the circuit pattern is 500 μm or less. A gap 46 is defined between the fifth region 45a and the circuit board 17b of the circuit pattern. A through-hole 42 is formed in the fifth region 45a, penetrating the thickness direction of the substrate.

[0055] In this semiconductor device 11b, the distance between the inner wall surface 27 of the wall portion 13a and the circuit board 17b of the circuit pattern 16 is 500 μm or less, and the fourth region 44a of the terminal 41 is directly connected to the circuit board 17b of the circuit pattern 16, which simplifies the device configuration and facilitates miniaturization. Furthermore, components such as wires connecting the terminal 41 and the circuit board 17b of the circuit pattern 16 are no longer necessary, which reduces inductance while eliminating the need for wiring. Therefore, this semiconductor device 11b facilitates miniaturization and reduces inductance.

[0056] Furthermore, in this semiconductor device 11b, a through-hole 42 is formed in the fifth region 45a, which has a gap 46 between it and the circuit pattern 16, penetrating the substrate 15 in the thickness direction. This gap 46 may be formed during ultrasonic bonding or other processes during manufacturing based on a design that takes tolerances into account. Even if air bubbles are trapped in the gap 46 when the sealant 14 is filled into the frame 13, the air bubbles can escape through the through-hole 42 formed in the fifth region 45a during degassing, thereby removing the air bubbles from the sealant 14. This prevents air bubbles from accumulating below the terminals 41, thereby preventing a decrease in the durability of the semiconductor device 11b. As a result, the reliability of this semiconductor device 11b can be improved.

[0057] In the above-described embodiments, at least one of the second region and the circuit pattern and the fourth region and the circuit pattern may be connected by welding, ultrasonic bonding, a conductive adhesive, or soldering. Such a connection can more reliably ensure conductivity while connecting the second region and the circuit pattern.

[0058] In the above-described embodiment, at least one of the first region and the third region may include a portion inserted into the wall portion, which allows the terminal to be pre-fixed to the wall portion of the frame body, thereby more reliably attaching the terminal to the frame body.

[0059] It should be understood that the embodiments disclosed herein are illustrative in all respects and are not limiting in any respect. The scope of the present invention is defined not by the above description but by the claims, and it is intended to include all modifications within the meaning and scope of the claims.

[0060] 11a, 11b semiconductor device, 12 base plate, 12a first surface, 13 frame body, 13a wall portion (first wall portion), 13b wall portion (second wall portion), 13c wall portion (third wall portion), 13d wall portion (fourth wall portion), 14 sealing material, 15 substrate, 16 circuit pattern, 17a, 17b, 17c, 17d, 17e, 17f, 17g circuit board, 18a first portion, 18b second portion, 18c third portion, 19a, 19b, 19c, 19d main terminal, 20 case, 21a, 21b, 21c, 21d, 21e, 21f Semiconductor chips, 22a, 22b, 22c, 22d, 22e, 22f, 23a, 23b, 23c, 23d, 23e, 23f, 24a, 24b, 24c, 24d, 24e, 24 Wires, 27 Inner wall surfaces, 29a, 29b, 29c, 29d Control terminals, 31a, 31b, 31c, 31d, 33a First regions, 32a, 32b, 32c, 32d, 34a Second regions, 41 Terminals, 42 Through holes, 43a Third regions, 44a Fourth regions, 45a Fifth regions, 46 Gap, D Distance.

Claims

1. A substrate having a circuit pattern; a semiconductor chip mounted on the circuit pattern and electrically connected to the circuit pattern; A frame including a wall portion; a plate-shaped terminal electrically connected to the circuit pattern, The wall portion surrounds the substrate, The terminal is a first region attached to the wall; A second region disposed inside the frame body, The distance between the inner wall surface of the wall portion and the circuit pattern is 500 μm or less, The second region is directly connected to the circuit pattern.

2. A substrate having a circuit pattern; a semiconductor chip mounted on the circuit pattern and electrically connected to the circuit pattern; A frame including a wall portion; a plate-shaped terminal electrically connected to the circuit pattern, The wall portion surrounds the substrate, The terminal is a third region attached to the wall; a fourth region disposed inside the frame and directly connected to the circuit pattern; a fifth region disposed between the third region and the fourth region, The distance between the inner wall surface of the wall portion and the circuit pattern is 500 μm or less, a gap is provided between the fifth region and the circuit pattern; A semiconductor device, wherein the fifth region has a through hole formed therein, the through hole penetrating the substrate in a thickness direction.

3. 3. The semiconductor device according to claim 1, wherein an inner wall surface of said wall portion is in contact with said circuit pattern.

4. The semiconductor device described in claim 1, wherein the second region and the circuit pattern are connected by welding, ultrasonic bonding, a conductive adhesive or solder.

5. 3. The semiconductor device according to claim 1, further comprising a base plate provided in contact with said substrate, said base plate being attached to said frame.

6. 3. The semiconductor device according to claim 1, further comprising a sealing material filled in a space surrounded by said wall portions.

7. 3. The semiconductor device according to claim 1, wherein the terminals include a control terminal that controls an operation of the semiconductor chip.

8. 3. The semiconductor device according to claim 1, wherein said terminals include main terminals that electrically connect said semiconductor device to an external device.

9. 3. The semiconductor device according to claim 1, wherein an outer wall surface of said substrate and an inner wall surface of said wall portion are in contact with each other.

10. A semiconductor device as described in claim 1, wherein the first region includes a portion inserted into the wall portion.

11. The semiconductor device according to claim 1 , wherein the semiconductor chip includes a SiC transistor chip.

12. 3. The semiconductor device according to claim 1, wherein an inner wall surface of said wall portion extends in a thickness direction of said substrate.

13. The semiconductor device described in claim 2, wherein the fourth region and the circuit pattern are connected by welding, ultrasonic bonding, a conductive adhesive or solder.

14. A semiconductor device as described in claim 2, wherein the third region includes a portion inserted into the wall portion.