Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor which makes it possible to prevent layer separation while also reducing internal stress differences. Provided is a multilayer ceramic capacitor 1 comprising end face exposure internal electrodes 15A and lateral face exposure internal electrodes 15B and comprising first dielectric layers 14A in which the end face exposure internal electrodes 15A are disposed and second dielectric layers 14B in which the lateral face exposure internal electrodes 15B are disposed. In each of the first dielectric layers 14A or the second dielectric layers 14B, an auxiliary internal electrode 16 is disposed toward one surface in which an internal electrode is not disposed, said auxiliary internal electrode 16 being separate from the internal electrode, being exposed at said one surface, and being opposite from a lead-out portion of another internal electrode that is adjacent to said internal electrode in the layering direction. Provided in each auxiliary internal electrode 16 is a through hole 17h which passes therethrough in the layering direction and in which is disposed a dielectric of the same material as the dielectric layer. The dielectric connects a dielectric layer that is on one main surface side and that contacts the auxiliary internal electrode 16 with a dielectric layer that is on another main surface side.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] There is a multi-terminal multilayer ceramic capacitor that includes a laminate in which dielectric layers on which internal electrodes exposed on end faces of the laminate are arranged and dielectric layers on which internal electrodes exposed on side faces of the laminate are arranged are alternately stacked, end face external electrodes arranged on the end faces, and side face external electrodes arranged on the side faces (see Patent Document 1).

[0003] JP 2010-98052 A

[0004] In multi-terminal multilayer ceramic capacitors, the internal electrodes extend in different directions on each layer. This causes the layers to shrink in different directions during sintering, which increases the internal stress difference between layers, especially in the lead-out regions where the internal electrode lead portions are located. This increases the possibility of peeling between layers.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor that can reduce internal stress differences and prevent peeling between layers.

[0006] In order to achieve the above object, the multilayer ceramic capacitor of the present invention comprises a laminate in which a plurality of dielectric layers, on which internal electrodes are arranged, are laminated, the laminate having two main surfaces provided on both sides in a lamination direction, two side surfaces provided on both sides in a width direction intersecting the lamination direction, and two end surfaces provided on both sides in a length direction intersecting the lamination direction and the width direction; and end face external electrodes provided on the end faces and side face external electrodes provided on the side faces of the laminate, the internal electrodes comprising end face-exposed internal electrodes exposed on the end faces and side face-exposed internal electrodes exposed on the side faces, the end face-exposed internal electrodes and the side face-exposed internal electrodes each having opposing portions facing each other and leading portions led out from the opposing portions, and the dielectric layers are formed on the dielectric layers on which the end face-exposed internal electrodes are arranged. and second dielectric layers on which the side-surface-exposed internal electrodes are arranged and which are laminated alternately with the first dielectric layers, wherein an auxiliary internal electrode is arranged on one of the side surfaces or end surfaces of at least one of the first and second dielectric layers, on which the internal electrode arranged on the one dielectric layer is not exposed, the auxiliary internal electrode being arranged at a distance from the internal electrode, exposed on the one surface, and facing an extended portion of another internal electrode adjacent to the internal electrode in the stacking direction, and the auxiliary internal electrodes each having a through hole penetrating in the stacking direction and in which a dielectric made of the same material as the dielectric layer is arranged, and the dielectric connects the dielectric layer on one main surface side in contact with the auxiliary internal electrode to the dielectric layer on the other main surface side.

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can reduce the internal stress difference and prevent peeling between layers.

[0008] 1 is a schematic perspective view of a multilayer ceramic capacitor 1. FIG. 1 is a cross-sectional view of a first embodiment of the multilayer ceramic capacitor 1 taken in the II-II direction in FIG. 1. FIG. 2 is a cross-sectional view of a first embodiment of the multilayer ceramic capacitor 1 taken in the III-III direction in FIG. 1. FIG. 3 is a cross-sectional view of the first embodiment along an end face exposed internal electrode 15A of the multilayer ceramic capacitor 1. FIG. 4 is a cross-sectional view of the first embodiment along a side face exposed internal electrode 15B of the multilayer ceramic capacitor 1. FIG. 5 is a diagram illustrating a manufacturing process of a laminate 2 in a manufacturing method of the multilayer ceramic capacitor 1. FIG. 6 is a flowchart illustrating a manufacturing method of the multilayer ceramic capacitor 1. FIG. 7 is a cross-sectional view of a second embodiment of the multilayer ceramic capacitor 1 taken in the II-II direction in FIG. 1. FIG. 8 is a cross-sectional view of a second embodiment of the multilayer ceramic capacitor 1 taken in the III-III direction in FIG. 1.

[0009] First Embodiment A multilayer ceramic capacitor 1 according to a first embodiment of the present invention will now be described. Fig. 1 is a schematic perspective view of the multilayer ceramic capacitor 1. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the first embodiment taken along the II-II direction in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the first embodiment taken along the III-III direction in Fig. 1.

[0010] (Multilayer ceramic capacitor 1) The multilayer ceramic capacitor 1 is a multilayer ceramic capacitor with a three-terminal structure, including end surface external electrodes 3 provided on both end surfaces C in the length direction L of the laminate 2, and side surface external electrodes 4 provided on both side surfaces B in the width direction W of the laminate 2. The laminate 2 includes an inner layer portion 11 in which a dielectric layer 14 and an internal electrode 15 are laminated, and an outer layer portion 12.

[0011] In this specification, the term indicating the orientation of the multilayer ceramic capacitor 1 refers to the direction in which the dielectric layers 14 and the internal electrodes 15 are stacked in the multilayer ceramic capacitor 1 as the stacking direction T. The direction that intersects with the stacking direction T and in which the pair of end face external electrodes 3 are provided is referred to as the length direction L. The direction that intersects with both the length direction L and the stacking direction T is referred to as the width direction W. In the embodiment, the stacking direction T, the length direction L, and the width direction W are perpendicular to one another.

[0012] Furthermore, in the following description, of the six outer surfaces of the laminate 2, a pair of outer surfaces on both sides in the stacking direction T will be referred to as main surfaces A, a pair of outer surfaces extending in the stacking direction T and on both sides in the width direction W will be referred to as side surfaces B, and a pair of outer surfaces extending in the stacking direction T and on both sides in the length direction L will be referred to as end surfaces C.

[0013] (Laminate 2) The laminate 2 includes an inner layer portion 11 and outer layer portions 12 disposed on both sides of the inner layer portion 11 in the stacking direction T. The laminate 2 preferably has rounded corners and ridges. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect.

[0014] (Inner Layer Portion 11) The inner layer portion 11 is formed by laminating a plurality of dielectric layers 14 and internal electrodes 15 along the lamination direction T.

[0015] (Dielectric Layer 14) The dielectric layer 14 is made of a ceramic material, such as BaTiO ３ The dielectric ceramic may be a ceramic material containing the above-mentioned main component and at least one of a manganese compound, an iron compound, a chromium compound, a cobalt compound, a nickel compound, or the like.

[0016] (Internal Electrode 15) The internal electrode 15 is preferably made of a metal material such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au.

[0017] The internal electrode 15 has a plurality of end-exposed internal electrodes 15A and a plurality of side-exposed internal electrodes 15B arranged alternately. When there is no need to particularly distinguish between the end-exposed internal electrodes 15A and the side-exposed internal electrodes 15B, they will be collectively referred to as the internal electrode 15.

[0018] Fig. 4 is a cross-sectional view taken along an end surface exposed internal electrode 15A of the multilayer ceramic capacitor 1. Fig. 5 is a cross-sectional view taken along a side surface exposed internal electrode 15B of the multilayer ceramic capacitor 1.

[0019] 4 , the end-exposed internal electrode 15A extends between both end faces C of the laminate 2 in the length direction L and is spaced a certain distance from both side faces B in the width direction W. The end-exposed internal electrode 15A has an end-facing portion 15Aa located in the center between both end faces C, and end-drawn portions 15Ab extending from the end-facing portion 15Aa to both end faces C. The end-drawn portions 15Ab extend to both end faces C, are exposed at the end faces C of the laminate 2, and are connected to the end external electrodes 3 provided on both side faces in the width direction W of the laminate 2.

[0020] 5 , the side surface-exposed internal electrode 15B is slightly smaller than the laminate 2 and is spaced a certain distance from both end faces C in the longitudinal direction L. The side surface-exposed internal electrode 15B has a side surface facing portion 15Ba located in the center between both side faces B, and side surface drawn portions 15Bb extending from the side surface facing portion 15Ba to both side faces B. The side surface drawn portions 15Bb extend to both side faces B, are exposed at the side faces B of the laminate 2, and are connected to the side surface external electrodes 4 provided on both side faces in the width direction W of the laminate 2.

[0021] The end surface facing portion 15Aa and the side surface facing portion 15Ba face each other and form a capacitor portion. In the following description, unless it is necessary to distinguish between the end surface facing portion 15Aa and the side surface facing portion 15Ba, they will be collectively referred to as the facing portion 15a. Unless it is necessary to distinguish between the end surface drawn portion 15Ab and the side surface drawn portion 15Bb, they will be collectively referred to as the drawn portion 15b. In addition, the region of the laminate 2 where the facing portion 15a is arranged will be referred to as the facing region, and the region where the end surface drawn portion 15Ab or the side surface drawn portion 15Bb is arranged will be referred to as the drawn region.

[0022] The dielectric layer 14 is formed by alternately stacking multiple layers of a first dielectric layer 14A on which an end-face-exposed internal electrode 15A exposed on the end face C is arranged, and a second dielectric layer 14B on which a side-face-exposed internal electrode 15B exposed on a portion of the side face B is arranged.

[0023] 2 and 3 , the outer layer portion 12 is a dielectric layer of a constant thickness that is disposed on the main surface A side of the inner layer portion 11. The outer layer portion 12 is made of the same material as the dielectric layer 14 of the inner layer portion 11.

[0024] (End Face External Electrodes 3) End face external electrodes 3 are arranged on both end faces C of the laminate 2. End face drawn portions 15Ab of the end face exposed internal electrodes 15A are connected to the end face external electrodes 3. The end face external electrodes 3 cover not only the end faces C but also parts of the main faces A and side faces B on the end face C side.

[0025] (Side surface external electrodes 4) Side surface external electrodes 4 are arranged on both side surfaces B of the laminate 2. The side surface external electrodes 4 are connected to the side surface drawn portions 15Bb of the side surface exposed internal electrodes 15B. The side surface external electrodes 4 cover not only the side surfaces B but also a portion of the side surface B side of the main surface A.

[0026] The end surface external electrode 3 and the side surface external electrode 4 include a base electrode layer 31 and a plating layer 32 disposed on the base electrode layer 31. The plating layer 32 includes a Ni (nickel) plating layer 321 disposed on the base electrode layer 31 and a Sn (tin) plating layer 322 disposed on the Ni plating layer 321.

[0027] 3 and 4 , in the first embodiment, a side-face-exposed auxiliary internal electrode 16A is arranged as an auxiliary internal electrode 16 on the side of the first dielectric layer 14A, on which the end-face-exposed internal electrode 15A is arranged, on which the end-face-exposed internal electrode 15A is not exposed. The side-face-exposed auxiliary internal electrode 16A is arranged at approximately the center in the length direction L, spaced apart from the end-face-exposed internal electrode 15A by a predetermined dimension in the length direction L. The side-face-exposed auxiliary internal electrode 16A is exposed on the side face B, and faces a side-face drawn portion 15Bb of the side-face-exposed internal electrode 15B, which is another internal electrode 15 adjacent in the stacking direction T to the end-face-exposed internal electrode 15A.

[0028] (The dimension d of the side surface exposed auxiliary internal electrode 16A １ As shown in FIG. 3, the dimension d of the side surface exposed auxiliary internal electrode 16A in the width direction W is １ is the dimension in the width direction W from the side surface B to the edge of the end surface exposed internal electrode 15A on the side surface B side, １ When this is done, D １ / 5<d １ <D １When the side surface-exposed auxiliary internal electrode 16A and the end surface-exposed auxiliary internal electrode 16B of a second embodiment described later are described together, the dimension in the width direction W of the auxiliary internal electrode 16 is represented as d, and the dimension in the width direction W from one surface to the edge of one surface of the internal electrode 15 is represented as D.

[0029] (Through Holes 16h) The side surface exposed auxiliary internal electrode 16A is provided with a plurality of through holes 16h penetrating in the stacking direction T. A dielectric material the same as the material of the dielectric layer 14 is disposed in the through holes 16h.

[0030] (Through holes 16h) When the side-surface-exposed auxiliary internal electrode 16A is divided into a side-surface region 16a located closer to the side surface B than the center in the width direction W, and a central region 16b located closer to the end-surface-exposed internal electrode 15A, the through holes 16h are provided in the central region 16b. However, it is sufficient that the through holes 16h are provided at least in the central region 16b, and they may also be provided in the side-surface region 16a. In this case, it is preferable that the number of through holes 16h provided in the central region 16b is greater than the number of through holes 16h provided in the side-surface region 16a.

[0031] (Dimension r of Through Hole 16h) The dimension r of the plurality of through holes 16h in the width direction W is d １ / 200≦r≦d １ The central region 16b has one or more, preferably two or more through holes 16h each having a diameter of 1 / 5.

[0032] (Manufacturing Method of Multilayer Ceramic Capacitor 1) Next, a manufacturing method of the multilayer ceramic capacitor 1 according to the embodiment will be described. Fig. 6 is a diagram illustrating the manufacturing steps of the laminate 2 in the manufacturing method of the multilayer ceramic capacitor 1. Fig. 7 is a flowchart illustrating the manufacturing method of the multilayer ceramic capacitor 1.

[0033] (Internal electrode pattern forming step S1) An end face exposed internal electrode 15A and a side face exposed auxiliary internal electrode 16A are formed with a conductive paste on a ceramic green sheet that will become the first dielectric layer 14A. Similarly, a side face exposed internal electrode 15B is formed with a conductive paste on a ceramic green sheet that will become the second dielectric layer 14B.

[0034] The ceramic green sheet is a strip-shaped sheet formed by forming a ceramic slurry containing ceramic powder, a binder, and a solvent onto a carrier film using a die coater, gravure coater, microgravure coater, or the like.

[0035] The end-face exposed internal electrodes 15A, the side-face exposed internal electrodes 15B, and the side-face exposed auxiliary internal electrodes 16A are formed by printing, such as screen printing, gravure printing, or letterpress printing.

[0036] The side surface-exposed auxiliary internal electrode 16A having the through holes 16h may be formed simultaneously with the end surface-exposed internal electrode 15A by using a printing pattern of the side surface-exposed auxiliary internal electrode 16A having the through holes 16h formed therein in advance. Alternatively, the end surface-exposed internal electrode 15A may be printed on a ceramic green sheet with ink having a predetermined viscosity, and then the side surface-exposed auxiliary internal electrode 16A may be printed with ink having a lower viscosity than the predetermined viscosity, so that the through holes 16h are formed in the side surface-exposed auxiliary internal electrode 16A during sintering. Alternatively, the end surface-exposed internal electrode 15A may be printed on a ceramic green sheet with ink having a predetermined metal content, and then the side surface-exposed auxiliary internal electrode 16A may be separately printed with ink having a lower metal content than the predetermined metal content, so that the through holes 16h are formed in the side surface-exposed auxiliary internal electrode 16A during sintering. Furthermore, after printing the end-face-exposed internal electrode 15A on the ceramic green sheet with ink having a metal with a predetermined particle size, the side-face-exposed auxiliary internal electrode 16A may be separately printed with ink having a metal with a particle size different from the predetermined particle size, so that a through hole 16h is formed in the side-face-exposed auxiliary internal electrode 16A during sintering.

[0037] (Laminating step S2) Ceramic sheets to become the first dielectric layers 14A on which the end-face exposed internal electrodes 15A are arranged and ceramic sheets to become the second dielectric layers 14B on which the side-face exposed internal electrodes 15B are arranged are alternately laminated. Subsequently, ceramic green sheets for the outer layer portions are arranged on top and bottom and thermocompression bonded to form a mother block.

[0038] (Mother Block Cutting Step S3) Next, the mother block is cut and divided in the length direction L and width direction W to manufacture a plurality of rectangular parallelepiped laminates 2.

[0039] (External electrode forming process S4) Next, end surface external electrodes 3 are formed on both end surfaces C of the laminate 2, and side surface external electrodes 4 are formed on both side surfaces B of the laminate 2. The end surface external electrodes 3 are connected to the end surface lead portions 15Ab of the end surface exposed internal electrodes 15A. The end surface external electrodes 3 are formed so as to cover not only the end surfaces C but also parts of the end surface C sides of the main surface A and side surfaces B. The side surface external electrodes 4 are connected to the side surface lead portions 15Bb of the side surface exposed internal electrodes 15B. The side surface external electrodes 4 are formed so as to cover not only the side surfaces B but also parts of the side surfaces B sides of the main surface A.

[0040] (Firing step S5) Then, the laminate is heated in a nitrogen atmosphere at a set firing temperature for a predetermined time, thereby firing the end surface external electrodes 3 and the side surface external electrodes 4 onto the laminate 2, and producing the multilayer ceramic capacitor 1 shown in FIG.

[0041] (Effect of auxiliary internal electrodes 16) Generally, in a multi-terminal multilayer ceramic capacitor such as a multilayer ceramic capacitor with a three-terminal structure, the extension direction of the internal electrodes differs from layer to layer. If the auxiliary internal electrodes 16 as in the embodiment are not provided, in the lead-out region, one of the adjacent layers has a lead portion as an internal electrode, while the other has no internal electrode. Therefore, during sintering, the shrinkage amounts of the layers in the lead-out region differ, and the difference in internal stress between the layers increases. This increases the possibility of peeling between the layers.

[0042] However, in the first embodiment, a side-exposed auxiliary internal electrode 16A as an auxiliary internal electrode 16 is arranged on the side of the first dielectric layer 14A on which the end-exposed internal electrode 15A is arranged, that is, on the side of the side B on which the end-exposed internal electrode 15A is not exposed.

[0043] Therefore, in the lead region, the lead portion 15b is arranged on one of the adjacent layers, and the auxiliary internal electrode 16 is arranged on the other layer. That is, internal electrodes are arranged on both of the adjacent dielectric layers 14 in the lead region. This reduces the difference in the amount of shrinkage of each layer during sintering, reduces the difference in internal stress, and reduces the possibility of peeling between layers.

[0044] (The dimension d of the auxiliary internal electrode 16 １ Effect of (1) The dimension d of the auxiliary internal electrode 16 in the width direction W satisfies D / 5<d<D×4 / 5, where D is the dimension in the width direction W from the side surface B to the edge of the end surface exposed internal electrode 15A on the side surface B side. This ensures a sufficient dimension d of the auxiliary internal electrode 16 in the width direction W, making it possible to more effectively suppress peeling between layers due to differences in internal stress.

[0045] (Effect of Having Through Holes 16h) Furthermore, the auxiliary internal electrode 16 is provided with a plurality of through holes 16h that penetrate in the stacking direction T. A dielectric made of the same material as the dielectric layer 14 is disposed in the through holes 16h. This dielectric connects the second dielectric layer 14B on the first main surface A side that contacts the auxiliary internal electrode 16 with the first dielectric layer 14A on the second main surface A side. The dielectric in the through holes 16h acts as an anchor, making it possible to more effectively suppress peeling between layers due to differences in internal stress.

[0046] (Effect of the through hole 16h being located in the central region) When the auxiliary internal electrode 16 is divided into a side region 16a located closer to the side surface B than the center in the width direction W of the auxiliary internal electrode 16, and a central region 16b located closer to the end surface exposed internal electrode 15A, the through hole 16h is located in the central region 16b. Therefore, an anchor effect is exerted in the central region 16b, and peeling between layers due to differences in internal stress can be more effectively suppressed.

[0047] (Effect of dimension r of through-hole 16h) The dimension r of the plurality of through-holes 16h in the width direction W is １ / 200≦r≦d １ The central region 16b has one or more through holes 16h, preferably two or more through holes 16h, each of which has a diameter of 1 / 5. １ / 200 is the minimum size that can be provided as the through hole 16h in the grain region. １ / 5, the width of the auxiliary internal electrode 16 is d １ Two or more through holes 16h can be arranged side by side in the width direction W in the central region 16b where the thickness is 1 / 2, and peeling between layers due to internal stress differences can be more effectively suppressed.

[0048] Second Embodiment Next, a multilayer ceramic capacitor 100 according to a second embodiment of the present invention will be described. In the second embodiment, FIG. 1 is common to the first embodiment. In the multilayer ceramic capacitor 100 according to the second embodiment, parts common to the multilayer ceramic capacitor 1 according to the first embodiment are assigned the same reference numerals, and common descriptions will be omitted.

[0049] Fig. 8 is a cross-sectional view of the multilayer ceramic capacitor 100 according to the second embodiment taken along line II-II in Fig. 1. Fig. 9 is a cross-sectional view of the multilayer ceramic capacitor 100 according to the second embodiment taken along line III-III in Fig. 1.

[0050] (Auxiliary Internal Electrode 16) In the first embodiment, the side surface-exposed auxiliary internal electrode 16A is arranged on the side surface B of the first dielectric layer 14A on which the end surface-exposed internal electrode 15A is arranged, where the end surface-exposed internal electrode 15A is not exposed, as the auxiliary internal electrode 16. However, in the second embodiment, as shown in Fig. 9, the side surface-exposed auxiliary internal electrode 16A is not arranged.

[0051] 8 , in the second embodiment, an end-face-exposed auxiliary internal electrode 16B is arranged as the auxiliary internal electrode 16 on the second dielectric layer 14B on which the side-face-exposed internal electrode 15B is arranged, on the side of the end face C on which the side-face-exposed internal electrode 15B is not exposed. The end-face-exposed auxiliary internal electrode 16B is arranged at approximately the center in the width direction W, spaced apart from the side-face-exposed internal electrode 15B by a predetermined dimension in the width direction W. The end-face-exposed auxiliary internal electrode 16B is exposed at the end face C, and faces the end-face drawn portion 15Ab of the end-face-exposed internal electrode 15A, which is another internal electrode 15 adjacent in the stacking direction T to the side-face-exposed internal electrode 15B.

[0052] Therefore, in the lead region, the lead portion 15b is arranged on one of the adjacent layers, and the end-face-exposed auxiliary internal electrode 16B is arranged on the other layer. That is, internal electrodes are arranged on both of the adjacent dielectric layers 14 in the lead region. This reduces the difference in the amount of shrinkage of each layer during sintering, reduces the difference in internal stress, and reduces the possibility of peeling between layers.

[0053] (Dimension d of end-face exposed auxiliary internal electrode 16B) Dimension d of end-face exposed auxiliary internal electrode 16B in the length direction L ２ is the dimension in the length direction L from the end face C to the edge of the side face exposed internal electrode 15B on the end face C side. ２ When this is done, D ２ / 5<d ２ <D ２ × 4 / 5. As a result, the dimension d ２ Since the difference in internal stress is sufficiently ensured, peeling between layers due to the difference in internal stress can be more effectively suppressed.

[0054] (Through holes 16h) The end face exposed auxiliary internal electrode 16B is provided with a plurality of through holes 16h penetrating in the stacking direction T. A dielectric made of the same material as the dielectric layer 14 is disposed in the through holes 16h. This dielectric connects the second dielectric layer 14B on the first main surface A side in contact with the auxiliary internal electrode 16 and the first dielectric layer 14A on the second main surface A side. The dielectric in the through holes 16h acts as an anchor, making it possible to more effectively suppress peeling between layers due to differences in internal stress.

[0055] 8 , when the auxiliary internal electrode 16 is divided into a side-face region 16a located closer to the end face C than the center in the longitudinal direction L of the auxiliary internal electrode 16, and a central region 16b located closer to the end face exposed internal electrode 15A, the through holes 16h are provided in the central region 16b. However, it is sufficient that the through holes 16h are provided at least in the central region 16b, and they may also be provided in the side-face region 16a. In this case, it is preferable that the number of through holes 16h provided in the central region 16b is greater than the number of through holes 16h provided in the side-face region 16a. Therefore, an anchor effect is exerted in the central region 16b, and peeling between layers due to internal stress differences can be more effectively suppressed.

[0056] (Dimension r of Through Hole 16h) The dimension r of the plurality of through holes 16h in the length direction L is d ２ / 200≦r≦d ２ The central region 16b has one or more through holes 16h, preferably two or more through holes 16h, each of which has a diameter of 1 / 5. ２ / 200 is the minimum size that can be provided as the through hole 16h in the grain region. ２ / 5, the width of the auxiliary internal electrode 16 is d ２ Two or more through holes 16h can be arranged side by side in the length direction L in the central region 16b where the width is 1 / 2.

[0057] Third Embodiment Next, a multilayer ceramic capacitor according to a third embodiment of the present invention will be described. In the multilayer ceramic capacitor 100 according to the third embodiment, the same reference numerals as those in the first and second embodiments are used, and common descriptions will be omitted.

[0058] In the third embodiment, as in the first embodiment, a side surface-exposed auxiliary internal electrode 16A is arranged as an auxiliary internal electrode 16 on the side surface B of the first dielectric layer 14A on which the end surface-exposed internal electrode 15A is arranged, where the end surface-exposed internal electrode 15A is not exposed. And, as in the second embodiment, an end surface-exposed auxiliary internal electrode 16B is arranged as an auxiliary internal electrode 16 on the side surface C of the second dielectric layer 14B on which the side surface-exposed internal electrode 15B is arranged, where the end surface C of the side surface-exposed internal electrode 15B is not exposed. Therefore, the third embodiment has the effects of both the first and second embodiments.

[0059] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various changes and modifications are possible.

[0060] <1> A multilayer ceramic capacitor comprising: a laminate in which a plurality of dielectric layers, each having an internal electrode disposed thereon, are stacked, the laminate having two main surfaces provided on both sides in a stacking direction, two side surfaces provided on both sides in a width direction intersecting the stacking direction, and two end surfaces provided on both sides in a length direction intersecting the stacking direction and the width direction; and end face external electrodes provided on the end faces and side face external electrodes provided on the side faces of the laminate, the internal electrodes comprising end face-exposed internal electrodes exposed on the end faces and side face-exposed internal electrodes exposed on the side faces, the end face-exposed internal electrodes and the side face-exposed internal electrodes each having opposing portions facing each other and leading portions drawn out from the opposing portions, the dielectric layers comprising first dielectric layers on which the end face-exposed internal electrodes are arranged, and second dielectric layers on which the side face-exposed internal electrodes are arranged and which are stacked alternately with the first dielectric layers, a multilayer ceramic capacitor, comprising: an auxiliary internal electrode disposed at a distance from the internal electrode, exposed on the one surface or the end surface of at least one of the first dielectric layer and the second dielectric layer, where the internal electrode disposed on the one dielectric layer is not exposed; the auxiliary internal electrode is disposed at a distance from the internal electrode, exposed on the one surface, and facing a lead portion of another internal electrode adjacent to the internal electrode in the stacking direction; the auxiliary internal electrodes each have a through hole penetrating in the stacking direction and in which a dielectric made of the same material as the dielectric layer is disposed; and the dielectric connects the dielectric layer on the one main surface side in contact with the auxiliary internal electrode to the dielectric layer on the other main surface side.

[0061] <2> The multilayer ceramic capacitor according to <1>, wherein the auxiliary internal electrodes are disposed on the first dielectric layers.

[0062] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the auxiliary internal electrodes are disposed on the second dielectric layers.

[0063] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein when the auxiliary internal electrode is divided at the center in a direction from the one surface on which the auxiliary internal electrode is exposed toward the internal electrode, into a side region on the side of the side surface and a central region on the side of the internal electrode, the through hole is arranged in the central region.

[0064] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein, when a dimension in a direction parallel to the width direction or the length direction from the one surface on which the auxiliary internal electrode is exposed to an edge of the internal electrode on the one surface side is D, and a dimension of the auxiliary internal electrode in a direction parallel to the width direction or the length direction from the one surface toward the internal electrode is d, D / 5<d<D×4 / 5 is satisfied.

[0065] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the auxiliary internal electrodes have the through holes, the maximum dimension r of which in a direction parallel to the width direction or the length direction from the one surface on which the auxiliary internal electrode is exposed toward the internal electrodes satisfies d / 200≦r≦d / 5.

[0066] 1 Multilayer ceramic capacitor 2 Laminated body 3 End surface external electrode 4 Side surface external electrode 14 Dielectric layer 14A First dielectric layer 14B Second dielectric layer 15 Internal electrode 15A End surface exposed internal electrode 15Aa End surface opposing portion 15Ab End surface drawing portion 15B Side surface exposed internal electrode 15Ba Side surface opposing portion 15Bb Side drawer part 15a Opposing part 15b Puller part 16 Auxiliary internal electrode 16A Side surface exposed auxiliary internal electrode 16B End face exposed auxiliary internal electrode 16a Side side region 16b Center side region 16h Through hole

Claims

1. a laminate in which a plurality of dielectric layers, on which internal electrodes are arranged, are laminated, the laminate having two main surfaces provided on both sides in a lamination direction, two side surfaces provided on both sides in a width direction intersecting the lamination direction, and two end surfaces provided on both sides in a length direction intersecting the lamination direction and the width direction; The laminate includes an end face external electrode disposed on the end face and a side face external electrode disposed on the side face, the internal electrodes include end surface exposed internal electrodes exposed at the end surfaces and side surface exposed internal electrodes exposed at the side surfaces, the end surface exposed internal electrodes and the side surface exposed internal electrodes each having an opposing portion opposing to each other and an extraction portion extracted from the opposing portion, the dielectric layer includes a first dielectric layer on which the end surface exposed internal electrodes are arranged, and a second dielectric layer on which the side surface exposed internal electrodes are arranged and which is laminated alternately with the first dielectric layer, In at least one of the first dielectric layer and the second dielectric layer, the side surface or the end surface is provided on one surface side where the internal electrode arranged on the one dielectric layer is not exposed, an auxiliary internal electrode is disposed so as to be spaced apart from the internal electrode, exposed on the one surface, and opposed to a lead portion of another internal electrode adjacent to the internal electrode in the stacking direction; each of the auxiliary internal electrodes has a through hole penetrating in the lamination direction and in which a dielectric made of the same material as the dielectric layer is disposed, and the dielectric layer on one main surface side in contact with the auxiliary internal electrode is connected to the dielectric layer on the other main surface side by the dielectric; Multilayer ceramic capacitor.

2. The auxiliary internal electrode is disposed on the first dielectric layer. The multilayer ceramic capacitor according to claim 1 .

3. The auxiliary internal electrode is disposed on the second dielectric layer. The multilayer ceramic capacitor according to claim 1 or 2.

4. when the auxiliary internal electrode is divided at the center in a direction from the one surface on which the auxiliary internal electrode is exposed toward the internal electrode, into a side region on the side of the side surface and a central region on the side of the internal electrode, the through hole is arranged in the central region. The multilayer ceramic capacitor according to claim 1 or 2.

5. When the dimension in the direction parallel to the width direction or the length direction from the one surface on which the auxiliary internal electrode is exposed to the edge of the one surface side of the internal electrode is defined as D, and the dimension in the direction parallel to the width direction or the length direction from the one surface toward the internal electrode of the auxiliary internal electrode is defined as d, D / 5<d<D×4 / 5 3. The multilayer ceramic capacitor according to claim 1, wherein

6. The auxiliary internal electrode has a maximum dimension r in a direction parallel to the width direction or the length direction from the one surface on which the auxiliary internal electrode is exposed toward the internal electrode, d / 200≦r≦d / 5 The through hole has The multilayer ceramic capacitor according to claim 1 or 2.