Shunt circuit

Abstract

A shunt transistor (50) is constituted of an N-type field effect transistor and forms a current path for maintaining the voltage of a power line (PL) at a shunt voltage when the power supply voltage (AVDD) is at or above the shunt voltage. A bias circuit (30) and an error amplifier (40) control the shunt transistor (50) so as to sequentially form, in accordance with a rise in the power supply voltage (AVDD) within a voltage range lower than the shunt voltage, a state in which the shunt transistor (50) is biased so as to operate in a sub-threshold region and a state in which the shunt transistor (50) is biased so as to operate in a strong inversion region. Furthermore, when the power supply voltage (AVDD) is at or above the shunt voltage, the bias circuit (30) and the error amplifier (40) set a gate voltage (Vgsnt) to the power supply voltage (AVDD) under a state in which the shunt transistor (50) operates in the strong inversion region.

Description

Shunt Circuit

[0001] The present disclosure relates to shunt circuits.

[0002] The application of energy harvesting, which converts natural energy such as sunlight into electric power, is expanding. However, when an energy harvesting power supply generates an input power supply voltage for a circuit such as a system LSI (Large Scale Integration), there is a concern that fluctuations in the generated energy may cause the power supply voltage of the circuit to become excessive, exceeding the withstand voltage of elements within the circuit.

[0003] For this reason, a so-called shunt circuit technology is known, which releases power to ground when the input power supply voltage exceeds a certain level. Japanese Patent Laid-Open Publication No. 2005-229563 (Patent Document 1) describes a power supply voltage monitoring circuit having a shunt circuit, and in particular, describes a technology for suppressing power consumption by the shunt circuit by providing an on / off control signal for the shunt circuit. The shunt circuit is configured to perform switching operation using a transistor that is connected between the power supply wiring and the ground wiring and is turned on and off in response to the on / off control signal.

[0004] Japanese Patent Application Laid-Open No. 2005-229563

[0005] However, in the configuration of Patent Document 1, when the power supply voltage exceeds the reference voltage, the comparator changes the logic level of the on / off control signal, and in response, the shunt transistor switches from an off state to an on state, thereby preventing the power supply voltage from rising.

[0006] This raises concerns about the long delay between when a rise in the power supply voltage is detected and when the shunt transistor is fully turned on and the current path required for the shunt is established. In particular, in energy harvesting power supply applications, which tend to experience large power supply voltage fluctuations as mentioned above, this delay time cannot be ignored, raising concerns about the occurrence of overvoltage.

[0007] The present disclosure has been made to solve such problems, and an object of the present disclosure is to provide a shunt circuit configuration that can achieve both the effect of preventing overvoltage and low power consumption.

[0008] According to one aspect of the present invention, a shunt circuit includes a voltage detection circuit for detecting a power supply voltage, a shunt transistor, and a shunt transistor control circuit for controlling the operating state of the shunt transistor. The shunt transistor is electrically connected between a power supply line receiving a power supply voltage and a reference voltage line transmitting a reference voltage, and forms a current path for maintaining the voltage of the power supply line at the shunt voltage when the power supply voltage exceeds a predetermined shunt voltage. The shunt transistor is an N-type field-effect transistor. The shunt transistor control circuit controls the shunt transistor so that, in a voltage range lower than the shunt voltage, a first bias state in which the shunt transistor is biased to operate in a subthreshold region and a second bias state in which the shunt transistor is biased to operate in a strong inversion region are sequentially formed in response to an increase in the power supply voltage detected by the voltage detection circuit. Furthermore, when the power supply voltage exceeds the shunt voltage, the shunt transistor control circuit sets the gate voltage of the shunt transistor to the power supply voltage while the shunt transistor is operating in the strong inversion region.

[0009] According to the present disclosure, in a region where the power supply voltage is lower than the shunt voltage, a minute current is generated to cause the shunt transistor to operate in the subthreshold region in response to an increase in the power supply voltage, and then the shunt transistor operates in the strong inversion region in response to a further increase in voltage. This allows a current path to be formed quickly by the shunt transistor when the power supply voltage becomes equal to or higher than the shunt voltage, thereby realizing a shunt circuit that can achieve both the effect of preventing overvoltage and low power consumption.

[0010] 1. A block diagram showing an example of the configuration of a shunt circuit according to a first embodiment. 2. A schematic waveform diagram explaining the operation of the voltage detection circuit shown in FIG. 1. 3. A circuit diagram explaining an example of the configuration of the bias circuit shown in FIG. 1. 4. A circuit diagram explaining an example of the configuration of the error amplifier shown in FIG. 1. 5. A conceptual diagram showing current-voltage characteristics in a subthreshold region (weak inversion region) and a strong inversion region of a transistor. 6. A conceptual waveform diagram explaining the operation of the shunt circuit according to the first embodiment. 7. A conceptual waveform diagram explaining the operation of the shunt circuit in Patent Document 1. 8. A conceptual waveform diagram explaining the operation of the shunt circuit according to the first embodiment. 9. A circuit diagram explaining an example of the configuration of the start pulse generation circuit shown in FIG. 10. 11. A timing chart explaining the operation of the bias circuit according to the second embodiment.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.

[0012] First Embodiment Fig. 1 is a block diagram showing an example of the configuration of a shunt circuit 100 according to a first embodiment.

[0013] As shown in FIG. 1 , the power supply wiring PL receives a power supply voltage AVDD from an input power supply 150. The input power supply 150 has a current source 160 that generates an input current Iin from power (external power supply voltage EXVDD) generated by energy harvesting or the like, and a capacitor 162. The capacitor 162 is connected between the power supply wiring PL and a reference voltage wiring NL that transmits a reference voltage AGND. The current source 160 outputs the input current Iin to the power supply wiring PL. The power supply voltage AVDD increases as the capacitor 162 is charged by the input current Iin.

[0014] Since the reference voltage AGND is typically ground (ground voltage), the reference voltage AGND will be referred to as the ground voltage AGND, and the reference voltage line NL will also be referred to as the ground line NL. Furthermore, the current source 160 may be configured as an AC current source, and the input power supply 150 may be configured to include a voltage source.

[0015] The load circuit 200 operates by receiving a power supply voltage AVDD from the power supply line PL. The shunt circuit 100 operates so that the power supply voltage AVDD on the power supply line PL does not exceed a predetermined shunt voltage VRsnt, i.e., so that AVDD≦VRsnt is maintained.

[0016] The shunt circuit 100 according to the first embodiment includes a voltage divider circuit 5 , voltage detection circuits 10 and 20 , a bias circuit 30 , an error amplifier 40 , and a shunt transistor 50 .

[0017] The voltage divider circuit 5 has resistor elements Rd1 and Rd2 connected in series between the power supply line PL and the ground line NL. The voltage divider circuit 5 generates a divided voltage VR by dividing the power supply voltage AVDD using the resistor elements Rd1 and Rd2. If the resistance values ​​of the resistor elements Rd1 and Rd2 are also denoted by the same symbols, then the voltage division ratio Kv = Rd2 / (Rd1 + Rd2) is used, and the relationship VR = Kv AVDD holds (0 < Kv < 1.0) between the power supply voltage AVDD and the divided voltage VR.

[0018] The voltage detection circuit 10 compares the divided voltage VR with a reference voltage Vref1, and outputs a detection signal VPOR having a logic level corresponding to the comparison result between the power supply voltage AVDD and a predetermined reference voltage VRpor. The detection signal VPOR corresponds to a so-called power-on reset signal. The reference voltage Vref1 of the voltage detection circuit 10 is set to be Kv times the reference voltage VRpor, taking into account the voltage division ratio Kv of the voltage divider circuit 5 (Vref1 = VRpor x Kv).

[0019] When the power supply voltage AVDD rises from a state lower than the determination voltage VRpor to a state equal to or higher than the determination voltage VRpor, the output of the voltage detection circuit 10 changes from a logical low level (hereinafter simply referred to as "L level") to a logical high level (hereinafter simply referred to as "H level"), thereby generating a detection signal VPOR. An inverter 11 generates an inverted signal VPORn of the detection signal VPOR.

[0020] The voltage detection circuit 20 compares the divided voltage VR with a reference voltage Vref2 to output a detection signal VSAV having a logic level corresponding to the comparison result between the power supply voltage AVDD and a predetermined reference voltage VRsav. The reference voltage VRsav is preset to a voltage higher than the reference voltage VRpor and lower than the shunt voltage VRsnt (VRpor<VRsav<VRsnt). The reference voltage Vref1 of the voltage detection circuit 20 is set to be Kv times the reference voltage VRsav, taking into account the voltage division ratio Kv of the voltage divider circuit 5 (Vref2=VRsav×Kv). The inverter 21 generates an inverted signal VSAVn of the detection signal VSAV.

[0021] When the power supply voltage AVDD rises from a state lower than the determination voltage VRsav to the determination voltage VRsav or higher, the output of the voltage detection circuit 20 changes from L level to H level, thereby generating the detection signal VSAV.

[0022] As a result, by generating the detection signals VPOR and VSAV, the voltage detection circuits 10 and 20 can detect whether the power supply voltage AVDD, when lower than the shunt voltage VRsnt, belongs to: (i) the voltage range of AGND≦AVDD<VRpor (VPOR=VSAV=L level) corresponding to the "third voltage range," (ii) the voltage range of VRpor≦AVDD<VRsav (VPOR=H level, VSAV=L level) corresponding to the "second voltage range," or (iii) the voltage range of VRsav≦AVDD<VRsnt (VPOR=VSAC=H level) corresponding to the "first voltage range."

[0023] The shunt transistor 50 is an N-type field effect transistor and is connected between the power supply line PL and the ground line NL. The gate of the shunt transistor 50 is connected to the output node of the error amplifier 40.

[0024] The error amplifier 40 compares the divided voltage VR with a reference voltage Vref3, amplifying the difference between the power supply voltage AVDD and a predetermined shunt voltage VRsnt, and outputs the amplified voltage to the gate of the shunt transistor 50. The reference voltage Vref3 of the error amplifier 40 is set to be Kv times the shunt voltage VRsnt, taking into account the voltage division ratio Kv of the voltage divider circuit 5 (Vref3 = VRsnt x Kv). The bias circuit 30 receives the detection signals VPOR and VSAV and the inverted signals VPORn and VSAVn, and supplies a bias current Ibias corresponding to the operating current of a group of transistors (described below) that constitute the error amplifier 40. The bias current Ibias is controlled in response to the detection signals VPOR and VSAV.

[0025] Generally, a resistor R0 and a capacitor C0 constituting a phase compensation RC circuit are connected in series between the gate of the shunt transistor 50 and the power supply line PL. As a result, when the output voltage of the error amplifier 40 changes, the gate voltage Vgsnt of the shunt transistor 50 changes with a time delay according to the time constant of the phase compensation RC circuit.

[0026] When the power supply voltage AVDD becomes equal to or higher than the shunt voltage VRsnt (AVDD≧VRsgt), the gate voltage Vgsnt is set to the H level, i.e., the power supply voltage AVDD, by the error amplifier 40. On the other hand, in a region where the power supply voltage AVDD is lower than the shunt voltage VRsnt (AVDD<VRsgt), the gate voltage Vgsnt changes according to the operating state (bias state) of the transistor group (described below) constituting the error amplifier 40 and the shunt transistor 50, which is determined depending on the bias current Ibias output from the bias circuit 30, as will be described later.

[0027] In this way, the operating state of the shunt transistor 50 changes depending on the operations of the bias circuit 30 and the error amplifier 40. That is, the bias circuit 30 and the error amplifier 40 can constitute one embodiment of a "shunt transistor control circuit."

[0028] Fig. 2 is a schematic waveform diagram illustrating the operation of the voltage detection circuits 10 and 20 shown in Fig. 1. Fig. 2 shows an example of operation when the power supply voltage AVDD rises due to the start of the input power supply 150 (for example, when the energy harvesting power supply starts generating power).

[0029] As shown in FIG. 2, when the input power supply 150 is started at time t0, the power supply voltage AVDD rises and becomes equal to or higher than the determination voltage VRpor at time t1, and further becomes equal to or higher than the determination voltage VRsav at time t2.

[0030] As a result, the detection signal VPOR from the voltage detection circuit 10 is at L level from time t0 to t1, but is at H level after time t1. Similarly, the detection signal VSAV from the voltage detection circuit 20 is at L level from time t0 to t2, but is at H level after time t2.

[0031] After time t2, the power supply voltage AVDD rises while both the detection signals VPOR and VSAV are generated (VPOR=VSAV=H level). At time t3, when the power supply voltage AVDD reaches the shunt voltage VRsnt, the shunt transistor 50 is turned on completely, and a current path that prevents the rise of the power supply voltage AVDD is formed between the power supply wiring PL and the ground wiring NL.

[0032] 2, for comparison, the waveform of the power supply voltage AVDD when the shunt circuit 100 is not provided is shown by a dotted line. As a result of providing the shunt circuit 100, the power supply voltage AVDD is maintained at the shunt voltage VRsnt after time t3.

[0033] In this embodiment, for example, the shunt voltage VRsnt is 5 V, whereas the determination voltage VRpor is about 1.5 V and the determination voltage VRsav is about 4 V. In addition, in this embodiment, the threshold voltage Vt (design value) of each transistor including the shunt transistor 50 is 1.0 V.

[0034] Next, an example of the configuration and detailed operation of the bias circuit 30 and the error amplifier 40 will be described.

[0035] Fig. 3 is a circuit diagram illustrating an example of the configuration of the bias circuit 30 shown in Fig. 1. As shown in Fig. 3, the bias circuit 30 includes transistors MN1 and MN2 configured as N-type field effect transistors, transistors MP1 to MP3 configured as P-type field effect transistors, resistance elements R1 and R2, and switches SW0 to SW2.

[0036] The transistors MP1 and MP2 are connected between the power supply line PL and the nodes N1 and N2, respectively. The transistor MP3 is connected between the power supply line PL and the output node Nob of the bias current Ibias. Since the gates of the transistors MP1 to MP3 are connected to the node N2, the transistor MP2 is diode-connected and the transistors MP1 to MP3 form a current mirror.

[0037] Here, the description will proceed assuming that the transistors MP1 to MP3 have the same transistor size. Therefore, the relationship I1=I2=Ibias holds between the current I1 at node N1, the current I2 at node N2, and the bias current Ibias.

[0038] The transistor MN1 is connected between the node N1 and the ground line NL, and the transistor MN2 is connected between the nodes N2 and N3. The transistor MN2 has a transistor size K times (K: K is a real number greater than 2) that of the transistor MN1.

[0039] The gates of transistors MN1 and MN2 are connected to node N1 via switch SW0 and to ground line NL via switch SW1. Switch SW0 is turned off when detection signal VPOR is at L level and turned on when detection signal VPOR is at H level. Conversely, switch SW1 is turned off when detection signal VPOR is at H level and turned on when detection signal VPOR is at L level in response to an inverted signal VPORn of detection signal VPOR. Therefore, the gates of transistors MN1 and MN2 are connected to node N1 or ground line NL (ground voltage AGND) in accordance with detection signal VPOR.

[0040] The resistive element R1 is connected between the node N3 and the ground wiring NL. The resistive element R2 is connected in series with the switch SW2 between the node N3 and the ground wiring NL. Hereinafter, the electrical resistance values ​​of the resistive elements R1 and R2 will also be referred to as R1 and R2. The switch SW2 is turned on when the detection signal VSAV is at an H level, and is turned off when the detection signal VSAV is at an L level.

[0041] When both the detection signals VPOR and VSAV are at the L level (AGND≦AVDD<VRpor: third voltage range), in the bias circuit 30, the switches SW0 and SW2 are turned off, while the switch SW1 is turned on. Therefore, in the bias circuit 30, the gate voltages of the transistors MN1 and MN2 become the ground voltage AGND, the gate-source voltage Vgs becomes 0, and the transistors MN1 and MN2 are completely off. Therefore, the currents I1 and I2 become 0, and the bias current Ibias also becomes zero (Ibias=0).

[0042] Next, the operation of the bias circuit 30 will be described when the detection signal VPOR is at a high level while the detection signal VSAV is at a low level (VPOR≦AVDD<VRsav: second voltage range). At this time, the switches SW1 and SW2 are turned off, while the switch SW0 is turned on. As a result, the gates of the transistors MN1 and MN2 are disconnected from the ground line NL and connected to the node N1. This causes a current I2 corresponding to the electrical resistance value (R1) of the resistor element R1 to be generated in the bias circuit 30. Furthermore, due to the current mirror formed by the transistors MP1 to MP3, I2 = I1 = Ibias. The resistor element R1 is designed to have an electrical resistance value (R1), for example, several hundred MΩ, such that the currents I1, I2, and Ibias generate a drain current Ids on the order of nanoamperes (nA) (e.g., on the order of 10 nA) to operate the field-effect transistor in the subthreshold region (weak inversion region).

[0043] Here, the drain current Ids in the subthreshold region of a field-effect transistor is expressed by the following formula (1) using the gate-source voltage Vgs, the threshold voltage Vt, the Boltzmann constant k, the temperature T [K], and the thermal voltage VT expressed by the elementary charge. Note that the coefficients η and I0 in formula (1) are constants determined by the process.

[0044] Ids=I0·(W / L)·exp((Vgs−Vt) / (η·VT)) (1) where VT=k·T / q When I1=I2 is solved for transistors MN1 and MN2 operating in the subthreshold region, the following equation (2) is obtained.

[0045] I1=I2=η·VT·ln(K) / R1 (2) That is, by adjusting the electrical resistance value of the resistance element R1, the bias circuit 30 can generate a bias current Ibias=Ib1 equivalent to the drain current Ids when each field effect transistor operates in the subthreshold region. As described above, Ib1 is adjusted to the order of 10 nA.

[0046] Next, the operation of the bias circuit 30 when both the detection signals VPOR and VSAV are at the H level (VRsav≦AVDD<VRsnt: first voltage range) will be described. At this time, the switch SW1 is turned off, while the switches SW0 and SW2 are turned on. As a result, in the bias circuit 30, compared to when the detection signal VPOR is at the H level and the detection signal VSAV is at the L level, the resistance elements R1 and R2 are connected in parallel between the node N3 and the ground wiring NL, and the electrical resistance value between the node N3 and the ground wiring NL changes.

[0047] Here, the resistor R2 is designed to have an electrical resistance (R2), for example, of about 100 kΩ, such that the currents I1, I2, and Ibias generate a drain current Ids on the order of microamperes (μA) (for example, on the order of 10 μA) to operate the field-effect transistor in the strong inversion region. In this way, since R2<<R1, when the switch SW2 is on, the electrical resistance between the node N3 and the ground wiring NL can be approximated to R2.

[0048] Here, the drain current Ids in the strong inversion region of a field-effect transistor is expressed by the following equations (3) and (4) using the gate-source voltage Vgs, the threshold voltage Vt, and a coefficient β. In equation (4), μ is the electron mobility, Cox is the gate capacitance per unit area, W is the gate width, and L is the gate length.

[0049] Ids=(1 / 2)・β・(Vgs-Vt) ２ (3) β=μ·Cox / (W / L) (4) When I1=I2 is solved for the transistors MN1 and MN2 operating in the strong inversion region, the following equation (5) is obtained.

[0050] I1=I2=(2 / β)・(1 / R2 ２ )·(1−1 / √K)) ... (5) By adjusting the electrical resistance value of the resistive element R2, the bias circuit 30 can generate a bias current Ibias=Ib2 equivalent to the drain current Ids when each field-effect transistor operates in the strong inversion region. As described above, Ib2 is adjusted to the order of 10 (μA).

[0051] In this way, the bias circuit 30 controls the bias current Ibias to Ibias=0 (VPOR=VSAV=L level), Ibias=Ib1 (VPOR=H level, VSAV=L level), or Ibias=Ib2 (VPOR=VSAV=H level) according to the detection signals VPOR and VSAV.

[0052] Fig. 4 is a circuit diagram illustrating an example configuration of the error amplifier 40 shown in Fig. 1. As shown in Fig. 4, the error amplifier 40 includes transistors MNB0, MNB1, and MN11 to MN14 configured as N-type field effect transistors, and transistors MP11 to MP14 configured as P-type field effect transistors.

[0053] The transistors MP11 and MP12 are connected between the power supply line PL and the nodes N11 and N12, respectively. The gates of the transistors MP11 and MP12 are connected to the nodes N11 and N12, respectively, and the transistors MP11 and MP12 are diode-connected.

[0054] Furthermore, transistor MP13 is connected between power supply line PL and node N14, and transistor MP14 is connected between power supply line PL and output node Ng connected to the gate of shunt transistor 50. The gate of transistor MP13 is connected to the gate of transistor MP12, and the gate of transistor MP14 is connected to the gate of transistor MP11. Transistors MP11 to MP14 form a folded active load.

[0055] The transistor MN13 is connected between the node N14 and the ground wiring NL, and the transistor MN14 is connected between the output node Ng and the ground wiring NL. The gates of the transistors MN13 and MN14 are connected to the node N14, and the transistor MN13 is diode-connected. The transistors MN13 and MN14 form an active load. The transistor MN14 is connected between the gate of the shunt transistor 50 and the ground wiring NL. As a whole, the error amplifier 40 including the transistors MN13 and MN14 and the shunt transistor 50 form a so-called shunt amplifier (shunt regulator).

[0056] The transistor MN11 is connected between the node N11 and the node N13, and the transistor MN12 is connected between the node N12 and the node N13. The divided voltage VR is input to the gate of the transistor MN11, and a determination voltage Vref3 (Vref3=Kv·VRsnt) corresponding to the shunt voltage VRsnt is input to the gate of the transistor MN12. The transistors MN11 and MN12 form a differential amplifier.

[0057] A transistor MNB1 is connected between the node N13 and the ground line NL, and a transistor MNB0 is connected between the output node Nob of the bias circuit 30 and the ground line NL. The gates of the transistors MNB0 and MNB1 are connected to the output node Nob. Therefore, the transistors MNB0 and MNB1 form a current mirror that converts the current I13 flowing through the node N13 into the bias current Ibias from the bias circuit 30. As a result, the operating current flowing through the group of transistors that make up the error amplifier 40 is controlled by the bias current Ibias from the bias circuit 30.

[0058] In the region where VR≧Vref3 (i.e., AVDD≧VRsnt), the output from the error amplifier 40 changes to the H level, and the gate voltage Vgsnt changes to the power supply voltage AVDD, fully turning on the shunt transistor 50. In contrast, in the region where VR<Vref3 (i.e., AVDD<VRsnt), the gate voltage Vgsnt from the shunt transistor 50 changes depending on the operating current (Ibias).

[0059] Fig. 5 is a conceptual diagram showing the current-voltage characteristics of a field-effect transistor in the subthreshold region (weak inversion region) and strong inversion. The horizontal axis of Fig. 5 shows the gate-source voltage Vgs, and the vertical axis shows the drain current Ids on a logarithmic scale.

[0060] 5, in the subthreshold region (weak inversion region), the drain current Ids changes exponentially with respect to the gate-source voltage Vgs, as shown in the above formula (1). On the other hand, in the strong inversion region, the drain current Ids increases as the square of the gate-source voltage Vgs, as shown in the above formula (3).

[0061] The gate-source voltage Vgs=Vbd, which is the boundary between the subthreshold region (weak inversion region) and the strong inversion region, relative to the threshold voltage Vt of the transistor, is given by the following equation (6):

[0062] 4, when Vref1≦VR<Vref2 (i.e., VRpor≦AVDD<VRsav), the bias circuit 30 controls the bias current Ibias to Ib1. In this voltage range, VR<Vref3 (AVDD<VRpsht), so the shunt transistor 50 is not turned on, and the transistor group constituting the error amplifier 40 and each transistor of the shunt transistor 50 are biased at an operating point OP1 in the subthreshold region by the bias current Ibias=Ib1 flowing through them. This bias state corresponds to the "first bias state."

[0063] At this time, the gate voltage of each transistor is determined as a gate-source voltage Vgs in the subthreshold region, which is a voltage value V1 according to an operating point OP1 on the Vgs-Ids characteristic line in the subthreshold region in FIG.

[0064] For example, when VPOR=H level and VSAV=L level (i.e., VRpor≦AVDD<VRsav), the bias current Ibias=Ib1 can be adjusted by the electrical resistance value of the resistance element R1 so that V1=Vt-0.2 [V] relative to the threshold voltage Vt.

[0065] Next, in the voltage range of Vref2≦VR<Vref3 (i.e., VRsav≦AVDD<VRsnt), the bias current Ibias is controlled to Ib2 by the bias circuit 30. Even in this voltage range, the shunt transistor 50 is not turned on, and the transistor group constituting the error amplifier 40 and each transistor of the shunt transistor 50 are placed in a bias state in which they operate in the strong inversion region due to the bias current Ibias=Ib2 flowing through them. This bias state corresponds to the "second bias state."

[0066] When the detection signal VSAV changes from L level to H level and the bias current Ibias changes to Ib2, the gate voltage Vgsnt is determined as the gate-source voltage Vgs in the strong inversion region to a voltage value V2 in accordance with the operating point OP2 on the Vgs-Ids characteristic line in the subthreshold region in FIG. 5.

[0067] For example, the bias current Ibias=Ib2 when the detection signal VPOR=VSAV=H level (i.e., in the range VRsav≦AVDD<VRsnt) can be adjusted by the electrical resistance value of the resistive element R2 so that V2=Vt+0.2 [V] relative to the threshold voltage Vt.

[0068] As a result, the shunt circuit 100 according to the first embodiment can operate as shown in FIG. 6 in response to an increase in the power supply voltage AVDD.

[0069] 6, in a voltage range in which the power supply voltage AVDD is lower than the determination voltage VRpor (i.e., VPOR=VSAV=L level) from time t0 to t1, the bias circuit 30 controls the bias current Ibias to 0, so that the transistors constituting the error amplifier 40 are completely turned off. As a result, the gate voltage Vgsnt of the shunt transistor 50 is controlled to 0, and the shunt transistor 50 is also completely turned off. In this state, the leakage current of each transistor and the shunt transistor 50 shown in FIGS. 3 and 4 is on the order of pA (picoamperes).

[0070] Next, from time t1 to t2 when the power supply voltage AVDD rises, in the voltage range of VRpor≦AVDD<VRsav (i.e., VPOR=H level, VSAV=L level), the bias circuit 30 controls the bias current Ibias to Ibias=Ib1 (FIG. 5) so that the error amplifier 40 and the transistors constituting the shunt transistor 50 operate at an operating point OP1 (FIG. 5) in the subthreshold region where the gate-source voltage Vgs is near the threshold voltage Vt. As a result, the gate voltage Vgsnt of the shunt transistor 50 is controlled to Vb1, and the shunt transistor 50 is biased in the subthreshold region (weak inversion region). In this state, the leakage current of each transistor and the shunt transistor 50 shown in FIGS. 3 and 4 is on the order of nA (nanoamperes).

[0071] Furthermore, in the voltage range VRsav≦AVDD<VRsnt (i.e., VPOR=VSAV=H level) from time t2 to t3 when the power supply voltage AVDD rises, the bias circuit 30 controls the bias current Ibias so that each transistor constituting the error amplifier 40 and the shunt transistor 50 operates in the strong inversion region.

[0072] At time t2 when the power supply voltage AVDD reaches the determination voltage VRsav, the bias circuit 30 controls the bias current Ibias to Ib2 (FIG. 5) so that the error amplifier 40 and the transistors constituting the shunt transistor 50 operate at an operating point OP2 (FIG. 5) within the strong inversion region where the gate-source voltage Vgs is near the threshold voltage Vt. As a result, the gate voltage Vgsnt of the shunt transistor 50 is controlled to Vb2, and the shunt transistor 50 is biased in the strong inversion region. In this state, the leakage current of the transistors and shunt transistor 50 shown in FIGS. 3 and 4 is on the order of μA (microamperes).

[0073] Between times t2 and t3, when the power supply voltage AVDD rises above the determination voltage VRsav after time t2, the current of the transistor MP1 increases slightly, which in turn increases the current of the transistor MN14 slightly, resulting in a slight increase in the gate voltage Vgsnt. In this voltage range, the gate voltage Vgsnt is at least lower than the shunt voltage VRsnt.

[0074] As the power supply voltage AVDD further rises and enters the voltage range of AVDD > VRsnt after time t3, the output of the error amplifier 40 changes to the H level, so that the gate voltage Vgsnt rises to the power supply voltage AVDD and the shunt transistor 50 turns fully on. As a result, a current path (shunt path) is formed from the power supply wiring PL to the ground wiring NL, and therefore, even if the power supplied from the input power supply 150 increases, the power supply voltage AVDD does not rise as indicated by the dotted line, and the power supply voltage AVDD is maintained at the shunt voltage VRsnt.

[0075] Next, the operation of the shunt circuit in Patent Document 1 will be compared with that of the shunt circuit according to Embodiment 1 using Figures 7 and 8. As in Figure 2, Figures 7 and 8 show, by dotted lines, the waveform of the power supply voltage AVDD when the shunt circuit is not provided, and also show conceptual waveforms of the power supply voltage AVDD and the current consumption Icns when the shunt circuit is provided.

[0076] 7 shows the operation of the shunt circuit in Patent Document 1. Referring to FIG. 7, the shunt circuit is started at time t0 and the power supply voltage AVDD rises. However, in the shunt circuit described in Patent Document 1, during the period until the power supply voltage AVDD rises to the shunt voltage VRsnt (times t0 to t3), the on / off control signals of the shunt circuit can cause each transistor constituting the shunt circuit to be in a "completely off state (leakage current on the order of pA)" as in this embodiment. Therefore, the current consumption Icns during this period can be made almost zero (on the order of pA).

[0077] However, at time t3 when the power supply voltage AVDD reaches the shunt voltage VRsnt, the shunt transistor must switch from a fully off state to a strong inversion region and then to a fully on state. Therefore, the gate voltage must change from 0 V to the strong inversion region, i.e., to the operating point OP2 in Figure 6. As described above, if Vt = 1.0 V and the voltage value V2 at the operating point OP2 = Vt + 0.2 V, then a gate charging time is required to increase the gate voltage from 0 V to 1.2 V in order to turn on the shunt transistor.

[0078] For example, if the sum of the gate capacitance of the shunt transistor and the capacitance value of the phase compensation capacitor C0 shown in Figure 1 is 10 [pF] and the gate charging current (equivalent to the operating current of the error amplifier) ​​is 10 [μA], the gate charging time Tc required for the shunt transistor 50 to operate in the strong inversion region is 10 [pF] · 1.2 [V] / 10 [μA] = 1.2 [μs].

[0079] Therefore, if the rate of change of the power supply voltage AVDD is fast compared to the gate charging time, a delay occurs in turning on the shunt transistor 50 relative to the rise in the power supply voltage AVDD, as shown in Fig. 7. This may cause the power supply voltage AVDD to rise higher than the shunt voltage VRsnt, resulting in a period of overvoltage.

[0080] In contrast, Fig. 8 shows the operation of the shunt circuit 100 according to embodiment 1. In Fig. 8, with respect to a change in power supply voltage AVDD equivalent to that in Fig. 7, before time t3 at which AVDD≧VRsnt, the transistors constituting the bias circuit 30 and the error amplifier 40 and the shunt transistor 50 change from a completely off state to a bias state in the subthreshold region (time t1) in response to an increase in power supply voltage AVDD, and then further change to a bias state in the strong inversion region (time t2).

[0081] That is, after the power supply voltage AVDD becomes equal to or greater than the judgment voltage VRsav, the power supply voltage AVDD reaches the shunt voltage VRsnt while the shunt transistor 50 is biased in the strong inversion region, so that a shunt path can be quickly formed by the shunt transistor 50 at the timing when AVDD≧VRsnt.

[0082] As described above, if the voltage value V1 of the operating point OP1 in the bias state in the subthreshold region (weak inversion region) is Vt-0.2 [V], the increase in gate voltage required to change the shunt transistor 50 from the bias state in the weak inversion region to the bias state in the strong inversion region is 0.4 [V]. Therefore, with a capacitance value of 10 [pF] and a charging current of 10 [μs] similar to those described in FIG. 7 , the gate charging time Tc for the shunt transistor 50 to operate in the strong inversion region is 10 [pF]·0.4 [V] / 10 [μA]=0.4 [μs], which is significantly shorter than the example shown in FIG. 7 .

[0083] As a result, it is possible to suppress an overvoltage caused by a delay in forming a shunt path by the shunt transistor 50 in response to an increase in the power supply voltage AVDD.

[0084] In the shunt circuit 100 according to the first embodiment, the current consumption Icns is substantially zero (a leakage current on the order of pA) during the period from time t0 to t3 in FIG. 8, while a current on the order of nA (Ib1 in FIG. 6) is consumed during the period from time t1 to t2 and a current on the order of μA (Ib2 in FIG. 6) is consumed during the period from time t2 to t3. However, these currents are small, and their disadvantages are small compared to the above-described effect of suppressing overvoltage. In particular, by providing a preliminary period in which the circuit operates in the subthreshold region with a minute current before operating in the strong inversion region, both low power consumption and high-speed operation can be achieved.

[0085] Therefore, according to the shunt circuit of the first embodiment, before the power supply voltage AVDD rises to the shunt voltage VRsnt, the shunt transistor 50 can be made to operate in advance in the subthreshold region and the strong inversion region, consuming a minute current (on the order of nA and μA) in response to the rise in the power supply voltage AVDD. As a result, when the power supply voltage AVDD reaches the shunt voltage VRsnt, a current path (shunt path) can be quickly formed by the shunt transistor 50, thereby enhancing the overvoltage suppression effect without significantly increasing power consumption.

[0086] Second Embodiment In a second embodiment, an improvement in the circuit configuration for further increasing the speed at which a current path is formed by the shunt transistor 50 when the power supply voltage AVDD reaches the shunt voltage VRsnt will be described.

[0087] 9 is a circuit diagram illustrating an example configuration of a bias circuit 30X according to embodiment 2. The shunt circuit according to embodiment 2 is configured by generating bias current Ibias using bias circuit 30X of FIG. 9 instead of bias circuit 30 (FIG. 3) in shunt circuit 100 described in embodiment 1. Other points are the same as those in embodiment 1, and therefore detailed description will not be repeated.

[0088] 9, the bias circuit 30X according to the second embodiment differs from the bias circuit 30 shown in FIG. 3 in that it further includes a resistor element R3 and a switch SW3 connected in series between the node N3 and the ground line NL. The resistor element R3 and the switch SW3 are connected in parallel to the resistor element R2 and the switch SW2. The other configuration of the bias circuit 30X is the same as that of the bias circuit 30.

[0089] The switch SW3 is turned on and off in response to the start pulse Vstr. Specifically, the switch SW3 is turned off during the L level period of the start pulse Vstr, and is turned on during the H level period of the start pulse Vstr.

[0090] 10 is a circuit diagram illustrating an example of the configuration of a start pulse Vstr generation circuit. Referring to FIG. 10, the start pulse generation circuit 31 includes a current source 32, a transistor 33, a capacitor 34, an inverter 35, and a logic gate 37.

[0091] The current source 32 is connected between the power supply wiring PL and the node N20. For example, the current source 32 can be configured by a diode-connected transistor. The transistor 33 is configured by, for example, an N-type field effect transistor, and is connected between the node N20 and the ground wiring NL. The detection signal VSAV from the voltage detection circuit 20 is input to the gate of the transistor 33.

[0092] The capacitor 34 is connected between the node N20 and the ground line NL. The inverter 35 outputs a voltage signal obtained by inverting the voltage level of the node N20 to the node N21.

[0093] During the L-level period of the detection signal VSAV, the transistor 33 is turned off, and the capacitor 34 is charged with a current from the current source 32, causing the voltage at the node N20 to be the power supply voltage AVDD, i.e., the H-level. At this time, the inverter 35 outputs an L-level voltage signal to the node N21.

[0094] When the detection signal VSAV changes from L level to H level, the transistor 33 turns on, discharging the capacitor 34 and changing the voltage at the node N20 to the ground voltage AGND, i.e., L level. As a result, the inverter 35 operates, and the voltage at the node N21 also changes from L level to H level.

[0095] However, there is a delay time between the time when the detection signal VSAV changes from L level to H level and the time when the voltage at node N21 changes from L level to H level, during which the voltage at node N20 changes from H level to L level due to the discharge of capacitor 34. This delay time depends on the product of the output current of current source 32 and the capacitance value of capacitor 34.

[0096] In this way, the inverter 35 inverts and outputs the voltage level of the node N20, thereby generating at the node N21 a delayed signal VSAVd of the detection signal VSAV that is in phase with the detection signal VSAV and to which the delay signal has been added.

[0097] The logic gate 37 generates a start pulse Vstr according to the result of a logical AND operation between the detection signal VSAV from the voltage detection circuit 20 and the delayed signal VSAVd generated at the node N21.

[0098] FIG. 11 shows a timing chart for explaining the operation of the bias circuit according to the second embodiment.

[0099] As shown in Figure 11, similar to Figure 2, at time t1, the detection signal VPOR from the voltage detection circuit 10 changes from L level to H level, and at time t2, the detection signal VSAV from the voltage detection circuit 20 changes from L level to H level.

[0100] The delayed signal VSAVd changes from L level to H level at time t2X, delayed by delay time Td relative to the detection signal VSAV. Therefore, the start pulse Vstr obtained by ANDing the detection signal VSAV and the delayed signal VSAVd is set to H level from time t2 to t2X, but is a pulse signal that is set to L level during the other periods. As can be seen from FIG. 11, during the H level period of the start pulse Vstr, the detection signals VPOR and VSAV are also at H level.

[0101] 9, during the H-level period of the start pulse Vstr, switch SW1 is turned off, while switches SW0, SW2, and SW3 are turned on. This results in parallel connection of resistor elements R1 to R3 between node N3 and ground wiring NL. The electrical resistance of resistor element R3 is designed to be lower than that of resistor element R2. For example, the electrical resistance of resistor element R2 is approximately 100 kΩ, while the electrical resistance of resistor element R3 is designed to be approximately 10 kΩ. In this way, while the bias current Ibias=Ib2 when resistor elements R1 and R2 are connected in parallel is on the order of 10 μA, the bias current Ibias=Ib3 when resistor elements R1 to R3 are connected in parallel can be set to the order of 100 μA (Ib3>Ib2).

[0102] 11, the bias current Ibias is set to Ib3 (e.g., 100 μA), which is larger than Ib2 (e.g., on the order of 10 μA), for a certain period (time t2 to t2X) immediately after the detection signal VSAV changes to the H level. Note that the length of the H level period of the start pulse Vstr corresponds to the delay time Td provided by the start pulse generation circuit 31, and therefore can be adjusted by the output current of the current source 32 and / or the capacitance value of the capacitor 34, as described above.

[0103] As a result, by increasing the bias current Ibias, i.e., the operating current of the error amplifier 40, for a certain period immediately after the shunt transistor 50 starts operating in the strong inversion region, the rate of change of the gate voltage Vgsnt when the power supply voltage AVDD reaches the shunt voltage VRsnt can be increased.

[0104] This allows a current path (shunt path) to be generated by the shunt transistor 50 more quickly when the power supply voltage AVDD reaches the shunt voltage VRsnt, thereby enhancing the effect of suppressing overvoltage.

[0105] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0106] 5 voltage divider circuit, 10, 20 voltage detection circuit, 30, 30X bias circuit, 31 start pulse generation circuit, 32, 160 current source, 33, MN1, MN2, MN11 to MN14, MNB0, MNB1, MP1 to MP3, MP11 to MP14 transistor, 34, 162, C0 capacitor, 35 inverter, 37 logic gate, 40 error amplifier, 50 shunt transistor, 100 shunt circuit, 150 input power supply, 200 load circuit, AGND ground voltage (reference voltage), AVDD power supply voltage, EXVDD external power supply voltage, Ibias bias current, Icns current consumption, NL ground wiring (reference voltage wiring), OP1, OP2 operating point, PL power supply wiring, R0 to R3, Rd1, Rd2 resistive elements, SW0 to SW3 Switch, Td delay time, VPOR, VSAV detection signal, VPORn inverted signal (detection signal), VR divided voltage, VRpor, VRsav, Vref1 to Vref3 judgment voltage, VRsnt shunt voltage, VSAVd delay signal (detection signal), Vgsnt gate voltage (shunt transistor), Vstr start pulse, Vt threshold voltage.

Claims

1. a shunt transistor electrically connected between a power supply wiring that receives a power supply voltage and a reference voltage wiring that transmits a reference voltage, and that forms a current path for maintaining the voltage of the power supply wiring at a predetermined shunt voltage when the power supply voltage becomes equal to or higher than the shunt voltage; a voltage detection circuit for detecting the power supply voltage; a shunt transistor control circuit that controls the operating state of the shunt transistor, the shunt transistor is an N-type field effect transistor, the shunt transistor control circuit controls the shunt transistor so that a first bias state in which the shunt transistor is biased to operate in a subthreshold region and a second bias state in which the shunt transistor is biased to operate in a strong inversion region are sequentially formed in response to an increase in the power supply voltage detected by the voltage detection circuit in a voltage range lower than the shunt voltage; The shunt transistor control circuit sets the gate voltage of the shunt transistor to the power supply voltage when the power supply voltage becomes equal to or higher than the shunt voltage, while the shunt transistor is operating in the strong inversion region.

2. The shunt transistor control circuit includes: an error amplifier for amplifying a difference voltage between the power supply voltage and the shunt voltage to set the gate voltage; a bias circuit that supplies an operating current flowing through a group of field effect transistors that constitute the error amplifier; the field effect transistor group includes an N-type field effect transistor electrically connected between the gate of the shunt transistor and the reference voltage wiring, the bias circuit supplies the operating current at a first current for operating the field effect transistor group in the subthreshold region in the first bias state, and supplies the operating current at a second current for operating the field effect transistor group in the strong inversion region in the second bias state; 2. The shunt circuit according to claim 1, wherein the gate voltage is determined by the shunt transistor being in a bias state according to the operating current when the power supply voltage is lower than the shunt voltage, and when the power supply voltage is equal to or higher than the shunt voltage, the gate voltage is set to the power supply voltage by the error amplifier.

3. the voltage detection circuit is configured to detect a voltage range to which the power supply voltage belongs, among a first voltage range, a second voltage range lower than the first voltage range, and a third voltage range lower than the second voltage range, which are obtained by dividing a voltage range lower than the shunt voltage; the shunt transistor control circuit controls an operating state of the shunt transistor in accordance with a voltage range to which the power supply voltage belongs and a comparison result between the power supply voltage and the shunt voltage; 2. The shunt circuit according to claim 1, wherein the shunt transistor control circuit sets the gate voltage to the reference voltage when the power supply voltage falls within the third voltage range, biases the shunt transistor to operate in the subthreshold region when the power supply voltage falls within the second voltage range, biases the shunt transistor to operate in the strong inversion region when the power supply voltage falls within the first voltage range, and sets the gate voltage to the power supply voltage when the power supply voltage becomes equal to or greater than the shunt voltage.

4. The shunt transistor control circuit includes: an error amplifier for amplifying a voltage difference between the power supply voltage and the shunt voltage to set the gate voltage; a bias circuit that supplies an operating current flowing through a group of field effect transistors that constitute the error amplifier; the field effect transistor group includes an N-type field effect transistor electrically connected between the gate of the shunt transistor and the reference voltage wiring, the bias circuit sets an operating current to zero when the power supply voltage is in the third voltage range, while supplying the operating current at a first current for operating the field effect transistor group in the subthreshold region when the power supply voltage is in the second voltage range, and supplying the operating current at a second current for operating the field effect transistor group in the strong inversion region when the power supply voltage is in the first voltage range; 4. The shunt circuit according to claim 3, wherein the gate voltage is determined by the shunt transistor being in a bias state according to the operating current when the power supply voltage is lower than the shunt voltage, and is set to the power supply voltage by the error amplifier when the power supply voltage is equal to or higher than the shunt voltage.

5. the first current is on the order of nanoamperes; 3. The shunt circuit according to claim 2, wherein the second current is on the order of microamperes.

6. 5. The shunt circuit according to claim 4, wherein the bias circuit sets the operating current to a third current higher than the second current for a predetermined period of time from the point at which the power supply voltage rises from the second voltage range to the first voltage range, and sets the operating current to the second current after the period of time has elapsed.

7. the gate voltage in the first bias state is higher than the reference voltage and lower than a threshold voltage of the shunt transistor; 7. The shunt circuit according to claim 1, wherein the gate voltage in the second bias state is higher than the threshold voltage and lower than the shunt voltage.