Semiconductor Device

Abstract

The semiconductor device (1) comprises a semiconductor layer (40), a first vertical MOS transistor (10) and a second vertical MOS transistor (20) formed in the semiconductor layer (40), a metal layer (30) in contact with the entire back surface side of the semiconductor layer (40), and a support (42) joined to the back surface side of the metal layer (30) via a conductive adhesive (41), in which, in a plan view, the support (42) has an area larger than that of the semiconductor layer (40) and contains the semiconductor layer (40), the thickness of the support (42) is larger than the thickness of the semiconductor layer (40), and includes the center of the semiconductor layer (40) and the outer periphery of the semiconductor layer (40) in a plan view. In a cross-sectional view of the semiconductor device (1), the semiconductor chip (2) excluding the support (42) and the conductive adhesive (41) from the semiconductor device (1) has a curved shape that is convex in a direction away from the support (42).

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device Regarding do. [Background technology]

[0002] In order to protect lithium-ion batteries from overcharging and / or over-discharging, a dual-configuration vertical MOS transistor capable of controlling bidirectional conduction with a single chip is used. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Pat. No. 4,616,413 Summary of the Invention [Problem to be solved by the invention]

[0004] In order to reduce the on-resistance of a dual-configuration vertical MOS transistor, it is preferable that the dual-configuration vertical MOS transistor (hereinafter, the dual-configuration vertical MOS transistor is also referred to as a "semiconductor chip") has a large area in a plan view and a thin semiconductor substrate. However, such a structure increases the warping of the semiconductor chip and reduces its strength. Patent Document 1 discloses a structure in which a printed circuit board is attached to a rigid metal plate via a conductive adhesive.

[0005] Therefore, an object of the present disclosure is to provide a semiconductor device including a dual-configuration vertical MOS transistor that can improve adhesion in a structure in which a rigid metal plate is attached via a conductive adhesive. [Means for solving the problem]

[0006] In order to solve the above problems, the semiconductor device according to the present disclosure is capable of face-down mounting. HalfA semiconductor device, comprising: a semiconductor substrate; a low-concentration impurity layer formed on a front surface side of the semiconductor substrate; and a first vertical MOS transistor formed in a first region of the semiconductor layer, the first vertical MOS transistor being a semiconductor layer formed by combining the semiconductor substrate and the low-concentration impurity layer. ,before The semiconductor substrate includes a second vertical MOS transistor formed in a second region adjacent to the first region in a plan view of the semiconductor layer, a first source electrode of the first vertical MOS transistor formed on a front surface side of the semiconductor layer, a second source electrode of the second vertical MOS transistor formed on the front surface side of the semiconductor layer, and a support formed on a rear surface side of the semiconductor substrate via a conductive adhesive, wherein the support has an area larger than that of the semiconductor layer in the plan view and contains the semiconductor layer. ,before The thickness of the support is greater than the thickness of the semiconductor layer, and includes the center of the semiconductor layer and the outer periphery of the semiconductor layer in the planar view. When the semiconductor chip of the semiconductor device is viewed in a cross-sectional view excluding the support and the conductive adhesive, the semiconductor chip has a curved shape that is convex in a direction away from the support.

[0007] According to the above configuration, in a dual-configuration vertical MOS transistor, it is possible to reduce the on-resistance, reduce the warpage of the semiconductor chip, and improve the strength of the semiconductor chip. Effect of the Invention

[0008] An object of the present disclosure is to provide a semiconductor device including a dual-configuration vertical MOS transistor, which reduces the on-resistance of the semiconductor chip, reduces warpage of the semiconductor chip, and improves the strength of the semiconductor chip. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment. [Figure 2A] FIG. 2A is a schematic plan view showing an example of the structure of the semiconductor device according to the first embodiment. [Figure 2B] FIG. 2B is a schematic cross-sectional view showing a main current flowing through the semiconductor device according to the first embodiment. [Figure 3A] FIG. 3A is a schematic plan view showing an example of the structure of the semiconductor device according to the first embodiment. [Figure 3B] FIG. 3B is a schematic perspective view showing an example of the structure of the semiconductor device according to the first embodiment. [Figure 4A] FIG. 4A is a flow diagram showing a part of the manufacturing process of the semiconductor device according to the first embodiment. [Figure 4B] FIG. 4B is a cross-sectional view illustrating a step of face-down mounting the semiconductor device according to embodiment 1. As shown in FIG. [Diagram 5] FIG. 5 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to Modification 1 of the first embodiment. [Figure 6] FIG. 6 is a graph showing the size range of a semiconductor chip that can enjoy the effects of the semiconductor device according to the first embodiment. [Figure 7A] FIG. 7A is a cross-sectional SEM image showing an example of the structure of the semiconductor device according to embodiment 1. FIG. [Figure 7B] FIG. 7B is a cross-sectional SEM image showing an example of the structure of the semiconductor device according to embodiment 1. [Figure 7C] FIG. 7C is a cross-sectional SEM image showing an example of the structure of the semiconductor device according to the first embodiment. [Figure 8A] FIG. 8A is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to Modification 2 of Embodiment 1. As shown in FIG. [Figure 8B] FIG. 8B is a schematic cross-sectional view showing an example of the structure of the semiconductor device of Modification 3 according to Embodiment 1. As shown in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a flow diagram showing a part of the manufacturing process of the semiconductor device according to the second embodiment. [Figure 11A] FIG. 11A is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the third embodiment. [Figure 11B]FIG. 11B is a schematic plan view showing an example of the structure of the processing support member in the semiconductor device according to the third embodiment. [Figure 11C] FIG. 11C is a schematic plan view showing an example of the structure of the semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, a specific example of a semiconductor device according to one aspect of the present disclosure will be described with reference to the drawings. Each embodiment shown here shows one specific example of the present disclosure. Therefore, the numerical values, shapes, components, arrangements and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present disclosure. In addition, each figure is a schematic diagram and is not necessarily an exact drawing. In each figure, the same reference numerals are given to substantially the same configurations, and duplicated explanations are omitted or simplified.

[0011] (Embodiment 1) [1. Structure of semiconductor device] FIG. 1 is a cross-sectional view showing an example of the structure of a semiconductor device. FIG. 2A is a plan view thereof, and the size and shape of the semiconductor device are examples except that the semiconductor device is rectangular (square or oblong). The size, shape and arrangement of the pads are also examples. FIG. 2B is a cross-sectional view showing a schematic view of a main current flowing through the semiconductor device. FIGS. 1 and 2B are cut surfaces taken along II in FIG. 2A.

[0012] In this disclosure, the semiconductor device 1 is described as including the metal layer 30, but the semiconductor device 1 is not necessarily limited to a configuration including the metal layer 30.

[0013] 1 and 2B, the semiconductor device 1 has a semiconductor substrate 32, a metal layer 30, and a low-concentration impurity layer 33 formed on the semiconductor substrate 32. In the present disclosure, the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as a semiconductor layer 40.

[0014] The semiconductor substrate 32 is disposed on the back surface side of the semiconductor layer 40, and is made of silicon of the first conductivity type containing impurities of the first conductivity type. The low-concentration impurity layer 33 is disposed on the front surface side of the semiconductor layer 40, and is formed in contact with the semiconductor substrate 32, and is of the first conductivity type, containing impurities of the first conductivity type at a concentration lower than the concentration of the impurities of the first conductivity type in the semiconductor substrate 32. The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0015] As shown in Figures 1 and 2A, the semiconductor device 1 has a first vertical MOS transistor 10 (hereinafter also referred to as "transistor 10") formed in a first region A1 in the semiconductor layer 40, and a second vertical MOS transistor 20 (hereinafter also referred to as "transistor 20") formed in a second region A2 in the semiconductor layer 40.

[0016] Here, as shown in Fig. 2A, the first region A1 and the second region A2 are adjacent to each other in a plan view of the semiconductor layer 40, and are one side and the other side that divide the semiconductor layer 40 in half in terms of area. In Fig. 2A, a virtual boundary line 90 between the first region A1 and the second region A2 is shown by a dashed line (for ease of understanding, the dashed line showing the boundary line 90 is shown extended to the outside of the semiconductor layer 40 and the semiconductor device 1). In Fig. 2A, the dashed line showing the first region A1 and the second region A2 does not strictly coincide with the semiconductor layer 40 and the boundary line 90 for ease of understanding, and is shown inside with a slight margin, but the outer periphery of the first region A1 and the outer periphery of the second region A2 substantially coincide with the outer periphery of the semiconductor layer 40 and the boundary line 90.

[0017] The metal layer 30 is formed in contact with the back surface of the semiconductor layer 40 (semiconductor substrate 32) and is made of, for example, silver (Ag) or copper (Cu). The metal layer 30 may contain trace amounts of elements other than metals that are mixed in as impurities during the manufacturing process of the metal material. The metal layer 30 may or may not be formed on the entire back surface of the semiconductor layer 40 (semiconductor substrate 32). The thickness of the metal layer 30 is preferably 10 μm or less, and more preferably 5 μm or less. The thickness of the metal layer 30 is, for example, 3 μm.

[0018] The support 42 is formed in indirect contact with the rear surface side of the metal layer 30 via a conductive adhesive 41. The support 42 is typically a flat metal plate having a thickness at least twice that of the semiconductor layer 40, for example, a uniform thickness of 200 μm in the plane. Hereinafter, the support 42 may be referred to as a thick-film metal plate 42. The thick-film metal plate 42 is made of a metal material mainly made of copper (Cu), for example. The conductive adhesive 41 is typically a silver paste.

[0019] As shown in FIG. 1, in this disclosure, a structure obtained by removing the support 42 and the conductive adhesive 41 from the semiconductor device 1 is referred to as a semiconductor chip 2. As shown in FIG. 1, the semiconductor chip 2 has a curved shape that is convex in a direction away from the support 42. The curved shape is, for example, a shape caused by warping. The amount of warping of the semiconductor chip 2 is the difference between the highest position and the lowest position in the Z direction on the upper or lower surface of the semiconductor layer 40 or the lower surface of the metal layer 30 when the semiconductor chip 2 is viewed in cross section. When the warping generated in the semiconductor chip 2 is a warping that is convex in a direction away from the support 42, the highest position is the center of the semiconductor layer 40 in a plan view, and the lowest position is the outer periphery of the semiconductor layer 40 in a plan view, particularly a corner on the outer periphery.

[0020] The center of the semiconductor layer 40 in a plan view refers to the intersection of diagonals of the semiconductor layer 40 in a plan view. In addition, the cross-sectional view of the semiconductor device 1 in this disclosure refers to the cross-section of the semiconductor device 1 viewed from a plane that includes both the center of the semiconductor layer 40 in the semiconductor chip 2 in a plan view and the outer periphery of the semiconductor layer 40 in the semiconductor chip 2 in a plan view. In this case, the outer periphery of the semiconductor layer 40 may be any position on the outer periphery of the semiconductor layer 40.

[0021] 1 and 2A, a first body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed in a first region A1 of the semiconductor layer 40 (low-concentration impurity layer 33). A first source region 14 containing impurities of the first conductivity type, a first gate conductor 15, and a first gate insulating film 16 are formed in the first body region 18.

[0022] The first gate insulating film 16 is formed inside a plurality of first gate trenches 17 formed to a depth from the upper surface of the semiconductor layer 40 through the first source region 14 and the first body region 18 to a part of the low-concentration impurity layer 33, and the first gate conductor 15 is formed inside the first gate trench 17 and on the first gate insulating film 16. The first gate conductor 15 is a buried gate electrode buried inside the semiconductor layer 40, and is electrically connected to the first gate pad 119.

[0023] The first source electrode 11 is composed of a portion 12 and a portion 13, and the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13. The portion 12 of the first source electrode 11 is a layer that is joined with solder during reflow in face-down mounting, and may be made of a metal material including, by way of non-limiting example, any one or more of nickel, titanium, tungsten, and palladium. The surface of the portion 12 may be plated with gold or the like.

[0024] Portion 13 of first source electrode 11 is a layer that connects portion 12 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0025] The thickness of the first source electrode 11 including the portions 12 and 13 is, for example, not less than 2 μm and not more than 13 μm.

[0026] A second body region 28 containing impurities of the second conductivity type is formed in the second region A2 of the low-concentration impurity layer 33. A second source region 24 containing impurities of the first conductivity type, a second gate conductor 25, and a second gate insulating film 26 are formed in the second body region 28.

[0027] The second gate insulating film 26 is formed inside a plurality of second gate trenches 27 formed to a depth from the upper surface of the semiconductor layer 40 through the second source region 24 and the second body region 28 to a part of the low-concentration impurity layer 33, and the second gate conductor 25 is formed on the second gate insulating film 26 inside the second gate trench 27. The second gate conductor 25 is a buried gate electrode buried inside the semiconductor layer 40, and is electrically connected to the second gate pad 129.

[0028] The second source electrode 21 is composed of a portion 22 and a portion 23, and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23. The portion 22 of the second source electrode 21 is a layer that is joined with solder during reflow in face-down mounting, and may be made of a metal material including, as a non-limiting example, any one or more of nickel, titanium, tungsten, and palladium. The surface of the portion 22 may be plated with gold or the like.

[0029] Portion 23 of second source electrode 21 is a layer that connects portion 22 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0030] The thickness of the second source electrode 21 including the portions 22 and 23 is, for example, not less than 2 μm and not more than 13 μm.

[0031] With the above-described configuration of transistor 10 and transistor 20, semiconductor substrate 32 functions as a common drain region in which the first drain region of transistor 10 and the second drain region of transistor 20 are common to each other. A part of the low-concentration impurity layer 33 on the side in contact with semiconductor substrate 32 may also function as the common drain region. Note that low-concentration impurity layer 33 is also a drift layer common to transistor 10 and transistor 20, and may be referred to as drift layer 33 in this specification.

[0032] Furthermore, the metal layer 30 functions as a common drain electrode that is a common electrode for the drain electrodes of the transistors 10 and 20. When the support 42 is a thick-film metal plate, not only the metal layer 30 but also the conductive adhesive 41 and the thick-film metal plate 42 function as a common drain electrode.

[0033] As shown in FIG. 1, the first body region 18 and the first source region 14 is covered with an interlayer insulating layer 34 having an opening, and through the opening of the interlayer insulating layer 34, a first body region 18 and The first source electrode 11 is connected to a portion 13 of the first source electrode 11 which is connected to the first source region 14. The interlayer insulating layer 34 and the first source electrode 11 The portion 13 is covered with a passivation layer 35 having an opening through which the first source electrode 11 is connected to part 12 which is connected to part 13.

[0034] Second Body Region 28 and the second source region 24 is covered with an interlayer insulating layer 34 having an opening, and through the opening of the interlayer insulating layer 34, a second body region 28; and The second source electrode 21 is connected to a portion 23 of the second source electrode 21 which is connected to the second source region 24. 21 The portion 23 is covered with a passivation layer 35 having an opening through which the second source electrode 21 It is connected to part 22 which is connected to part 23 of the

[0035] Therefore, the multiple first source pads 111 and the multiple second source pads 121 respectively refer to regions where the first source electrodes 11 and the second source electrodes 21 are partially exposed on the surface of the semiconductor device 1, that is, portions of so-called terminals. Similarly, the one or more first gate pads 119 and the one or more second gate pads 129 respectively refer to regions where the first gate electrode 19 (not shown in FIGS. 1, 2A, and 2B) and the second gate electrode 29 (not shown in FIGS. 1, 2A, and 2B) are partially exposed on the surface of the semiconductor device 1, that is, portions of so-called terminals.

[0036] In the present disclosure, in plan view, the first region A1 includes only components constituting the first vertical MOS transistor 10, and the second region A2 includes only components constituting the second vertical MOS transistor 20. The boundary line 90 may be considered as an imaginary line that traces the center position of the interval between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. Although it has a finite width, it may also be considered as the interval itself (even in the case of the interval, it can be recognized as a line with the naked eye or when viewed at low magnification).

[0037] In the semiconductor device 1, for example, the first conductivity type may be N type and the second conductivity type may be P type, with the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 being N-type semiconductors, and the first body region 18 and the second body region 28 being P-type semiconductors.

[0038] In addition, in the semiconductor device 1, for example, the first conductivity type may be P type and the second conductivity type may be N type, with the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 being P-type semiconductors, and the first body region 18 and the second body region 28 being N-type semiconductors.

[0039] [2. Operation of dual-configuration vertical MOS transistor] In the following description, the conductive operation of the semiconductor device 1 will be described assuming that the transistor 10 and the transistor 20 are so-called N-channel transistors, in which the first conductivity type is N-type and the second conductivity type is P-type.

[0040] 3A and 3B are respectively a plan view and a perspective view of an approximate unit configuration of a transistor 10 (or a transistor 20) repeatedly formed in the X direction and the Y direction of the semiconductor device 1. For ease of understanding, the semiconductor substrate 32, the metal layer 30, the conductive adhesive 41, the thick-film metal plate 42, the passivation layer 35, the first source electrode 11 (or the second source electrode 21), and the interlayer insulating layer 34 are not shown in FIG.

[0041] The structure of the transistor 10 is similar to that of the transistor 20. Therefore, in the following, the reference numeral of the transistor 10 will be used to describe the approximate unit configuration.

[0042] The Y direction is parallel to the upper surface of the semiconductor layer 40 and is the direction in which the first gate trench 17 extends. The X direction is parallel to the upper surface of the semiconductor layer 40 and perpendicular to the Y direction. The Z direction is perpendicular to both the X direction and the Y direction and is the direction in which the semiconductor device extends. 1 In this disclosure, the Y direction may be referred to as the first direction, the X direction as the second direction, and the Z direction as the third direction.

[0043] 3A and 3B, the transistor 10 includes a first connection portion 18a that electrically connects the first body region 18 and the first source electrode 11. The first connection portion 18a is a region of the first body region 18 in which the first source region 14 is not formed, and contains the same second conductivity type impurity as the first body region 18. The first source region 14 and the first connection portion 18a are alternately and periodically arranged in the Y direction. The same applies to the transistor 20.

[0044] In the semiconductor device 1, when a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21, and a voltage equal to or higher than a threshold value is applied to the second gate electrode 29 (second gate conductor 25) with the second source electrode 21 as a reference, a conductive channel is formed in the second body region 28 near the second gate insulating film 26. As a result, a main current flows through the path of the first source electrode 11-the first connection portion 18a-the first body region 18-the low-concentration impurity layer 33-the semiconductor substrate 32-the metal layer 30-the conductive adhesive 41-the thick film metal plate 42-the conductive adhesive 41-the metal layer 30-the semiconductor substrate 32-the low-concentration impurity layer 33-the conductive channel formed in the second body region 28-the second source region 24-the second source electrode 21, and the semiconductor device 1 becomes conductive. In this conductive path, a PN junction is present at the contact surface between the second body region 28 and the low-concentration impurity layer 33, and functions as a body diode.

[0045] Similarly, in the semiconductor device 1, when a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first source electrode 11, and a voltage equal to or higher than the threshold value is applied to the first gate electrode 19 (first gate conductor 15) with the first source electrode 11 as a reference, a conductive channel is formed in the first body region 18 near the first gate insulating film 16. As a result, a main current flows through the path of the second source electrode 21-the second connection portion 28a-the second body region 28-the low-concentration impurity layer 33-the semiconductor substrate 32-the metal layer 30-the conductive adhesive 41-the thick film metal plate 42-the conductive adhesive 41-the metal layer 30-the semiconductor substrate 32-the low-concentration impurity layer 33-the conductive channel formed in the first body region 18-the first source region 14-the first source electrode 11, and the semiconductor device 1 becomes conductive. In this conductive path, a PN junction is present at the contact surface between the first body region 18 and the low-concentration impurity layer 33, and functions as a body diode.

[0046] 2B shows a schematic diagram of the bidirectional flow of the main current with arrows. The flow of the main current in the horizontal direction (X direction) occurs in each of the layers of the metal layer 30, the conductive adhesive 41, the thick-film metal plate 42, and the semiconductor substrate 32. Since the resistivity of the metal layer 30 and the thick-film metal plate 42 is lower than that of the other layers, by making the metal layer 30 or the thick-film metal plate 42 thicker, the cross-sectional area of ​​the main current path is enlarged, and the on-resistance of the semiconductor device 1 can be reduced.

[0047] [3. Manufacturing method of semiconductor device] A method for manufacturing the semiconductor device 1 will now be described.

[0048] 4A is a simplified diagram showing part of the manufacturing process of the semiconductor device 1 in the present embodiment 1. The structure of each dual-configuration vertical MOS transistor, which will be separated later, is formed in a grid shape on a silicon wafer by step 501.

[0049] Next, in step 502, the back side of the silicon wafer (corresponding to the semiconductor substrate 32 in terms of each dual-configuration vertical MOS transistor to be individually separated later) is thinned. In the thinning process in step 502, it is preferable to control the thickness of the semiconductor layer 40 to be 15 μm or more and 100 μm or less, and more preferably, to be 15 μm or more and 75 μm or less.

[0050] Next, in step 503, a metal layer 30 is formed on the thinned backside of the silicon wafer. The metal layer 30 may be a multi-layer structure including, for example, multiple metal layers. The multiple metal layers may be formed individually by any method, such as deposition, sputtering, or plating.

[0051] Next, in step 504, the silicon wafer is diced to separate each dual-configuration vertical MOS transistor. Since the thick-film metal plate 42 is not yet bonded to each of the separated dual-configuration vertical MOS transistors, each of the separated dual-configuration vertical MOS transistors is in a state that can be called the semiconductor chip 2 described above.

[0052] Next, in step 505, a thick-film metal plate 42 to which a conductive adhesive 41 such as silver paste has been applied in advance is prepared, and the back side of the metal layer 30 of the semiconductor chip 2 is bonded to the thick-film metal plate 42. The amount of pressure applied is set to, for example, 5 μm to 10 μm, and the thickness of the conductive adhesive 41 after hardening and bonding is calculated to be a target value (for example, 20 μm to 60 μm), and the conductive adhesive 41 is applied to the surface of the thick film metal plate 42.

[0053] The conductive adhesive 41 is an adhesive for bonding the back surface side of the metal layer 30 to the thick film metal plate 42. When viewed after the conductive adhesive 41 has hardened and the thick film metal plate 42 has been bonded, it is desirable that the entire back surface side of the metal layer 30 is evenly covered with the conductive adhesive 41.

[0054] The thick-film metal plate 42 is selected to have an area larger than that of the semiconductor substrate 32 in a plan view, and during bonding, the plates are aligned so that a margin of approximately equal width is provided from the outer periphery of the metal layer 30 to the outer periphery of the closest thick-film metal plate 42 in a plan view. As an example, as shown in Fig. 2A, the thick-film metal plate 42 has a similar shape to the semiconductor layer 40. The semiconductor layer 40 and the thick-film metal plate 42 having similar shapes means that the semiconductor layer 40 and the thick-film metal plate 42 have the same shape in a plan view and differ only in area.

[0055] Furthermore, if the thick metal plate 42 is a so-called flat plate, which has a uniform thickness macroscopically and has no steps or uneven shapes, it is convenient for bonding the semiconductor layer 40. In the present embodiment 1, the thick metal plate 42 will be described as being a flat plate.

[0056] During bonding, it is common to align the semiconductor chip 2, which has a relatively small area, with the thick film metal plate 42, which has a relatively large area, as the receiving side. The conductive adhesive 41 may protrude from the back surface of the metal layer 30 in a plan view. The amount of protruding conductive adhesive 41 may or may not be uniform along the outer periphery of the semiconductor layer 40 in a plan view. FIG. 2A shows, as an example, a case where the protruding conductive adhesive 41 is uniform.

[0057] In step 505, in order to harden the conductive adhesive 41 such as silver paste, the thick film metal plate 42 is heated to about 170° C. while the semiconductor chip 2 is attached to it. The conductive adhesive 41 hardens at about 170° C., and the metal layer 30 and the thick film metal plate 42 are bonded to form the semiconductor device 1.

[0058] In addition Thick film metal plate 42 During the heat treatment at a high temperature of 170°C, the semiconductor chip 2 warps. As described above, the thickness of the semiconductor layer 40 is preferably 15 μm to 75 μm, and the thickness of the first source electrode 11 and the second source electrode 21 is preferably 2 μm to 13 μm. The thickness of the metal layer 30 is preferably 5 μm or less. By appropriately selecting the thickness of each layer, the direction of warping of the semiconductor chip 2 at 170°C can be controlled.

[0059] For example, if the thickness of the semiconductor layer 40 is 53 μm, the thickness of the first source electrode 11 and the second source electrode 21 is 5 μm, and the thickness of the metal layer 30 is 3 μm, then at 170° C., the semiconductor chip 2 will warp in a convex manner in the direction away from the thick metal plate 42 (the +Z direction in the cross-sectional view of FIG. 1).

[0060] FIG. 4B is a schematic diagram showing the semiconductor device 1 when it is mounted face-down.

[0061] [4. Discussion] Hereinafter, the effects achieved by the semiconductor device 1 according to the first embodiment will be described.

[0062] In a dual-configuration vertical MOS transistor, in order to reduce the on-resistance during conduction, it is required to make the semiconductor substrate 32 (semiconductor layer 40) thin and the metal layer 30 thick. A semiconductor chip 2 configured in this way is prone to warping that convexly forms in the -Z direction at high temperatures. The thinner the semiconductor layer 40 and the thicker the metal layer 30, the greater the warping that occurs at high temperatures.

[0063] In particular, when a dual-configuration vertical MOS transistor with low on-resistance is required, it is effective to increase the area of ​​the semiconductor chip 2 in a plan view in order to increase the total gate width of the channel. However, if the area is large, the warping of the semiconductor chip 2 increases significantly.

[0064] When mounting the semiconductor chip 2 face-down on the mounting board, a reflow process must be performed using a solder joint material at a high temperature of approximately 240°C. It is known that if the amount of warping of the semiconductor chip 2 at 240°C exceeds 40μm, mounting problems are likely to occur regardless of the direction of the warping, so it is necessary to keep the amount of warping of the semiconductor chip 2 below 40μm.

[0065] The configuration of the semiconductor device 1 according to the first embodiment is particularly effective for the semiconductor chip 2 having a thin semiconductor layer 40 and a large area, as described above. In the semiconductor device 1, the support 42 is a thick-film metal plate, and is connected to the metal layer 30 with a conductive adhesive 41. Therefore, even if the metal layer 30 is thin, if the thick-film metal plate 42 is sufficiently thick, the thick-film metal plate 42 becomes a horizontal conduction path, so that the on-resistance of the semiconductor device 1 can be reduced. In the semiconductor chip 2, the warpage that occurs can be reduced by making the metal layer 30 thin.

[0066] Furthermore, since the semiconductor chip 2 is bonded to the thick film metal plate 42 at approximately 170°C, which is lower than 240°C, the amount of warping of the semiconductor chip 2 can be suppressed to the same level as that occurring at approximately 170°C. If a material that does not remelt, such as silver paste, is selected as the conductive adhesive 41, the warping of the semiconductor chip 2 already bonded to the thick film metal plate 42 will not increase during the reflow process (240°C) when mounting the semiconductor device 1 face-down on the mounting board.

[0067] Furthermore, if the thick metal plate 42 is sufficiently thick, it can act as a support for the semiconductor chip 2, thereby compensating for the reduction in strength of the semiconductor chip 2 caused by thinning the semiconductor layer 40.

[0068] Therefore, the thick film metal plate 42 of the semiconductor device 1 according to the present embodiment 1 has the effect of physically compensating for the thinness of the semiconductor layer 40 and electrically compensating for the thinness of the metal layer 30. In the extreme, the metal layer 30 does not necessarily have to exist. In that case, as in Modification 1 of the present embodiment 1 shown in FIG. 5, the conductive adhesive 41 is directly bonded to the entire surface of the back surface side of the semiconductor substrate 32 (semiconductor layer 40).

[0069] The structure of the semiconductor device 1 having the thick film metal plate 42 according to the present embodiment 1 is more useful the larger the area of ​​the semiconductor layer 40 in the semiconductor chip 2 in a plan view and the thinner the semiconductor layer 40. Conversely, there is little point in joining the thick film metal plate 42 to a semiconductor chip 2 in which the area of ​​the semiconductor layer 40 in a plan view is small and the semiconductor layer 40 is thick. Therefore, the dimensions (area and thickness) of the semiconductor chip 2 for which the structure of the semiconductor device 1 having the thick film metal plate 42 according to the present embodiment 1 is useful were examined.

[0070] 6 shows a graph of the area and thickness (from the upper surface of the low-concentration impurity layer 33 to the lower surface of the semiconductor substrate 32) of the semiconductor layer 40 in a plan view required to make the on-resistance of the semiconductor chip 2 1 [mΩ] or less, and the amount of warping of the semiconductor chip 2 that occurs at that time. Here, 1 [mΩ] is a guideline, but a low on-resistance of, for example, 1 [mΩ] or less is required when a large current is passed, which has become increasingly popular in recent years in battery protection circuits.

[0071] The horizontal axis represents the area S [mm 2 ], and the left vertical axis is the thickness h [mm] of the semiconductor layer 40 in the semiconductor chip 2. The shape of the semiconductor layer 40 is a square. For example, a 2.5×2.5 mm square has an area of ​​6.2 mm 2 ], 3.4×3.4[mm] has an area of ​​11.5[mm 2]. The marks O are the thicknesses of the semiconductor layer 40 when the on-resistance of the semiconductor chip 2 is exactly 1.00 [mΩ]. The marks △ are the thicknesses of the semiconductor layer 40 when the on-resistance of the semiconductor chip 2 is exactly 0.75 [mΩ]. When calculating the thickness of the semiconductor layer 40, it is assumed that the metal layer 30 of the semiconductor chip 2 is made of silver (Ag) and has a thickness of 50 [μm].

[0072] In order to achieve a low on-resistance of 1.00 [mΩ] or less, it is necessary to configure the semiconductor chip 2 so that its structure falls within the region below and including the curve connecting the plots of circles. If the area of ​​the semiconductor layer 40 in the semiconductor chip 2 in a planar view is small, the thickness of the semiconductor layer 40 must be made thin, but if the area of ​​the semiconductor layer 40 in the semiconductor chip 2 in a planar view is large, the thickness of the semiconductor layer 40 can be made thick to a certain extent.

[0073] The line connecting the plots marked with circles has the relationship h = 0.016 × S - 0.042 (dashed line in Figure 6, 6.2 ≦ S ≦ 11.5, with good accuracy), and therefore, to achieve an on-resistance of 1.00 mΩ or less, the semiconductor layer 40 in the semiconductor chip 2 is required to have the relationship h ≦ 0.016 × S - 0.042.

[0074] The line connecting the plots marked with △ has the relationship h=0.014×S-0.074 (dashed line in FIG. 6, 6.2≦S≦11.5, with good accuracy), and therefore, to make the on-resistance 0.75 mΩ or less, the semiconductor layer 40 in the semiconductor chip 2 is required to have the relationship h≦0.014×S-0.074.

[0075] The vertical axis on the right of FIG. 6 indicates the amount of warping [μm] that occurs when the semiconductor chip 2 is at a high temperature of 240° C. The marks □ plot the amount of warping that occurs when Ag is formed as the metal layer 30 with a thickness of 50 μm in the configuration (area S and thickness h) of the semiconductor layer 40 in each of the semiconductor chips 2 indicated by the marks ◯. The reason why Ag with a thickness of 50 μm is set as the metal layer 30 provided in the semiconductor chip 2 is to enable comparison with the structure of the semiconductor device 1 according to the first embodiment that includes the thick film metal plate 42. Ag with good resistivity is selected as the material for the metal layer 30, and a thickness of 50 μm is selected because the contribution to the reduction of the on-resistance is almost saturated.

[0076] The reason why the shape of the semiconductor layer 40 is square in plan view is that a square shape reduces the amount of warping the most even with the same configuration (area S and thickness h). Therefore, the plot of square marks in Fig. 5 can be said to represent the minimum amount of warping in a state of a semiconductor chip 2 that can be electrically compared with the semiconductor device 1 according to the first embodiment.

[0077] According to FIG. 6, when the on-resistance is required to be 1.00 [mΩ] or less, the area is 6.2 [mm 2 ] or more, the warpage at 240[℃] exceeds 40[μm]. 2 ] At this level, it is difficult to mount the semiconductor chip 2 as is, and measures to reduce the amount of warping are required.

[0078] Even if the on-resistance is 1.00 [mΩ], the area of ​​the semiconductor chip 2 in a plan view is 6.2 [mm 2 In the case where the warpage is less than 6.2 mm, the amount of warpage is less than 40 μm, and therefore mounting can be performed with the semiconductor chip 2 as is. 2 ], if it is acceptable for the on-resistance to exceed 1.00 [mΩ], there is no need to make the thickness of the semiconductor layer 40 excessively thin, so the amount of warping falls below 40 [μm] and mounting can be performed as is in the semiconductor chip 2.

[0079] Therefore, it is square in plan view and has a size of 6.2 mm 2 When an on-resistance of 1.00 mΩ or less is required for a semiconductor chip 2 having an area of ​​2.5 × 2.5 mm or more, that is, when the relationship h≦0.016×S-0.042 holds for the semiconductor layer 40 in the semiconductor chip 2, it is preferable to join a thick film metal plate 42 as in the semiconductor device 1 of this embodiment 1.

[0080] Furthermore, for example, when the on-resistance is required to be 0.75 [mΩ] or less, it is necessary to further reduce the thickness of the semiconductor layer 40 in the semiconductor chip 2. That is, when the relationship h≦0.014×S−0.074 is satisfied for the semiconductor layer 40 in the semiconductor chip 2, it is more preferable to bond the thick film metal plate 42 as in the semiconductor device 1 according to the first embodiment.

[0081] Now, in the semiconductor device 1 of this embodiment 1, by appropriately selecting the thicknesses of the semiconductor layer 40 (semiconductor substrate 32), the first source electrode 11, the second source electrode 21, and the metal layer 30, the warping of the semiconductor chip 2 at 170°C can be controlled to be convex in the direction away from the support 42 (the +Z direction).

[0082] 1, when the back surface of the metal layer 30 is warped so as to be convex in the direction away from the thick film metal plate 42 (+Z direction), the conductive adhesive 41 becomes sandwiched between the metal layer 30 and the thick film metal plate 42. In particular, the end of the metal layer 30 moves relatively closer to the thick film metal plate 42 (-Z direction) due to the curvature of the semiconductor chip 2, and pushes the conductive adhesive 41 toward the thick film metal plate 42. When the semiconductor chip 2 has such a curved shape, it is possible to enjoy the effect of increasing the degree of adhesion of the bond between the semiconductor chip 2 and the thick film metal plate 42.

[0083] Therefore, in a cross-sectional view of the semiconductor device 1, when the semiconductor chip 2 of the semiconductor device 1 is viewed excluding the thick film metal plate 42 and the conductive adhesive 41, it is desirable that the semiconductor chip 2 has a curved shape that is convex in a direction away from the thick film metal plate 42. In other words, it is desirable that the thickness of the conductive adhesive 41 directly below the semiconductor layer 40 at the outer periphery of the semiconductor layer 40 in a plan view is thinner than the thickness of the conductive adhesive 41 directly below the semiconductor layer 40 at the center of the semiconductor layer 40 in a plan view.

[0084] 7A, 7B, and 7C show cross-sectional SEM images of the semiconductor device 1 according to the first embodiment mounted face-down on a mounting board. Fig. 7B is an enlarged cross-sectional SEM image of a portion surrounded by a dashed line in Fig. 7A, and Fig. 7C is an enlarged cross-sectional SEM image of a portion surrounded by a dashed line in Fig. 7B. In the semiconductor device 1 shown in Figs. 7A to 7C, the semiconductor layer 40 has a thickness of 53 [μm], the first source electrode 11 and the second source electrode 21 have a thickness of 4 [μm], the metal layer 30 has a thickness of 3 [μm], and the thick metal plate 42 has a thickness of 200 [μm].

[0085] Horizontal line A in Figures 7B and 7C Plane view The interface position between the semiconductor layer 40 and the metal layer 30 at the center of the semiconductor layer 40 is Plane view 7C is extended to the outer periphery of the semiconductor layer 40. Also, horizontal line B in Fig. 7C indicates the interface position between the semiconductor layer 40 and the metal layer 30 on the outer periphery of the semiconductor layer 40. In Fig. 7C, horizontal line B is closer to the thick metal plate 42 (in the -Z direction) than horizontal line A, and Z The directional spacing is 2 μm.

[0086] Therefore, the semiconductor chip 2 is warped in a convex shape in the direction away from the thick metal plate 42 (the +Z direction), and the amount of warping is 2 μm. The conductive adhesive 41 that bonds the semiconductor chip 2 and the thick metal plate 42 is sandwiched between them and hardens, covering the entire back surface side of the semiconductor chip 2. No voids or areas that are likely to peel off were found in the conductive adhesive 41, and it can be confirmed that the degree of adhesion is good.

[0087] As a result of the inventors' investigation, it was found that the effect of improving the adhesion can be stably obtained if the warpage of the semiconductor chip 2 at 170[℃] is 2[μm] or more. If the warpage is less than 2[μm] or if the warpage is convex in the opposite direction, the effect of sandwiching the conductive adhesive 41 between the semiconductor chip 2 and the thick film metal plate 42 cannot be stably obtained, and traces of the conductive adhesive 41 peeling off at the end of the semiconductor device 1 may be seen.

[0088] The warping of the semiconductor chip 2 at high temperatures is due to the first source electrode 11 and the second source electrode 21 being formed on the front side of the semiconductor layer 40. In addition, when the metal layer 30 is provided on the rear side of the semiconductor layer 40, the formation of the metal layer 30 also has an effect. The warping direction (also called the curvature direction) and the warping amount (also called the curvature amount) of the semiconductor chip 2 are determined by the relationship between the physical properties such as the linear expansion coefficient and Young's modulus of the semiconductor layer 40, the first source electrode 11, the second source electrode 21, and the metal layer 30, and their respective thicknesses.

[0089] When the semiconductor chip 2 does not include the metal layer 30 (in the first modification of the first embodiment shown in FIG. 5), the warping of the semiconductor chip 2 is determined only by the relationship between the semiconductor layer 40 and the first and second source electrodes 11 and 21. Since the linear expansion coefficient of the metal type is usually larger, the direction of the warping that occurs at high temperatures becomes convex in the +Z direction. The amount of warping is determined by the relative relationship between the semiconductor layer 40 and the thicknesses of the first and second source electrodes 11 and 21, and the thinner the semiconductor layer 40 is and the thicker the first and second source electrodes 11 and 21 are, the greater the warping.

[0090] When the semiconductor chip 2 includes a metal layer 30, the thickness is mainly determined by the relationship between the metal layer 30 and the first and second source electrodes 11 and 21. Furthermore, the linear expansion coefficients of the metal species constituting the first and second source electrodes 11 and 21 and the metal species constituting the metal layer 30 are often close to each other, so the direction and amount of warping are often determined by the thickness of each. When it is required to control the warping to be convex in the +Z direction, it is desirable to make the thickness of the metal layer 30 thinner than the thickness of the first and second source electrodes 11 and 21. This is because a thicker film thickness increases the stress due to expansion at high temperatures, resulting in a curved shape that is convex in that direction.

[0091] As described above, in order to increase the adhesion of the bond between the metal layer 30 and the thick metal plate 42, it is necessary for the semiconductor chip 2 to warp in the direction away from the thick metal plate 42 (+Z direction). However, if the amount of warping is too large, voids are likely to occur in the conductive adhesive 41 near the center of the semiconductor layer 40 in a plan view. As a result of the inventors' investigation, it was found that the occurrence of voids can be stably prevented by adjusting the amount of warping of the semiconductor chip 2 at 170° C. to 20 μm or less. Therefore, it is preferable that the amount of warping of the semiconductor chip 2 at 170° C. be 2 μm or more and 20 μm or less.

[0092] In order for the semiconductor chip 2 to have a curved shape that is convex in the direction away from the thick metal plate 42 (+Z direction), the thickness of the semiconductor layer 40 in the semiconductor chip 2 is preferably 100 [μm] or less, and more preferably 75 [μm] or less. This is because it is difficult to form the first source electrode 11 and the second source electrode 21 with extremely large thicknesses, and it is easier to curve the semiconductor chip 2 when the semiconductor layer 40 is thin. In addition, the reduction in strength of the semiconductor chip 2 caused by the thinning of the semiconductor layer 40 can be compensated for by joining the thick metal plate 42, so that in the present disclosure, the side effects of thinning the semiconductor layer 40 can be reduced.

[0093] However, if the thickness of the semiconductor layer 40 becomes extremely thin, for example, less than 15 μm, cracks are likely to occur in the semiconductor layer 40 (semiconductor substrate 32) during dicing. Therefore, the thickness of the semiconductor layer 40 is preferably 15 μm or more and 100 μm or less, and more preferably 15 μm or more and 75 μm or less.

[0094] The thickness of the first source electrode 11 and the second source electrode 21 are preferably, for example, 2 μm or more and 13 μm or less. If the semiconductor chip 2 does not include the metal layer 30, the warpage amount at 170° C. can be 2 μm or more even if the thickness of the first source electrode 11 and the second source electrode 21 is 2 μm to 5 μm, if the semiconductor layer 40 is thin. However, when the semiconductor layer 40 is thick, it is preferable to change the thickness of the first source electrode 11 and the second source electrode 21 accordingly to a thicker thickness, such as 10 μm to 13 μm.

[0095] With the above-mentioned film thickness configuration, the direction in which the semiconductor chip 2 warps at high temperatures can be controlled to a direction in which the semiconductor chip 2 becomes convex away from the thick film metal plate 42 (+Z direction), and the amount of warping can be controlled to be between 2 μm and 20 μm.

[0096] 1, in the semiconductor device 1 according to the first embodiment, the conductive adhesive 41 often forms a substantially triangular fillet that partially rises onto the side wall of the semiconductor chip 2. In the semiconductor device 1 according to the first embodiment, the semiconductor chip 2 has a curved shape that is convex in the direction away from the thick film metal plate 42, and as a result, the fillet of the conductive adhesive 41 may reach a position close to the upper surface of the semiconductor layer 40, as shown in FIGS. 7A to 7C.

[0097] As shown in FIG. 7C, when the fillet angle is defined based on the upper surface of the thick metal plate 42, it was found that the semiconductor device 1 according to the first embodiment has an angle of at least 20[deg]. Therefore, the conductive adhesive 41 may protrude from the outer periphery of the semiconductor layer 40 by a maximum of (h+hp) / tan(20[deg])[mm] in plan view. Here, the total thickness of the metal layer 30 directly below and the conductive adhesive 41 at the corner of the semiconductor layer 40 in plan view is defined as hp[mm]. The reason why the corner of the semiconductor layer 40 is specified is because it is the place where the conductive adhesive 41 is most pressed in due to the warpage of the semiconductor chip 2. In addition, tan is a tangent function.

[0098] If the area of ​​the thick metal plate 42 in plan view is not sufficiently larger than the area of ​​the semiconductor layer 40, there is a concern that the protruding conductive adhesive 41 will not be contained within the thick metal plate 42. Therefore, the area of ​​the thick metal plate 42 in plan view must be prepared taking into consideration the protruding conductive adhesive 41 by the length of the bottom side of the fillet of the conductive adhesive 41.

[0099] If the shortest distance from the outer periphery of the semiconductor layer 40 to the outer periphery of the thick metal plate 42 in a plan view is L [mm], the thickness of the semiconductor layer 40 is h [mm], and the total thickness of the metal layer 30 directly below the semiconductor layer 40 and the conductive adhesive 41 at the corner of the semiconductor layer 40 in a plan view is hp [mm], then since the fillet of the conductive adhesive 41 has a minimum angle of 20 [deg], it is desirable that the relationship L≧(h+hp) / tan(20 [deg]) hold. If this relationship holds, the conductive adhesive 41 will not protrude beyond the outer periphery of the thick metal plate 42 all around the semiconductor layer 40 in a plan view.

[0100] A modification of the semiconductor device 1 according to the first embodiment will be described below.

[0101] 8A shows a schematic cross-sectional view of Modification 2 of the semiconductor device 1 according to the embodiment 1. In the semiconductor device 1 according to Modification 2, the support 42 has a curved shape that is convex in the direction toward the semiconductor chip 2. The curved shape of the support 42 is, for example, During the heat treatment for bonding the metal layer 30 and the support 42 via the conductive adhesive 41, It is a shape caused by warping of the support 42. The amount of warping of the support 42 is the difference between the highest position and the lowest position in the Z direction on the upper or lower surface of the support 42 when the support 42 is viewed in cross section. When the warping generated in the support 42 is a warp that is convex in the direction toward the semiconductor chip 2, the highest position is the center of the support 42 in a plan view, and the lowest position is the outer periphery of the support 42 in a plan view, particularly a corner on the outer periphery.

[0102] The direction and amount of warping of the support 42 can be controlled by adjusting the amount of warping of the semiconductor chip 2 generated at 170°C, the thickness and / or material of the support 42, and the thickness and / or material of the conductive adhesive 41, or the bonding conditions. The easiest way to adjust is to make the thickness of the support 42 thinner. If the thickness of the support 42 is made thinner, the amount of warping of the support 42 at the time when the semiconductor device 1 is completed can be increased, but the rigidity of the semiconductor device 1 will decrease. For this reason, as a guideline, it is preferable that the thickness of the support 42 is designed so that the amount of warping of the support 42 is smaller than the amount of warping of the semiconductor chip 2.

[0103] As shown in FIG. 8A, in semiconductor device 1, when the amount of curvature of support 42 is smaller than the amount of curvature of semiconductor chip 2 and support 42 has a curved shape that is convex in the direction toward semiconductor chip 2, the pressure applied to conductive adhesive 41 is reduced compared to when support 42 is not curved, and the length by which conductive adhesive 41 protrudes from semiconductor layer 40 in a planar view can be reduced.

[0104] 8B shows a schematic cross-sectional view of Modification 3 of the semiconductor device 1 according to the embodiment 1. In the semiconductor device 1 according to Modification 3, the support 42 has a curved shape that is convex in a direction away from the semiconductor chip 2. As shown in FIG. 8B, in the semiconductor device 1, when the amount of curvature of the support 42 is smaller than the amount of curvature of the semiconductor chip 2 and the support 42 has a curved shape that is convex in a direction away from the semiconductor chip 2, it is possible to prevent voids from being generated between the semiconductor chip 2 and the conductive adhesive 41 near the center of the semiconductor layer 40 in a plan view, compared to when the support 42 is not curved.

[0105] (Embodiment 2) A semiconductor device 100 according to a second embodiment, which is obtained by partially modifying the configuration of the semiconductor device 1 according to the first embodiment, will be described below.

[0106] The semiconductor device 100 of embodiment 2 is an example of a configuration in which the support 42, which was the thick film metal plate of embodiment 1, is changed to an insulating support 420, and further a support metal layer 300 is formed on the front side of the insulating support 420, i.e., the side that is bonded to the semiconductor chip 2.

[0107] Here, regarding the semiconductor device 100 of embodiment 2, the components similar to those of the semiconductor device 1 of embodiment 1 have already been explained, so they are given the same reference numerals and their detailed explanations are omitted, and the explanation focuses on the differences from the semiconductor device 1.

[0108] [1. Configuration of Semiconductor Device] 9 shows a schematic cross-sectional view of a semiconductor device 100 according to embodiment 2. The semiconductor device 1 according to embodiment 1 is different in that the support 42 is changed to an insulating support 420, and a support metal layer 300 is formed on the front side of the insulating support 420. The support metal layer 300 may cover the entire front side of the insulating support 420 so that the side surface is flush with that of the insulating support 420. Alternatively, as shown in FIG. 9, the support metal layer 300 may cover only a part of the front side of the insulating support 420.

[0109] [2. Manufacturing method of semiconductor device] 10 shows a simplified diagram of a part of the manufacturing process of the semiconductor device 100 according to embodiment 2. Steps 501 to 504 are the same as those of the manufacturing process of the semiconductor device 1 according to embodiment 1. Step 506 corresponds to step 505 in embodiment 1.

[0110] In the second embodiment, the semiconductor chip 2 is bonded to the insulating support 420 in step 506. In step 506, the support metal layer 300 is formed in advance on the front side of the insulating support 420, and the conductive adhesive 41 is applied to the upper surface of the support metal layer 300. The conductive adhesive 41 is, for example, a silver paste, and is hardened at a high temperature of 170° C. to bond the semiconductor chip 2 to the insulating support 420 or the support metal layer 300.

[0111] [3. Consideration] In the semiconductor device 100 according to this embodiment, since the insulating support 420 is used, the rigidity can be improved compared to the thick film metal plate according to the first embodiment. An example of a material with good rigidity is a silicon substrate. When the silicon substrate is used as the insulating support 420, the same effect as that of the semiconductor device 1 according to the first embodiment, which uses a thick film metal plate, can be achieved with a thinner dimension.

[0112] On the other hand, in the semiconductor device 100 according to the second embodiment, the support metal layer 300 is provided on the surface of the insulating support 420, and this serves as a conductive path to realize a sufficiently low on-resistance. The semiconductor device 100 according to the second embodiment is particularly useful when the thickness of the support metal layer 300 is greater than the thickness of the first source electrode 11 and the thickness of the second source electrode 21 in the semiconductor chip 2.

[0113] In the semiconductor device 1 according to the first embodiment, if the thickness of the metal layer 30 in the semiconductor chip 2 is made larger than the thickness of the first source electrode 11 and the thickness of the second source electrode 21, the direction of the warp generated in the semiconductor chip 2 at 170° C. cannot be made convex in the direction away from the support 42. In contrast, in the semiconductor device 100 according to the second embodiment, if the thickness of the metal layer 30 in the semiconductor chip 2 is made smaller than the thickness of the first source electrode 11 and the thickness of the second source electrode 21, the direction of the warp generated in the semiconductor chip 2 at 170° C. can be made convex in the direction away from the support 42.

[0114] The support metal layer 300 desirably covers the entire area to which the back side of the semiconductor chip 2 is bonded. Therefore, the front side of the insulating support 420 is provided with the support metal layer 300 formed in an area larger than the semiconductor layer 40 in a plan view, and the thickness of the support metal layer 300 is desirably larger than the thicknesses of the first source electrode 11 and the second source electrode 21.

[0115] (Embodiment 3) The following is an embodiment of the present invention. 1 A semiconductor device 200 according to a third embodiment, which is a part of the configuration of the semiconductor device 1 according to the first embodiment, will be described.

[0116] The semiconductor device 200 of embodiment 3 is an example of a configuration in which the support 42 of embodiment 1, which is a thick film metal plate and a flat plate with a uniform thickness within its surface, is changed to a processed support 430 which is a thick film metal plate and has been subjected to surface processing.

[0117] Here, regarding the semiconductor device 200 of embodiment 3, the components similar to those of the semiconductor device 1 of embodiment 1 have already been explained, so they are given the same reference numerals and their detailed explanations are omitted, and the explanation focuses on the differences from the semiconductor device 1.

[0118] [1. Configuration of Semiconductor Device] Fig. 11A shows a schematic cross-sectional view of the semiconductor device 200 according to the third embodiment. Fig. 11B shows a schematic plan view of a processed support 430 according to the third embodiment. Fig. 11C shows a schematic plan view of the semiconductor device 200 after the semiconductor chip 2 is mounted on the processed support 430. This embodiment differs from the semiconductor device 1 according to the first embodiment in that the support 42 is changed to the processed support 430.

[0119] When only the processing support 430 is viewed, the surface of the processing support 430 (the surface to be bonded to the semiconductor chip 2) is divided into a first area that includes the center of the processing support 430 in a plan view and does not include the outer periphery of the processing support 430, and a second area that surrounds the first area and is the remaining area of ​​the surface of the processing support 430, as shown in Fig. 11B. In Fig. 11A and Fig. 11B, the imaginary boundary between the first area and the second area is indicated by a dashed line.

[0120] In the first region, the thickness of the processed support 430 is constant, but in the second region, a groove is formed on a part of the surface of the processed support 430, and the processed support 430 has a portion where the thickness is thinner than in the first region. In the third embodiment, an example is shown in which the thickness of the processed support 430 is equal to the thickness in the first region near the outer periphery of the processed support 430 in the second region. However, the thickness of the processed support 430 in the second region may be constant, or may be gradually thinner than the thickness of the processed support 430 in the first region.

[0121] In the semiconductor device 200, the semiconductor chip 2 is bonded to the front surface side of the processing support 430 via the conductive adhesive 41, and as shown in Figures 11A and 11C, the semiconductor chip 2 is disposed so that the outer periphery of the semiconductor layer 40 in the semiconductor chip 2 is contained within the width of the groove formed in the second area of ​​the processing support 430 in a plan view. Note that Figure 11C omits the illustration of the conductive adhesive 41 which would appear to protrude from the semiconductor chip 2 in a plan view.

[0122] Therefore, in the semiconductor device 200 of this embodiment 3, the area of ​​the first range on the surface of the processing support 430 in a planar view is smaller than the area of ​​the semiconductor layer 40 in the semiconductor chip 2, and the semiconductor layer 40 is joined so as to cover the entire first range in a planar view.

[0123] [2. Consideration] With the above-mentioned configuration, it is possible to suppress the length by which the conductive adhesive 41 protrudes horizontally from the semiconductor layer 40 in a plan view. Since the second range of the processing support 430 is processed to have a groove shape, the extruded conductive adhesive 41 flows into the groove. Since the extruded conductive adhesive 41 can be accumulated to a certain extent in the groove, it is possible to suppress the horizontal protrusion length and the height by which the conductive adhesive 41 protrudes onto the side surface of the semiconductor chip 2 by appropriately changing the width and depth of the groove.

[0124] Although the semiconductor device according to one aspect of the present disclosure has been described above based on the first to third embodiments and the first to third modifications, the present disclosure is not limited to these embodiments and modifications. As long as it does not deviate from the spirit of the present disclosure, various modifications conceived by a person skilled in the art to these embodiments and forms constructed by combining components in different embodiments and modifications may also be included within the scope of one or more aspects of the present disclosure. [Industrial Applicability]

[0125] A semiconductor device including a vertical MOS transistor according to the present invention can be widely used as a device for controlling the conduction state of a current path. [Explanation of symbols]

[0126] 1, 100, 200 Semiconductor device 2. Semiconductor chips 10 Transistor (first vertical MOS transistor) 11 First source electrode 12, 13 parts 14 First Source Region 15 First gate conductor 16 First gate insulating film 17 First gate trench 18 First Body Region 18a First connection area 19 First gate electrode 20 Transistor (second vertical MOS transistor) 21 Second source electrode 22, 23 parts 24 Second Source Region 25 Second gate conductor 26 Second gate insulating film 27 Second gate trench 28 Second Body Region 28a Second connection area 29 Second gate electrode 30 metal layer 32 Semiconductor Substrate 33 Low concentration impurity layer (drift layer) 34 Interlayer insulation layer 35 Passivation Layer 40 Semiconductor layer 41 Conductive adhesive 42 Support (thick film metal plate) 300 Support metal layer 420 Insulating Support 430 Processing support 90 Border 111 First Source Pad 119 First Gate Pad 121 Second Source Pad 129 Second Gate Pad A1 First Area A2 Second Area

Claims

1. A semiconductor device capable of face-down mounting, A semiconductor substrate; a low concentration impurity layer formed on a front surface side of the semiconductor substrate; When the semiconductor substrate and the low-concentration impurity layer are combined to form a semiconductor layer, a first vertical MOS transistor formed in a first region of the semiconductor layer; a second vertical MOS transistor formed in a second region adjacent to the first region in a plan view of the semiconductor layer; a first source electrode of the first vertical MOS transistor formed on a front surface side of the semiconductor layer; a second source electrode of the second vertical MOS transistor formed on a front surface side of the semiconductor layer; A support body formed on a back surface side of the semiconductor substrate via a conductive adhesive, In the plan view, the support has an area larger than that of the semiconductor layer and contains the semiconductor layer; the thickness of the support is greater than the thickness of the semiconductor layer; When a semiconductor chip of the semiconductor device is viewed in a cross-sectional view including a center of the semiconductor layer and an outer periphery of the semiconductor layer in the plan view, the semiconductor chip has a curved shape that is convex in a direction away from the support. Semiconductor device.

2. In the plan view, the semiconductor layer has a square shape, At the outer periphery of the semiconductor layer in the plan view, the thickness of the conductive adhesive directly below the semiconductor layer is smaller than the thickness of the conductive adhesive directly below the semiconductor layer at the center of the semiconductor layer in the plan view. The semiconductor device according to claim 1 .

3. In the plan view, the semiconductor layer is 6.2 mm ２ ] or more, The area of ​​the semiconductor layer is S [mm ２ ], and the thickness of the semiconductor layer is h [mm]. The relationship h≦0.016×S−0.042 holds true. The semiconductor device according to claim 2 .

4. In the plan view, the semiconductor layer is 11.5 mm ２ ] or less, The relationship h≦0.014×S−0.074 holds true. The semiconductor device according to claim 3 .

5. a metal layer is provided on a back surface side of the semiconductor substrate, the metal layer being in contact with the entire back surface of the semiconductor substrate; In the plan view, the shortest length of the closest distance from the outer periphery of the semiconductor layer to the outer periphery of the support is L [mm], At the corners of the semiconductor layer in the plan view, the sum of the thicknesses of the metal layer and the conductive adhesive directly below the semiconductor layer is expressed as hp [mm]. The relationship L≧(h+hp) / tan(20[deg]) is established. The semiconductor device according to claim 3 .

6. The support is made of a metal. The semiconductor device according to claim 3 .

7. a metal layer is provided on a back surface side of the semiconductor substrate, the metal layer being in contact with the entire back surface of the semiconductor substrate; The thickness of the first source electrode and the thickness of the second source electrode are greater than the thickness of the metal layer. The semiconductor device according to claim 3 .

8. The conductive adhesive directly bonds the entire surface of the back surface of the semiconductor substrate. The semiconductor device according to claim 3 .

9. a support metal layer is provided on a front surface side of the support and connected to an area larger than an area of ​​the semiconductor substrate in the plan view; a thickness of the support metal layer is greater than a thickness of the first source electrode and a thickness of the second source electrode; The support is made of an insulating material. The semiconductor device according to claim 1 .

10. In the plan view, the front surface side of the support has a first area that includes a center of the support but does not include an outer periphery of the support, and a second area that surrounds the first area, In the cross-sectional view, the first area has a constant height, and the second area includes a portion that is lower than the height of the first area. In the plan view, an area of ​​the first region is smaller than an area of ​​the semiconductor substrate, The semiconductor substrate is disposed so as to entirely cover the first area of ​​the support in the plan view. The semiconductor device according to claim 3 .

11. The second area also includes a portion where the height of the second area is the same as the height of the first area. The semiconductor device according to claim 10.

12. In the cross-sectional view, the support has a curved shape that is convex in a direction toward the semiconductor chip, The amount of curvature of the support is smaller than the amount of curvature of the semiconductor chip. The semiconductor device according to claim 3 .

13. In the cross-sectional view, the support has a curved shape that is convex in a direction away from the semiconductor chip, The amount of curvature of the support is smaller than the amount of curvature of the semiconductor chip. The semiconductor device according to claim 3 .

Images