Semiconductor device and battery-less multi-rotation encoder

Abstract

A semiconductor device (SD1) is operated by current pulses generated by a power generation element (1). The semiconductor device (SD1) is provided. The semiconductor device (SD1) comprises: a processing circuit (6) that executes a series of processing by using the current pulses; and determination circuits (130, 230) that determine whether the power generation amount of the power generation element (1) is sufficient. The determination circuits (130, 230) determine whether a first determination condition has been satisfied during the generation of the current pulses by the power generation element (1) before the start of the series of processing, and determine whether a second determination condition has been satisfied during the execution of the series of processing. The processing circuit (6) starts the series of processing if the first determination condition has been satisfied, and suspends the series of processing if the second determination condition has not been satisfied.

Description

Semiconductor device and batteryless multi-rotation encoder

[0001] The present disclosure relates to a semiconductor device, and further to a batteryless multi-turn encoder.

[0002] Many semiconductor devices have been developed that operate using power generated by energy harvesting elements that convert energy obtained from the surrounding environment into electricity. Some energy harvesting elements convert induced currents generated in coils due to changes in magnetic fields into electricity. A battery-less multi-rotation encoder is an example of a device that uses a power generating element that utilizes such changes in magnetic fields, and it can determine the rotation direction and speed of a motor without an external power source.

[0003] Japanese Patent No. 5769879 (Patent Document 1) discloses a battery-less multi-rotation encoder device that uses a power generating element that exhibits the large Barkhausen effect. The large Barkhausen effect is a phenomenon in which magnetization changes abruptly in a certain magnetic field when the external magnetic field changes.

[0004] Specifically, the batteryless multi-rotation encoder described in this document includes a rotation detection mechanism and a signal processing circuit. The rotation detection mechanism includes a magnet with N magnetic poles circumferentially arranged around the rotating shaft, which rotates with the rotating shaft. L (L is 2 or more) detection coils are made of magnetic wire that exhibits the Barkhausen effect on the magnetic field of the magnet and are arranged around the rotating circumference of the magnet with shifted phase angles. Each detection coil generates voltage pulses of opposite signs and sends them to the signal processing circuit. The signal processing circuit includes a controller that stores the detection coil status in memory and an adder that updates the rotation speed in response to changes in the status of each detection coil. The signal processing circuit performs a series of operations using only power generated by a full-wave rectifier circuit and a constant voltage circuit using voltage pulses from the detection coils, and terminates its operation before the next voltage pulse is generated.

[0005] Patent No. 5769879

[0006] Conventional semiconductor devices using energy-harvesting elements, such as the battery-less multi-rotation encoder described in Japanese Patent No. 5769879 (Patent Document 1), complete a series of operations for each current pulse generated by the power generating element. Therefore, the signal processing circuit begins processing only after the capacitance element that stores the charge generated by the power generating element has accumulated all the charge necessary for the series of operations. If power runs out during the series of operations, the processing may not be performed correctly, resulting in data errors.

[0007] However, waiting until all the charge required for the series of processes has accumulated in the capacitive element means that a high voltage is applied to the coil inside the power generating element. When a voltage is applied to a coil, it tends to pass a current in a direction that cancels out the voltage. This reverse current impedes the generated current, creating a problem: the higher the generated voltage, the greater the amount of charge canceled out by the reverse current. On the other hand, if the capacitance of the capacitive element is increased to suppress the generated voltage, the charge required to reach the voltage required to drive the signal processing circuit increases, creating another problem: more charge is left unused.

[0008] The present disclosure has been made in consideration of the above problems, and one of its objectives is to provide a semiconductor device that efficiently utilizes a current pulse generated by a power generating element.

[0009] In one embodiment, a semiconductor device is provided that operates using a current pulse generated by a power generating element. The semiconductor device includes a processing circuit that executes a series of processes using the current pulse, and a determination circuit that determines whether the power generation amount of the power generating element is sufficient. The determination circuit determines whether a first determination condition is satisfied before the series of processes is started and while the power generating element is generating a current pulse, and determines whether a second determination condition is satisfied while the series of processes is being executed. The processing circuit starts the series of processes if the first determination condition is satisfied, and suspends the series of processes if the second determination condition is not satisfied.

[0010] According to the above embodiment, a series of processes is started when it is determined that the amount of power generated by the power generating element is sufficient while a current pulse is being generated by the power generating element, and the processes are interrupted when it is determined that the amount of power generated is insufficient while the series of processes are being executed, thereby enabling efficient use of the current pulse generated by the power generating element.

[0011] 1. It is a circuit block diagram of a batteryless multi-rotation encoder according to embodiment 1. 2. It is a timing chart showing an example of normal processing of the batteryless multi-rotation encoder of FIG. 1. 3. It is a timing chart showing an example of interrupt processing of the batteryless multi-rotation encoder of FIG. 1. 4. It is a diagram conceptually showing the amount of charge stored in a capacitive element at the start and end of each of read, update, and write processing. 5. It is a diagram conceptually showing the change in voltage of a capacitive element over time. 6. It is a circuit diagram showing an example of the configuration of a reference voltage generation circuit and a voltage determination circuit of FIG. 1. 7. It is a circuit diagram showing an example of the configuration of a charge amount determination circuit of FIG. 1. 8. It is a circuit diagram showing an example of the configuration of a selection circuit of FIG. 1. 9. It is a circuit diagram showing an example of the configuration of a constant voltage circuit of FIG. 1. 10. It is a circuit diagram showing an example of the configuration of a POR circuit of FIG. 1. 11. It is a circuit block diagram of a batteryless multi-rotation encoder according to embodiment 2. 12. It is a timing chart showing an example of normal processing of the batteryless multi-rotation encoder of FIG. 1. 13. It is a timing chart showing an example of interrupt processing of the batteryless multi-rotation encoder of FIG. 11. It is a diagram for explaining an example of a mechanism for detecting a write error. 14. It is a circuit diagram showing an example of the configuration of a peak determination circuit of FIG. 11. It is a circuit diagram showing another example of the configuration of a peak determination circuit of FIG. 11. 21. It is a circuit block diagram of a batteryless multi-rotation encoder according to embodiment 3. It is a timing chart showing an example of normal processing of the batteryless multi-rotation encoder of FIG. 17. It is a circuit block diagram of a batteryless multi-rotation encoder according to embodiment 4. It is a timing chart showing an example of normal processing of the batteryless multi-rotation encoder of FIG. 19. It is a circuit diagram showing an example of the configuration of the variable voltage generator of FIG. 19. It is a diagram for explaining an example of a method of supplying voltage to the power supply terminal of the voltage buffer of FIG. 21. It is a circuit block diagram of a batteryless multi-rotation encoder according to embodiment 5. It is a timing chart showing an example of normal processing of the batteryless multi-rotation encoder of FIG.

[0012] Each embodiment will be described in detail below with reference to the drawings. In the following embodiments, a battery-less multi-rotation encoder will be described as an example, but the technology of the present disclosure is not limited thereto. For example, the technology of the present disclosure can be applied to various semiconductor devices that operate with current pulses from a power generation element that generates power using electromagnetic induction. In the following description, the same or corresponding parts will be designated by the same reference numerals, and their description may not be repeated.

[0013] Embodiment 1. [Configuration of a Batteryless Multi-Rotation Encoder] Fig. 1 is a circuit block diagram of a batteryless multi-rotation encoder ENC1 according to embodiment 1. The batteryless multi-rotation encoder ENC1 in Fig. 1 includes a power generation element 1 that generates power using electromagnetic induction, and a semiconductor device SD1 that operates using current pulses generated by this power generation element 1.

[0014] While FIG. 1 representatively shows one power generating element 1, in an actual batteryless multi-rotation encoder, multiple coils are arranged around the rotation axis as multiple power generating elements 1 with shifted phase angles. When the magnet rotates with the rotation axis, the direction of the magnetic field changes, and current pulses are generated in the power generating element 1 by electromagnetic induction. The current pulses are converted into voltage pulses when electric charge generated by the power generating element 1 is stored in a storage capacitance element within the semiconductor device SD1. Because the multiple power generating elements 1 are arranged at different phase angles, current pulses are generated at different rotation angles. As will be described later, the digital processing circuit 6 determines the rotation speed and direction of the rotation axis based on the number of generated current pulses, the position of the power generating element, and the direction of the current pulses.

[0015] In the present disclosure, the current pulse generated by the power generating element 1 and the voltage pulse after conversion are collectively referred to as a power generating pulse.

[0016] The semiconductor device SD1 includes rectifier circuits 101, 201, capacitance elements 102, 202 for storing electricity, voltage determination circuits 103, 203, charge amount determination circuits 104, 204, reference voltage generation circuits 105, 205, a selection circuit 2, a constant voltage circuit 3, a POR (Power On Reset) circuit 4, an oscillation circuit 5, a digital processing circuit 6, and a non-volatile memory 7.

[0017] The voltage determination circuit 103 and the charge determination circuit 104 constitute a determination circuit 130 that determines whether or not the amount of power generated by the power generating element 1 is sufficient. The voltage determination circuit 203 and the charge determination circuit 204 constitute a determination circuit 230 that determines whether or not the amount of power generated by the power generating element 1 is sufficient.

[0018] The power generating element 1 is connected to the rectifier circuit 101 and the rectifier circuit 201. The rectifier circuit 101 and the rectifier circuit 201 are connected to the power generating element 1 so that the rectification directions are opposite to each other. The output of the rectifier circuit 101 is stored in the capacitance element 102, and the output of the rectifier circuit 201 is stored in the capacitance element 202. Therefore, depending on the polarity of the current pulse generated in the power generating element 1, charge is stored in one of the capacitance elements 102 and 202, generating a voltage.

[0019] 1, the rectifier circuit 101 includes diodes 101A and 101B. A first end 1A of the coil serving as the power generating element 1 is connected to a high-potential node 120 of the capacitance element 102 via the forward diode 101A. A second end 1B of the coil serving as the power generating element 1 is connected to a low-potential node of the capacitance element 102, i.e., ground GND, via the reverse diode 101B.

[0020] Similarly, the rectifier circuit 201 includes diodes 201A and 201B. A first end 1A of the coil serving as the power generating element 1 is connected to a node on the low potential side of the capacitance element 202, i.e., ground GND, via a reverse diode 201B. A second end 1B of the coil serving as the power generating element 1 is connected to a high potential side node 220 of the capacitance element 202 via a forward diode 201A.

[0021] The voltage Vpls1 of the high potential side node 120 of the capacitance element 102 is input to the selection circuit 2, the voltage evaluation circuit 103, the charge amount evaluation circuit 104, and the reference voltage generation circuit 105. The voltage Vpls2 of the high potential side node 220 of the capacitance element 202 is input to the selection circuit 2, the voltage evaluation circuit 203, the charge amount evaluation circuit 204, and the reference voltage generation circuit 205.

[0022] The reference voltage generation circuit 105 generates a constant reference voltage Vref1 that does not depend on the magnitude of the voltage Vpls1 based on the voltage Vpls1 of the capacitive element 102. The generated reference voltage Vref1 is input to the voltage evaluation circuit 103 and the charge amount evaluation circuit 104. Similarly, the reference voltage generation circuit 205 generates a constant reference voltage Vref2 that does not depend on the magnitude of the voltage Vpls2 based on the voltage Vpls2 of the capacitive element 202. The generated reference voltage Vref2 is input to the voltage evaluation circuit 203 and the charge amount evaluation circuit 204.

[0023] The voltage evaluation circuit 103 determines whether a first determination condition, that is, the voltage Vpls1 of the capacitive element 102 exceeds a first determination value, is satisfied. This determines whether the voltage level of the voltage Vpls1 of the capacitive element 102 is sufficient to start processing in the digital processing circuit 6. The voltage evaluation circuit 103 outputs the determination result as a determination signal Vdet1 to the selection circuit 2 and the digital processing circuit 6. Similarly, the voltage evaluation circuit 203 determines whether a first determination condition, that is, the voltage Vpls2 of the capacitive element 202 exceeds a first determination value, is satisfied. This determines whether the voltage level of the voltage Vpls2 of the capacitive element 202 is sufficient to start processing in the digital processing circuit 6. The voltage evaluation circuit 203 outputs the determination result as a determination signal Vdet2 to the selection circuit 2 and the digital processing circuit 6.

[0024] The selection circuit 2 selects one of the voltages Vpls1 and Vpls2 that has reached a sufficient voltage level based on the determination signals Vdet1 and Vdet2, and outputs the selected voltage Vpls1 or Vpls2 to the constant voltage circuit 3.

[0025] The charge amount determination circuit 104 receives inputs of the voltage Vpls1 of the capacitive element 102 and the reference voltage Vref1, as well as inputs a determination timing signal Vtm1 from the digital processing circuit 6. When the determination timing signal Vtm1 is activated (for example, becomes high level), the charge amount determination circuit 104 determines whether a second determination condition is met, that is, the amount of charge accumulated in the capacitive element 102 exceeds a second determination value. This determines whether the amount of charge accumulated in the capacitive element 102 is sufficient for subsequent processing by the digital processing circuit 6. When the charge amount determination circuit 104 determines that the amount of charge in the capacitive element 102 is insufficient (i.e., the second determination condition is not met), it outputs an interrupt signal Vstop1 indicating an active state (for example, high level) to the digital processing circuit 6.

[0026] Similarly, the charge amount determination circuit 204 receives the voltage Vpls2 of the capacitive element 202 and the reference voltage Vref2 as input, and also receives a determination timing signal Vtm2 from the digital processing circuit 6. The charge amount determination circuit 204 determines whether the charge amount of the capacitive element 202 (proportional to the voltage Vpls2) exceeds a second determination value when the determination timing signal Vtm2 is activated. This determines whether the charge amount of the capacitive element 202 is sufficient for subsequent processing by the digital processing circuit 6. If the charge amount determination circuit 204 determines that the charge amount of the capacitive element 202 is insufficient (i.e., the second determination condition is not satisfied), it outputs an interruption signal Vstop2 indicating an active state (for example, high level) to the digital processing circuit 6.

[0027] The constant voltage circuit 3 generates a constant power supply voltage Vdig used in the POR circuit 4, the oscillator circuit 5, the digital processing circuit 6, and the nonvolatile memory 7 from the voltage Vpls1 or Vpls2 selected by the selection circuit 2. The constant voltage circuit 3 is, for example, an LDO (Low Drop Out) circuit.

[0028] The POR circuit 4 releases the reset signal RST when the power supply voltage Vdig output from the constant voltage circuit 3 reaches the minimum operating power supply voltage.

[0029] The oscillator circuit 5 supplies a clock signal CLK to the digital processing circuit 6 and the nonvolatile memory 7. The configuration of the oscillator circuit 5 is not particularly limited. For example, it may be a ring oscillator, a crystal oscillator, or a ceramic oscillator.

[0030] The digital processing circuit 6 is configured by a logic circuit and outputs a write signal Write to the nonvolatile memory 7, and receives an input of a read signal Read from the nonvolatile memory 7.

[0031] [Operation of Batteryless Multi-Rotation Encoder] Next, the operation of the batteryless multi-rotation encoder ENC1 of Fig. 1 will be described. Fig. 2 is a timing chart showing an example of normal processing of the batteryless multi-rotation encoder ENC1 of Fig. 1. Fig. 3 is a timing chart showing an example of interruption processing of the batteryless multi-rotation encoder ENC1 of Fig. 1. Fig. 2 and Fig. 3 correspond to each other, and corresponding parts are assigned the same reference numerals.

[0032] 1 and 2 , the current generated in power generating element 1 is selectively supplied to capacitance element 102 or capacitance element 202 through rectifier circuit 101 or rectifier circuit 201 depending on the direction of the current. The supplied current is stored as charge in the capacitance element and converted into a voltage.

[0033] 1 , when a current is generated in a direction from the second terminal 1B to the first terminal 1A of the power generating element 1, the rectifier circuit 101 becomes conductive. In this case, the current generated in the power generating element 1 is supplied to the capacitance element 102. Conversely, when a current is generated in a direction from the first terminal 1A to the second terminal 1B of the power generating element 1, the rectifier circuit 201 becomes conductive. In this case, the current generated in the power generating element 1 is supplied to the capacitance element 202.

[0034] The voltage Vpls1 of the capacitive element 102 is input to the reference voltage generation circuit 105, which generates a reference voltage Vref1. The voltage evaluation circuit 103 generates a evaluation voltage VD from the reference voltage Vref1 generated by the reference voltage generation circuit 105, and determines whether the voltage Vpls1 of the capacitive element 102 is higher or lower than the evaluation voltage VD. The evaluation result is output to the digital processing circuit 6 as a evaluation signal Vdet1. If the voltage Vpls1 of the capacitive element 102 is higher than the evaluation voltage VD, a high level is output as the evaluation signal Vdet1, and if the voltage Vpls1 is lower than the evaluation voltage VD, a low level is output as the evaluation signal Vdet1.

[0035] If the determination voltage VD is expressed as the product of VDa and VDb (i.e., VD=VDa×VDb), comparing the voltage Vpls1 with the determination voltage VD is equivalent to comparing Vpls1 / VDa with VDb. Therefore, it is not necessary to use the voltage Vpls1 of the capacitive element 102 as the comparison target as is.

[0036] Similarly, the voltage Vpls2 of the capacitive element 202 is input to the reference voltage generation circuit 205, which generates a reference voltage Vref2. The voltage evaluation circuit 203 generates a evaluation voltage VD from the reference voltage Vref2 generated by the reference voltage generation circuit 205, and determines whether Vpls2 is higher or lower than the evaluation voltage VD. The evaluation result is output to the digital processing circuit 6 as a evaluation signal Vdet2. If the voltage Vpls2 of the capacitive element 202 is higher than the evaluation voltage VD, a high level is output as the evaluation signal Vdet2, and if the voltage Vpls2 is lower than the evaluation voltage VD, a low level is output as the evaluation signal Vdet2.

[0037] Although the above description has been given assuming that the determination signals Vdet1 and Vdet2 are positive logic signals, the determination signals Vdet1 and Vdet2 may be negative logic signals.

[0038] Specifically, in the case of FIG. 2, at time t1, the voltage Vpls1 of the capacitance element 102 exceeds the determination voltage VD, so that the determination signal Vdet1 output from the voltage determination circuit 103 switches to a high level.

[0039] The selection circuit 2 selectively supplies either the voltage Vpls1 or Vpls2 to the constant voltage circuit 3 based on the logical values ​​of the determination signals Vdet1 and Vdet2. When the determination signal Vdet1 is at a high level, the voltage Vpls1 is selected, and when the determination signal Vdet2 is at a high level, the voltage Vpls2 is selected. Since it is conceivable that both signals may be at a high level at the same time, the selection circuit 2 performs exclusive processing, such as preferentially selecting the determination signal that first indicated an active state.

[0040] When voltage Vpls1 or Vpls2 is supplied to constant voltage circuit 3, constant voltage circuit 3 outputs voltage Vdig. In the case of Fig. 2, voltage Vpls1 is input to constant voltage circuit 3 at time t1, causing power supply voltage Vdig to rise. Voltage Vdig is supplied as a power supply voltage to POR circuit 4, oscillator circuit 5, digital processing circuit 6, and nonvolatile memory circuit 7.

[0041] At the next time t2, when the power supply voltage Vdig reaches the desired voltage, the POR circuit 4 releases the reset signal RST. In the case of FIG. 2, the reset signal RST switches from high to low. This enables the oscillator circuit 5, digital processing circuit 6, and nonvolatile memory 7 to operate and start processing.

[0042] The series of processes executed in the batteryless multi-rotation encoder can be briefly explained as follows. First, the digital processing circuit 6 counts the number of current pulses generated each time a current pulse is generated in the power generating element 1, and determines the direction of the current pulse based on the determination signals Vdet1 and Vdet2. Next, the digital processing circuit 6 determines the rotation speed and rotation direction (hereinafter collectively referred to as the rotation state) of the object to be observed based on this information. The digital processing circuit 6 then stores the determined rotation state in the non-volatile memory 7.

[0043] In order to perform the above processing, when the processing is started at time t2, the digital processing circuit 6 first reads (Reads) information on the previous rotation state from the nonvolatile memory 7 between time t2 and time t3.

[0044] During the next period from time t3 to time t4, the digital processing circuit 6 determines the current rotation state based on the previous rotation state that has been read and the determination signals Vdet1 and Vdet2, and updates (Updates) the rotation state.

[0045] At time t4 when the update of the rotation state is completed, if the determination signal Vdet1 is valid, the digital processing circuit 6 transmits an active (high level) determination timing signal Vtm1 to the charge amount determination circuit 104.

[0046] Upon receiving the activated determination timing signal Vtm1, the charge amount determination circuit 104 determines whether the charge accumulated in the capacitance element 102 at this time is equal to or greater than a determination value. If the charge amount of the capacitance element 102 is equal to or greater than the determination value, the charge amount determination circuit 104 sets the interruption signal Vstop1 to low level, and if the charge amount of the capacitance element 102 is less than the determination value, the interruption signal Vstop1 to high level. Here, the determination value of the charge amount determination circuit 104 is determined based on the amount of charge required for the write process to the nonvolatile memory 7.

[0047] If the relationship between the charge amount of the capacitance element 102 and the voltage Vpls1 of the capacitance element 102 is known in advance, a value converted into a voltage may be used as the determination value. For example, if the capacitance C of the capacitance element 102 is constant regardless of the voltage Vpls1, the charge amount is expressed as C×Vpls1. In the charge amount determination circuits 104 and 204 of the first embodiment, the determination value converted into a voltage is determined based on the reference voltages Vref1 and Vref2.

[0048] Alternatively, the digital processing circuit 6 may not send the determination timing signal Vtm1 to the charge amount determination circuit 104, but the charge amount determination circuit 104 may constantly compare the charge amount of the capacitance element 102 with the determination value and constantly transmit the result to the digital processing circuit 6. In this case, the digital processing circuit 6 uses the determination result received at the timing (time t4) when the update of the rotation state is completed.

[0049] If the interruption signal Vstop1 is at a low level, the digital processing circuit 6 determines that the charge necessary for the subsequent processing has accumulated in the capacitive element 102. In this case, the digital processing circuit 6 writes the updated data (i.e., information on the rotation state) to the nonvolatile memory 7 between the next time t4 and time t5, and ends the series of processing.

[0050] At time t6 after the series of processes is completed, when the voltage Vpls1 of the capacitive element 102 falls below the lower limit operating voltage VL of the constant voltage circuit 3, the power supply voltage Vdig output from the constant voltage circuit 3 decreases. This causes the reset signal RST to go high, and various circuits are reset.

[0051] 3, when the interruption signal Vstop1 is at a high level at time t4, the digital processing circuit 6 determines that the charge required for the subsequent processing has not accumulated in the capacitive element 102. In this case, the digital processing circuit 6 executes the interruption processing without writing the updated data to the nonvolatile memory 7.

[0052] The processing when the determination signal Vdet2 is valid is similar to that described above. In this case, at time t4 when the update of the rotation state is completed, the digital processing circuit 6 transmits an active (high level) determination timing signal Vtm2 to the charge amount determination circuit 204. In response to the determination timing signal Vtm2, the digital processing circuit 6 determines whether the charge accumulated in the capacitive element 202 at this time is equal to or greater than the determination value. If the charge amount of the capacitive element 202 is equal to or greater than the determination value, the charge amount determination circuit 204 sets the interrupt signal Vstop2 to low level. If the charge amount of the capacitive element 202 is less than the determination value, the digital processing circuit 6 sets the interrupt signal Vstop2 to high level. If the interrupt signal Vstop2 is low level, the digital processing circuit 6 writes the updated data to the nonvolatile memory 7 and terminates the series of processing. On the other hand, if the interrupt signal Vstop2 is high level, the digital processing circuit 6 executes an interrupt process that does not write the updated data to the nonvolatile memory 7.

[0053] If the interruption process is executed without writing the update data to the nonvolatile memory 7, a necessary pulse detection will be missed. In such cases, a correction algorithm for correcting the rotation position is known, as described in, for example, the aforementioned Japanese Patent No. 5769879 (Patent Document 1). This allows the number of rotations to be counted without missing any counts based on the corrected rotation position even when a pulse detection is missed. Furthermore, it is desirable to write error information indicating that an error has occurred to the nonvolatile memory 7 during the interruption process. The error information can be used as effective information when correcting the rotation position in the event of a missing pulse, thereby improving the accuracy of the correction.

[0054] As described above, even if processing does not start after all the charges required for processing have been accumulated, by determining whether the required charges are insufficient during processing, processing can be completed without abnormal termination.

[0055] [Effects of First Embodiment] The effects of the first embodiment will be described below in comparison with a comparative example with reference to FIGS. 4 and 5. FIG.

[0056] FIG. 4 is a diagram conceptually showing the amount of charge stored in the capacitive elements 102 and 202 at the start and end of each of the read, update, and write processes.

[0057] 4, the amount of charge required for the read process is denoted as "Read," the amount of charge required for the update process is denoted as "Update," and the amount of charge required for the write process is denoted as "Write." Also, the amount of charge generated after the start of the process is denoted as "Charge."

[0058] It is not possible to use the charge corresponding to the lower limit voltage VL of the constant voltage circuit 3. This unusable charge is expressed as the product of the capacitance of the capacitance elements 102 and 202 and the lower limit voltage VL of the constant voltage circuit 3.

[0059] In the comparative example, processing is started after it is confirmed that the charge required for all processes, including reading, updating, and writing, has accumulated. In this case, the determination voltage VD1 of the voltage determination circuits 103 and 203 is determined by (the lower limit operating voltage of the constant voltage circuit) + (the charge required for all processes) × (the capacitance of the capacitive element), and cannot be lowered below that value.

[0060] Furthermore, in the comparative example, the lower limit of the charge amount at which all processes can be executed occurs when the determination voltage VD1 is equal to the peak value of the voltages Vpls1 and Vpls2 of the capacitance elements 102 and 202. In this case, no charge is supplied after the voltage determination, and charge is consumed in each process after the voltage determination, causing the voltages Vpls1 and Vpls2 of the capacitance elements 102 and 202 to gradually decrease and reach the lower limit operating voltage VL of the constant voltage circuit 3 when all processes are completed.

[0061] On the other hand, in this embodiment, the determination voltage VD2 of the voltage determination circuits 103, 203 can be (the lower limit operating voltage of the constant voltage circuit) + (the charge required for reading and updating) × (the capacitance of the capacitance element). In other words, the determination voltage of the voltage determination circuits 103, 203 can be lowered by the voltage equivalent value VD3 of the charge required for the write process. However, in order to complete the write process, the charge required for the write process needs to be supplied from the power generation element 1 from the start of the process to the start of the write process. Whether the charge required for the write process (Charge) has been supplied to the capacitance element 102, 202 is determined by the charge amount determination circuit 104, 204.

[0062] In this embodiment, it is assumed that the read process and update process are performed correctly, but if there is no problem even if the process ends abnormally, the determination voltage VD2 can be reduced to the lower limit voltage VL of the constant voltage circuit 3. Even if the voltages Vpls1 and Vpls2 of the capacitance elements 102 and 202 become less than the lower limit voltage VL during the read process or update process, the data in the digital processing circuit 6 is simply reset, and abnormal data is not written to the nonvolatile memory 7.

[0063] 5 is a diagram conceptually showing the change over time of the voltage Vpls1 of the capacitive element 102. The voltage Vpls1 shown in FIG. 5 corresponds to the case where the amount of charge is greater than the minimum amount of charge shown in FIG.

[0064] In the comparative example indicated by the dashed line, the amount of charge sufficient to execute all processes is stored in the capacitive element 102 at the process start time t202. In this case, the peak value of the voltage Vpls1 of the capacitive element 102 is equal to or greater than the determination voltage VD1 of the voltage determination circuit 103.

[0065] On the other hand, in the case of this embodiment shown by the solid line, the determination voltage VD2 of the voltage determination circuit 103 can be made lower than the determination voltage VD1 of the comparative example. Therefore, processing starts before the peak value, that is, at time t2 during power generation by the power generation element 1. As a result, the peak value of the generated voltage can be lowered, and the reverse current generated in the coil serving as the power generation element 1 can be suppressed.

[0066] As described above, the batteryless multi-rotation encoder ENC1 of this embodiment determines whether the charge in the capacitance elements 102 and 202 is sufficient to execute the subsequent process during a series of processes. This allows the start of the series of processes to be accelerated and the increase in voltage of the capacitance elements 102 and 202 to be suppressed. As a result, the voltage applied to the coil serving as the power generating element 1 can be suppressed, thereby suppressing the reverse voltage generated in the coil and increasing the effective generated charge. Therefore, even if the power generating capacity of the power generating element is relatively low, it is possible to prevent missed detection of power generation pulses and determine the rotation state.

[0067] In this embodiment, an example has been described in which the amount of charge of the capacitive elements 102 and 202 is determined before the write process, but the amount of charge may be determined before the read process or the update process. However, since charges generated after the amount of charge is determined are not taken into account in the charge amount determination, it is desirable to determine the amount of charge as late as possible. The amount of charge may also be determined at multiple times.

[0068] [Configuration Examples of Various Circuits] Below, configuration examples of the reference voltage generation circuits 105, 205, voltage evaluation circuits 103, 203, charge amount evaluation circuits 104, 204, selection circuit 2, constant voltage circuit 3, and POR circuit 4 in Figure 1 will be described. The circuit configurations shown below are merely examples and are not limited to these. Any circuit configuration may be used as long as it has the above-mentioned functions.

[0069] (Reference Voltage Generation Circuit and Voltage Evaluation Circuit) Fig. 6 is a circuit diagram showing an example of the configuration of the reference voltage generation circuit 105 and the voltage evaluation circuit 103 in Fig. 1. The reference voltage generation circuit 205 and the voltage evaluation circuit 203 also have the same configuration.

[0070] The reference voltage generating circuit 105 includes a plurality of diodes 301 connected in series, an NMOS (N-channel Metal-Oxide-Semiconductor) transistor 302, and resistance elements 303 to 305. In the case of FIG. 6, three diodes 301A to 301C are provided as the plurality of diodes 301.

[0071] The drain terminal of NMOS transistor 302 is connected to high potential side node 120 of capacitive element 102. The source terminal of NMOS transistor 302 is connected to ground GND via series-connected resistor elements 303 and 304. The gate terminal of NMOS transistor 302 is connected to high potential side node 120 via resistor element 305, and is also connected to ground GND via diodes 301A to 301C connected in series in the forward direction.

[0072] According to the above configuration, the source voltage of NMOS transistor 302 is a constant voltage determined according to the forward voltages of diodes 301A to 301C, regardless of voltage Vpls1 at high potential side node 120. This constant source voltage is divided by resistor elements 303 and 304, and the divided voltage is output from connection node 309 of resistor elements 303 and 304 as reference voltage Vref1.

[0073] The voltage evaluation circuit 103 includes a voltage comparator CMP1 and resistance elements 306 and 307. The resistance elements 306 and 307 are connected in series between the high potential side node 120 and ground GND. A non-inverting input terminal of the voltage comparator CMP1 is connected to a connection node 310 of the resistance elements 306 and 307. A reference voltage Vref1 is input to an inverting input terminal of the voltage comparator CMP1.

[0074] According to the above configuration, the voltage comparator CMP1 compares the reference voltage Vref1 with a divided voltage obtained by dividing the voltage Vpls1 of the capacitive element 102 by the resistive elements 306 and 307. When the divided voltage of the voltage Vpls1 is greater than the reference voltage Vref1, the voltage comparator CMP1 activates the determination signal Vdet1.

[0075] (Charge Amount Determination Circuit) Fig. 7 is a circuit diagram showing an example of the configuration of the charge amount determination circuit 104 in Fig. 1. In Fig. 7, assuming that the amount of charge in the capacitance element 102 is proportional to the voltage, the charge amount determination circuit 104 compares the voltage Vpls1 of the capacitance element 102 with a reference voltage 317. The charge amount determination circuit 204 has a similar configuration.

[0076] Specifically, the electric charge determination circuit 104 includes a voltage comparator CMP2, a D flip-flop 316, and a reference voltage 317. The inverting input terminal of the voltage comparator CMP2 is connected to the high-potential node 120 of the capacitive element 102. The reference voltage 317 is input to the non-inverting input terminal of the voltage comparator CMP2. The reference voltage 317 is generated, for example, from a reference voltage Vref1. The comparison result of the voltage comparator CMP2 is input to an input terminal D of the D flip-flop 316. An interrupt signal Vstop1 is output from an output terminal Q of the D flip-flop 316. Furthermore, a determination timing signal Vtm1 is input to a clock terminal CLK of the D flip-flop 316, and a determination signal Vdet1 is input to an inverting reset terminal RSTB of the D flip-flop 316.

[0077] According to the above configuration, the D flip-flop 316 holds a logical value representing the comparison result of the voltage comparator CMP2 input to the input terminal D at the timing when the determination timing signal Vtm1 is activated to a high level. The D flip-flop 316 outputs the held logical value as an interruption signal Vstop1 from the output terminal Q. Therefore, when the reference voltage 317 is higher than the voltage Vpls1 of the capacitive element 102, a high-level interruption signal Vstop1 is output from the D flip-flop 316. When the determination signal Vdet1 switches from a high level to a low level, the D flip-flop 316 is reset, and the interruption signal Vstop1 returns to a low level.

[0078] (Selection Circuit) Fig. 8 is a circuit diagram showing an example of the configuration of selection circuit 2 in Fig. 1. Referring to Fig. 8, selection circuit 2 includes bidirectional switches 321 and 322, and NAND circuits 323 and 324 forming a flip-flop.

[0079] The bidirectional switch 321 is configured by connecting two PMOS (P-channel Metal-Oxide-Semiconductor) transistors 321A and 321B in series with opposite polarity. Similarly, the bidirectional switch 322 is configured by connecting two PMOS transistors 322A and 322B in series with opposite polarity. The output node 320 of the selection circuit 2 is connected to the high-potential side node 120 of the capacitance element 102 via the bidirectional switch 321, and is also connected to the high-potential side node 220 of the capacitance element 202 via the bidirectional switch 322.

[0080] The determination signal Vdet1 is input to a first input terminal of the NAND circuit 323. The determination signal Vdet2 is input to a first input terminal of the NAND circuit 324. The output terminal of the NAND circuit 323 is connected to a second input terminal of the NAND circuit 324 and is also connected to the gate terminals of the PMOS transistors 321A and 321B that constitute the bidirectional switch 321. The output terminal of the NAND circuit 324 is connected to the second input terminal of the NAND circuit 323 and is also connected to the gate terminals of the PMOS transistors 322A and 322B that constitute the bidirectional switch 322.

[0081] According to the above configuration, when the determination signal Vdet1 is at a high level and the determination signal Vdet2 is at a low level, the output signal of the NAND circuit 323 becomes a low level and the output signal of the NAND circuit 324 becomes a high level. As a result, the bidirectional switch 321 becomes conductive and the bidirectional switch 322 becomes non-conductive, and therefore the voltage Vpls1 of the capacitive element 102 is output from the output node 320 of the selection circuit 2.

[0082] Conversely, when the determination signal Vdet1 is at a low level and the determination signal Vdet2 is at a high level, the output signal of the NAND circuit 323 becomes a high level and the output signal of the NAND circuit 324 becomes a low level. As a result, the bidirectional switch 321 becomes non-conductive and the bidirectional switch 322 becomes conductive, so that the voltage Vpls2 of the capacitive element 202 is output from the output node 320 of the selection circuit 2.

[0083] (Constant Voltage Circuit) Fig. 9 is a circuit diagram showing an example of the configuration of constant voltage circuit 3 of Fig. 1. Referring to Fig. 9, constant voltage circuit 3 includes a PMOS transistor 331, resistance elements 332 and 333, a differential amplifier AMP1, and a reference voltage 334. Reference voltage 334 may be generated using reference voltages Vref1 and Vref2.

[0084] A source terminal of the PMOS transistor 331 is connected to an output node 320 of the selection circuit 2. A drain terminal of the PMOS transistor 331 is connected to an output node 335 of the constant voltage circuit 3 and is also connected to ground GND via series-connected resistor elements 332 and 333. A non-inverting input terminal of the differential amplifier AMP1 is connected to a connection node 336 of the resistor elements 332 and 333.

[0085] According to the above configuration, negative feedback is applied so that the voltage of the connection node 336 becomes equal to the reference voltage 334, so that the power supply voltage Vdig output from the output node 335 becomes a constant value independent of the magnitude of the voltages Vpls1 / Vpls2.

[0086] 10 is a circuit diagram showing an example of the configuration of the POR circuit 4 of FIG. 1. Referring to FIG. 10, the POR circuit 4 includes a low-pass filter 340 including a resistor element 341 and a capacitor 342, a voltage comparator CMP3, and a reference voltage 343. The reference voltage 343 may be generated using reference voltages Vref1 and Vref2.

[0087] 10 , the power supply voltage Vdig output from the constant voltage circuit 3 is input to the inverting input terminal of a voltage comparator CMP3 via a low-pass filter 340. A reference voltage 343 is input to the non-inverting input terminal of the voltage comparator CMP3. With this configuration, the reset signal RST is released when the power supply voltage Vdig reaches the reference voltage 343. The low-pass filter 340 is provided to suppress noise and overshoot in the power supply voltage Vdig output from the constant voltage circuit 3.

[0088] Embodiment 2. [Configuration of batteryless multi-rotation encoder] Figure 11 is a circuit block diagram of a batteryless multi-rotation encoder ENC2 according to embodiment 2. The semiconductor device SD2 of the batteryless multi-rotation encoder ENC2 in Figure 11 differs from the semiconductor device SD1 of the batteryless multi-rotation encoder ENC1 in Figure 1 in that it includes peak determination circuits 106, 206 instead of the charge amount determination circuits 104, 204. The voltage determination circuit 103 and the peak determination circuit 106 form a determination circuit 130, and the voltage determination circuit 203 and the peak determination circuit 206 form a determination circuit 230.

[0089] The peak determination circuit 106 receives the voltage Vpls1 of the capacitive element 102 and the reference voltage Vref1 output from the reference voltage generation circuit 105. The peak determination circuit 106 determines whether a second determination condition, that is, the peak value of the voltage Vpls1 of the capacitive element 102 has reached a determination voltage VP, is satisfied, and outputs a determination signal Vpeak1 indicating the determination result to the digital processing circuit 6.

[0090] Similarly, the peak determination circuit 206 receives the voltage Vpls2 of the capacitive element 202 and the reference voltage Vref2 output from the reference voltage generation circuit 205. The peak determination circuit 206 determines whether a second determination condition, that is, the peak value of the voltage Vpls2 of the capacitive element 202 has reached a determination voltage VP, is satisfied, and outputs a determination signal Vpeak2 indicating the determination result to the digital processing circuit 6.

[0091] Other configurations in FIG. 11 are similar to those in FIG. 1, so the same or corresponding parts are designated by the same reference numerals and description thereof will not be repeated.

[0092] [Operation of Batteryless Multi-Rotation Encoder] Next, the operation of the batteryless multi-rotation encoder ENC2 of Fig. 11 will be described. Fig. 12 is a timing chart showing an example of normal processing of the batteryless multi-rotation encoder ENC2 of Fig. 11. Also, Fig. 13 is a timing chart showing an example of interruption processing of the batteryless multi-rotation encoder ENC2 of Fig. 11.

[0093] 2 and 3 of the first embodiment, and are similar in operation except for peak determination by peak determination circuits 106 and 206. The determination timing signals Vtm1 and Vtm2 used in charge amount determination circuits 104 and 204 in the first embodiment are not required.

[0094] Specifically, the peak determination circuit 106 continuously monitors whether or not the peak value of the voltage Vpls1 of the capacitance element 102 has reached the determination voltage VP from the start of power generation by the power generating element 1. More specifically, if the peak value of the voltage Vpls1 of the capacitance element 102 exceeds the determination voltage VP even once, the peak determination circuit 106 maintains the determination signal Vpeak1 that it outputs in an active state (for example, high level), and if the peak value never exceeds the determination voltage VP, maintains the determination signal Vpeak1 in an inactive state (for example, low level).

[0095] In practice, the waveform of the voltage Vpls1 of the capacitive element 102 has an upwardly convex waveform that gradually rises during power generation, reaches a peak, and then gradually drops. Therefore, when the current voltage Vpls1 of the capacitive element 102 at least temporarily exceeds the determination voltage VP, the peak determination circuit 106 switches the determination signal Vpeak1 from low level to high level, and thereafter maintains the determination signal Vpeak1 at high level.

[0096] The peak determination circuit 206 operates in a similar manner. Specifically, the peak determination circuit 206 maintains the determination signal Vpeak2 it outputs in an active state (for example, a high level) when the peak value of the voltage Vpls2 of the capacitive element 202 exceeds the determination voltage VP at least temporarily, and maintains the determination signal Vpeak2 in an inactive state (for example, a low level) if the peak value never exceeds the determination voltage VP.

[0097] Before starting the write process, the digital processing circuit 6 monitors the determination signals Vpeak1 and Vpeak2 output from the peak determination circuits 106 and 206. If the determination signals Vpeak1 and Vpeak2 are high, the digital processing circuit 6 starts the write process, and if they are low, the digital processing circuit 6 does not execute the write process. The timing for determining whether the determination signals Vpeak1 and Vpeak2 are high or not is preferably immediately before starting the write process. If the determination is performed earlier and the voltages Vpls1 and Vpls2 of the capacitive elements 102 and 202 reach their peaks after the determination, there is the disadvantage that the charge generated by the power generating element 1 between the determination and the time when the voltages reach their peaks is not taken into account.

[0098] 12 , at time t21, the voltage Vpls1 of the capacitive element 102 reaches the determination voltage VP, so the peak determination circuit 106 switches the determination signal Vpeak1 from low to high. The determination signal Vpeak1 is then maintained at high until time t6, at which time the voltage Vpls1 of the capacitive element 102 drops to the lower limit voltage VL of the constant voltage circuit 3.

[0099] After the update process is completed, at time t4 immediately before the start of the write process, the digital processing circuit 6 confirms that the determination signal Vpeak1 is at a high level, and then starts the write process.

[0100] In the case of FIG. 13, after the power generation element 1 starts generating power, the voltage Vpls1 of the capacitance element 102 never reaches the determination voltage VP, so the peak determination circuit 106 maintains the determination signal Vpeak1 at a low level.

[0101] After the update process is completed, at time t4 immediately before the start of the write process, if the digital processing circuit 6 confirms that the determination signal Vpeak1 is at a low level, it executes an interruption process without starting the write process.

[0102] [Effects and Modifications] When the waveforms of the voltages Vpls1 and Vpls2 of the capacitive elements 102 and 202 rise smoothly, reach a peak, and then fall smoothly, the above method can achieve the same effect as in embodiment 1. However, when the waveforms of the voltages Vpls1 and Vpls2 repeatedly increase and decrease, it may not be possible to determine whether the amount of power generation is sufficient to complete a series of processes by judging only the peak value. Therefore, it is desirable that the digital processing circuit 6 be equipped with a mechanism for detecting write errors.

[0103] 14 is a diagram illustrating an example of a mechanism for detecting write errors. Error detection bits are provided at the beginning and end of data written to the nonvolatile memory 7 during a write process. The digital processing circuit 6 writes "0" to the first and last bits of the write data when an even-numbered (2n) power generation pulse is generated. The digital processing circuit 6 writes "1" to the first and last bits of the write data when an odd-numbered (2n+1) power generation pulse is generated.

[0104] Referring to FIG. 14A, if writing is performed normally, the first and last bits of the read data when the 2n+1th power generation pulse is generated will be "0", and the first and last bits of the read data when the 2(n+1)th power generation pulse is generated will be "1".

[0105] Referring to Figure 14(B), if the write operation stops during the (2n+1)th write, a "1" is written as the first error detection bit of the write data, but a "1" is not written as the last error detection bit of the write data. As a result, the first and last bits of the read data when the (2(n+1))th power generation pulse is generated do not match. This makes it possible to determine that the write operation has not been completed, allowing error processing to be performed.

[0106] The write error detection mechanism may be incorporated into the digital processing circuit 6 of the semiconductor device SD1 of the first embodiment for safety purposes in preparation for situations where unexpected charge consumption occurs.

[0107] [Configuration Example of Peak Determination Circuit] A configuration example of the peak determination circuits 106 and 206 in Fig. 11 will be described below. The circuit configuration shown below is merely an example and is not limited to this. Any circuit configuration may be used as long as it has the above-described functions.

[0108] Fig. 15 is a circuit diagram showing an example of the configuration of the peak determination circuit 106 of Fig. 11. In the peak determination circuit 106 shown in Fig. 15, the threshold of the voltage comparator has hysteresis. The peak determination circuit 206 has a similar configuration.

[0109] Specifically, the peak determination circuit 206 includes resistive elements 350, 351, and 352, a voltage comparator CMP4, a NOT circuit 354, and a PMOS transistor 353. The resistive elements 350, 351, and 352 are connected in series in this order between the high-potential node 120 of the capacitive element 102 and ground GND. The non-inverting input terminal of the voltage comparator CMP4 is connected to a connection node 356 between the resistive elements 351 and 352. A reference voltage Vref1 is input to the inverting input terminal of the voltage comparator CMP4. The PMOS transistor 353 is connected in parallel with the resistive element 350. The output terminal of the voltage comparator CMP4 is connected to an output node 357 of the peak determination circuit 106 and to the gate terminal of the PMOS transistor 353 via the NOT circuit 354.

[0110] According to the above configuration, when the voltage Vpls1 is relatively small, the output of the voltage comparator CMP4 is at a low level, and the PMOS transistor 353 is in an off state. Here, if the resistance values ​​of the resistive elements 350, 351, and 352 are r0, r1, and r2, respectively, the voltage comparator CMP4 compares the voltage Vpls1 with the first threshold value Vref1×(r0+r1+r2) / r2.

[0111] Next, when the voltage Vpls1 exceeds the first threshold, the output of the voltage comparator CMP4 goes high, and the PMOS transistor 353 turns on. In this case, the voltage comparator CMP4 compares the voltage Vpls1 with the second threshold Vref1×(r1+r2) / f2. Because the second threshold is smaller than the first threshold, the output of the voltage comparator CMP4 remains high. A similar effect can be achieved by adding a latch circuit to the output of the voltage comparator CMP4.

[0112] Fig. 16 is a circuit diagram showing another example of the configuration of the peak determination circuit 106 of Fig. 11. The peak determination circuit 106 of Fig. 16 detects the height of the peak of the voltage Vpls2 using a peak detection circuit and compares the detected peak height with a reference voltage. A peak determination circuit 206 has a similar configuration.

[0113] Specifically, the peak determination circuit 106 includes a peak detection circuit 360, a voltage comparator CMP5, and a reference voltage 364. The peak detection circuit 360 includes a diode 361, an NMOS transistor 362, and a capacitor 363. The reference voltage 364 may be generated using reference voltages Vref1 and Vref2.

[0114] The anode of the diode 361 is connected to the high-potential node 120 of the capacitance element 102, and the cathode of the diode 361 is connected to ground GND via the capacitor 363. With this configuration, the voltage Vpls1 is held in the capacitor 363 until the voltage Vpls1 reaches its peak. A reset signal RST1 is input to the gate terminal of the NMOS transistor 362, thereby resetting the voltage of the capacitor 363. A voltage comparator CMP5 compares the voltage of the capacitor 363 with a reference voltage 364, and sets the determination signal Vpeak1 to a high level when the voltage of the capacitor 363 exceeds the reference voltage 364.

[0115] Embodiment 3. [Configuration of batteryless multi-rotation encoder] Fig. 17 is a circuit block diagram of a batteryless multi-rotation encoder ENC3 according to embodiment 3. The semiconductor device SD3 of the batteryless multi-rotation encoder ENC3 in Fig. 17 differs from the semiconductor device SD1 of the batteryless multi-rotation encoder ENC1 in Fig. 1 in the following points.

[0116] First, a boost circuit 107 is provided between a connection node 121, which commonly connects the selection circuit 2, the voltage evaluation circuit 103, the charge amount evaluation circuit 104, and the reference voltage generation circuit 105, and a high-potential side node 120 of the capacitance element 102. Similarly, a boost circuit 207 is provided between a connection node 221, which commonly connects the selection circuit 2, the voltage evaluation circuit 203, the charge amount evaluation circuit 204, and the reference voltage generation circuit 205, and a high-potential side node 220 of the capacitance element 202.

[0117] Furthermore, another capacitance element 108 is connected between the connection node 121 and ground GND. Similarly, another capacitance element 208 is connected between the connection node 221 and ground GND.

[0118] The boost circuit 107 generates a voltage Vpls1 by boosting the voltage V1 of the capacitive element 102. The voltage Vpls1 is stored as an electric charge in the capacitive element 108. The constant voltage circuit 3 generates a power supply voltage Vdig from the voltage Vpls1 of the capacitive element 108. Similarly, the boost circuit 207 generates a voltage Vpls2 by boosting the voltage V2 of the capacitive element 202. The voltage Vpls2 is stored as an electric charge in the capacitive element 208. The constant voltage circuit 3 generates a power supply voltage Vdig from the voltage Vpls2 of the capacitive element 208.

[0119] There are no particular limitations on the configuration of the boost circuits 107 and 207. For example, they may be configured to be connected to an isolated or non-isolated DC / DC converter via a buffer amplifier for converting current into voltage.

[0120] 1, the same or corresponding parts are designated by the same reference numerals and description thereof will not be repeated. Note that the boost circuits 107, 207 and the capacitance elements 108, 208 in FIG. 17 can also be combined with the semiconductor device SD2 of the battery-less multi-rotation encoder ENC2 of the second embodiment shown in FIG.

[0121] [Operation of Batteryless Multi-Rotation Encoder] Figure 18 is a timing chart showing an example of normal processing of the batteryless multi-rotation encoder ENC3 of Figure 17. The timing chart of Figure 18 differs from the timing chart of Figure 2 in that the voltage Vpls1 obtained by boosting the voltage V1 of the capacitive element 102 is used to drive the constant voltage circuit 3, but other points in Figure 18 are similar to those in Figure 2. In Figure 18, parts that are the same as or correspond to those in Figure 2 are given the same reference numerals.

[0122] Specifically, the constant voltage circuit 3 starts operating when the boosted voltage Vpls1 reaches the determination voltage VD of the voltage determination circuit 103. This causes the digital processing circuit 6 to execute the read process and update process.

[0123] Furthermore, at the timing (time t4) when the determination timing signal Vtm1 switches from low level to high level, the charge amount determination circuit 104 determines whether the charge amount corresponding to the boosted voltage Vpls1 is equal to or greater than the determination value. As a result, if the charge amount corresponding to the boosted voltage Vpls1 is equal to or greater than the determination value, the digital processing circuit 6 executes the write process and completes the series of processes. On the other hand, if the charge amount corresponding to the boosted voltage Vpls1 is less than the determination value, the digital processing circuit 6 executes the interrupt process without writing the updated data to the nonvolatile memory 7, as described with reference to FIG. 3.

[0124] In this way, it is determined whether the voltages Vpls1 and Vpls2 obtained by boosting the voltages V1 and V2 of the capacitance elements 102 and 202 directly connected to the power generation element 1, rather than the voltages V1 and V2, are sufficient to start the read process, and whether they correspond to a sufficient amount of charge to execute the write process.

[0125] As described above, according to the battery-less multi-rotation encoder ENC3 of the third embodiment, even if the voltages V1, V2 of the capacitance elements 102, 202 directly connected to the power generating element 1 are low, the boost voltages Vpls1, Vpls2 sufficient to drive the constant voltage circuit 3 can be obtained, and the digital processing circuit 6 can start processing. As a result, the voltage applied to the power generating element 1 can be kept low, thereby suppressing the reverse current generated in the power generating element 1 and allowing more charge to be used.

[0126] Furthermore, even if the capacitance of the capacitance elements 108, 208 on the output side of the boost circuits 107, 207 is reduced, the voltage applied to the power generating element 1 does not increase. Therefore, the capacitance of the capacitance elements 108, 208 can be reduced. This reduces the "unusable charge" described with reference to FIG. 4 , i.e., (capacitance of the capacitance element) × (lower limit operating voltage of the constant voltage circuit), allowing more charge to be used. However, it should be noted that depending on the power conversion efficiency of the boost circuits 107, 207, a considerable amount of charge may be lost in the boost circuits 107, 207. Therefore, if the increase in the amount of usable charge due to the above effect is greater than the decrease in charge in the boost circuits 107, 207, the charge generated in the power generating element 1 can be used more efficiently.

[0127] 19 is a circuit block diagram of a batteryless multi-rotation encoder ENC4 according to embodiment 4. In embodiment 4, an example of a simple boost circuit using a capacitance element is shown.

[0128] Specifically, the semiconductor device SD4 of the batteryless multi-rotation encoder ENC4 of FIG. 19 differs from the semiconductor device SD1 of the batteryless multi-rotation encoder ENC1 of FIG. 1 in that it further includes other capacitance elements 109, 209 and variable voltage generators 110, 210.

[0129] One end of capacitance element 109 is connected to high-potential node 120 of capacitance element 102, and the other end of capacitance element 109 is connected to ground GND via variable voltage generator 110. That is, the series connection of capacitance element 109 and variable voltage generator 110 is connected in parallel to capacitance element 102. Similarly, one end of capacitance element 209 is connected to high-potential node 220 of capacitance element 202, and the other end of capacitance element 209 is connected to ground GND via variable voltage generator 210. That is, the series connection of capacitance element 209 and variable voltage generator 210 is connected in parallel to capacitance element 202.

[0130] The variable voltage generator 110 increases the output voltage when the boost signal Vup1 received from the digital processing circuit 6 becomes active (for example, high level). Similarly, the variable voltage generator 210 increases the output voltage when the boost signal Vup2 received from the digital processing circuit 6 becomes active (for example, high level).

[0131] 1, the same or corresponding parts are designated by the same reference numerals and description thereof will not be repeated. Note that capacitive elements 109, 209 and variable voltage generators 110, 210 in Fig. 19 can also be combined with semiconductor device SD2 of battery-less multi-rotation encoder ENC2 of embodiment 2 shown in Fig. 11.

[0132] [Operation of Batteryless Multi-Rotation Encoder] Fig. 20 is a timing chart showing an example of normal processing of the batteryless multi-rotation encoder ENC4 of Fig. 19. The timing chart of Fig. 20 corresponds to the timing chart of the first embodiment of Fig. 2, and therefore the same reference numerals as in Fig. 2 are used for corresponding parts.

[0133] As in the first embodiment, when a current pulse is generated in the power generating element 1, the path along which the current flows is selectively determined by the direction of the current pulse and the operation of the rectifier circuits 101 and 201. When the current flows in a direction that enables the rectifier circuit 101, charge is supplied to the capacitance elements 102 and 109, and the voltage Vpls1 of the high-potential side node 120 rises. At this time, the output voltage of the variable voltage generator 110 is maintained at the GND level or a low voltage.

[0134] At time t1, when the voltage Vpls1 of the high-potential side node 120 reaches the determination voltage VD, the voltage determination circuit 103 switches the determination signal Vdet1 from low to high, as in the case of embodiment 1. This causes the selection circuit 2 to supply the voltage Vpls1 to the constant voltage circuit 3, and the constant voltage circuit 3 generates the power supply voltage Vdig from the supplied voltage Vpls1.

[0135] When the power supply voltage Vdig reaches a specified voltage at time t2 and the reset signal RST is released, the digital processing circuit 6 starts a series of processes (read, update, write) in the same manner as in the first embodiment.

[0136] The digital processing circuit 6 switches the boost signal Vup1 from low to high at time t31, which is before time t4 at which the determination timing signal Vtm1 sent to the charge amount determination circuit 104 is switched from low to high. This increases the output voltage of the variable voltage generator 110, and this increase in output voltage increases the voltage Vpls1 of the high-potential side node 120, so that the amount of charge that can be processed by the digital processing circuit 6 can be increased.

[0137] At the next time t4, the digital processing circuit 6 switches the determination timing signal Vtm1 from low to high. In response to the determination timing signal Vtm1, the charge amount determination circuit 104 determines whether the charge amount corresponding to the voltage Vpls1 of the high-potential-side node 120 is equal to or greater than the determination value. As a result, if the charge amount corresponding to the voltage Vpls1 is equal to or greater than the determination value, the digital processing circuit 6 executes the write process and completes the series of processes. On the other hand, if the charge amount corresponding to the voltage Vpls1 is less than the determination value, the digital processing circuit 6 executes the interrupt process without writing the updated data to the non-volatile memory 7, as described with reference to FIG. 3 .

[0138] The above has been described in terms of the case where a current pulse flows in a direction that enables the rectifier circuit 101, but the operation of the semiconductor device SD4 is similar when a current pulse flows in a direction that enables the rectifier circuit 201.

[0139] In addition, although the above describes a case where the digital processing circuit 6 outputs the boost signal Vup1, thereby causing the variable voltage regulator 110 to switch the output voltage, a circuit other than the digital processing circuit 6 may also output the boost signal Vup1.

[0140] [Effects of the Fourth Embodiment] The following describes how much the amount of charge that can be processed can be increased by increasing the output voltage of the variable voltage generator 110. The following description also applies to the case where the output voltage of the variable voltage generator 210 is increased when charge is accumulated in the capacitive elements 202 and 209 as a result of the rectifier circuit 201 being enabled.

[0141] If the increase in the output voltage of the variable voltage generator 110 is ΔV, the electrostatic capacitance of the capacitive element 102 is C102, and the electrostatic capacitance of the capacitive element 109 is C109, then the increase ΔVpls1 in the voltage Vpls1 of the high potential side node 120 is expressed as follows: ΔVpls1=C109×ΔV / (C102+C109) (1) This increase ΔVpls1 in the voltage of the high potential side node 120 means that the charge available for processing by the digital processing circuit 6 has increased by ΔVpls1×(C102+C109).

[0142] [Configuration Example of Variable Voltage Devices 110, 210] Below, a configuration example of the variable voltage devices 110, 210 in Fig. 19 will be described. The circuit configuration shown below is merely an example and is not limited to this. Any circuit configuration may be used as long as it has the above-mentioned functions.

[0143] Fig. 21 is a circuit diagram showing an example of the configuration of the variable voltage generator 110 of Fig. 19. Fig. 21 also shows the capacitance elements 102 and 109 of Fig. 19. The variable voltage generator 210 has a similar configuration.

[0144] Specifically, the variable voltage generator 110 includes an NMOS transistor 370, a voltage buffer 371, and resistors 372 and 373. The output terminal of the voltage buffer 371 is connected to the high-potential node 120 of the capacitor 102 via a capacitor 109. As will be described later with reference to FIG. 22 , a voltage Vbuf, which is different from the voltage Vpls1 of the capacitor 102, is supplied to the power supply terminal of the voltage buffer 371. The input terminal of the voltage buffer 371 is connected to the high-potential node 120 via a resistor 372 and to ground GND via a resistor 373. Furthermore, an NMOS transistor 370 is connected in parallel with the resistor 373. An inverted signal ( / Vup1) of the boost signal Vup1 is input to the gate terminal of the NMOS transistor 370.

[0145] Fig. 22 is a diagram for explaining an example of a method for supplying voltage Vbuf to the power supply terminal of voltage buffer 371 in Fig. 21. As shown in Fig. 22, a capacitance element 402 is provided in addition to capacitance elements 102 and 202 connected to power generating element 1. A switch 380 is connected between high potential side node 220 of capacitance element 102 and high potential side node 420 of capacitance element 402, and a switch 381 is connected between high potential side node 220 of capacitance element 202 and high potential side node 420 of capacitance element 402. The low potential side nodes of capacitance elements 102, 202, and 402 are connected to ground GND.

[0146] When the digital processing circuit 6 executes a series of processes using the charge accumulated in the capacitance element 102, it transfers the residual charge remaining from the processes to the capacitance element 402 by turning on the corresponding switch 380 for a certain period after the series of processes are completed. Similarly, when the digital processing circuit 6 executes a series of processes using the charge accumulated in the capacitance element 202, it transfers the residual charge remaining from the processes to the capacitance element 402 by turning on the corresponding switch 381 for a certain period after the series of processes are completed. In the initial state, no charge exists in the capacitance element 402, but if continuous operation is performed, the charge can be held in the capacitance element 402. The residual charge can be reused by using the voltage Vbuf generated in the capacitance element 402 as the power supply voltage for the voltage buffer 371.

[0147] Note that the capacitance element 402 may be connected to the capacitance elements 109 and 209 via a switch instead of the capacitance elements 102 and 202, or may be connected to both the capacitance elements 102 and 202 and the capacitance elements 109 and 209 via a switch. Similarly, the semiconductor device SD3 in Fig. 17 may also be provided with a capacitance element 402 for accumulating residual charge that is configured to be temporarily connected to at least one of the capacitance elements 102 and 202 and the capacitance elements 108 and 208. In this case, the boost circuits 107 and 207 in Fig. 17 operate using the voltage of the capacitance element 402 as a power supply voltage.

[0148] According to the configuration of the variable voltage generator 110 described above, when the boost signal Vup1 is at a low level, the NMOS transistor 370 is turned on, which causes the input terminal of the voltage buffer 371 to be at ground potential and the low-potential node of the capacitance element 109 to be at ground level. In this case, the charge generated by the power generating element 1 is accumulated in the capacitance elements 102 and 109.

[0149] When the boost signal Vup1 goes high, the NMOS transistor 370 is turned off, causing the voltage at the input terminal of the voltage buffer 371 to rise to the divided voltage obtained by dividing the voltage of the capacitance element 102 by the resistance elements 372 and 373. As a result, the divided voltage obtained by dividing the voltage of the capacitance element 102 by the resistance elements 372 and 373 is added to the voltage of the capacitance element 109 via the voltage buffer 371.

[0150] Embodiment 5. [Configuration of a batteryless multi-rotation encoder] Fig. 23 is a circuit block diagram of a batteryless multi-rotation encoder ENC5 according to embodiment 5. Embodiment 5 is a modification of embodiment 4, and is characterized in that the variable voltage generators 110 and 210 are configured to switch the output voltage after power generation by the power generating element 1 has ended.

[0151] Specifically, the semiconductor device SD5 of the batteryless multi-rotation encoder ENC5 of FIG. 23 differs from the semiconductor device SD1 of the batteryless multi-rotation encoder ENC1 of FIG. 1 in that it further includes a current determination circuit 111 between the high potential side node 120 of the capacitance element 102 and the high potential side node 122 of the capacitance element 109, and further includes a current determination circuit 211 between the high potential side node 220 of the capacitance element 202 and the high potential side node 222 of the capacitance element 209.

[0152] The current determination circuit 111 determines whether or not a current flows between the high potential side node 120 of the capacitance element 102 and the high potential side node 122 of the capacitance element 109. After this current becomes zero, the current determination circuit 111 outputs a control signal to the variable voltage generator 110 so as to increase the output voltage of the variable voltage generator 110.

[0153] As an example, the current determination circuit 111 includes a resistive element 111A and a voltage comparator 111B. The resistive element 111A is connected between a high potential side node 120 of the capacitive element 102 and a high potential side node 122 of the capacitive element 109. The voltage comparator 111B compares the voltages generated across the resistive element 111A to determine whether the voltage generated across the resistive element 111A is zero. However, the configuration of the current determination circuit 111 is not limited to this configuration.

[0154] Similarly, current determination circuit 211 determines whether or not a current flows between high potential side node 220 of capacitance element 202 and high potential side node 222 of capacitance element 209. After this current becomes zero, current determination circuit 211 outputs a control signal to variable voltage generator 210 so as to increase the output voltage of variable voltage generator 210.

[0155] As an example, the current determination circuit 211 includes a resistive element 211A and a voltage comparator 211B. The resistive element 211A is connected between a high potential side node 220 of the capacitive element 202 and a high potential side node 222 of the capacitive element 209. The voltage comparator 211B compares the voltages generated across the resistive element 211A to determine whether the voltage generated across the resistive element 211A is zero. However, the configuration of the current determination circuit 211 is not limited to this configuration.

[0156] 23 is similar to that of FIG. 1, the same or corresponding parts are designated by the same reference numerals and description thereof will not be repeated. Note that capacitance elements 109, 209, variable voltage devices 110, 210, and current determination circuits 111, 211 in FIG. 23 can also be combined with semiconductor device SD2 of battery-less multi-rotation encoder ENC2 of embodiment 2 shown in FIG.

[0157] [Operation of Batteryless Multi-Rotation Encoder] FIG. 24 is a timing chart showing an example of normal processing of the batteryless multi-rotation encoder ENC5 of FIG.

[0158] The timing chart of Fig. 24 corresponds to the timing chart of Fig. 20 of the fourth embodiment, but differs from the timing chart of Fig. 20 in that an output signal indicating the determination result of current determination circuit 111 is used instead of boost signal Vup1 output from digital processing circuit 6. Since the other points in Fig. 24 are the same as those in Fig. 20, the same or corresponding parts are designated by the same reference numerals and description thereof will not be repeated.

[0159] If variable voltage devices 110 and 210 step up while power generating element 1 is generating power, the voltage applied to power generating element 1 increases, causing a reverse current to inhibit power generation. To prevent this, in embodiment 5, variable voltage devices 110 and 210 step up after power generation by power generating element 1 has finished. Specifically, current determination circuit 111 determines the end of power generation by power generating element 1 by detecting that the current flowing from high potential side node 120 of capacitance element 102 to high potential side node 122 of capacitance element 109 has become zero.

[0160] 24, current evaluation circuit 111 outputs a high-level signal when it detects a current flowing in the direction from high-potential side node 120 of capacitance element 102 to high-potential side node 122 of capacitance element 109. Current evaluation circuit 111 outputs a low-level signal when the current becomes zero. Variable voltage generator 110 increases the output voltage at time t31 when the output of current evaluation circuit 111 switches from high to low.

[0161] As described above, according to the batteryless multi-rotation encoder ENC5 of the fifth embodiment, the output voltages of the variable voltage generators 110 and 210 increase after the power generation of the power generating element 1 has finished. Therefore, it is possible to suppress an increase in the reverse current of the power generating element 1 caused by an increase in the voltage of the high-potential side nodes 120 and 220, and to increase the amount of effective charge that can be used for processing in the digital processing circuit 6, as in the fourth embodiment.

[0162] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of this application is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0163] 1 power generating element, 2 selection circuit, 3 constant voltage circuit, 4 POR circuit, 5 oscillation circuit, 6 digital processing circuit, 7 non-volatile memory circuit, 101, 201 rectifier circuit, 102, 108, 109, 202, 208, 209 capacitance element, 103, 203 voltage determination circuit, 104, 204 charge amount determination circuit, 105, 205 reference voltage generation circuit, 106, 206 peak determination circuit, 107, 207 boost circuit, 110, 210 variable voltage generator, 111, 211 current determination circuit, 120, 122, 220, 222 high potential side node, 130, 230 determination circuit, ENC1 to ENC5 batteryless multi-rotation encoder, GND ground, RST reset signal, SD1 to SD5 semiconductor device.

Claims

1. A semiconductor device that operates by a current pulse generated by a power generating element, a processing circuit that executes a series of processes using the current pulses; a determination circuit for determining whether the amount of power generated by the power generating element is sufficient; the determination circuit determines whether a first determination condition is satisfied before the start of the series of processes and while the power generating element is generating the current pulse, and determines whether a second determination condition is satisfied while the series of processes is being executed; The processing circuit starts the series of processes if the first determination condition is satisfied, and suspends the series of processes if the second determination condition is not satisfied.

2. the semiconductor device further includes a first capacitive element that stores the current pulse; 2. The semiconductor device according to claim 1, wherein said processing circuit executes said series of processes using a voltage at a high potential side node of said first capacitance element.

3. The semiconductor device includes: a first capacitive element; a second capacitive element that stores the current pulse; a booster circuit that boosts the voltage of the second capacitance element and outputs the boosted voltage to the first capacitance element; 2. The semiconductor device according to claim 1, wherein said processing circuit executes said series of processes using a voltage at a high potential side node of said first capacitance element.

4. the semiconductor device further includes a third capacitive element; the third capacitance element is configured to be temporarily connected to at least one of the first capacitance element and the second capacitance element after the series of processes is completed, thereby transferring residual charge of the at least one capacitance element to the third capacitance element; 4. The semiconductor device according to claim 3, wherein said booster circuit operates using the voltage of said third capacitance element as a power supply voltage.

5. The semiconductor device includes: a first capacitance element and a second capacitance element for storing the current pulse; a variable voltage generator connected between a low potential side node of the first capacitance element and ground, the output voltage of the variable voltage generator increases after the first determination condition is met and before the second determination condition is met; 2. The semiconductor device according to claim 1, wherein said processing circuit executes said series of processes using a voltage at a high potential side node of said first capacitance element.

6. a current determination circuit that determines whether or not a current flows between a high potential side node of the first capacitance element and a high potential side node of the second capacitance element; 6. The semiconductor device according to claim 5, wherein the output voltage of said variable voltage generator increases when said current determination circuit determines that a current flowing between a high potential side node of said first capacitance element and a high potential side node of said second capacitance element has become zero.

7. the semiconductor device further includes a third capacitive element; the third capacitance element is configured to be temporarily connected to at least one of the first capacitance element and the second capacitance element after the series of processes is completed, thereby transferring residual charge of the at least one capacitance element to the third capacitance element; 6. The semiconductor device according to claim 5, wherein said variable voltage generator operates using the voltage of said third capacitance element as a power supply voltage.

8. a constant voltage circuit that generates a constant power supply voltage from a voltage at a high potential side node of the first capacitance element when the first determination condition is satisfied; 8. The semiconductor device according to claim 2, wherein said processing circuit operates on said constant power supply voltage.

9. 3. The semiconductor device according to claim 2, wherein said first determination condition includes that a voltage at a high potential side node of said first capacitance element is equal to or greater than a first determination value.

10. 10. The semiconductor device according to claim 9, wherein said second determination condition includes that an amount of charge stored in said first capacitance element is equal to or greater than a second determination value.

11. 10. The semiconductor device according to claim 9, wherein said second determination condition includes that a peak value of a voltage at a high potential side node of said first capacitance element is equal to or greater than a second determination value.

12. 10. The semiconductor device according to claim 9, wherein said second determination condition includes a condition that a voltage at a high potential side node of said first capacitive element at least temporarily exceeds a second determination value.

13. the series of processes includes a first process and a second process that is executed after completion of the first process, the first determination value is based on an amount of power generation required to complete the first process, the second determination value is based on an amount of power generation required to complete the second process, 13. The semiconductor device according to claim 10, wherein the processing circuit does not execute the second process if the second determination condition is not satisfied after the first process is completed.

14. The semiconductor device further includes a nonvolatile memory, the first processing includes a processing of reading data from the nonvolatile memory and a processing of updating the read data, 14. The semiconductor device according to claim 13, wherein the second processing includes a processing of writing the updated data to the nonvolatile memory.

15. 15. The semiconductor device according to claim 14, wherein said processing circuit writes error information to said nonvolatile memory if said second determination condition is not satisfied after completion of said first processing.

16. 15. The semiconductor device according to claim 14, further comprising error detection bits at the beginning and end of the updated data written to the nonvolatile memory.

17. a plurality of power generating elements as the power generating elements arranged around a rotation axis with a phase angle shift; and the semiconductor device according to any one of claims 1 to 7 and 9 to 12, which operates by a current pulse generated by each of the plurality of power generating elements; A battery-less multi-rotation encoder, wherein each of the plurality of power generating elements includes a coil that generates power using electromagnetic induction.

18. the series of processes includes a process of counting the number of generated current pulses, 18. The batteryless multi-rotation encoder according to claim 17, wherein the processing circuit corrects the count number of the current pulses when the series of processes is interrupted.