Multilayer electronic component and mounting structure for multilayer electronic component

Abstract

A multilayer ceramic capacitor according to the present invention comprises: a laminate that has first and second surfaces that are opposite in the layering direction, third and fourth surfaces that are opposite in a first direction that is orthogonal to the layering direction, and fifth and sixth surfaces that are opposite in a second direction that is orthogonal to the layering direction and the first direction; and an external electrode that is provided on the fifth surface of the laminate. The first external electrode comprises: a base electrode layer that is provided on the fifth surface and is connected to an internal electrode of the laminate; an Sn-Cu diffusion layer that is provided on the base electrode layer and includes tin and copper; an Sn-Ni diffusion layer that is provided outside the Sn-Cu diffusion layer and includes tin and nickel; and an Ni plating layer that is provided on the Sn-Ni diffusion layer and includes nickel as a principal component. There is a gap at the interface between the base electrode layer and the Sn-Cu diffusion layer.

Description

Multilayer electronic component and mounting structure for multilayer electronic component

[0001] The present disclosure relates to a multilayer electronic component and a mounting structure for the multilayer electronic component.

[0002] In recent years, there has been a demand for improved reliability in multilayer ceramic capacitors for electronic components and in-vehicle applications.

[0003] For example, in the multilayer ceramic capacitor described in Patent Document 1, internal electrode layers are arranged inside a laminated chip having a dielectric layer containing a ceramic material that functions as a dielectric. The internal electrode layers are exposed on the surface of the laminated chip, and external electrodes are arranged so as to be joined to the internal electrodes. The surfaces of the external electrodes are provided with plating layers mainly composed of metals such as copper (Cu), nickel (Ni), and tin (Sn).

[0004] Patent Document 2 describes that hydrogen generated by a chemical reaction during the plating layer formation process is absorbed into the internal electrodes, and the absorbed hydrogen gradually reduces the dielectric layer around the internal electrodes, deteriorating the insulation resistance.

[0005] JP 2022-119088 A JP 1-80011 A

[0006] An object of the present disclosure is to suppress deterioration of insulation resistance in a multilayer electronic component.

[0007] The multilayer electronic component of the present disclosure comprises a laminate having a first surface and a second surface opposed to each other in a stacking direction, a third surface and a fourth surface opposed to each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface opposed to each other in a second direction perpendicular to the stacking direction and the first direction, a first external electrode disposed on the fifth surface of the laminate, and a second external electrode disposed on the sixth surface of the laminate. The laminate comprises an inner dielectric layer, and an internal electrode laminated on the inner dielectric layer in the stacking direction and having an end located on the fifth surface or the sixth surface. The first external electrode comprises a base electrode layer disposed on the fifth surface and connected to the internal electrode, a Sn—Cu diffusion layer disposed on the base electrode layer and containing tin and copper, a Sn—Ni diffusion layer disposed outside the Sn—Cu diffusion layer and containing tin and nickel, and a Ni plating layer disposed on the Sn—Ni diffusion layer and containing nickel as a main component. A gap exists at the interface between the base electrode layer and the Sn—Cu diffusion layer.

[0008] According to the present disclosure, it is possible to prevent deterioration of insulation resistance in a multilayer electronic component.

[0009] 1A and 1B are perspective views of a multilayer ceramic capacitor according to a first embodiment of the present disclosure; a cross-sectional view taken along line II-II in FIG. 1; a cross-sectional view taken along line III-III in FIG. 1; an exploded perspective view of an inner layer portion according to a first embodiment of the present disclosure; an enlarged view of region R in FIG. 2; a perspective view of a multilayer ceramic capacitor according to a second embodiment of the present disclosure; a cross-sectional view taken along line VII-VII in FIG. 6; a cross-sectional view taken along line VIII-VIII in FIG. 6; a cross-sectional view taken along line IX-IX in FIG. 8; a cross-sectional view taken along line X-X in FIG. 8; an enlarged view of region R1 in FIG. 7; an enlarged view of region R2 in FIG. 8; a perspective view of a mounting structure of a multilayer ceramic capacitor according to a second embodiment of the present disclosure; a cross-sectional view taken along line XIV-XIV in FIG. 13; a cross-sectional view taken along line XV-XV in FIG. 13; a flowchart for explaining a method for manufacturing a multilayer ceramic capacitor according to a first embodiment of the present disclosure;

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0011] Note that each embodiment exemplifies an embodiment of the present disclosure, and the present disclosure is not limited to the content of the embodiment. Furthermore, it is possible to combine the contents described in different embodiments, and the implementation content in such cases is also included in the present disclosure. Furthermore, the drawings are intended to facilitate understanding of the specification and may be drawn schematically, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0012] 1. Multilayer Ceramic Capacitor (First Embodiment) A multilayer ceramic capacitor according to a first embodiment of this disclosure will be described.

[0013] Fig. 1 is a perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present disclosure, Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1, and Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1.

[0014] The drawings may show the stacking direction X, width direction Y, and length direction Z of the multilayer ceramic capacitor 10, and these directions may be referred to in the following description. The width direction Y of this embodiment is an example of a first direction according to the present disclosure, and the length direction Z is an example of a second direction according to the present disclosure. The width direction Y of this embodiment may be an example of the second direction according to the present disclosure, and the length direction Z may be an example of the second direction according to the present disclosure.

[0015] 1 , the multilayer ceramic capacitor 10 has a laminate 12, a first external electrode 30a, and a second external electrode 30b. In the following description, when there is no need to particularly distinguish between the first external electrode 30a and the second external electrode 30b, one of these may be simply referred to as the external electrode 30. The multilayer ceramic capacitor 10 according to this embodiment is an example of a multilayer electronic component according to the present disclosure.

[0016] The laminate 12 of this embodiment has a rectangular parallelepiped or approximately rectangular parallelepiped shape as a whole. The laminate 12 has a first surface 12a and a second surface 12b that face each other in the stacking direction X, a third surface 12c and a fourth surface 12d that face each other in the width direction Y, and a fifth surface 12e and a sixth surface 12f that face each other in the length direction Z. In this embodiment, the stacking direction X, the width direction Y, and the length direction Z are perpendicular to each other. The laminate 12 preferably has rounded corners and ridges. A corner refers to a portion where three adjacent surfaces of the laminate 12 intersect. A ridge refers to a portion where two adjacent surfaces of the laminate 12 intersect. Concave and recessed portions may be formed on some or all of the first surface 12a and the second surface 12b, the third surface 12c and the fourth surface 12d, and the fifth surface 12e and the sixth surface 12f.

[0017] 2 and 3, the laminate 12 includes an inner layer portion 13, a first outer layer portion 16a, and a second outer layer portion 16b. In the following description, the first outer layer portion 16a and the second outer layer portion 16b may be simply referred to as the outer layer portion 16.

[0018] (Inner Layer Portion 13) The inner layer portion 13 has a plurality of internal electrodes 13a and a plurality of inner dielectric layers 14a. The inner layer portion 13 is a portion located between the internal electrode 13a among the plurality of internal electrodes 13a that is closest to the first outer layer portion 16a and the internal electrode 13a among the plurality of internal electrodes 13a that is closest to the second outer layer portion 16b. In other words, the inner layer portion 13 is a portion located between the internal electrode 13a adjacent to the first outer layer portion 16a and the internal electrode 13a adjacent to the second outer layer portion 16b.

[0019] The plurality of inner dielectric layers 14a are stacked in a stacking direction X. The material of each inner dielectric layer 14a is arbitrary. For example, barium titanate (BaTiO ３ The dielectric ceramics containing BaTiO as a main component can be used as the material of the inner dielectric layer 14a. In particular, the material of the inner dielectric layer 14a is BaTiO ３ However, the perovskite-type compound may have a plurality of crystal grains containing BaTiO ３ Instead of calcium titanate (CaTiO３ ), strontium titanate (SrTiO ３ ), calcium zirconate (CaZrO ３ Dielectric ceramics containing other compounds as the main component, such as BaTiO, may also be used as the material for the inner dielectric layer 14a. ３ , CaTiO ３ , SrTiO ３ , CaZrO ３ The material for the inner dielectric layer 14 a may be a material obtained by adding, as a secondary component, compounds such as manganese (Mn) compounds, iron (Fe) compounds, chromium (Cr) compounds, cobalt (Co) compounds, or nickel (Ni) compounds in a content range less than that of the main component to the main component such as the above. The thickness of the inner dielectric layer 14 a, i.e., the dimension in the stacking direction X, is arbitrary, but is preferably, for example, 10.0 μm or less.

[0020] Each internal electrode 13a is disposed between two adjacent dielectric layers in the stacking direction X among the plurality of dielectric layers included in the laminate 12. The internal electrode 13a may be disposed between two adjacent internal dielectric layers 14a in the stacking direction X among the plurality of internal dielectric layers 14a. The internal electrode 13a may be disposed between an internal dielectric layer 14a disposed adjacent to each other in the stacking direction X and an outer dielectric layer 17a of the outer layer portion 16. The internal dielectric layer 14a is disposed between the two internal electrodes 13a adjacent to each other in the stacking direction X. The internal electrode 13a is disposed in contact with the internal dielectric layer 14a.

[0021] The internal electrode 13a in this embodiment is a plate-shaped electrode. The internal electrode 13a extends in the longitudinal direction Z. The internal electrode 13a has a first end exposed on either the fifth surface 12e or the sixth surface 12f, and a second end located inside the laminate 12.

[0022] 2 , in this embodiment, each internal electrode 13 a is exposed on either the fifth surface 12 e or the sixth surface 12 f of the laminate 12. The multiple internal electrodes 13 a include internal electrodes 13 a that are exposed on the fifth surface 12 e but not on the sixth surface 12 f, and internal electrodes 13 a that are exposed on the sixth surface 12 f but not on the fifth surface 12 e. The internal electrodes 13 a that are exposed on the fifth surface 12 e but not on the sixth surface 12 f and the internal electrodes 13 a that are exposed on the sixth surface 12 f but not on the fifth surface 12 e are arranged alternately in the stacking direction X.

[0023] FIG. 4 is an exploded perspective view of the inner layer portion 13. Referring to FIG. 4, each internal electrode 13a has a counter electrode portion 15a and an extraction electrode portion 15b. The counter electrode portion 15a is a portion of the internal electrode 13a that faces another adjacent internal electrode 13a in the stacking direction X. The extraction electrode portion 15b is a portion of the internal electrode 13a other than the counter electrode portion 15a. The counter electrode portions 15a of two adjacent internal electrodes 13a in the stacking direction X face each other with the inner dielectric layer 14a interposed therebetween, thereby forming a capacitance. Furthermore, each extraction electrode portion 15b is exposed on either the fifth surface 12e or the sixth surface 12f.

[0024] The shape of the internal electrode 13a is not particularly limited, but is preferably rectangular when viewed from the stacking direction X. The corners of the counter electrode portion 15a may be chamfered or rounded, and the corners of the extraction electrode portion 15b may be chamfered or rounded.

[0025] The internal electrode 13a preferably has a uniform thickness along the width direction Y, i.e., a dimension in the stacking direction X. The thickness of the end portion of the internal electrode 13a in the width direction Y may be thicker than the thickness of the central portion of the internal electrode 13a in the width direction Y.

[0026] In this embodiment, the main component of the internal electrode 13a is copper (Cu). However, the main component of the internal electrode 13a is optional, and other metals such as Ni, palladium (Pd), or silver (Ag) may be used instead of Cu. The main component of the internal electrode 13a may also be an alloy of Ni, Pd, Ag, Cu, or the like with other metals.

[0027] The thickness of the internal electrode 13a is not limited, but is preferably, for example, 0.2 μm or more and 2.0 μm or less.

[0028] 2 and 3, the first outer layer portion 16a and the second outer layer portion 16b are arranged with the inner layer portion 13 sandwiched between them in the stacking direction X. The first outer layer portion 16a is arranged on one side of the inner layer portion 13 in the stacking direction X (the upper side in FIGS. 2 and 3). In other words, the first outer layer portion 16a is arranged on the first surface 12a side of the inner layer portion 13. The second outer layer portion 16b is arranged on the other side of the stacking direction X (the lower side in FIGS. 2 and 3). In other words, the second outer layer portion 16b is arranged on the second surface 12b side of the inner layer portion 13.

[0029] The outer layer portion 16 has a plurality of outer dielectric layers 17a. The plurality of outer dielectric layers 17a are stacked in the stacking direction X. The material of each outer dielectric layer 17a is arbitrary. For example, BaTiO ３ The outer dielectric layer 17a may be made of a dielectric ceramic containing BaTiO as a main component. ３ Instead of CaTiO ３ , SrTiO ３ , CaZrO ３ Alternatively, a dielectric ceramic containing other compounds as the main component may be used as the material for the outer dielectric layer 17a. ３ , CaTiO ３ , SrTiO ３ , CaZrO ３The material for the outer dielectric layer 17a may be formed from a main component different from that for the inner dielectric layer 14a.

[0030] Although not shown, insulating layers may be disposed on the third surface 12c and the fourth surface 12d of the laminate 12. The insulating layers can prevent moisture from penetrating the interface between the internal electrode 13a and the inner dielectric layer 14a, the interface between the internal electrode 13a and the outer dielectric layer 17a, and into the interior of the laminate 12. Furthermore, it is preferable that the insulating layers have the same or similar components as the inner dielectric layer 14a or the outer dielectric layer 17a. When the insulating layer has the same or similar components as the inner dielectric layer 14a, the adhesion between the insulating layer and the inner dielectric layer 14a is improved. When the insulating layer has the same or similar components as the outer dielectric layer 17a, the adhesion between the insulating layer and the outer dielectric layer 17a is improved.

[0031] The insulating layer may also be arranged so as to be bonded to the internal electrode 13 a. In this case, the surface of the insulating layer not bonded to the internal electrode 13 a becomes the third surface 12 c and the fourth surface 12 d. In other words, when the insulating layer is bonded to the internal electrode 13 a, the surface of the insulating layer arranged on the opposite side to the internal electrode 13 a constitutes the third surface 12 c and the fourth surface 12 d of the laminate 12.

[0032] The insulating layer preferably includes an inner layer that is the innermost layer in the width direction Y and an outer layer that is the outermost layer in the width direction Y. Incidentally, the provision of the inner layer and the outer layer makes it possible to easily confirm the boundary by observation using an optical microscope due to the difference in sinterability between the inner layer and the outer layer. In other words, there is a boundary between the inner layer and the outer layer. There may be multiple boundaries.

[0033] The insulating layer is not limited to a two-layer structure, and may have a three-layer or more structure. When the insulating layer includes three or more layers, the layer disposed on the innermost side in the width direction Y is referred to as the inner layer, and the layer disposed on the outermost side in the width direction Y is referred to as the outer layer.

[0034] A step layer 19 is disposed on the same plane as the internal electrodes 13a. Without the step layer 19, a difference in thickness would occur between the portion where the internal electrodes 13a are disposed and the portion where the internal electrodes 13a are not disposed, which could result in distortion during pressing or other processes during the manufacturing process of the multilayer ceramic capacitor 10, as described below, resulting in structural defects. In contrast, in this embodiment, the step layer 19 can fill in the step corresponding to the thickness of the internal electrodes 13a in the stacking direction X, thereby alleviating distortion during pressing or other processes during the manufacturing process of the multilayer ceramic capacitor 10 and suppressing structural defects. The step layer 19 preferably has the same or substantially the same thickness as the internal electrodes 13a disposed on the same plane. The step layer 19 preferably contains the same or substantially the same components as the inner dielectric layer 14a.

[0035] (External Electrode 30) The first external electrode 30a is disposed on the fifth surface 12e of the laminate 12. In this embodiment, the first external electrode 30a is disposed on the first surface 12a, the second surface 12b, the third surface 12c, the fourth surface 12d, and the fifth surface 12e. The first external electrode 30a may be disposed only on the fifth surface 12e of the laminate 12, but is preferably disposed continuously on the fifth surface 12e, the first surface 12a, and the second surface 12b. It is more preferable that the first external electrode 30a is also disposed on the third surface 12c and the fourth surface 12d. The first external electrode 30a is joined to the internal electrode 13a exposed on the fifth surface 12e of the laminate 12. As a result, the first external electrode 30 a is electrically connected to the internal electrode 13 a disposed on the fifth surface 12 e of the laminate 12 .

[0036] The second external electrode 30b is disposed on the sixth surface 12f of the laminate 12. In this embodiment, the first external electrode 30a is disposed on the first surface 12a, the second surface 12b, the third surface 12c, the fourth surface 12d, and the sixth surface 12f. The second external electrode 30b may be disposed only on the sixth surface 12f of the laminate 12, but is preferably disposed continuously on the sixth surface 12f, the first surface 12a, and the second surface 12b. It is more preferable that the second external electrode 30b is also disposed on the third surface 12c and the fourth surface 12d. The second external electrode 30b is bonded to the internal electrode 13a exposed on the sixth surface 12f of the laminate 12. As a result, the second external electrode 30b is electrically connected to the internal electrode 13a disposed on the sixth surface 12f of the laminate 12.

[0037] Fig. 5 is an enlarged view of region R in Fig. 2. Fig. 5 shows an enlarged view of a portion of the first external electrode 30a, but the second external electrode 30b has a similar configuration to the first external electrode 30a.

[0038] As shown in Figures 2, 3, and 5, the external electrode 30 comprises a base electrode layer 31, a Sn-Cu diffusion layer 32 arranged to cover the base electrode layer 31, a Sn-Ni diffusion layer 33, a Ni plating layer 34, and a Sn plating layer 35.

[0039] The base electrode layer 31 of the first external electrode 30a is made of a baking layer. The baking layer contains a glass component and a metal. The glass component contained in the baking layer contains at least one selected from boron (B), silicon (Si), barium (Ba), magnesium (Mg), aluminum (Al), and lithium (Li). In this embodiment, the glass component contained in the baking layer is silicon dioxide (SiO ２ ) to which at least one element selected from B, Ba, Mg, Al, and Li is added. The metal contained in the baking layer includes Cu.

[0040] The base electrode layer 31 of the first external electrode 30a is disposed on the fifth surface 12e side of the laminate 12. The base electrode layer 31 of the first external electrode 30a in this embodiment is disposed continuously on the first surface 12a, the second surface 12b, the third surface 12c, the fourth surface 12d, and the fifth surface 12e of the laminate 12. The base electrode layer 31 of the first external electrode 30a is electrically connected to the internal electrode 13a exposed on the fifth surface 12e.

[0041] The base electrode layer 31 of the second external electrode 30b is disposed on the sixth surface 12f side of the laminate 12. In this embodiment, the base electrode layer 31 of the second external electrode 30b is disposed continuously on the first surface 12a, the second surface 12b, the third surface 12c, the fourth surface 12d, and the sixth surface 12f of the laminate 12. The base electrode layer 31 of the first external electrode 30a is electrically connected to the internal electrode 13a exposed on the sixth surface 12f.

[0042] The Sn—Cu diffusion layer 32 is disposed on the base electrode layer 31. In other words, the Sn—Cu diffusion layer 32 is disposed so as to cover the base electrode layer 31. By disposing the Sn—Cu diffusion layer 32 so as to cover the base electrode layer 31, it is possible to suppress the penetration of hydrogen into the laminate 12, and therefore to suppress deterioration of the insulation resistance.

[0043] The Sn—Cu diffusion layer 32 contains tin (Sn) and copper (Cu). More specifically, in the Sn—Cu diffusion layer 32, Cu is diffused into Sn. The Sn content in the Sn—Cu diffusion layer 32 of this embodiment is higher than the Cu content in the Sn—Cu diffusion layer 32. The Sn—Cu diffusion layer 32 of this embodiment is a region with a Cu content of 10% or more. Specifically, a cross section of the external electrode 30 including the lamination direction X and the length direction Z (for example, a cross section obtained by polishing the multilayer ceramic capacitor 10 in the width direction Y to one-half its dimension in the width direction Y) is subjected to linear analysis at a magnification of 10,000 times using a JEOL Scanning Electron Microscope (SEM, model number: JSM-7800F). The X-ray spectra of Cu and Sn at this time were measured, and the ratio of Cu to Sn was calculated from the intensity of the measured spectrum. The region where the Cu content was 10% or more was determined to be the Sn—Cu diffusion layer 32 .

[0044] As shown in FIG. 5 , a void P is disposed at the interface between the base electrode layer 31 and the Sn—Cu diffusion layer 32. The void P disposed at the interface between the base electrode layer 31 and the Sn—Cu diffusion layer 32 means that the void P is in contact with the base electrode layer 31 and the Sn—Cu diffusion layer 32. The void P disposed at the interface between the base electrode layer 31 and the Sn—Cu diffusion layer 32 can trap moisture within the void P, thereby improving moisture resistance reliability. Furthermore, the porosity of the void P is preferably 0.1% or more and 2.0% or less, and more preferably 0.4% or more and 0.6% or less. By setting the void P within the above range, moisture can be sufficiently trapped in the void P, and a decrease in mechanical strength due to the void P can be suppressed.

[0045] The porosity is calculated by binarizing the metal portions and void portions in an image obtained by measuring a cross section including the stacking direction X and the length direction Z (for example, a cross section obtained when the multilayer ceramic capacitor 10 is polished in the width direction Y to 1 / 2 of its dimension in the width direction Y) using a JEOL Ltd. scanning electron microscope (SEM, model number: JSM-7800F) at a magnification of 7000 times, using image processing software (for example, GIMP). For example, in a field of view including the interface between the base electrode layer 31 and the Sn—Cu diffusion layer 32, the ratio of the area occupied by voids P to the area occupied by the base electrode layer 31 and the Sn—Cu diffusion layer 32 is calculated as the porosity.

[0046] The thickness of the Sn--Cu diffusion layer 32 is preferably 0.1 μm or more and 0.5 μm or less.

[0047] The Sn—Ni diffusion layer 33 of this embodiment is disposed outside the Sn—Cu diffusion layer 32. In other words, the Sn—Ni diffusion layer 33 is disposed so as to cover the Sn—Cu diffusion layer 32.

[0048] The Sn—Ni diffusion layer 33 contains tin (Sn) and nickel (Ni). More specifically, in the Sn—Ni diffusion layer 33, Ni is diffused into Sn. The Sn content in the Sn—Ni diffusion layer 33 of this embodiment is higher than the Ni content in the Sn—Ni diffusion layer 33 itself. The Sn—Ni diffusion layer 33 of this embodiment is a region with a Ni content of 10% or more. Specifically, a cross section of the external electrode 30 including the stacking direction X and the length direction Z (for example, a cross section obtained by polishing the multilayer ceramic capacitor 10 in the width direction Y to half its dimension in the width direction Y) is subjected to linear analysis at a magnification of 10,000 times using a JEOL SEM. X-ray spectra of Ni and Sn at this time are measured, and the ratio of Ni to Sn is calculated from the intensity of the measured spectrum. The region with a Ni content of 10% or more is defined as the Sn—Ni diffusion layer 33.

[0049] The thickness of the Sn—Cu diffusion layer 32 is greater than the thickness of the Sn—Ni diffusion layer 33. By providing a thicker Sn—Cu diffusion layer 32, which has a greater stress relaxation effect than the Sn—Ni diffusion layer 33, the mechanical strength can be improved.

[0050] An intermediate Sn plating layer 36 having an Sn content of 90% or more is disposed between the Sn—Cu diffusion layer 32 and the Sn—Ni diffusion layer 33. The thickness of the intermediate Sn plating layer 36 is preferably 1.0 μm or more and 5.0 μm or less. By making the thickness of the intermediate Sn plating layer 36 1.0 μm or more and 5.0 μm or less, the intermediate Sn plating layer 36 can effectively function as a barrier layer that prevents moisture from penetrating.

[0051] The Ni plating layer 34 is disposed on the Sn—Ni diffusion layer 33. In other words, the Ni plating layer 34 is disposed so as to cover the Sn—Ni diffusion layer 33. The main component of the Ni plating layer 34 is Ni. In the Ni plating layer 34 of this embodiment, the Ni content is 90% or more.

[0052] The Sn plating layer 35 is disposed on the Ni plating layer 34. In other words, the Sn plating layer 35 is disposed so as to cover the Ni plating layer 34. In yet other words, the Sn plating layer 35 is the outermost layer of the external electrode 30. The main component of the Sn plating layer 35 is Sn. In the Sn plating layer 35 of this embodiment, the Sn content is 90% or more.

[0053] (Effects) The multilayer ceramic capacitor 10 according to this embodiment can provide the following effects.

[0054] When voids P are disposed at the interface between the base electrode layer 31 and the Sn—Cu diffusion layer 32, moisture can be trapped within the voids P, thereby suppressing deterioration of the insulation resistance.

[0055] By setting the porosity of the voids P to 0.1% or more and 2.0% or less, and further 0.4% or more and 0.6% or less, moisture can be sufficiently trapped in the voids P and the reduction in mechanical strength due to the voids P can be minimized.

[0056] The thickness of the Sn—Cu diffusion layer 32 is greater than the thickness of the Sn—Ni diffusion layer 33. By providing a thicker Sn—Cu diffusion layer 32, which has a greater stress relaxation effect than the Sn—Ni diffusion layer 33, the mechanical strength can be improved.

[0057] An intermediate Sn plating layer 36 having an Sn content of 90% or more is disposed between the Sn—Cu diffusion layer 32 and the Sn—Ni diffusion layer 33. This allows the intermediate Sn plating layer 36 to function as a barrier layer that prevents moisture from penetrating, thereby suppressing deterioration of the insulation resistance of the multilayer ceramic capacitor 100.

[0058] Second Embodiment A multilayer ceramic capacitor according to a second embodiment of this disclosure will be described below. The multilayer ceramic capacitor according to the second embodiment has the same configuration as the multilayer ceramic capacitor according to the first embodiment, except for the shape and arrangement of the internal electrodes and the number and configuration of the external electrodes. In the second embodiment, components that are the same as or similar to those in the first embodiment are designated by the same or similar reference numerals, and detailed descriptions thereof will be omitted.

[0059] Fig. 6 is a perspective view of the multilayer ceramic capacitor 110 according to this embodiment. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 6. Fig. 8 is a cross-sectional view taken along line VIII-VIII in Fig. 6.

[0060] 6 , the multilayer ceramic capacitor 110 of this embodiment includes a laminate 112, a first external electrode 130a, a second external electrode 130b, a third external electrode 130c, and a fourth external electrode 130d. In the following description, when there is no need to particularly distinguish between the four external electrodes 130a, 130b, 130c, and 130d, one of the four external electrodes 130a, 130b, 130c, and 130d may be simply referred to as the external electrode 130. The multilayer ceramic capacitor 110 of this embodiment is an example of a multilayer electronic component according to the present disclosure.

[0061] 7, 8, 9, and 10, the internal electrodes of this embodiment include a first internal electrode 113a having an end portion located on the fifth surface 112e and an end portion located on the sixth surface 112f, and a second internal electrode 113b having an end portion located on the third surface 112c and an end portion located on the fourth surface 112d. As shown in FIG. 9, the first internal electrode 113a has a counter electrode portion 115a and two lead electrode portions 115b. Each lead electrode portion 115b is exposed on the fifth surface 112e or the sixth surface 112f. As shown in FIG. 10, the second internal electrode 113b has a counter electrode portion 115c and two lead electrode portions 115d. Each lead electrode portion 115d is exposed on the third surface 112c or the fourth surface 112d. 9, the extension electrode portion 115b and the counter electrode portion 115a have approximately the same dimension in the width direction Y, but the dimension in the width direction Y of the extension electrode portion 115b may be narrower toward the nearest one of the fifth surface 112e and the sixth surface 112f. The first internal electrode 113a and the second internal electrode 113b are arranged in the stacking direction X, sandwiching the inner dielectric layer 14a therebetween.

[0062] The external electrodes 130 are arranged on each of the four sides of the laminate 112 when viewed along the stacking direction X. The first external electrode 130a and the second external electrode 130b are arranged to cover a portion of the first surface 112a, a portion of the second surface 112b, a portion of the third surface 112c and the fourth surface 112d, and the fifth surface 112e or the sixth surface 112f of the laminate 112. The first external electrode 130a and the second external electrode 130b are electrically connected to the first internal electrode 113a shown in FIG. 9. The third external electrode 130c and the fourth external electrode 130d are arranged to cover a portion of the first surface 112a, a portion of the second surface 112b, and the third surface 112c or the fourth surface 112d of the laminate 112. The third external electrode 130c and the fourth external electrode 130d are electrically connected to the second internal electrode 113b shown in FIG.

[0063] The external electrode 130 has a configuration similar to that of the external electrode 30 according to the first embodiment. As shown in Figures 7, 8, 9, and 10, the external electrode 130 includes a base electrode layer 31, a Sn-Cu diffusion layer 32 arranged so as to cover the base electrode layer, a Sn-Ni diffusion layer 33 arranged outside the Sn-Cu diffusion layer 32, a Ni plating layer 34 arranged on the Sn-Ni diffusion layer 33, and a Sn plating layer 35. The base electrode layers 31 of the first external electrode 130a and the second external electrode 130b are an example of a base electrode layer according to the present disclosure, and the base electrode layers 31 of the third external electrode 130c and the fourth external electrode 130d are an example of a second base electrode layer according to the present disclosure. The Sn—Cu diffusion layer 32 of the first external electrode 130 a and the second external electrode 130 b is an example of a Sn—Cu diffusion layer according to the present disclosure, the Sn—Cu diffusion layer 32 of the third external electrode 130 c and the fourth external electrode 130 d is an example of a second Sn—Cu diffusion layer according to the present disclosure, the Sn—Ni diffusion layer 33 of the first external electrode 130 a and the second external electrode 130 b is an example of a Sn—Ni diffusion layer according to the present disclosure, and the Sn—Ni diffusion layer 33 of the third external electrode 130 c and the fourth external electrode 130 d is an example of a second Sn—Ni diffusion layer according to the present disclosure. The Ni plating layer 34 of the first external electrode 130a and the second external electrode 130b is an example of a Ni plating layer according to the present disclosure, the Ni plating layer 34 of the third external electrode 130c and the fourth external electrode 130d is an example of a second Ni plating layer according to the present disclosure, the Sn plating layer 35 of the first external electrode 130a and the second external electrode 130b is an example of a Sn plating layer according to the present disclosure, and the Sn plating layer 35 of the third external electrode 130c and the fourth external electrode 130d is an example of a second Sn plating layer according to the present disclosure.

[0064] 11 and 12 , a void P is disposed at the interface between the base electrode layer 31 and the Sn—Cu diffusion layer 32. Disposing a void P at the interface between the base electrode layer 31 and the Sn—Cu diffusion layer 32 means that the void P is in contact with the base electrode layer 31 and the Sn—Cu diffusion layer 32. The void P between the first external electrode 130 a and the second external electrode 130 b is an example of a void according to the present disclosure, and the void P between the third external electrode 130 c and the fourth external electrode 130 d is an example of a second void according to the present disclosure.

[0065] Fig. 13 is a perspective view showing a mounting structure of a multilayer electronic component according to this embodiment. Fig. 14 is a cross-sectional view taken along line XIV-XIV in Fig. 13. Fig. 15 is a cross-sectional view taken along line XV-XV in Fig. 13.

[0066] 13 to 15, a multilayer ceramic capacitor mounting structure 210 according to this embodiment includes the multilayer ceramic capacitor 110 according to this embodiment and a mounting substrate 70. The mounting substrate 70 includes a core material 72 of the substrate, and conductor lands (connecting conductors) 74 arranged on a substrate-side mounting surface 72a of the core material 72 of the substrate.

[0067] The first conductor land 74a is electrically connected to and mechanically bonded to the first external electrode 130a of the multilayer ceramic capacitor 110 by a bonding material 76. The second conductor land 74b is electrically connected to and mechanically bonded to the second external electrode 130b of the multilayer ceramic capacitor 110 by a bonding material 76. The third conductor land 74c is electrically connected to and mechanically bonded to the third external electrode 130c of the multilayer ceramic capacitor 110 by a bonding material 76. The fourth conductor land 74d is electrically connected to and mechanically bonded to the fourth external electrode 130d of the multilayer ceramic capacitor 110 by a bonding material 76.

[0068] The conductor land 74 may be provided on the main surface of the core material 72 of the substrate opposite to the substrate-side mounting surface 72a.

[0069] The material of the conductor lands 74 is not particularly limited, but may be, for example, a metal such as Cu, Au, Pd, or Pt. The thickness of the conductor lands 74, i.e., the dimension in the stacking direction X, is not particularly limited, but is preferably, for example, 20 μm or more and 200 μm or less. The bonding material 76 may be, for example, a high-heat-resistant epoxy adhesive or solder.

[0070] In the above description, the mounting substrate 70 corresponds to the mounting substrate of the present disclosure. However, the connecting conductor of the present disclosure is not limited to a so-called land or other conductor that is provided between the multilayer electronic component 110 and the mounting substrate 70 and can electrically connect the two, and is not limited to other uses, functions, shapes, names, etc.

[0071] In this embodiment, each of the four external electrodes 130a, 130b, 130c, and 130d has the above-described configuration, i.e., a configuration similar to that of the external electrode 30 according to the first embodiment, but is not limited to this. Two of the four external electrodes 130a, 130b, 130c, and 130d that are arranged in opposing positions may have the above-described configuration. Only the first external electrode 130a and the second external electrode 130b may have the above-described configuration, or only the third external electrode 130c and the fourth external electrode 130d may have the above-described configuration.

[0072] In the multilayer ceramic capacitor 110 of the second embodiment, if the configuration of the external electrodes 30 of the multilayer ceramic capacitor 10 according to the first embodiment is applied to the external electrode 130 to which a positive potential is applied, among the four external electrodes 130a, 130b, 130c, and 130d, the same effects as those of the multilayer ceramic capacitor 10 according to the first embodiment can be achieved. Also, if the configuration of the external electrodes 30 of the multilayer ceramic capacitor 10 according to the first embodiment is applied to the first external electrode 130a and the second external electrode 130b, all of the four external electrodes 130a, 130b, 130c, and 130d, the same effects as those of the multilayer ceramic capacitor 10 according to the first embodiment can be achieved.

[0073] 2. Manufacturing Method of Multilayer Ceramic Capacitor A manufacturing method of a multilayer ceramic capacitor will be described below with reference to FIG. 16. FIG. 16 is a flowchart for explaining a manufacturing method of a multilayer ceramic capacitor. In the following description, a manufacturing method of the multilayer ceramic capacitor 10 according to the first embodiment will be described as an example. The multilayer ceramic capacitor 110 according to the second embodiment can be manufactured by the same manufacturing method as the manufacturing method of the multilayer ceramic capacitor 10 according to the first embodiment.

[0074] In step S1, a dielectric sheet, a conductive paste for the internal electrodes, and a conductive paste for the external electrodes are prepared. The dielectric sheet, the conductive paste for the internal electrodes, and the conductive paste for the external electrodes each contain a binder and a solvent.

[0075] In step S2, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet, thereby forming a dielectric sheet for the internal layer portion on which the internal electrode pattern of the internal layer portion 13 is printed. Printing the conductive paste for the internal electrodes on the dielectric sheet may be performed by, for example, screen printing or gravure printing.

[0076] In step S3, the dielectric sheets and the dielectric sheets for the internal electrodes are stacked and pressed in the stacking direction by, for example, a hydrostatic press to form a laminated block.

[0077] In step S4, the laminated block is cut into laminated chips of a predetermined size, after which the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0078] In step S5, the stacked chips are fired to form the stacked body 12 according to this embodiment.

[0079] In step S6, a conductive paste for the external electrodes containing a glass component and Cu is applied to the fifth surface 12 e and the sixth surface 12 f by, for example, a dipping method or a method in which the conductive paste is applied by extruding it from a slit plate, and then a baking process is performed to form the base electrode layer 31.

[0080] In step S7, an Sn—Cu diffusion layer 32 and an Sn—Ni diffusion layer 33 are formed. Specifically, an Sn plating is formed on the base electrode layer 31, an Ni plating is formed on the Sn plating, and heat treatment is performed at a temperature equal to or higher than the melting point of the Sn plating, thereby diffusing the Sn plating into the base electrode layer 31 and the Ni plating. Electrolytic plating is preferably used as the plating process. Barrel plating is preferably used as the plating method. As a result, Sn is diffused into Cu in the base electrode layer 31, forming the Sn—Cu diffusion layer 32, the Sn—Ni diffusion layer 33, and the Ni plating layer 34. At this time, voids P are formed at the interface between the base electrode layer 31 and the Sn—Cu diffusion layer 32. Here, the porosity and the thicknesses of the Sn—Cu diffusion layer 32 and the Sn—Ni diffusion layer 33 can be controlled by controlling the temperature or time of the heat treatment. The thickness of the Sn—Cu diffusion layer 32 and the Sn—Ni diffusion layer 33 can also be controlled by controlling the thickness of the Sn plating formed on the Ni plating. In this case, the region where Cu and Ni are not diffused is defined as an intermediate Sn plating layer 36.

[0081] In step S8, a Ni plating layer 34 and a Sn plating layer 35 are formed. Electrolytic plating is preferably used as the plating process. Barrel plating is preferably used as the plating method. In this case, if the Ni plating layer 34 is formed in step S7, only the Sn plating layer 35 may be formed.

[0082] When four external electrodes are arranged on the laminate 112 as in the second embodiment, the base electrode layer 31 is arranged on the third to sixth surfaces 12c to 12f in step S6. In step S7, the Sn—Cu diffusion layer 32 and the Sn—Ni diffusion layer 33 are selectively formed on the third to sixth surfaces 12c to 12f, thereby forming the external electrodes 30 according to the present disclosure on desired surfaces.

[0083] As described above, although the embodiments of the present disclosure have been disclosed in the above description, the present disclosure is not limited thereto. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present disclosure, and such modifications are included in the present disclosure.

[0084] For example, although the step layer 19 is disposed on the same plane as the internal electrode 13a in Figures 2, 3, and 4, the step layer 19 does not have to be disposed on the same plane as the internal electrode 13a. Although the step layer 19 is disposed on the same plane as the internal electrode 113a in Figures 7 to 10, the step layer 19 does not have to be disposed on the same plane as the internal electrode 113a. In other words, the step layer 19 does not have to be provided in the inner layer portion 13.

[0085] The present disclosure includes the following aspects: <1> A laminate having a first surface and a second surface opposed to each other in a stacking direction, a third surface and a fourth surface opposed to each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface opposed to each other in a second direction perpendicular to the stacking direction and the first direction, a first external electrode disposed on the fifth surface of the laminate, and a second external electrode disposed on the sixth surface of the laminate, wherein the laminate comprises an inner dielectric layer, and an internal electrode laminated on the inner dielectric layer in the stacking direction and having an end located on the fifth surface or the sixth surface, the first external electrode comprising: a base electrode layer disposed on the fifth surface and connected to the internal electrode; a Sn—Cu diffusion layer disposed on the base electrode layer and containing tin and copper; and a Sn—Ni diffusion layer disposed outside the Sn—Cu diffusion layer and containing tin and nickel. a Ni plating layer mainly composed of nickel and disposed on the Sn—Ni diffusion layer, wherein a gap exists at the interface between the base electrode layer and the Sn—Cu diffusion layer. <2> The multilayer electronic component according to <1>, wherein an intermediate Sn plating layer is disposed between the Sn—Cu diffusion layer and the Sn—Ni diffusion layer. <3> The multilayer electronic component according to <1> or <2>, wherein the Sn—Cu diffusion layer is thicker than the Sn—Ni diffusion layer. <4> The multilayer electronic component according to any one of <1> to <3>, comprising: a third external electrode disposed on the third surface of the laminate; and a fourth external electrode disposed on the fourth surface of the laminate.<5> The multilayer electronic component according to <4>, wherein the laminate includes a second internal electrode stacked on the internal dielectric layer in the stacking direction and having an end located on the third surface, and the third external electrode includes: a second base electrode layer disposed on the third surface and connected to the second internal electrode; a second Sn—Cu diffusion layer disposed on the second base electrode layer and containing tin and copper; a second Sn—Ni diffusion layer disposed outside the second Sn—Cu diffusion layer and containing tin and nickel; and a second Ni plating layer disposed on the second Sn—Ni diffusion layer and containing nickel as a main component, and wherein a second void exists at an interface between the second base electrode layer and the second Sn—Cu diffusion layer. <6> A mounting structure for a multilayer electronic component, comprising: the multilayer electronic component according to <4> or <5>; and a mounting board on which the multilayer electronic component is mounted, in which a positive potential is applied to the first external electrode and the second external electrode.

[0086] REFERENCE SIGNS LIST 10 Multilayer ceramic capacitor 12 Laminate 13 Inner layer portion 13a Internal electrode 14a Inner dielectric layer 15a Counter electrode portion 15b Lead electrode portion 16 Outer layer portion 16a First outer layer portion 16b Second outer layer portion 17a Outer dielectric layer 19 Step layer 30 External electrode 30a First external electrode 30b Second external electrode 31 Base electrode layer 32 Sn—Cu diffusion layer 33 Sn—Ni diffusion layer 34 Ni plating layer 35 Sn plating layer

Claims

1. a laminate having a first surface and a second surface facing each other in a stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; a first external electrode disposed on the fifth surface of the laminate; a second external electrode disposed on the sixth surface of the laminate; and Equipped with The laminate is an inner dielectric layer; an internal electrode laminated on the inner dielectric layer in the lamination direction and having an end located on the fifth surface or the sixth surface; Equipped with The first external electrode is a base electrode layer disposed on the fifth surface and connected to the internal electrode; a Sn—Cu diffusion layer disposed on the base electrode layer and containing tin and copper; an Sn—Ni diffusion layer containing tin and nickel and disposed outside the Sn—Cu diffusion layer; a Ni plating layer mainly composed of nickel disposed on the Sn—Ni diffusion layer; Equipped with The multilayer electronic component has a void at the interface between the base electrode layer and the Sn—Cu diffusion layer.

2. 2. The multilayer electronic component according to claim 1, wherein an intermediate Sn plating layer is disposed between the Sn--Cu diffusion layer and the Sn--Ni diffusion layer.

3. 3. The multilayer electronic component according to claim 1, wherein the thickness of said Sn--Cu diffusion layer is greater than the thickness of said Sn--Ni diffusion layer.

4. a third external electrode disposed on the third surface of the laminate; a fourth external electrode disposed on the fourth surface of the laminate; The multilayer electronic component according to claim 1 or 2, comprising:

5. A third external electrode disposed on the third surface of the laminate; a fourth external electrode disposed on the fourth surface of the laminate; The multilayer electronic component according to claim 3 , comprising:

6. the laminate includes a second internal electrode stacked on the internal dielectric layer in the stacking direction and having an end portion located on the third surface, The third external electrode is a second base electrode layer disposed on the third surface and connected to the second internal electrode; a second Sn—Cu diffusion layer disposed on the second base electrode layer and containing tin and copper; a second Sn—Ni diffusion layer containing tin and nickel and disposed outside the second Sn—Cu diffusion layer; a second Ni plating layer disposed on the second Sn—Ni diffusion layer and containing nickel as a main component; Equipped with 5. The multilayer electronic component according to claim 4, wherein a second void exists at the interface between said second underlying electrode layer and said second Sn--Cu diffusion layer.

7. The laminate includes a second internal electrode laminated on the inner dielectric layer in the lamination direction and having an end located on the third surface; The third external electrode is a second base electrode layer disposed on the third surface and connected to the second internal electrode; a second Sn—Cu diffusion layer disposed on the second base electrode layer and containing tin and copper; a second Sn—Ni diffusion layer containing tin and nickel and disposed outside the second Sn—Cu diffusion layer; a second Ni plating layer disposed on the second Sn—Ni diffusion layer and containing nickel as a main component; Equipped with 6. The multilayer electronic component according to claim 5, wherein a second void exists at the interface between said second base electrode layer and said second Sn--Cu diffusion layer.

8. The multilayer electronic component according to claim 4; a mounting substrate on which the multilayer electronic component is mounted; A mounting structure for a multilayer electronic component comprising: A mounting structure for a multilayer electronic component, wherein a positive potential is applied to the first external electrode and the second external electrode.

9. A laminated electronic component according to claim 1, a mounting substrate on which the multilayer electronic component is mounted; A mounting structure for a multilayer electronic component comprising: A mounting structure for a multilayer electronic component, wherein a positive potential is applied to the first external electrode.