Power supply device

Abstract

According to the present invention, a first converter comprises: first to fourth switching elements connected in series with each other from a reference node toward a node receiving an input voltage; a flying capacitor; an intermediate capacitor; and a first inductor. The intermediate capacitor is provided between the connection node between the second and third switching elements and the reference node. A second converter comprises: a switching output stage connected to the connection node between the second and third switching elements; and a second inductor. A control circuit generates an output voltage lower than the input voltage through the state controls of each switching element and the switching output stage.

Description

power supply

[0001] The present disclosure relates to a power supply device.

[0002] A multiphase converter is a type of power supply device that uses switching elements, and is capable of producing high output power and low output ripple.

[0003] Japanese Patent Application Laid-Open No. 2022-6829

[0004] Previous power supplies capable of multiphase operation have room for improvement.

[0005] An object of the present disclosure is to provide a good power supply device capable of performing multi-phase operation.

[0006] a first inductor provided between the first node and an output node to which the output voltage is applied; a second inductor provided between the first node and an output node to which the output voltage is applied; a first switching element provided between a reference node having a potential lower than the input voltage and a first node; a second switching element provided between the first node and a second node; a third switching element provided between the second node and a third node; a fourth switching element provided between the third node and a power supply node receiving the input voltage; a flying capacitor provided between the first node and the third node; an intermediate capacitor provided between the second node and the reference node; and a first inductor provided between the first node and an output node to which the output voltage is applied; the second converter has a switching output stage connected to the second node; and a second inductor provided between the switching output stage and the output node; and the control circuit generates the output voltage at the output node by controlling the states of the first to fourth switching elements and the switching output stage.

[0007] According to the present disclosure, it is possible to provide a good power supply device capable of performing multi-phase operation.

[0008] FIG. 1 is a configuration diagram of a power supply device according to a first embodiment of the present disclosure. FIG. 2 is an explanatory diagram of the operation of a hybrid buck converter in the power supply device according to the first embodiment of the present disclosure. FIG. 3 is an explanatory diagram of the operation of the power supply device according to the first embodiment of the present disclosure (state ST1). FIG. 4 is an explanatory diagram of the operation of the power supply device according to the first embodiment of the present disclosure (state ST2). FIG. 5 is an explanatory diagram of the operation of the power supply device according to the first embodiment of the present disclosure (state ST3). FIG. 6 is an explanatory diagram of the operation of the power supply device according to the first embodiment of the present disclosure (state ST4). FIG. 7 is an internal configuration diagram of a control circuit according to the first embodiment of the present disclosure. FIG. 8 is a first example timing chart of the power supply device according to the first embodiment of the present disclosure. FIG. 9 is a second example timing chart of the power supply device according to the first embodiment of the present disclosure. FIG. 10 is a configuration diagram of a power supply device according to a second embodiment of the present disclosure. FIG. 11 is a diagram showing the relationship between a control circuit and multiple converters according to the second embodiment of the present disclosure. FIG. 12 is a diagram showing the relationship between a plurality of clock signals in a power supply device according to the second embodiment of the present disclosure.

[0009] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, the same parts are designated by the same reference numerals, and duplicate descriptions of the same parts will be omitted as a general rule. In this specification, for the sake of simplicity, symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated.

[0010] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductive part having a reference potential of 0 V (zero volts) or the 0 V reference potential itself. When a component, electrode, or node is connected to ground, it means that the component, electrode, or node is connected to a reference node having a reference potential of 0 V. The reference node and ground can be read interchangeably.

[0011] A level refers to the level of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any given signal or voltage, a high level signal or voltage strictly means that the signal or voltage level is high, and a low level signal or voltage strictly means that the signal or voltage level is low. For any given signal or voltage, a transition from a low level to a high level is called a rising edge, and a transition from a high level to a low level is called a falling edge.

[0012] Any switching element can be configured with a transistor. For any transistor configured as a FET (field effect transistor), including a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Furthermore, unless otherwise specified, the back gate of any MOSFET can be considered to be short-circuited to the source.

[0013] Hereinafter, the on and off states of any switching element may be simply referred to as on and off. For any switching element, switching from the off state to the on state is referred to as turning on, and switching from the on state to the off state is referred to as turning off. Furthermore, for any switching element, the period during which the switching element is in the on state is referred to as the on period, and the period during which the switching element is in the off state is referred to as the off period.

[0014] For any signal that takes a high or low signal level, the period during which the signal level is high is referred to as a high-level period, and the period during which the signal level is low is referred to as a low-level period. The same applies to any voltage that takes a high or low voltage level.

[0015] Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, or node, may be understood to refer to an electrical connection.

[0016] If two arbitrary voltages to be compared are voltages v1 and v2, then "v1>v2" indicates that voltage v1 is higher than voltage v2, and "v1<v2" indicates that voltage v1 is lower than voltage v2. The same applies to other equations that include physical quantities other than voltage.

[0017] <<First Embodiment>> A first embodiment of the present disclosure will be described. Fig. 1 shows the configuration of a power supply device 1A according to the first embodiment of the present disclosure. In the power supply device 1A, two-channel converters 10 and 20 form a two-phase multi-phase converter.

[0018] The power supply device 1A receives a positive input voltage V from a voltage source (not shown). ＩＮ is supplied, and the input voltage V ＩＮ By stepping down the voltage, a positive output voltage V ＯＵＴ Generates an output voltage V ＯＵＴ is the input voltage V ＩＮ The power supply device 1A has an output voltage V ＯＵＴ That is, in a steady state, the output voltage V ＯＵＴ The target voltage is substantially equal to the target voltage. Hereinafter, the target voltage is referred to as "V ＴＧ In the power supply device 1A, the intermediate voltage V ＭＩＤ is generated. The output voltage V ＯＵＴ is the intermediate voltage V ＭＩＤ Also, in the steady state, the intermediate voltage V ＭＩＤ is essentially the input voltage V ＩＮ Therefore, "V ＩＮ >2 x V ＯＵＴ " is true. "V ＩＮ >2 x VＯＵＴ As long as " is true, the input voltage V ＩＮ and output voltage V ＯＵＴ The value of "V" is arbitrary. ＩＮ >2 x V ＴＧ As long as " is true, the input voltage V ＩＮ and target voltage V ＴＧ The value of is arbitrary. For example, the input voltage V ＩＮ is 48V, and the target voltage V ＴＧ (i.e., the output voltage V ＯＵＴ ) is 12V or 5V.

[0019] Regarding the power supply device 1A, the steady state is when the output voltage V ＯＵＴ rises from 0V to the target voltage V ＴＧ After reaching ＯＵＴ is the target voltage V ＴＧ This refers to a state in which the temperature is stabilized at .

[0020] The power supply device 1A includes a converter 10, a converter 20, and a control circuit 30. The converter 10 functions as a reference converter, and the converter 20 functions as an additional converter (a converter added to the reference converter). In the power supply device 1A, the converters 10 and 20 each output a current to an output node ND. ＯＵＴ , which supplies the output node ND ＯＵＴ output voltage V having a desired voltage value ＯＵＴ Generates.

[0021] As components of the converter 10 and the converter 20, the power supply device 1A includes switching elements M1 to M4, ML and MH, and a capacitor C ＦＬＹ , C ＭＩＤ and C ＯＵＴ and inductors L1 and L2. ＦＬＹ can be called a flying capacitor. ＭＩＤ can be referred to as the intermediate capacitor. ＯＵＴ can be referred to as the output capacitor.

[0022] The converter 10 is a first channel converter. The components of the converter 10 include switching elements M1 to M4 and a capacitor C ＦＬＹ and C ＭＩＤ The converter 20 is a second-channel converter. The components of the converter 20 include switching elements MH and ML and an inductor L2. The capacitor C ＯＵＴ is used in common by the converters 10 and 20. That is, the capacitor C ＯＵＴ are components of the converters 10 and 20, and are shared by the converters 10 and 20.

[0023] The converter 10 includes a buck converter and a stacked converter. The buck converter in the converter 10 includes switching elements M1 and M2, an inductor L1, and a capacitor C ＯＵＴ In cooperation with the intermediate voltage V ＭＩＤ By lowering the voltage at the output node ND ＯＵＴ Output voltage V ＯＵＴ The switching elements M1 and M2 function as a low-side switching element and a high-side switching element in the buck converter in the converter 10.

[0024] The stacked converter in converter 10 includes switching elements M3 and M4 and capacitor C ＦＬＹ and an input voltage V ＩＮ to intermediate voltage V ＭＩＤ The capacitor C ＭＩＤ can be understood to be included in the components of the stacked converter.

[0025] The converter 20 is a buck converter itself. The converter 20 has a capacitor C ＯＵＴ In cooperation with the intermediate voltage V ＭＩＤ By lowering the voltage at the output node ND ＯＵＴ Output voltage V ＯＵＴ The switching elements ML and MH function as a low-side switching element and a high-side switching element in the converter 20.

[0026] The configuration of the power supply device 1A in Fig. 1 will be described in more detail. In this embodiment, the switching elements M1 to M4, ML, and MH are each configured with an N-channel MOSFET. For this reason, hereinafter, the switching elements M1 to M4, ML, and MH may be referred to as transistors M1 to M4, ML, and MH.

[0027] The transistors M1 to M4 are connected in series between the ground and a node ND4. The transistor M1 is provided between the ground and the node ND1, the transistor M2 is provided between the nodes ND1 and ND2, the transistor M3 is provided between the nodes ND2 and ND3, and the transistor M4 is provided between the nodes ND3 and ND4. More specifically, the source of the transistor M1 is connected to the ground. The drain of the transistor M1 and the source of the transistor M2 are connected to the node ND1. The drain of the transistor M2 and the source of the transistor M3 are connected to the node ND2. The drain of the transistor M3 and the source of the transistor M4 are connected to the node ND3. The drain of the transistor M4 is connected to the node ND4. The node ND4 is connected to the input voltage V ＩＮ That is, the node ND4 is a power supply node that receives the input voltage V ＩＮ The signals supplied to the gates of the transistors M1 to M4 are referred to as gate signals G1 to G4, respectively.

[0028] Capacitor C ＦＬＹ is provided between the nodes ND3 and ND1. That is, the capacitor C ＦＬＹ The first end of the capacitor C is connected to the node ND3. ＦＬＹ The second end of the transistor ND1 is connected to the node ND1.

[0029] Capacitor C ＭＩＤ is provided between the node ND2 and the ground. That is, the capacitor C ＭＩＤ The first end of the capacitor C is connected to the node ND2. ＭＩＤ The second end of the capacitor C is connected to ground. ＭＩＤ The first end of the capacitor C ＭＩＤ The voltage at node ND2 corresponds to the positive electrode of the intermediate voltage V ＭＩＤ That is, the capacitor CＭＩＤ At the intermediate voltage V ＭＩＤ A charge of 1000kJ / s is accumulated.

[0030] The inductor L1 is connected between the node ND1 and the output node ND ＯＵＴ That is, a first end of the inductor L1 is connected to the node ND1, and a second end of the inductor L1 is connected to the output node ND ＯＵＴ is connected to.

[0031] Capacitor C ＯＵＴ is the output node ND ＯＵＴ and ground. That is, the capacitor C ＯＵＴ The first end of the output node ND ＯＵＴ and a capacitor C ＯＵＴ The second end of the capacitor C is connected to ground. ＯＵＴ The first end of the capacitor C ＯＵＴ This corresponds to the positive electrode of the output node ND. ＯＵＴ The voltage at is the output voltage V ＯＵＴ That is, the capacitor C ＯＵＴ At the output voltage V ＯＵＴ A charge of 1000kJ / s is accumulated.

[0032] The transistor MH is connected to the nodes ND2 and ND ＳＷ The transistor ML is connected to the node ND. ＳＷ and the ground. More specifically, the source of the transistor ML is connected to the ground. The drain of the transistor ML and the source of the transistor MH are connected to the node ND. ＳＷ The drain of the transistor MH is connected to the node ND2 (switch node). The signals supplied to the gates of the transistors ML and MH are referred to as gate signals GL and GH, respectively.

[0033] Inductor L2 is connected to node ND ＳＷ and the output node ND ＯＵＴ That is, the first end of the inductor L2 is connected to the node ND ＳＷ and the second end of the inductor L2 is connected to the output node ND ＯＵＴ is connected to.

[0034] The control circuit 30 is connected to the gates of the transistors M1 to M4, ML, and MH, and controls the states (on / off states) of the transistors M1 to M4, ML, and MH individually by supplying gate signals G1 to G4, GL, and GH to the transistors M1 to M4, ML, and MH. By controlling the states of the transistors M1 to M4, ML, and MH with the control circuit 30, the input voltage V ＩＮ The lower desired output voltage V ＯＵＴ is the output node ND ＯＵＴ The control circuit 30 may be formed of a semiconductor integrated circuit.

[0035] Any of the gate signals G1 to G4, GL, and GH will be referred to as the gate signal Gx. Of the transistors M1 to M4, ML, and MH, the transistor that receives the gate signal Gx at its gate will be referred to as the transistor Mx. When the gate signal Gx is at a high level, the transistor Mx is on, and when the gate signal Gx is at a low level, the transistor Mx is off. Therefore, during the high-level period of the gate signal G1, the transistor M1 is on, and during the low-level period of the gate signal G1, the transistor M1 is off. Similarly, during the high-level period of the gate signal G2, the transistor M2 is on, and during the low-level period of the gate signal G2, the transistor M2 is off. The same is true for the transistors M3, M4, ML, and MH. A high-level gate signal Gx has a potential higher than the potential that is higher than the source potential of the transistor Mx by the gate threshold voltage of the transistor Mx. A low-level gate signal Gx may have a potential equivalent to the source potential of the transistor Mx.

[0036] The transistors M1 and M2 form a switching output stage 11 in the converter 10. The transistors ML and MH form a switching output stage 21 in the converter 20. The switching output stages 11 and 21 are each connected to a node ND2 and are connected to an intermediate voltage V ＭＩＤ The voltage is reduced.

[0037] The control circuit 30 performs switching control on the switching output stage 11 to alternately switch on and off the transistors M1 and M2, thereby supplying the intermediate voltage V ＭＩＤ Separately, the control circuit 30 controls the switching output stage 21 to alternately turn on and off the transistors ML and MH, thereby causing the converter 20 to step down the intermediate voltage V ＭＩＤ In the power supply device 1A, the intermediate voltage V ＭＩＤ and the intermediate voltage V ＭＩＤ The output node ND ＯＵＴ Output voltage V ＯＵＴ occurs.

[0038] Output node ND ＯＵＴ is connected to a load (not shown). The load is connected to an output voltage V ＯＵＴ The output node ND is an arbitrary load that drives the ＯＵＴ The current supplied to the load from ＬＤ The load current I ＬＤ corresponds to the output current of the power supply device 1A. The current flowing through the inductor L1 is the inductor current I Ｌ１ The current flowing through the inductor L2 is called the inductor current I Ｌ２ In this case, it is assumed that the power supply device 1A is operating in the continuous current mode. In the continuous current mode, current always flows from the first terminal to the second terminal of each of the inductors L1 and L2, that is, the capacitor C ＯＵＴ A current always flows through the inductors L1 and L2 in the direction in which the capacitor is charged.

[0039] The operation of the converter 10 will now be described with reference to FIG. ＦＬＹ (i.e., the potential at the node ND1) as a reference. ＦＬＹ The current that increases the potential at the first end of the capacitor C ＦＬＹ The reverse current is the charging current of the capacitor C ＦＬＹ is the discharge current of the capacitor C ＭＩＤRegarding the intermediate voltage V ＭＩＤ The current that increases the intermediate voltage V ＭＩＤ The current that decreases the capacitance is the discharge current.

[0040] The control circuit 30 alternately switches the states of the transistors M1 to M4 between states STa and STb. In state STa, the transistors M1 and M3 are off and the transistors M2 and M4 are on. In state STb, the transistors M1 and M3 are on and the transistors M2 and M4 are off.

[0041] In state STa, currents 811 and 813 are generated. The current 811 flows through the capacitor C ＭＩＤ from the output node ND through the transistor M2 and the inductor L1. ＯＵＴ is the current going to the capacitor C ＭＩＤ The current 813 is generated by the discharge of the input voltage V ＩＮ The voltage is applied from node ND4 to capacitor C ＦＬＹ The current 813 flows into the capacitor C ＦＬＹ is charged.

[0042] In state STb, currents 812 and 814 are generated. The current 812 flows from ground through transistor M1 and inductor L1 to output node ND. ＯＵＴ The current 814 flows into the capacitor C ＦＬＹ through the transistor M3 to the capacitor C ＭＩＤ The current 814 flows through the capacitor C ＦＬＹ is generated by the discharge of the capacitor C ＭＩＤ contributes to charging.

[0043] In state STa, transistors M2 and M4 are on, so that capacitor C ＦＬＹ and C ＭＩＤ For ＦＬＹ and C ＭＩＤ In the state STb, the capacitor C ＦＬＹ and C ＭＩＤAs a result, the transistors M1 to M4 and the capacitor C ＦＬＹ and C ＭＩＤ Therefore, in the steady state, the capacitor C ＭＩＤ The intermediate voltage V ＭＩＤ is approximately the voltage (V ＩＮ That is, the converter 10 converts the input voltage V ＩＮ The intermediate voltage V corresponds to the divided voltage of ＭＩＤ is generated.

[0044] Meanwhile, the intermediate voltage V ＭＩＤ Therefore, the converter 10 can be called a hybrid buck converter that combines a switched capacitor circuit and a synchronous buck converter.

[0045] The switched capacitor circuit generates an input voltage V ＩＮ is reduced to half, and the resulting intermediate voltage V ＭＩＤ High efficiency can be achieved by further stepping down the voltage using a synchronous buck converter.

[0046] For example, if the input voltage V is 48V, ＩＮ to 12V output voltage V ＯＵＴ Consider the case where a 48V input voltage V is generated. As a reference method, a simple synchronous buck converter is used to directly step down 48V to 12V. In the reference method, ＩＮ By switching between these, a square wave voltage (a square wave voltage that fluctuates between approximately 0 V and 48 V) is generated, and the square wave voltage is rectified and smoothed to obtain an output voltage of 12 V. In contrast, in the power supply device 1A, the voltage (V ＩＮ / 2) to generate a square wave voltage (a square wave voltage that fluctuates between approximately 0 V and 24 V), and then the square wave voltage is rectified and smoothed to obtain an output voltage of 12 V. Therefore, compared to power supply devices related to the reference method, power supply device 1A can keep switching losses low.

[0047] There are several factors that contribute to the reduction of switching loss, some of which are listed below. In the reference method, the switching duty is relatively small. When the switching duty is relatively small, the effects of loss during periods when the instantaneous value of the square wave voltage rises and falls become relatively large. In contrast, when the power supply device 1A is used, the input voltage to the synchronous buck converter is a voltage (V ＩＮ / 2), the switching duty is relatively large compared to the reference method, which leads to an improvement in switching loss. Also, during the switching process, various parasitic capacitances are charged and discharged. In the power supply device 1A, the input voltage to the synchronous buck converter is a voltage (V ＩＮ / 2), the loss due to charging and discharging of the parasitic capacitance can be kept relatively low compared to the reference method.

[0048] Furthermore, in the power supply device 1A, in addition to the synchronous buck converter in the hybrid type buck converter (10), an intermediate voltage V ＭＩＤ By providing a synchronous buck converter (20) that performs a step-down operation of the buck converter (20) and operating them in multiphase, high output power and low output ripple are achieved. A reference method in which multiple hybrid buck converters are operated in multiphase can also achieve increased output power and low output ripple, but the reference method increases the number of parts by the number of hybrid buck converters. The power supply device 1A also achieves the effect of reducing the number of parts compared to the reference method.

[0049] The states of the transistors M1 to M4 are switched between states STa and STb, while the states of the transistors ML and MH are switched between a state where the transistor ML is on and the transistor MH is off, and a state where the transistor ML is off and the transistor MH is on. Therefore, the states of the transistors M1 to M4, ML, and MH are in any of states ST1 to ST4 shown in FIGS. 3 to 6.

[0050] The control circuit 30 can set the states of the transistors M1 to M4, ML and MH to one of states ST1 to ST4.

[0051] As shown in Figure 3, in state ST1, the transistors M1, M3, and ML are in the off state, and the transistors M2, M4, and MH are in the on state. In state ST1, the state of the transistors M1 to M4 is state STa (see Figure 2). Therefore, in state ST1, the above currents 811 and 813 are generated in the converter 10. On the other hand, in state ST1, a current 821 is generated in the converter 20. The current 821 flows through the capacitor C ＭＩＤ from the output node ND through the transistor MH and the inductor L2. ＯＵＴ is the current going to the capacitor C ＭＩＤ It is generated by the discharge of

[0052] As shown in Figure 4, in state ST2, the transistors M1, M3, and MH are in the off state, and the transistors M2, M4, and ML are in the on state. In state ST2, the state of the transistors M1 to M4 is state STa (see Figure 2). Therefore, in state ST2, the above currents 811 and 813 are generated in the converter 10. On the other hand, in state ST2, a current 822 is generated in the converter 20. The current 822 flows from the ground to the output node ND through the transistor ML and the inductor L2. ＯＵＴ Heading towards.

[0053] As shown in Figure 5, in state ST3, transistors M2, M4, and ML are off, and transistors M1, M3, and MH are on. In state ST3, the states of transistors M1 to M4 are state STb (see Figure 2). Therefore, in state ST3, the above-mentioned currents 812 and 814 are generated in converter 10. On the other hand, in state ST3, the above-mentioned current 821 is generated in converter 20.

[0054] As shown in FIG. 6, in state ST4, transistors M2, M4, and MH are in the off state, and transistors M1, M3, and ML are in the on state. In state ST4, the states of transistors M1 to M4 are in state STb (see FIG. 2). Therefore, in state ST4, the above-mentioned currents 812 and 814 are generated in converter 10. On the other hand, in state ST4, the above-mentioned current 822 is generated in converter 20.

[0055] Fig. 7 shows the internal configuration of the control circuit 30. Figs. 8 and 9 show timing charts relating to first and second operation examples of the control circuit 30. Figs. 8 and 9 each show, from top to bottom, the waveforms of the signals CLK1, CMPOUT1, CLK2, CMPOUT2, G1 to G4, GH, and GL.

[0056] The control circuit 30 includes an error amplifier 31, ramp circuits 32_1 and 32_2, current information acquisition circuits 33_1 and 33_2, adders 34_1 and 34_2, PWM comparators 35_1 and 35_2, and controllers 36_1 and 36_2. The power supply device 1A is provided with resistors R1 and R2. A first end of the resistor R1 is connected to an output node ND. ＯＵＴ The second end of the resistor R1 is connected to the first end of the resistor R2, and the second end of the resistor R2 is connected to ground. An output voltage V ＯＵＴ Feedback voltage V according to ＦＢ The feedback voltage V ＦＢ is the output voltage V ＯＵＴ Therefore, the output voltage V ＯＵＴ The resistors R1 and R2 are proportional to the feedback voltage V ＦＢ A feedback voltage generating circuit is formed to generate the feedback voltage V ＦＢ is supplied to the control circuit 30. However, it may be understood that the feedback voltage generating circuit is included in the components of the control circuit 30. ＯＵＴ It is the feedback voltage V ＦＢ In any case, the feedback voltage V ＦＢ is the output voltage V ＯＵＴ Information on the output voltage V ＯＵＴ (information indicating the value of

[0057] The error amplifier 31 is a current output type transconductance amplifier. The error amplifier 31 has an inverting input terminal, a non-inverting input terminal, and an output terminal. A feedback voltage V ＦＢ A predetermined reference voltage V ＲＥＦ The reference voltage V ＲＥＦis a DC voltage having a predetermined positive voltage value, and is generated by a reference voltage generating circuit (not shown) in the control circuit 30. The output terminal of the error amplifier 31 is connected to the wiring WR ＥＲＲ When the power supply device 1A is started, the reference voltage V ＲＥＦ Although a soft start control may be performed to gradually increase the value of from 0 V to a predetermined positive voltage value, the existence of the soft start control will be ignored below.

[0058] The error amplifier 31 outputs a feedback voltage V ＦＢ and the reference voltage V ＲＥＦ By outputting a current signal corresponding to the difference between the feedback voltage V ＦＢ and the reference voltage V ＲＥＦ Error voltage V according to the difference between ＥＲＲ Wiring WR ＥＲＲ Specifically, the error amplifier 31 generates a feedback voltage V ＦＢ is the reference voltage V ＲＥＦ When the error voltage V ＥＲＲ Wiring WR from its own output terminal so that ＥＲＲ and outputs a current to the feedback voltage V ＦＢ is the reference voltage V ＲＥＦ When the error voltage V ＥＲＲ Wiring WR to reduce ＥＲＲ The current is drawn from the wiring WR ＥＲＲ A phase compensation circuit including a capacitor may be connected between the input and ground.

[0059] The ramp circuit 32_1 generates a predetermined initial voltage V ＩＮＴ The ramp voltage V monotonically increases at a predetermined rate of change from ＲＡＭＰ１ In the ramp circuit 32_1, an initial voltage V ＩＮＴ is, for example, 0 V, but may be different from 0 V. During the off period of the transistor M2, the ramp voltage V ＲＡＭＰ１ is the initial voltage V ＩＮＴ It is fixed in place.

[0060] The current information acquisition circuit 33_1 acquires current information of the inductor L1 and outputs a sense voltage V ＩＬ１The current information of the inductor L1 is the inductor current I Ｌ１ This is information indicating the value of the sense voltage V ＩＬ１ is a positive proportional coefficient and the inductor current I Ｌ１ Therefore, the inductor current I Ｌ１ As the sense voltage V ＩＬ１ rises, and the inductor current I Ｌ１ With the decrease in the sense voltage V ＩＬ１ Here, "V ＩＬ１ = k ＩＶ ×I Ｌ１ ". k ＩＶ is a predetermined positive coefficient.

[0061] Sense voltage V ＩＬ１ indicates the current information of the inductor L1, the sense voltage V ＩＬ１ The method for generating the inductor current I Ｌ１ By directly detecting the current with a current sensor, the sense voltage V ＩＬ１ The current sensor here may be a shunt resistor (not shown) inserted in series between the inductor L1 and the node ND1. Alternatively, for example, the current flowing through the transistor M2 during the on-period of the transistor M2 (hence the inductor current I Ｌ１ ) or by detecting the current flowing through the transistor M1 during the ON period of the transistor M1 (thus the inductor current I Ｌ１ ) is detected, the sense voltage V ＩＬ１ Alternatively, the inductor current I Ｌ１ By detecting the voltage at any point where a voltage corresponding to ＩＬ１ may be generated.

[0062] The adder 34_1 calculates the lamp voltage V ＲＡＭＰ１ With respect to the sense voltage V ＩＬ１ By adding these, the slope voltage V ＳＬＰ１ That is, "V ＳＬＰ１ =V ＲＡＭＰ１ +V ＩＬ１ "

[0063] The PWM comparator 35_1 outputs an error voltage V ＥＲＲ and the slope voltage V ＳＬＰ１ and generates and outputs a signal CMPOUT1 indicating the comparison result. ＥＲＲ is input, and the slope voltage V ＳＬＰ１ is input to the PWM comparator 35_1. ＳＬＰ１ <V ＥＲＲ " is established, a low level signal CMPOUT1 is output, and "V ＳＬＰ１ >V ＥＲＲ " is established, a high level signal CMPOUT1 is output. ＳＬＰ１ =V ＥＲＲ When "is established," the signal CMPOUT1 has a low level or a high level.

[0064] A signal CMPOUT1 and a reference clock signal CLK1 are input to the controller 36_1. The reference clock signal CLK1 is generated by an internal clock generating circuit (not shown) provided in the control circuit 30. The reference clock signal CLK1 has a predetermined frequency f ＰＷＭ The reference clock signal CLK1 is a rectangular wave signal having a frequency f ＰＷＭ The signal has a high level for a short time at intervals equal to the reciprocal of the value of the reference signal (see FIGS. 8 and 9).

[0065] In response to a predetermined level change in the reference clock signal CLK1, the controller 36_1 generates a rising edge in the gate signals G2 and G4 (i.e., switches the levels of the gate signals G2 and G4 from low to high) to turn on the transistors M2 and M4, and generates a falling edge in the gate signals G1 and G3 (i.e., switches the levels of the gate signals G1 and G3 from high to low) to turn off the transistors M1 and M3. The predetermined level change (first predetermined level change) in the reference clock signal CLK1 here is a change in the reference clock signal CLK1 from low to high, but it may also be a change in the reference clock signal CLK1 from high to low.

[0066] After transistors M2 and M4 are turned on and transistors M1 and M3 are turned off, the slope voltage V ＳＬＰ１ After a monotonous rise in ＳＬＰ１ <V ＥＲＲ "From the established state of "V ＳＬＰ１ >V ＥＲＲ When the rising edge occurs in the signal CMPOUT1, the controller 36_1 generates a falling edge in the gate signals G2 and G4 to turn off the transistors M2 and M4, and generates a rising edge in the gate signals G1 and G3 to turn on the transistors M1 and M3. As the transistor M2 turns off, the ramp voltage V ＲＡＭＰ１ is a sufficiently low initial voltage V ＩＮＴ Since it decreases to "V ＳＬＰ１ <V ＥＲＲ ” is established, and a falling edge is quickly generated in the signal CMPOUT1. The time from when the transistors M2 and M4 are turned on and the transistors M1 and M3 are turned off to when the transistors M2 and M4 are turned off and the transistors M1 and M3 are turned on is defined as time t ＯＮ１ It is called.

[0067] The ramp circuit 32_2 generates a predetermined initial voltage VＩＮＴ The ramp voltage V monotonically increases at a predetermined rate of change from ＲＡＭＰ２ In the ramp circuit 32_2, an initial voltage V ＩＮＴ is, for example, 0 V, but may be different from 0 V. During the off period of the transistor MH, the ramp voltage V ＲＡＭＰ２ is the initial voltage V ＩＮＴ The ramp circuit 32_2 has the same configuration as the ramp circuit 32_1. Therefore, the ramp voltage V ＲＡＭＰ２ The rate of change of the ramp voltage V during the on-period of the transistor M2 is ＲＡＭＰ１ is equal to the rate of change of

[0068] The current information acquisition circuit 33_2 acquires current information of the inductor L2 and outputs a sense voltage V ＩＬ２ The current information of the inductor L2 is the inductor current I Ｌ２ This is information indicating the value of the sense voltage V ＩＬ２ is a positive proportional coefficient and the inductor current I Ｌ２ Therefore, the inductor current I Ｌ２ As the sense voltage V ＩＬ２ rises, and the inductor current I Ｌ２ With the decrease in the sense voltage V ＩＬ２ Here, "V ＩＬ２ = k ＩＶ ×I Ｌ２ "Let us assume that

[0069] Sense voltage V ＩＬ２ indicates the current information of the inductor L2, the sense voltage V ＩＬ２ The method for generating the inductor current I Ｌ２ By directly detecting the current with a current sensor, the sense voltage V ＩＬ２ The current sensor here may be the inductor L2 and the node ND ＳＷ Alternatively, for example, the current flowing through the transistor MH during the ON period of the transistor MH (therefore, the inductor current I Ｌ２) or by detecting the current flowing through the transistor ML during the ON period of the transistor ML (hence the inductor current I Ｌ２ ) is detected, the sense voltage V ＩＬ２ Alternatively, the inductor current I Ｌ２ By detecting the voltage at any point where a voltage corresponding to ＩＬ２ may be generated.

[0070] The adder 34_2 calculates the lamp voltage V ＲＡＭＰ２ With respect to the sense voltage V ＩＬ２ By adding these, the slope voltage V ＳＬＰ２ That is, "V ＳＬＰ２ =V ＲＡＭＰ２ +V ＩＬ２ "

[0071] The PWM comparator 35_2 outputs the error voltage V ＥＲＲ and the slope voltage V ＳＬＰ２ and generates and outputs a signal CMPOUT2 indicating the comparison result. ＥＲＲ is input, and the slope voltage V ＳＬＰ２ is input to the PWM comparator 35_2. ＳＬＰ２ <V ＥＲＲ " is established, a low level signal CMPOUT2 is output, and "V ＳＬＰ２ >V ＥＲＲ " is established, a high level signal CMPOUT2 is output. ＳＬＰ２ =V ＥＲＲ When "is established," the signal CMPOUT2 has a low level or a high level.

[0072] A signal CMPOUT2 and a shift clock signal CLK2 are input to the controller 36_2. The shift clock signal CLK2 is a signal obtained by shifting the phase of the reference clock CLK1. Therefore, the reference clock signal CLK1 and the shift clock signal CLK2 have the same frequency f ＰＷＭand have different phases. As with the reference clock CLK1, the shift clock signal CLK2 has a low level in principle and a frequency f ＰＷＭ The shift clock signal CLK2 has a high level for a very short time at intervals equal to the reciprocal of the reference clock CLK1 (see FIGS. 8 and 9). The shift clock signal CLK2 may be generated in the control circuit 30 based on the reference clock CLK1. Here, the shift clock signal CLK2 is assumed to be a signal whose phase is delayed by 180° from the reference clock signal CLK1. Therefore, the phase difference between the clock signals CLK1 and CLK2 is 180°. Setting the delay amount to 180° results in the output voltage V ＯＵＴ However, the amount of delay in phase of the shift clock signal CLK2 from the phase of the reference clock signal CLK1 may be other than 180° (for example, it may be 170° or 190°).

[0073] When a predetermined level change occurs in the shift clock signal CLK2, the controller 36_2 generates a rising edge in the gate signal GH to turn on the transistor MH and generates a falling edge in the gate signal GL to turn off the transistor ML. The predetermined level change (second predetermined level change) in the shift clock signal CLK2 here is a change from low level to high level in the shift clock signal CLK2, but it may also be a change from high level to low level in the shift clock signal CLK2.

[0074] After the transistor MH is turned on and the transistor ML is turned off, the slope voltage V ＳＬＰ２ After a monotonous rise in ＳＬＰ２ <V ＥＲＲ "From the established state of "V ＳＬＰ２ >V ＥＲＲ When the rising edge occurs in the signal CMPOUT2, the controller 36_2 generates a falling edge in the gate signal GH to turn off the transistor MH, and generates a rising edge in the gate signal GL to turn on the transistor ML. As the transistor MH turns off, the ramp voltage V ＲＡＭＰ２ is a sufficiently low initial voltage VＩＮＴ Since it decreases to "V ＳＬＰ２ <V ＥＲＲ ” is established, and a falling edge is quickly generated in the signal CMPOUT2. The time from when the transistor MH is turned on and the transistor ML is turned off to when the transistor MH is turned off and the transistor ML is turned on is defined as time t ＯＮ２ It is called.

[0075] By the above-described switching control by the controllers 36_1 and 36_2, the states of the transistors M1 to M4, ML and MH are switched among states ST1 to ST4 as shown in FIGS.

[0076] In the timing chart of Figure 8, the on-duty of transistor M2 and the on-duty of transistor MH are both less than 50%. In contrast, in the timing chart of Figure 9, the on-duty of transistor M2 and the on-duty of transistor MH are both greater than 50%. The on-duty of transistor M2 indicates the ratio of the on-period of transistor M2 to the sum of the on-period of transistor M2 and the off-period of transistor M2. Similarly, the on-duty of transistor MH indicates the ratio of the on-period of transistor MH to the sum of the on-period of transistor MH and the off-period of transistor MH. Output voltage V ＯＵＴ Various operating conditions (the above-mentioned on-duty, time t ＯＮ１ and t ＯＮ２ 8 or 9 appears depending on the operation.

[0077] In the timing chart of FIG. 8 , the state immediately before the rising edge of reference clock signal CLK1 is state ST4. In the timing chart of FIG. 8 , state ST4 immediately before the rising edge of reference clock signal CLK1 is considered to be the initial state. In the timing chart of FIG. 8 , the states of transistors M1 to M4, ML, and MH are switched from state ST4, which is the initial state, to state ST2 at the rising edge of reference clock signal CLK1, then switched from state ST2 to state ST4 at the rising edge of signal CMPOUT1, then switched from state ST4 to state ST3 at the rising edge of shift clock signal CLK2, and then returned from state ST3 to state ST4, which is the initial state, at the rising edge of signal CMPOUT2. Thereafter, the same operation is repeated.

[0078] In the timing chart of FIG. 9 , the state immediately before the rising edge of reference clock signal CLK1 is state ST3. In the timing chart of FIG. 9 , state ST3 immediately before the rising edge of reference clock signal CLK1 is considered to be the initial state. In the timing chart of FIG. 9 , the states of transistors M1 to M4, ML, and MH are switched from state ST3, which is the initial state, to state ST1 at the rising edge of reference clock signal CLK1, then switched from state ST1 to state ST2 at the rising edge of signal CMPOUT2, then switched from state ST2 to state ST1 at the rising edge of shift clock signal CLK2, and then returned from state ST1 to state ST3, which is the initial state, at the rising edge of signal CMPOUT1. Thereafter, the same operation is repeated.

[0079] "V ＯＵＴ =V ＴＧ "When "V ＦＢ =V ＲＥＦ "V ＯＵＴ =V ＴＧ Starting from the state where "" is established, the load current I ＬＤ Through the increase of "V ＯＵＴ <V ＴＧ "So, "V ＦＢ <V ＲＥＦ ", so the error voltage V ＥＲＲThe error voltage V ＥＲＲ The increase in the ON period of the transistor M2 causes an increase in the ON period of the transistor M1. Ｌ１ As the on-period of the transistor MH increases, the inductor current I Ｌ２ increases, resulting in an output voltage V ＯＵＴ is the target voltage V ＴＧ On the other hand, "V ＯＵＴ =V ＴＧ Starting from the state where "" is established, the load current I ＬＤ Through the decrease of "V ＯＵＴ >V ＴＧ "So, "V ＦＢ >V ＲＥＦ ", so the error voltage V ＥＲＲ The error voltage V ＥＲＲ The decrease in the ON period of the transistor M2 reduces the inductor current I Ｌ１ As the on-period of the transistor MH decreases, the inductor current I Ｌ２ decreases, resulting in the output voltage V ＯＵＴ is the target voltage V ＴＧ In this way, the output voltage V ＯＵＴ and target voltage V ＴＧ Control is performed to reduce the difference between the

[0080] The above-mentioned time t ＯＮ１ is the error voltage V ＥＲＲ (hence the output voltage V ＯＵＴ ) and the sense voltage V ＩＬ１ (and therefore depends on the current information of the inductor L1). In other words, the controller 36_1 controls the output voltage V ＯＵＴ Based on the information on the current of the inductor L1 and the information on the current of the inductor L1, the controller 36_1 controls the switching of the transistors M1 to M4 in synchronization with the reference clock signal CLK1. The controller 36_1 turns on the transistors M2 and M4 and turns off the transistors M1 and M3 in response to a predetermined level change in the reference clock signal CLK1, and then controls the output voltage V ＯＵＴ and the time tＯＮ１ After this time has elapsed, transistors M2 and M4 are turned off and transistors M1 and M3 are turned on.

[0081] The above-mentioned time t ＯＮ２ is the error voltage V ＥＲＲ (hence the output voltage V ＯＵＴ ) and the sense voltage V ＩＬ２ (and therefore depends on the current information of the inductor L2). In other words, the controller 36_2 controls the output voltage V ＯＵＴ The controller 36_2 controls the switching of the transistors ML and MH in synchronization with the shift clock signal CLK2 based on the information on the output voltage V ＯＵＴ and the time t ＯＮ２ After this time has elapsed, transistor MH is turned off and transistor ML is turned on.

[0082] The set of the switching output stage 11 and the inductor L1 in the converter 10 and the set of the switching output stage 21 and the inductor L2 in the converter 20 have the same configuration. ＭＩＤ In addition, the switching control of transistors M1 and M2 based on the current information of inductor L1 is equivalent to the switching control of transistors ML and MH based on the current information of inductor L2. Therefore, multiphase operation is achieved with the output current of converter 10 and the output current of converter 20 balanced.

[0083] In the power supply device 1A, the inductor current I Ｌ１ corresponds to the output current of the converter 10, and the inductor current I Ｌ２ corresponds to the output current of the converter 20. At each timing, the inductor current I Ｌ１ and I Ｌ２ Although the instantaneous values ​​of the inductor current I Ｌ１and the inductor current I Ｌ２ The output current of converter 10 and the output current of converter 20 are each pulsating currents, and the two output currents have different phases. That is, power supply device 1A is a two-phase multiphase converter (a multiphase DC / DC converter).

[0084] The circuit configuration of Fig. 7 is an example, and the configuration of the control circuit 30 can be modified in various ways as long as the above balance regarding the current is achieved. For example, a modification may be applied in which the adders 34_1 and 34_2 are deleted from the control circuit 30 of Fig. 7 and instead current information of the inductors L1 and L2 is fed back to the error amplifier 31 side. In this modification, ＳＬＰ１ =V ＲＡＭＰ１ " and "V ＳＬＰ２ =V ＲＡＭＰ２ " and at the same time, a voltage (V ＥＲＲ -V ＩＬ１ ) is input to the inverting input terminal of the PWM comparator 35_2, and a voltage (V ＥＲＲ -V ＩＬ２ ) is input to the PWM comparator 35_1 according to this modification. ＳＬＰ１ =V ＲＡＭＰ１ <V ＥＲＲ -V ＩＬ１ ", the signal CMPOUT1 is set to a low level, and "V ＳＬＰ１ =V ＲＡＭＰ１ >V ＥＲＲ -V ＩＬ１ ", the signal CMPOUT1 is set to a high level. Similarly, the PWM comparator 35_2 according to this modification ＳＬＰ２ =V ＲＡＭＰ２ <V ＥＲＲ -V ＩＬ２ ", the signal CMPOUT2 is set to a low level, and "V ＳＬＰ２ =V ＲＡＭＰ２ >V ＥＲＲ -V ＩＬ２ If "", the signal CMPOUT2 is set to high level.

[0085] <<Second Embodiment>> A second embodiment of the present disclosure will be described. The second embodiment and the third embodiment described below are embodiments based on the first embodiment, and for matters not specifically described in the second and third embodiments, the description of the first embodiment also applies to the second and third embodiments unless there is a contradiction. However, when interpreting the description of the second embodiment, the description of the second embodiment may take precedence for matters that contradict between the first and second embodiments (the same applies to the third embodiment described below). As long as there is no contradiction, any two or more of the first to third embodiments may be combined.

[0086] 10 shows the configuration of a power supply 1B according to a second embodiment of the present disclosure. The power supply 1B has one channel of converter 10 and n channels of converter 20, which together form an (n+1) phase multi-phase converter. When "n=1," the power supply 1B is the same as the power supply 1A of the first embodiment. In the second embodiment, n represents any integer equal to or greater than 2.

[0087] The power supply device 1B of FIG. 10 is obtained by modifying the power supply device 1A of FIG. 1 by adding (n-1) converters 20. Therefore, the power supply device 1B comprises a converter 10, n converters 20, and a control circuit 30. However, with the addition of the converter 20, the control circuit 30 of the power supply device 1B controls the states of the transistors ML and MH of each converter 20 in addition to controlling the states of the transistors M1 to M4. In the power supply device 1B, the converter 10 and the n converters 20 each supply a current to the output node ND. ＯＵＴ , which supplies the output node ND ＯＵＴ output voltage V having a desired voltage value ＯＵＴ Generates.

[0088] The configuration and operation of the converter 10 in the power supply device 1B are the same as those in the first embodiment. ＦＬＹ and C ＭＩＤ and inductor L1. The converter 10 receives an input voltage V ＩＮ to intermediate voltage V ＭＩＤ and a capacitor C ＯＵＴIn cooperation with the intermediate voltage V ＭＩＤ By lowering the voltage at the output node ND ＯＵＴ Output voltage V ＯＵＴ Generates.

[0089] In the power supply device 1B, the n-channel converters 20 have the same configuration. The configuration and operation of each converter 20 are the same as those shown in the first embodiment. Therefore, each converter 20 includes transistors ML and MH and an inductor L2. Each converter 20 includes a capacitor C ＯＵＴ In cooperation with the intermediate voltage V ＭＩＤ By lowering the voltage at the output node ND ＯＵＴ Output voltage V ＯＵＴ Generates.

[0090] Hereinafter, when it is necessary to distinguish between the n-channel converters 20, the n-channel converters 20 will be referred to as converters 20[1] to 20[n]. Converter 10 can be considered to be the first-channel converter, and in this case, converters 20[1] to 20[n] are the second to (n+1)-th channel converters.

[0091] Capacitor C ＯＵＴ is used for both converters 10 and 20[1] to 20[n]. That is, capacitor C ＯＵＴ are components of the converters 10 and 20[1] to 20[n], and are shared by the converters 10 and 20[1] to 20[n].

[0092] The drains of all the transistors MH in the converters 20[1] to 20[n] are commonly connected to a node ND2, which supplies an intermediate voltage V ＭＩＤ In each of the converters 20[1] to 20[n], the source of the transistor MH and the drain of the transistor ML are connected to the node ND ＳＷ and the source of the transistor ML is connected to ground. In each of the converters 20[1] to 20[n], the first end of the inductor L2 is connected to a node ND ＳＷ The second ends of all the inductors L2 in the converters 20[1] to 20[n] are connected to the output node ND ＯＵＴ are commonly connected to

[0093] The control circuit 30 is connected to the gates of the transistors M1 to M4, and also to the gates of the transistors ML and MH in each of the converters 20[1] to 20[n]. The control circuit 30 controls the states (on / off states) of the transistors M1 to M4 individually by supplying gate signals G1 to G4 to the transistors M1 to M4. In addition, the control circuit 30 controls the states (on / off states) of the transistors ML and MH individually by supplying gate signals GL and GH to the gates of the transistors ML and MH in each of the converters 20[1] to 20[n]. By controlling the states of the transistors M1 to M4 and the transistors ML and MH by the control circuit 30, the input voltage V ＩＮ The lower desired output voltage V ＯＵＴ is the output node ND ＯＵＴ occurs in.

[0094] The control circuit 30 includes the components shown in Fig. 7. That is, the control circuit 30 in the power supply device 1B includes an error amplifier 31, ramp circuits 32_1 and 32_2, current information acquisition circuits 33_1 and 33_2, adders 34_1 and 34_2, PWM comparators 35_1 and 35_2, and controllers 36_1 and 36_2. However, whereas the control circuit 30 in the power supply device 1A is provided with a control block consisting of the ramp circuit 32_2, the current information acquisition circuit 33_2, the adder 34_2, the PWM comparator 35_2, and the controller 36_2 for one channel, the control circuit 30 in the power supply device 1B is provided with the above control block for n channels.

[0095] 11, the control blocks for n channels provided in the control circuit 30 of the power supply device 1B are referred to as control blocks BLK[1] to BLK[n]. The operation of each of the control blocks BLK[1] to BLK[n] is similar to that of the control blocks in the first embodiment.

[0096] The control blocks BLK[1] to BLK[n] execute switching control for the switching output stage 21 of the converters 20[1] to 20[n]. At this time, the control block BLK[i] executes switching control for the switching output stage 21 of the converter 20[i]. That is, the control block BLK[i] supplies gate signals GH and GL to the transistors MH and ML of the converter 20[i]. i represents any natural number. The switching control for the switching output stage 21 of the converter 20[i] is the same as the switching control for the switching output stage 21 in the first embodiment.

[0097] Each shift clock signal CLK2 in the control blocks BLK[1] to BLK[n] is a signal obtained by shifting the phase of the reference clock CLK1. Therefore, the reference clock signal CLK1 and all the shift clock signals CLK2 have the same frequency f ＰＷＭ The reference clock signal CLK1 and each shift clock signal CLK2 have different phases. In this case, the control circuit 30 causes the phase of the shift clock signal CLK2 in the control block BLK[1], the phase of the shift clock signal CLK2 in the control block BLK[2], ..., the phase of the shift clock signal CLK2 in the control block BLK[n] to be different from one another.

[0098] The shift clock signal CLK2 in the control block BLK[i] will be specifically referred to by the symbol "CLK2[i]." As a result, as shown in FIG. 12, the control circuit 30 causes the phase of the reference clock signal CLK1 and the phases of the (n+1) clock signals consisting of the shift clock signals CLK2[1] to CLK2[n] to differ from each other.

[0099] The shift clock signal CLK2[1] is a signal obtained by delaying the phase of the reference clock signal CLK1 by a predetermined amount Δθ. The shift clock signal CLK2[i+1] is a signal obtained by delaying the phase of the shift clock signal CLK2[i] by a predetermined amount Δθ. The phase delay of the shift clock signal CLK2[n] from the reference clock signal CLK1 is less than 360°. When "n=3", for example, the predetermined amount Δθ is 90°.

[0100] Third Embodiment A third embodiment of the present disclosure will be described. In the third embodiment, modified techniques, applied techniques, supplementary matters, etc. to the first or second embodiment will be described.

[0101] The power supply device 1A or 1B according to the present disclosure can be applied to any device or system that requires a stable DC voltage. For example, the power supply device 1A or 1B may be applied to a power supply system for a data center. In this case, for example, the output voltage V ＯＵＴ may be 48V, and the power supply unit 1A or 1B outputs an output voltage V ＯＵＴ In recent years, reducing power consumption in data centers has become an important issue, and a transition from 12V power buses to 48V power buses is underway. It is necessary to supply power from the 48V power bus to server systems or storage devices such as semiconductor memory or magnetic disks with high efficiency, and there is a strong demand for higher power and a reduced number of components. By using power supply unit 1A or 1B, it is possible to achieve higher power through multi-phase operation, while also achieving the effect of reducing the number of components.

[0102] Alternatively, the power supply device 1A or 1B may be applied to a primary power supply in a vehicle such as an automobile. In this case, the power supply device 1A or 1B receives an input voltage V ＩＮ Directly receives the output voltage V ＯＵＴ and an output voltage V ＯＵＴmay function as a driving voltage for any system (e.g., a level 3 or higher autonomous driving system) installed in the vehicle. Alternatively, for example, power supply unit 1A or 1B may be applied to a power supply for a charging system. The charging system may charge the battery of an electric vehicle. Alternatively, for example, power supply unit 1A or 1B may be applied to a power supply for a base station.

[0103] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0104] The channel types of the FETs (field effect transistors) shown in each embodiment are merely examples. The channel type of any FET can be changed between P-channel and N-channel without departing from the spirit of the invention. Therefore, for example, the transistors M1 to M4, ML, and MH may be formed of P-channel MOSFETs, or N-channel MOSFETs and P-channel MOSFETs may be mixed among the transistors M1 to M4, ML, and MH.

[0105] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor other than an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0106] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0107] <<Supplementary Notes>> Supplementary notes are provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0108] A power supply device according to one aspect of the present disclosure is ＩＮ ) to an output voltage (V ＯＵＴ ), the power supply device (1A, 1B) configured to generate a voltage, the power supply device (1A, 1B) comprising a first converter (10), a second converter (20), and a control circuit (30), the first converter including a first switching element (M1) provided between a reference node having a potential lower than the input voltage and a first node, a second switching element (M2) provided between the first node and a second node, a third switching element (M3) provided between the second node and a third node, a fourth switching element (M4) provided between the third node and a power supply node receiving the input voltage, and a flying capacitor (C) provided between the first node and the third node. ＦＬＹ ) and an intermediate capacitor (C) provided between the second node and the reference node. ＭＩＤ ) and a first inductor (L1) provided between the first node and an output node to which the output voltage is applied, the second converter has a switching output stage (21) connected to the second node and a second inductor (L2) provided between the switching output stage and the output node, and the control circuit generates the output voltage at the output node by controlling the states of the first to fourth switching elements and the switching output stage (first configuration).

[0109] This makes it possible to form a power supply device that can perform highly efficient multiphase operation with a simple configuration.

[0110] In the power supply device according to the first configuration, the control circuit controls the states of the first to fourth switching elements to generate an intermediate voltage (V ＭＩＤ ) at the second node, and the first converter performs a step-down operation of the intermediate voltage through switching control of the first switching element and the second switching element, and the second converter performs a step-down operation of the intermediate voltage by controlling the switching output stage in a phase different from the switching control of the first switching element and the second switching element, so that the output voltage is generated at the output node by the step-down operation of the first converter and the step-down operation of the second converter (second configuration).

[0111] This allows for highly efficient multiphase operation with a simple configuration.

[0112] In the power supply device according to the second configuration, the switching output stage may have a high-side switching element (MH) provided between the second node and a switch node, and a low-side switching element (ML) provided between the switch node and the reference node, the second inductor is provided between the switch node and the output node, and the control circuit may be configured to cause the second converter to perform a step-down operation of the intermediate voltage by performing switching control of the high-side switching element and the low-side switching element in a phase different from that of the switching control of the first switching element and the second switching element (third configuration).

[0113] In the power supply device according to the third configuration, the control circuit stores information on the output voltage (V ＦＢ ) and the current information (V ＩＬ１a first controller (36_1) configured to alternately control the set of the first switching element and the third switching element and the set of the second switching element and the fourth switching element to be on or off in synchronization with a reference clock signal (CLK1) based on information on the output voltage and current information (V ＩＬ２ and a second controller (36_2) configured to alternately control the high-side switching element and the low-side switching element to be on or off in synchronization with a shift clock signal (CLK2) based on a reference clock signal (CLK1), wherein the shift clock signal is a signal obtained by shifting the phase of the reference clock signal (fourth configuration).

[0114] In the power supply device according to the fourth configuration, the first controller turns on the second switching element and the fourth switching element and turns off the first switching element and the third switching element in response to a predetermined level change in the reference clock signal, and then, ＯＮ１ ) has elapsed, the second controller turns off the second switching element and the fourth switching element and turns on the first switching element and the third switching element, and the second controller turns on the high-side switching element and turns off the low-side switching element in response to a predetermined level change in the shift clock signal, and then waits a time (t ＯＮ２ ) has elapsed, the high-side switching element is turned off and the low-side switching element is turned on (fifth configuration).

[0115] In the power supply device according to any one of the first to fifth configurations, an output capacitor (C ＯＵＴ ) may be provided (sixth configuration).

[0116] The power supply device according to any one of the first to sixth configurations may have a configuration (seventh configuration) in which a plurality of the second converters are provided.

[0117] In the power supply device according to the seventh configuration, the control circuit may perform switching control of the switching output stage of each second converter in a phase different from the switching control of the first switching element and the second switching element, and for each combination of two second converters included in the plurality of second converters, the control circuit may perform switching control of the switching output stage of one second converter and switching control of the switching output stage of the other second converter in mutually different phases (eighth configuration).

[0118] A power supply device according to one aspect of the present disclosure is ＩＮ ) is the intermediate voltage (V ＭＩＤ ), and performs a step-down operation of the intermediate voltage, a second converter (20) configured to perform a step-down operation of the intermediate voltage separately from the first converter, and a control circuit (30), and ＯＵＴ ), and the control circuit causes the first converter to perform a step-down operation and the second converter to perform a step-down operation in mutually different phases (ninth configuration).

[0119] This allows for highly efficient multi-phase operation.

[0120] 1A, 1B Power supply device 10, 20 Converter 11, 21 Switching output stage 30 Control circuit M1 to M4, ML, MH Switching elements (transistors) G1 to G4, GL, GH Gate signal C ＦＬＹ Capacitor (Flying Capacitor) C ＭＩＤ Capacitor (intermediate capacitor) C ＯＵＴ Capacitor (output capacitor) L1, L2 Inductor V ＩＮ Input voltage V ＯＵＴ Output voltage VＭＩＤ Intermediate voltage ND1 to ND4, ND ＳＷ Node ND ＯＵＴ Output node I Ｌ１ , I Ｌ２ Inductor current I ＬＤ Load current 31 Error amplifier 32_1, 32_2 Ramp circuit 33_1, 33_2 Current information acquisition circuit 34_1, 34_2 Adder 35_1, 35_2 PWM comparator 36_1, 36_2 Controller R1, R2 Resistor V ＦＢ Feedback voltage V ＲＥＦ Reference voltage V ＥＲＲ Error voltage WR ＥＲＲ Wiring V ＲＡＭＰ１ , V ＲＡＭＰ２ Lamp voltage V ＩＬ１ , V ＩＬ２ Sense voltage V ＳＬＰ１ , V ＳＬＰ２ Slope voltage CLK1 Reference clock signal CLK2 Shift clock signal 20[1] to 20[n] Converter BLK[1] to BLK[n] Control block CLK2[1] to CLK2[n] Shift clock signal

Claims

1. A power supply device configured to generate an output voltage lower than an input voltage from the input voltage, the power supply device comprising: a first converter, a second converter, and a control circuit; The first converter is a first switching element provided between a reference node having a potential lower than the input voltage and a first node; a second switching element provided between the first node and a second node; a third switching element provided between the second node and a third node; a fourth switching element provided between the third node and a power supply node receiving the input voltage; a flying capacitor provided between the first node and the third node; an intermediate capacitor provided between the second node and the reference node; a first inductor provided between the first node and an output node to which the output voltage is applied; The second converter is a switching output stage connected to the second node; a second inductor provided between the switching output stage and the output node; The control circuit generates the output voltage at the output node by controlling the states of the first to fourth switching elements and the switching output stage. , power supply.

2. The control circuit By controlling the states of the first to fourth switching elements, an intermediate voltage corresponding to a divided voltage of the input voltage is generated at the second node, and the first converter performs a step-down operation of the intermediate voltage through switching control of the first switching element and the second switching element; and The second converter performs a step-down operation of the intermediate voltage by performing a switching control of the switching output stage in a phase different from that of the first switching element and the second switching element, and the output voltage is generated at the output node by the step-down operation of the first converter and the step-down operation of the second converter.

10. The power supply device of claim 1.

3. the switching output stage includes a high-side switching element provided between the second node and a switch node, and a low-side switching element provided between the switch node and the reference node; the second inductor is provided between the switch node and the output node, The control circuit controls the high-side switching element and the low-side switching element in a phase different from that of the first switching element and the second switching element, thereby causing the second converter to perform a step-down operation of the intermediate voltage.

3. The power supply device of claim 2.

4. The control circuit a first controller configured to alternately control the set of the first switching element and the third switching element and the set of the second switching element and the fourth switching element to be on or off in synchronization with a reference clock signal based on information about the output voltage and information about a current through the first inductor; a second controller configured to alternately control the high-side switching element and the low-side switching element to be turned on or off in synchronization with a shift clock signal based on information about the output voltage and information about a current through the second inductor; The shift clock signal is a signal obtained by shifting the phase of the reference clock signal.

4. The power supply device according to claim 3.

5. the first controller turns on the second switching element and the fourth switching element and turns off the first switching element and the third switching element in response to a predetermined level change in the reference clock signal, and then turns off the second switching element and the fourth switching element and turns on the first switching element and the third switching element when a time corresponding to information on the output voltage and information on the current of the first inductor has elapsed; The second controller turns on the high-side switching element and turns off the low-side switching element when a predetermined level change occurs in the shift clock signal, and then turns off the high-side switching element and turns on the low-side switching element when a time corresponding to the output voltage information and the second inductor current information has elapsed.

5. The power supply device according to claim 4.

6. An output capacitor is provided between the output node and the reference node.

6. The power supply device according to claim 1.

7. A plurality of the second converters are provided.

6. The power supply device according to claim 1.

8. the control circuit performs switching control of the switching output stage of each second converter in a phase different from that of the switching control of the first switching element and the second switching element; For each combination of two second converters included in the plurality of second converters, the control circuit executes switching control of the switching output stage of one second converter and switching control of the switching output stage of the other second converter in mutually different phases.

8. The power supply device of claim 7.

9. a first converter configured to generate an intermediate voltage that is a divided voltage of an input voltage and to perform a step-down operation of the intermediate voltage; a second converter configured to perform a step-down operation of the intermediate voltage separately from the first converter; a control circuit that generates an output voltage lower than the intermediate voltage based on the step-down operation of the first converter and the step-down operation of the second converter; The control circuit causes the first converter to perform a step-down operation and the second converter to perform a step-down operation in mutually different phases. , power supply.