Control circuit and DC / DC converter

Abstract

Control circuits (200, 200a) control multi-phase DC / DC converters (100, 100a) including switching output stages of a plurality of channels (Ch1-Ch4). A multi-phase controller (204) that determines the number of effective channels in accordance with a load current (Iout) is provided, and the multi-phase controller (204) is constituted such that, when the number of effective channels is to be increased, the number of effective channels is set to the maximum number of channels once.

Description

Control circuit and DC / DC converter

[0001] The present invention relates to a control circuit and a DC / DC converter controlled by the control circuit.

[0002] Conventionally, there is known a DC / DC converter that has a switching output stage for multiple channels and switches between active channels to supply power to a load (see, for example, Patent Document 1). In this DC / DC converter, a control circuit switches the number of active channels based on the load current supplied to the load.

[0003] JP 2017-135812 A

[0004] In DC / DC converters, the load current may fluctuate when the load output fluctuates or when the load is replaced. If the load current increases suddenly, the charge drawn from the output capacitor becomes greater than the charge charging the output capacitor, causing the output voltage to drop. This drop in output voltage may cause the load to operate unstable.

[0005] For example, the present disclosure provides a control circuit configured to control a multi-phase DC / DC converter having a switching output stage with multiple channels, the control circuit having a multi-phase controller that determines the number of effective channels in response to a load current, and the multi-phase controller that temporarily sets the number of effective channels to the maximum when increasing the number of effective channels.

[0006] According to the present disclosure, in a multi-phase DC / DC converter, fluctuations in output voltage due to changes in load current can be suppressed.

[0007] FIG. 1 is an overall configuration diagram of a DC / DC converter according to an embodiment of the present disclosure. FIG. 2 is a schematic circuit diagram of a pulse signal generating unit. FIG. 3 is a timing chart when the number of phases of the DC / DC converter changes. FIG. 4 is a flowchart showing a procedure for changing the number of phases of the DC / DC converter. FIG. 5 is an overall configuration diagram of a DC / DC converter according to a modified example of the present disclosure. FIG. 6 is a schematic circuit diagram of a pulse signal generating unit for each channel. FIG. 7 is a timing chart showing the operation of the pulse signal generating unit. FIG. 8 is a timing chart when the number of phases of the DC / DC converter according to the modified example changes.

[0008] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings referred to, the same parts are designated by the same reference numerals, and duplicated descriptions of the same parts will be omitted as a general rule.

[0009] First, some terms used in describing the embodiments of the present disclosure will be explained. A line refers to a wiring through which an electrical signal is propagated or applied. A ground refers to a reference conductive part having a reference potential of 0 V (zero volts), or refers to the 0 V potential itself. The reference conductive part is formed of a conductor such as metal. A potential of 0 V is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground.

[0010] In this specification, a MOS (Metal Oxide Semiconductor field effect transistor) refers to a transistor whose gate structure is made up of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value, an insulating layer, and a P-channel, N-channel, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0011] "Level" refers to the level of potential, and for any signal or voltage, a Hi level has a higher potential than a Lo level. Any digital signal has a signal level of Hi level or Lo level. For any signal or voltage of interest, a signal or voltage being at a Hi level strictly means that the signal or voltage level is at a Hi level, and a signal or voltage being at a Lo level strictly means that the signal or voltage level is at a Lo level. A level for a signal may be expressed as a signal level, and a level for a voltage may be expressed as a voltage level. For any signal of interest, when the signal is at a Hi level, the inverted signal of the signal is at a Lo level, and when the signal is at a Lo level, the inverted signal of the signal is at a Hi level.

[0012] For any signal that has a Hi or Lo signal level, the period during which the signal level is Hi is referred to as the Hi level period. Similarly, for a similar signal, the period during which the signal level is Lo is referred to as the Lo level period. The same applies to any voltage that has a Hi or Lo voltage level.

[0013] When a switching transistor is in the ON state, conduction occurs between both ends of the switch. On the other hand, when the switching transistor is in the OFF state, conduction does not occur between both ends of the switch. Hereinafter, the ON state and OFF state of a switching transistor may be simply referred to as ON and OFF. Furthermore, the period in which a switching transistor is in the ON state may be referred to as the ON period, and the period in which a switching transistor is in the OFF state may be referred to as the OFF period. Furthermore, switching a switching transistor from an OFF state to an ON state may be referred to as turning ON, and switching from an ON state to an OFF state may be referred to as turning OFF.

[0014] For any transistor configured as a field-effect transistor, including a MOS field-effect transistor, the ON state refers to a state in which the drain and source of the transistor are conductive. The OFF state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as field-effect transistors. In any MOS field-effect transistor shown below, the back gate is connected to the source unless otherwise specified.

[0015] When referring to multiple parts that form a circuit, such as any circuit elements, wiring (lines), or nodes, "connection" includes mechanical connection as well as electrical connection, in other words, a state in which electricity flows. In other words, "connect" includes "electrical connection."

[0016] <DC / DC converter 100> Fig. 1 is an overall configuration diagram of a DC / DC converter 100 according to an embodiment of the present disclosure. In the DC / DC converter 100 shown in Fig. 1, a DC input voltage Vin is supplied to a line 101. A load Z is connected to an output line 102.

[0017] The DC / DC converter 100 receives an input voltage Vin on an input line 101 and generates a stepped-down output voltage Vout on an output line 102. The DC / DC converter 100 is configured with an M-channel (M is an integer equal to or greater than 2) switching output stage. The number of channels M is arbitrary and is determined according to the load, such as 2 channels, 3 channels, 4 channels, 6 channels, 8 channels, 12 channels, or 16 channels. Note that the DC / DC converter 100 of this embodiment will be described as having 4 channels. The DC / DC converter 100 has an output circuit 110 and a control circuit 200.

[0018] <Output Circuit 110> The output circuit 110 forms a half-bridge inverter for each of channels Ch1 to Ch4, and includes a high-side switching transistor M1, a low-side switching transistor M2, and an inductor L1. The output circuit 110 includes an output capacitor C1 and resistors R11 and R12 that are common to channels Ch1 to Ch4. The resistors R11 and R12 divide the output voltage Vout and generate a feedback signal Vfb that corresponds to the output voltage Vout. The feedback signal Vfb is fed back to the control circuit 200.

[0019] In this specification, channel numbers are indicated by subscripts as necessary. For example, in the case of channel Ch2, the high-side switching transistor M1_2, the low-side switching transistor M2_2, and the inductor L1_2 are indicated.

[0020] In the switching output stage of each channel, the high-side switching transistor M1 is an n-channel MOS transistor, and the low-side switching transistor M2 is an n-channel MOS transistor. The drain of the high-side switching transistor M1 is connected to the input line 101. That is, the input voltage Vin is supplied to the drain of the high-side switching transistor M1.

[0021] In the switching output stage of each channel, the source of the high-side switching transistor M1 and the drain of the low-side switching transistor M2 are connected at a connection point P1.

[0022] The source of the low-side switching transistor M2 is connected to the ground potential GND. A switching voltage Vsw is generated at the connection point P1. Note that the switching voltage Vsw is approximately the same for the enabled channels Ch1 to Ch4.

[0023] The gate of the high-side switching transistor M1 is connected to a driver 203 (described later) and is supplied with a high-side drive signal HG (described later). The gate of the low-side switching transistor M2 is connected to a driver 203 and is supplied with a low-side drive signal LG (described later). As will be described in detail later, when the high-side drive signal HG is at a high level, the high-side switching transistor M1 is turned on. When the low-side drive signal LG is at a high level, the low-side switching transistor M2 is turned on.

[0024] In each channel, a first end of an inductor L1 is connected to a connection point P1. Second ends of the inductors L1 of the channels are connected to a connection point P2 common to all the channels. A first end of an output capacitor C1 is connected to the connection point P2, and a second end of the output capacitor C1 is connected to ground potential. The connection point P2 and the first end of the output capacitor C1 are connected to an output line 102, and the output line 102 is connected to a load Z.

[0025] <Control Circuit 200> The control circuit 200 is a functional integrated circuit (IC) integrated on a single semiconductor substrate. The control circuit 200 controls the high-side switching transistor M1 and the low-side switching transistor M2 of the appropriate active channel CH1 to CH4 based on the load current Iout. Note that the high-side switching transistor M1 and the low-side switching transistor M2 may be integrated into the control circuit 200.

[0026] As shown in FIG. 1, the control circuit 200 includes an error amplifier 201 common to all channels, pulse signal generating units 202_1 to 202_4 provided for each channel, drivers 203_1 to 203_4 provided for each channel, and a multi-phase controller 204.

[0027] The error amplifier 201 amplifies the difference between a feedback signal Vfb corresponding to the output voltage Vout of the DC / DC converter 100 and its target value Vref to generate a difference signal Comp. The feedback signal Vfb is input to the inverting input terminal of the error amplifier 201, and the target value Vref is input to the non-inverting input terminal.

[0028] <Pulse Signal Generator 202> Figure 2 is a schematic circuit diagram of the pulse signal generator 202. Note that subscripts are omitted from the pulse signal generator 202 shown in Figure 2. The pulse signal generator 202 corresponds to multiple channels, that is, one is provided for each channel. As shown in Figure 2, each pulse signal generator 202 has a clock signal generator 205, a PWM comparator 206, a slope circuit 207, and an RS latch circuit 208.

[0029] A system clock signal Cks, which is a reference for the operation of the control circuit 200, is input to the clock signal generation unit 205. The clock signal generation unit 205 generates a pulse clock signal Ckd based on the system clock signal Cks. The pulse clock signal Ckd is a pulse signal that specifies the timing of the rise of a PWM (Pulse Width Modulation) signal Spwm, which will be described later. The pulse clock signal Ckd is a pulse signal that rises in synchronization with the rise or fall of the system clock signal Cks, and the timing of the rise of the pulse clock signal Ckd is determined by the channel.

[0030] The clock signal generating unit 205 of each channel generates a pulse clock signal Ckd that is out of phase with the pulse clock signal Ckd of a different channel (see FIG. 3 described later). By shifting the pulse clock signal Ckd between channels in this way, the timing of turning on and off the high-side switching transistor M1 and the timing of turning on and off the low-side switching transistor M2 of each channel are shifted, thereby suppressing the generation of switching noise.

[0031] The slope circuit 207 generates a slope signal Slp, which is, for example, a sawtooth voltage signal. The pulse clock signal Ckd is input to the slope circuit 207. The slope circuit 207 generates the slope signal Slp in synchronization with the rising edges of the pulse clock signal Ckd.

[0032] The PWM comparator 206 compares the difference signal Comp with the slope signal Slp. The difference signal Comp is input to the inverting input terminal of the PWM comparator 206, and the slope signal Slp is input to the non-inverting input terminal. The PWM comparator 206 outputs a PWM reset signal Spr indicating the comparison result between the difference signal Comp and the slope signal Slp. The PWM reset signal Spr takes a high level when the difference signal Comp is lower than the slope signal Slp, and takes a low level when the opposite is true.

[0033] The pulse clock signal Ckd is input to the set terminal of the RS latch circuit 208. Furthermore, the PWM reset signal Spr is input to the reset terminal of the RS latch circuit 208. The output of the RS latch circuit 208 is the PWM signal Spwm. Note that, as will be described in detail later, the PWM signal Spwm rises to high level when the pulse clock signal Ckd rises to high level. At this time, since the slope signal Slp is smaller than the difference signal Comp, the PWM reset signal Spr is low level. Therefore, the PWM signal Spwm output from the RS latch circuit 208 is held at high level.

[0034] The PWM reset signal Spr goes high when the slope signal Slp becomes larger than the differential signal Comp. As a result, the PWM signal Spwm output from the RS latch circuit 208 goes low. That is, the PWM signal Spwm rises when the pulse clock signal Ckd rises, and remains high while it is larger than the differential signal Comp.

[0035] The PWM signal Spwm generated by the pulse signal generating unit 202 of each channel is input to the driver 203 of each channel.

[0036] The driver 203 of each channel generates a high-side drive signal HG and a low-side drive signal LG based on the PWM signal Spwm so that the high-side switching transistor M1 and the low-side switching transistor M2 are controlled to be turned ON / OFF complementarily.

[0037] The term "complementary" refers to a state in which the high-side switching transistor M1 and the low-side switching transistor M2 are alternately turned on and off. The PWM signal Spwm is a signal that indicates the period during which the high-side switching transistor M1 is turned on.

[0038] The high level of the high-side drive signal HG is a voltage level that turns on the high-side switching transistor M1. Similarly, the high level of the low-side drive signal LG is a voltage level required to turn on the low-side switching transistor M2.

[0039] The high-side drive signal HG and the low-side drive signal LG output from the driver 203 of each channel do not necessarily have a completely switched Hi level and Lo level. For example, they may include a dead time during which both the high-side switching transistor M1 and the low-side switching transistor M2 are turned off.

[0040] The multi-phase controller 204 acquires the load current Iout and determines the number of channels (number of phases) to be enabled based on the load current Iout.

[0041] The multi-phase controller 204 outputs an enable signal Phen to the pulse signal generating unit 202 of each channel. The enable signal Phen is a signal that takes a low level or a high level, and a channel to which a high-level enable signal Phen is supplied is a valid channel.

[0042] The multi-phase controller 204 compares the load current Iout with each of the thresholds Ith1, Ith2, and Ith3, and determines the number of channels (number of phases) to be enabled based on the results. The multi-phase controller 204 sets the number of enabled channels to 1 when the load current Iout is less than the threshold Ith1, sets the number of enabled channels to 2 when the load current Iout is equal to or greater than the threshold Ith1 and less than Ith2, sets the number of enabled channels to 3 when the load current Iout is equal to or greater than the threshold Ith2 and less than Ith3, and sets the number of enabled channels to 4 when the load current Iout is equal to or greater than the threshold Ith1.

[0043] In this embodiment, when the multi-phase controller 204 determines that the number of channels to be enabled is 1, it enables channel Ch1. Similarly, when the multi-phase controller 204 determines that the number of channels to be enabled is 2, it enables channels Ch1 and Ch2, when it determines that the number of channels to be enabled is 3, it enables channels Ch1 to Ch3, and when it determines that the number of channels to be enabled is 4, it enables all channels Ch1 to Ch4. Note that the number of enabled channels and the channels to be enabled are not limited to those described above, and other combinations may be used.

[0044] The control circuit 200 and the DC / DC converter 100 including the same have the configurations described above.

[0045] <Operation of DC / DC Converter 100> The DC / DC converter 100 operates to prevent the output voltage Vout from decreasing when the load current Iout increases suddenly. Specifically, when the load current Iout exceeds a range determined by the current threshold, the multi-phase controller 204 executes a phase change operation to switch the phase so that the maximum phase is reached, regardless of the final value of the load current Iout.

[0046] In the DC / DC converter 100, when operating with a number of effective channels greater than the number of effective channels determined by the load current Iout and the thresholds Ith1, Ith2, and Ith3, problems are unlikely to occur because the switching output stages of each of the channels Ch1 to Ch4 can operate with ample capacity.

[0047] On the other hand, if the DC / DC converter 100 operates with fewer effective channels than the determined number, charge is drawn from the output capacitor C1, causing a drop in the output voltage Vout. Therefore, the multi-phase controller 204 compares the load current Iout with the thresholds Ith1, Ith2, and Ith3, and if it determines that the number of effective channels needs to be increased, it enables all channels. The operation of the DC / DC converter 100 when the number of channels changes will be described below with reference to the drawings.

[0048] Figure 3 is a timing chart showing the change in the number of phases of the DC / DC converter 100. Figure 4 is a flowchart showing the procedure for changing the number of phases of the DC / DC converter 100. The vertical and horizontal axes of the timing charts in this specification are enlarged or reduced as appropriate for ease of understanding. Furthermore, the waveforms shown are simplified, exaggerated, or emphasized for ease of understanding.

[0049] The timing chart of FIG. 3 shows changes over time in the system clock signal Cks, the load current Iout, the enable signals Phen_1 to Phen_4 of each channel, the pulse clock signals Ckd_1 to Ckd_4, the PWM signals Spwm_1 to Spwm_4, the inductor currents IL_1 to IL_4, and the output voltage Vout.

[0050] 3 shows a case where the number of active channels is 1 until time t1, and the number of phases increases due to an increase in the load current Iout at time t1. As shown in FIG. 3, the load current Iout is less than the threshold Ith1 until time t1. Therefore, the multi-phase controller 204 outputs the enable signal Phen_1 for channel Ch1 at a high level and the enable signals Phen_2 to Phen_4 for the other channels Ch2 to Ch4 at a low level.

[0051] Note that the load current Iout and the output voltage Vout are stable until time t1, so the PWM signal Spwm_1 during that period has an ON duty ratio that is sufficient to maintain a constant inductor current IL_1 and switching voltage Vsw.

[0052] 3, pulse clock signal Ckd_2 of channel Ch2 is delayed by time Tm relative to pulse clock signal Ckd_1 of channel Ch1. Similarly, pulse clock signal Ckd_3 is delayed by time Tm relative to pulse clock signal Ckd_2, and pulse clock signal Ckd_4 is delayed by time Tm relative to pulse clock signal Ckd_3. In this way, by staggering the rising edges of pulse clock signals Ckd_1 to Ckd_4, switching noise caused by simultaneous operation of each switching output stage is suppressed.

[0053] During the period up to time t1, only the enable signal Phen_1 is at Hi level. Therefore, only the pulse signal generating unit 202_1 of channel Ch1 generates a PWM signal Spwm_1 that rises to Hi level. The pulse signal generating units 202_2 to 202_4 of the remaining channels Ch2 to Ch4 output PWM signals Spwm_2 to Spwm_4, which are fixed at Lo level.

[0054] As shown in FIG. 4 , the multi-phase controller 204 acquires the load current Iout (step S101). The multi-phase controller 204 determines whether the current load current Iout is less than the threshold value Ith1 (step S102). If it is determined that the load current Iout is less than the threshold value Ith1 (Yes in step S102), the multi-phase controller 204 determines to maintain the current number of active channels and returns to acquiring the load current Iout (step S101). Note that in this embodiment, the number of active channels is increased from 1, so the load current Iout is compared with the threshold value Ith1, but the threshold value varies depending on the current number of active channels.

[0055] If it is determined that the load current Iout is equal to or greater than the threshold value Ith1 (No in step S102), the multi-phase controller 204 determines that the number of active channels needs to be increased. Then, the multi-phase controller 204 switches the enable signals Phen_2 to Phen_4 to the Hi level (step S103).

[0056] 3, after time t1, when the load current Iout is compared with the threshold value Ith1, the enable signals Phen_2 to Phen_4 are switched to a high level so that all channels are enabled. The pulse signal generating units 202_2 to 202_4 generate rising PWM signals Spwm_2 to Spwm_4 at the timing when the pulse clock signals Ckd_2 to Ckd_4 rise immediately after the enable signals Phen_2 to Phen_4 are switched to a high level (step S204). That is, in the DC / DC converter 100, when increasing the number of enabled channels, the control circuit 200 temporarily determines to set the number of enabled channels to the maximum.

[0057] Even when the DC / DC converter 100 is operated with the maximum number of enabled channels, the output voltage Vout may not immediately reach a predetermined voltage. Therefore, the DC / DC converter 100 continues to operate with all channels enabled for a predetermined period (step S105). Note that the predetermined period is the time it takes for the output voltage Vout to stabilize at a constant voltage. Therefore, instead of switching based on the period, the output voltage Vout may be monitored, and the DC / DC converter 100 may be operated with all channels enabled until the output voltage Vout stabilizes at a constant voltage.

[0058] In the DC / DC converter 100, when the number of effective channels is greater than the optimum number, the switching output stage of each channel has a margin of error, enabling stable operation. However, power consumption increases. Therefore, after a certain period of time has elapsed, the multi-phase controller 204 in the DC / DC converter 100 changes the number of effective channels to match the load current Iout (step S106). In the DC / DC converter 100, the multi-phase controller 204 determines the optimum number of effective channels based on the load current Iout.

[0059] Furthermore, in the DC / DC converter 100, the output voltage Vout may fluctuate even when the number of effective channels is reduced. Therefore, when reducing the number of effective channels in the DC / DC converter 100, the control circuit 200 reduces the number of effective channels by one channel at a time. By reducing the number in this manner, it is possible to reduce the power consumed by the DC / DC converter 100 while suppressing fluctuations in the output voltage Vout.

[0060] In this embodiment, a case is described in which the number of effective channels is increased from 1 due to an increase in the load current Iout, but the present invention is not limited to this. For example, when increasing the number of effective channels from 2, the multi-phase controller 204 first sets the number of effective channels to the maximum and then controls the number of effective channels to an optimum number.

[0061] As described above, in the multi-phase DC / DC converter 100, when the number of effective channels is increased, the multi-phase controller 204 first sets the number of effective channels to the maximum and then adjusts the number to an optimal number. When the number of effective channels is reduced, the multi-phase controller 204 reduces the number of effective channels by one channel at a time. By changing the number of effective channels as described above, the DC / DC converter 100 can suppress a drop (fluctuation) in the output voltage Vout even when the load current Iout changes. This allows the DC / DC converter 100 to supply a stable voltage and current to the load Z, thereby stabilizing the operation of the load Z.

[0062] <Modification> A modification of the present disclosure will be described with reference to the drawings. Fig. 5 is an overall configuration diagram of a DC / DC converter 100a according to a modification of the present disclosure. DC / DC converter 100a of this modification differs from DC / DC converter 100 shown in Fig. 1 in that control circuit 200a has a pulse signal generating unit 212 instead of pulse signal generating unit 202. Parts of DC / DC converter 100a that are substantially the same as those of DC / DC converter 100 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0063] When increasing the number of effective channels in the DC / DC converter 100, it is preferable to output the switching voltage Vsw and the inductor currents IL_1 to IL_4 from the switching output stages of all channels as quickly as possible. Therefore, the pulse signal generating unit 212 of each channel has an edge detection circuit 300 that detects the switching of the enable signal Phen from Lo level to Hi level and outputs the force signal Sc.

[0064] The pulse signal generating unit 212 will be described in detail with reference to the drawings. Fig. 6 is a schematic circuit diagram of the pulse signal generating unit 212 for each channel. Note that in Fig. 6, the channel numbers are not shown.

[0065] 6, the pulse signal generating unit 212 includes an edge detection circuit 300 and an OR circuit 209. The edge detection circuit 300 also includes a first flip-flop 31, a second flip-flop 32, a NOT circuit 33, and an AND circuit 34.

[0066] The first flip-flop 31 and the second flip-flop 32 are both D flip-flops having clear terminals. A system clock signal Cks is input to the clock terminals of the first flip-flop 31 and the second flip-flop 32. A system reset signal Srs is input to the reset terminals of the first flip-flop 31 and the second flip-flop 32.

[0067] The enable signal Phen is input to the D terminal of the first flip-flop 31. The first flip-flop 31 holds the state of the enable signal Phen input to the D terminal at the rising edge of the system clock signal Cks, and outputs the state as the first output signal Sq1 from the output terminal.

[0068] The first output signal Sq1 output from the output terminal is input to the D terminal of the second flip-flop 32. The second flip-flop 32 holds the state of the first output signal Sq1 input to the D terminal at the rising edge of the system clock signal Cks, and outputs it as the second output signal Sq2 from the output terminal.

[0069] The AND circuit 34 receives the first output signal Sq1 and an inverted output signal Sr obtained by inverting the second output signal Sq2 in the NOT circuit 33. The AND circuit 34 outputs a force signal Sc, which is input to the OR circuit 209. The OR circuit 209 receives the force signal Sc and the pulse clock signal Ckd.

[0070] The PWM set signal Spt, which is the output signal of the OR circuit 209, is input to a set terminal of an RS latch circuit 208. A PWM reset signal Spr, which determines the ON period of the PWM signal Spwm, is input to a reset terminal of the RS latch circuit 208. The output signal of the RS latch circuit 208 is the PWM signal Spwm.

[0071] The operation of the pulse signal generating unit 212 configured as described above will be described with reference to the drawings. Fig. 7 is a timing chart showing the operation of the pulse signal generating unit 212. The timing chart shown in Fig. 7 shows changes over time in the system clock signal Cks, the pulse clock signal Ckd, the enable signal Phen, the first output signal Sq1, the second output signal Sq2, the inverted output signal Sr, the forced signal Sc, the PWM set signal Spt, the PWM reset signal Spr, the PWM signal Spwm, and the forced drive signal Sdc.

[0072] 7, the enable signal Phen switches from low to high at time t2. The enable signal Phen is input to the D terminal of the first flip-flop 31, and the first output signal Sq1 switches to high at the rising edge of the system clock signal Cks immediately after time t2 (time t3).

[0073] The first output signal Sq1 switches to Hi level at the rising edge of the system clock signal Cks, but the timing at which the second output signal Sq2 from the second flip-flop 32 switches to Hi level is delayed. That is, at time t3, the second output signal Sq2 is Lo level. Then, at the rising edge of the system clock signal Cks immediately after the delay time for the first output signal Sq1 has elapsed (time t4), the second output signal Sq2 switches to Hi level.

[0074] That is, at time t3, the first output signal Sq1 switches to high level, but the second output signal Sq2 remains low level, and the inverted output signal Sr obtained by inverting the second output signal Sq2 is high level. Therefore, at time t3, the high-level first output signal Sq1 and the high-level inverted output signal Sr are input to the AND circuit 34. At time t3, the force signal Sc, which is the output signal of the AND circuit 34, becomes high level.

[0075] At time t4, the second output signal Sq2 switches from low to high, causing the inverted output signal Sr to switch from high to low. Furthermore, the inverted output signal Sr switching to low also causes the forcing signal Sc, which is the output of the AND circuit 34, to switch to low.

[0076] That is, the edge detection circuit 300 of the pulse signal generating section 212 generates a high-level force signal Sc from time t3 to time t4, and the force signal Sc is low before time t3 and after time t4.

[0077] From time t3 to time t4, the forcing signal Sc is at a high level, so the PWM set signal Spt, which is the output signal of the OR circuit 209, is at a high level regardless of the state of the pulse clock signal Ckd.

[0078] At time t3, the PWM reset signal Spr is at Lo level. Therefore, when a Hi-level PWM set signal Spt is input to the input terminal of the RS latch circuit 208 at time t3, the RS latch circuit 208 outputs a forced drive signal Sdc fixed at Hi level. Upon receiving the forced drive signal Sdc, the driver 203 supplies a high-side drive signal HG and a low-side drive signal LG to the high-side switching transistor M1 and the low-side switching transistor M2, respectively. The forced drive signal Sdc is a signal that drives the driver 203, and can be said to be part of the PWM signal Spwm.

[0079] In the pulse signal generating unit 212, the PWM reset signal rises to a high level at time t4, thereby resetting the output of the RS latch circuit 208. In other words, the pulse signal generating unit 212 outputs the forced drive signal Sdc to the driver 203 for a predetermined period from time t3 to time t4.

[0080] After time t4 has elapsed, the OR circuit 209 receives the low-level force signal Sc and pulse clock signal Ckd. Therefore, the PWM set signal Spt has the same waveform as the pulse clock signal Ckd, i.e., it rises to high at the same timing. The RS latch circuit 208 then outputs a PWM signal Spwm that rises when the PWM set signal Spt rises and is low while the PWM reset signal Spr is high. In other words, it is high while the PWM reset signal Spr is low.

[0081] The pulse signal generating unit 212 outputs the forced drive signal Sdc and the PWM signal Spwm through the above-described operation. The operation of increasing the number of effective channels in the DC / DC converter 100a will now be described with reference to the drawings. Figure 8 is a timing chart showing the change in the number of phases in the modified DC / DC converter 100a.

[0082] The timing chart shown in FIG. 8 shows changes over time in the system clock signal Cks, the load current Iout, the enable signals Phen_1 to Phen_4 of each channel, the pulse clock signals Ckd_1 to Ckd_4, the PWM signals Spwm_1 to Spwm_4, the inductor currents IL_1 to IL_4, and the output voltage Vout.

[0083] 8, the DC / DC converter 100a operates with one active channel, i.e., only channel Ch1 is active. At time t2, the multi-phase controller 204 determines that the number of active channels needs to be increased. At time t2, the multi-phase controller 204 simultaneously switches enable signals Phen_2 to Phen_4 to the Hi level.

[0084] The pulse signal generating units 202_1 to 202_4 of each channel forcibly fix the PWM signals Spwm_1 to Spwm_4 to the Hi level from time t3, which is the timing when the system clock signal Cks rises immediately after time t2, to time t4. Then, after time t4 has passed, the pulse signal generating units 202_1 to 202_4 of each channel Ch1 to Ch4 output the PWM signals Spwm_1 to Spwm_4 such that the pulse clock signals Ckd_1 to Ckd_4 rise and have the designated ON duty ratio.

[0085] In this modified example, channel Ch1 has already been selected as an active channel. Therefore, since the enable signal Phen_1 is at a high level around time t2, the forcing signal Sc_i remains at a low level. Therefore, the pulse signal generating unit 202_1 for channel Ch1 continues to generate the PWM signal Spwm_1 using the pulse clock signal Ckd_1 and the PWM reset signal. Furthermore, when operating with the maximum number of channels while channel Ch1 is not active, such as during startup, the pulse signal generating unit 202_1 for channel Ch1, like the pulse signal generating units 202_2 to 202_4 for the other channels, generates the PWM signal Spwm_1 that is maintained at a high level from time t3 to time t4.

[0086] In this way, when the DC / DC converter 100a determines all channels as active channels and operates, it adjusts so that all switching output stages start operating simultaneously. This shortens the time from when the multi-phase controller 204 detects an increase in the load current Iout until all channels Ch1 to Ch4 (excluding channels that were already active) start operating. As a result, it is possible to quickly respond to a decrease in the output voltage Vout due to an increase in the load current Iout, and to suppress the drop in the output voltage Vout.

[0087] <Others> The above-described embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present disclosure is indicated by the claims rather than the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0088] The control circuit (200, 200a) described above is configured to control a multiphase DC / DC converter (100, 100a) having a switching output stage for a plurality of channels (Ch1 to Ch4). It has a multiphase controller (204) that determines the number of effective channels in accordance with the load current (Iout), and the multiphase controller (204) is configured to initially set the number of effective channels to the maximum number when increasing the number of effective channels (first configuration).

[0089] In the control circuit (200, 200a) of the first configuration, the multi-phase controller (204) may be configured (second configuration) to switch to the maximum number of channels and then switch to the effective number of channels according to the load current (Iout) after a predetermined time has elapsed.

[0090] In the control circuit (200, 200a) of the first or second configuration, a configuration (third configuration) may be used in which the number of effective channels is reduced by one when switching from the maximum number of channels to the number of effective channels according to the load.

[0091] In the control circuit (200a) of any of the first to third configurations, the multi-phase controller (204) may be configured (fourth configuration) to simultaneously enable the switching output stages of at least all channels (Ch1 to Ch4) that are switched to active when switching to the maximum number of channels.

[0092] The control circuit (200, 200a) of any of the first to fourth configurations may have a configuration (fifth configuration) configured to include a plurality of pulse signal generating units (202_1 to 202_4) that generate PWM (Pulse Width Modulation) signals (Spwm_1 to Spwm_4) for each channel (Ch1 to Ch4) that determine the operation timing of the switching output stage, and a plurality of drivers (203_1 to 203_4) that drive the switching output stages of each channel (Ch1 to Ch4) in accordance with the PWM signals (Spwm_1 to Spwm_4) of each channel.

[0093] In the control circuit (200, 200a) of the fifth configuration, the pulse signal generating units (202_1 to 202_4) are configured to perform control so as to generate PWM signals (Spwm_1 to Spwm_4) that are out of phase with the PWM signals (Spwm_1 to Spwm_4) generated by the pulse signal generating units (202_1 to 202_4) of different channels (Ch1 to Ch4) (sixth configuration).

[0094] In the control circuit (200a) of the sixth configuration, the multi-phase controller (204) transmits enable signals (Phen_1 to Phen_4) that switch the channels (Ch1 to Ch4) between enabled and disabled to the pulse signal generating units (202_1 to 202_4) of the multiple channels (Ch1 to Ch4), respectively, and the pulse signal generating units (202_1 to 202_4) have edge detection units (300) configured to detect switching of the enable signals (Phen_1 to Phen_4), and the pulse signal generating units (202_1 to 202_4) are configured to output forced drive signals to the drivers (203_1 to 203_4) that forcibly operate the switching output stages for a predetermined period after the edge detection units (300) detect the enable signals (Phen_1 to Phen_4) that enable the channels (Ch1 to Ch4). This is a seventh configuration.

[0095] This is a configuration (eighth configuration) in which the control circuit (200, 200a) of any one of the first to seventh configurations is monolithically integrated on a single semiconductor substrate.

[0096] This is a configuration (ninth configuration) configured to have a DC / DC converter having a control circuit (200, 200a) of any one of the first to eighth configurations and a multi-channel switching output stage.

[0097] 100, 100a DC / DC converter 101 Input line 102 Output line 110 Output circuit 200, 200a Control circuit 201 Error amplifier 202, 212 Pulse signal generating section 203 Driver 204 Multiphase controller 205 Clock signal generating section 206 PWM comparator 207 Slope circuit 208 RS latch circuit 209 OR circuit 300 Edge detection circuit 31 First flip-flop 32 Second flip-flop 33 NOT circuit 34 AND circuit C1 Output capacitor L1 Inductor M1 High-side switching transistor M2 Low-side switching transistor R11, R12 Resistor Z Load

Claims

1. A control circuit configured to control a multi-phase DC / DC converter having a switching output stage for multiple channels, the control circuit comprising: a multi-phase controller configured to determine a number of effective channels in response to a load current, the multi-phase controller configured to initially set the number of effective channels to a maximum number when increasing the number of effective channels.

2. The control circuit according to claim 1, wherein the multi-phase controller is configured to switch to the effective channel number according to the load current when a predetermined time has elapsed after switching to the maximum channel number.

3. The control circuit according to claim 1, configured to reduce the number of effective channels by one when switching from the maximum number of channels to a number of effective channels according to a load.

4. The control circuit according to claim 1, wherein the multi-phase controller is configured to simultaneously enable the switching output stages of at least all channels that are enabled when switching to the maximum number of channels.

5. The control circuit according to claim 1, configured to have: a plurality of pulse signal generating units that generate, for each channel, a PWM signal that determines the operation timing of the switching output stage; and a plurality of drivers that drive the switching output stages of each channel based on the PWM signal.

6. The control circuit according to claim 5, wherein the plurality of pulse signal generating units are configured to generate PWM signals that are out of phase with respect to the PWM signals generated by the pulse signal generating units of the different channels.

7. The control circuit of claim 5, wherein the multi-phase controller transmits an enable signal for switching the channel between enabled and disabled to each of the plurality of pulse signal generating units, the pulse signal generating unit having an edge detection unit configured to detect switching of the enable signal, and the pulse signal generating unit is configured to output a forced drive signal to the driver for forcibly operating the switching output stage for a predetermined period after the edge detection unit detects the enable signal that enables the channel.

8. The control circuit according to claim 1, which is configured to be monolithically integrated on a single semiconductor substrate.

9. A DC / DC converter configured to have the switching output stage of multiple channels and a control circuit according to any one of claims 1 to 8.

Images