Signal transmission apparatus, electronic device, and vehicle

Abstract

A signal transmission apparatus 400 comprises: a first chip 410 into which an input pulse signal IN is input; and a second chip 420 which, by carrying out isolated communication with the first chip 410, generates an output pulse signal OUT corresponding to the input pulse signal IN and drives a switching element. The second chip 420 includes a self-diagnosis circuit 600 for diagnosing whether or not each part of the second chip 420 functions correctly in response to a self-diagnosis command B_CMD transmitted from the first chip 410. The self-diagnosis circuit 600 disables the self-diagnosis command B_CMD when the self-diagnosis operation of the second chip 420 is finished.

Description

Signal transmission devices, electronic devices, vehicles

[0001] The present disclosure relates to a signal transmission device, an electronic device, and a vehicle.

[0002] BACKGROUND ART Signal transmission devices that transmit signals between a primary circuit system and a secondary circuit system while electrically insulating the primary circuit system from the secondary circuit system have been used in various applications (such as power supply devices or motor drive devices).

[0003] An example of the related prior art is Patent Document 1 by the applicant of the present application.

[0004] International Publication No. 2022 / 070944

[0005] [Summary] However, in conventional signal transmission devices, there is room for improvement in terms of the self-diagnosis function.

[0006] For example, a signal transmission device according to the present disclosure includes a first chip configured to receive an input pulse signal, and a second chip configured to generate an output pulse signal corresponding to the input pulse signal by performing insulated communication with the first chip to drive a switch element, the second chip including a self-diagnosis circuit configured to diagnose whether each part of the second chip is functioning correctly in response to a self-diagnosis command transmitted from the first chip, and the self-diagnosis circuit disables the self-diagnosis command when the self-diagnosis operation of the second chip is completed.

[0007] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. FIG. 2 is a diagram showing the basic structure of a transformer chip. FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil is formed in the semiconductor device of FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view (separation structure) of region XIII shown in FIG. 7. FIG. 9 is a diagram schematically showing an example layout of a transformer chip. FIG. 10 is a diagram showing a detailed configuration of a signal transmission device. FIG. 11 is a diagram showing an example configuration of an electronic device incorporating a signal transmission device. FIG. 12 is a diagram showing an example of self-diagnosis operation. FIG. 13 is a diagram showing a first embodiment of a signal transmission device. FIG. 14 is a diagram showing a transmission operation of a self-diagnosis command. FIG. 15 is a diagram showing a first malfunction condition of a self-diagnosis circuit. FIG. 16 is a diagram showing a second malfunction condition of a self-diagnosis circuit. FIG. 17 is a diagram showing a second embodiment of a signal transmission device. Fig. 18 is a diagram showing the invalidation of a self-diagnosis command (self-diagnosis completed). Fig. 19 is a diagram showing the invalidation of a self-diagnosis command (secondary side restart). Fig. 20 is a diagram showing the cancellation of the invalidation of a self-diagnosis command (primary side restart). Fig. 21 is a diagram showing an example of elimination of a malfunction of a self-diagnosis circuit (input noise). Fig. 22 is a diagram showing an example of elimination of a malfunction of a self-diagnosis circuit (output noise). Fig. 23 is a diagram showing the exterior of a vehicle.

[0008] [Detailed Description] <Signal Transmission Device (Basic Configuration)> Figure 1 shows the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while isolating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is formed by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0009] The controller chip 210 is a semiconductor chip that operates by receiving a power supply voltage VCC1 (for example, a maximum of 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0010] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. In other words, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signal S11 or S21 in response to the logic level of the input pulse signal IN.

[0011] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0012] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0013] The driver chip 220 is a semiconductor chip that operates by receiving a power supply voltage VCC2 (for example, a maximum of 30 V relative to GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse receiving circuit 223, and a driver 224.

[0014] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0015] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0016] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0017] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0018] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0019] More specifically, the transformer 231 outputs a received pulse signal S12 from the secondary coil 231s in response to a transmitted pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a received pulse signal S22 from the secondary coil 232s in response to a transmitted pulse signal S21 input to the primary coil 232p.

[0020] As described above, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to a rise signal and a fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0021] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, separate from the controller chip 210 and driver chip 220, and these three chips are sealed in a single package.

[0022] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby making it possible to reduce manufacturing costs.

[0023] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (BEVs [battery electric vehicles], HEVs [hybrid electric vehicles], PHEVs / PHVs (plug-in hybrid electric vehicles / plug-in hybrid vehicles), or xEVs such as FCEVs / FCVs (fuel cell electric vehicles / fuel cell vehicles)).

[0024] <Transformer Chip (Basic Structure)> Next, the basic structure of the transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of the transformer chip 230. In the transformer chip 230 shown in this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that face each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that face each other in the vertical direction.

[0025] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0026] The primary coil 231p is laid in a spiral shape starting from a first end connected to the internal terminal X21, surrounding the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. On the other hand, the primary coil 232p is laid in a spiral shape starting from a first end connected to the internal terminal X23, surrounding the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0027] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via the conductive wiring Y21 and the via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via the conductive wiring Y22 and the via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via the conductive wiring Y23 and the via Z23. The external terminals T21 to T23 are arranged in a straight line and are used for wire bonding with the controller chip 210.

[0028] The secondary coil 231s is laid in a spiral shape starting from a first end connected to the external terminal T24, surrounding the periphery of the external terminal T24 in a counterclockwise direction, and its second end corresponding to its end point is connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape starting from a first end connected to the external terminal T26, surrounding the periphery of the external terminal T26 in a clockwise direction, and its second end corresponding to its end point is connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0029] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0030] <Transformer Chip (Two-Channel Type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which the low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which the high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0031] 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0032] The wide bandgap semiconductor is a semiconductor with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0033] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0034] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0035] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0036] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating sidewalls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0037] The insulating sidewalls 53A to 53D include a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C, and a fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form ground surfaces that are flush with the chip sidewalls 44A to 44D.

[0038] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and multiple (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The multiple interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, approximately 2 μm).

[0039] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0040] The second insulating layer 59 is formed on the first insulating layer 58. The second insulating layer 59 contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0041] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0042] The semiconductor device 5 includes a first functional device 45 formed in an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inward of the insulating layer 51 and spaced apart from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0043] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the description of the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0044] 5 to 7 , the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0045] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0046] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0047] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0048] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0049] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the form shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0050] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0051] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a plan view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a plan view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0052] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0053] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0054] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0055] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0056] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0057] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0058] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0059] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0060] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in a plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in a plan view.

[0061] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0062] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0063] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0064] The multiple high potential terminals 12 are each formed in a region close to the corresponding transformer 21A to 21D in a plan view. The closeness of the high potential terminal 12 to the transformer 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0065] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0066] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0067] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0068] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0069] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0070] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of the first low potential wirings 31, a plurality of the second low potential wirings 32, a plurality of the first high potential wirings 33, and a plurality of the second high potential wirings 34 are formed.

[0071] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0072] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0073] The plurality of first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. The plurality of first low-potential wirings 31 have the same structure. In the following, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low-potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the description of the structure of the other first low-potential wirings 31, and will be omitted.

[0074] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0075] The through wiring 71, the low-potential connecting wiring 72, the lead-out wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the lead-out wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0076] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0077] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0079] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0080] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0081] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0082] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0083] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0084] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the lead-out wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the lead-out wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the lead-out wiring 73, respectively.

[0085] 6 and 7 , the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A to 12D and the second inner ends 27 of the corresponding transformers 21A to 21D (high-potential coils 23). The plurality of first high-potential wirings 33 each have a similar structure. The following description will be given taking the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0086] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, multiple) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0087] The high-potential connecting wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connecting wiring 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connecting wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connecting wiring 81 is formed spaced apart from the low-potential connecting wiring 72 in a plan view and does not face the low-potential connecting wiring 72 in the normal direction Z. This increases the insulation distance between the low-potential connecting wiring 72 and the high-potential connecting wiring 81, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0088] The plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. Each of the plurality of pad plug electrodes 82 has a planar area that is smaller than the planar area of ​​the high potential connecting wiring 81 in a plan view.

[0089] 7, the distance D1 between the low potential terminal 11 and the high potential terminal 12 preferably exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2<D1). The distance D1 preferably exceeds the total thickness DT of the multiple interlayer insulating layers 57 (DT<D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values ​​of the distance D1 and the distance D2 are arbitrary and are adjusted appropriately depending on the dielectric strength voltage to be achieved.

[0090] 6 and 7, semiconductor device 5 includes dummy patterns 85 embedded in insulating layer 51 so as to be located around transformers 21A to 21D in a plan view.

[0091] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A to 21D. In other words, the dummy pattern 85 does not function as a part of the transformers 21A to 21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses electric field concentration on the high-potential coil 23. In this form, the dummy pattern 85 is routed with a line density per unit area equal to that of the high-potential coil 23. Having the line density of the dummy pattern 85 equal to that of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within a range of ±20% of the line density of the high-potential coil 23.

[0092] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0093] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0094] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0095] The dummy patterns 85 include floating dummy patterns formed in an electrically floating state within the insulating layer 51 so as to be positioned around the transformers 21A to 21D.

[0096] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0097] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0098] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0099] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0100] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0101] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The second functional device 60 may include a circuit network in which any two or more of the passive devices, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0102] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0103] 5 to 7 , the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape spaced apart from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0104] The device region 62 is a region that includes the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. The outer region 63 is a region outside the device region 62.

[0105] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0106] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 that surrounds the device region 62 in plan view.

[0107] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0108] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low-potential terminals 11 and the plurality of high-potential terminals 12. Furthermore, within the insulating layer 51, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating principal surface 52. Within the insulating layer 51, the seal conductor 61 may face a part of the second functional device 60 in a direction parallel to the insulating principal surface 52.

[0109] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (a plurality in this embodiment) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0110] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in a plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0111] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end-shaped form. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) form.

[0112] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0113] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined by the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0114] 7 and 8 , the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the seal conductor 61 to electrically isolate the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0115] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0116] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a band shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 is embedded toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0117] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0118] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed within the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0119] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0120] 7 , the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0121] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. Increasing the total thickness of the inorganic insulating layer 140 can increase the dielectric strength voltage on the high-potential coil 23.

[0122] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable that the first inorganic insulating layer 141 be thicker than the second inorganic insulating layer 142.

[0123] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. However, in this case, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0124] The inorganic insulating layer 140 covers the entire seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the low potential terminal 11. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the high potential terminal 12.

[0125] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0126] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Furthermore, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0127] The organic insulating layer 145 includes a first portion 146 covering the low-potential side region and a second portion 147 covering the high-potential side region. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low-potential terminal openings 148 that expose a plurality of low-potential terminals 11 (low-potential pad openings 143) in a region outside the seal conductor 61. The first portion 146 may have an overlapping portion that rises onto the periphery (overlapping portion) of the low-potential pad opening 143.

[0128] The second portion 147 is formed at a distance from the first portion 146, exposing the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0129] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0130] The embodiments of the present disclosure can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may also be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0131] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0132] In the above embodiment, an example has been described in which the second functional device 60 is formed. However, the second functional device 60 is not necessarily required and may be removed.

[0133] In the above embodiment, the dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0134] In the above-described embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes a plurality of transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0135] 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0136] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s forming a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s forming a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0137] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0138] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0139] That is, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0140] Pads a7 and b7 are connected to one end of the primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0141] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are drawn out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0142] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0143] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break has occurred in each coil, but also to appropriately reject defective products in which an abnormal resistance value has occurred in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0144] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0145] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0146] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0147] 9, the first transformer 301 to the fourth transformer 304 are arranged in a coupled arrangement according to the respective signal transmission directions. Referring to this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary chip to the secondary chip, are formed into a first pair by a first guard ring 305. Furthermore, for example, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary chip to the primary chip, are formed into a second pair by a second guard ring 306.

[0148] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0149] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0150] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0151] 9, it is desirable that the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are wound so as to form a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. By using such a configuration, the area where the primary coil and the secondary coil overlap each other becomes larger, which makes it possible to improve the transmission efficiency of the transformer.

[0152] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0153] 10 is a diagram showing a detailed configuration example of a signal transmission device. The signal transmission device 400 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 400p to the secondary circuit system 400s and drives the gate of a power transistor (not shown) provided in the secondary circuit system 400s while electrically insulating the primary circuit system 400p (VCC1-GND1 system) from the secondary circuit system 400s (VCC2-GND2 system).

[0154] The signal transmission device 400 has a plurality of external terminals (in this figure, ASC pin, BISTON pin, BISTOUT pin, COMP pin, ENA pin, FB pin, FETG pin, FLT pin, GND1 pin, GND2 pin, INA pin, INB pin, NC pin, OSFB pin, OUT1H pin, OUT1L pin, OUT2 pin, PROOUT1 pin, PROOUT2 pin, RDY pin, RT pin, SCPIN pin, SENSE pin, VCC1 pin, VCC2 pin, and VEE2 pin) as means for establishing electrical connection with the outside of the device.

[0155] On the first side (= the left side in this figure) of the package forming the signal transmission device 400, there are arranged, in order from top to bottom, a GND1 pin, a FLT pin, an ENA pin, an INA pin, an INB pin, an OSFB pin, a RDY pin, a BISTOUT pin, a VCC1 pin, a BISTON pin, an ASC pin, an NC pin, an RT pin, a COMP pin, an NC pin, a SENSE pin, an NC pin, a FETG pin, and a GND1 pin.

[0156] In this way, the external terminals of the primary circuit system 400p (ASC pin, BISTON pin, BISTOUT pin, COMP pin, ENA pin, FETG pin, FLT pin, GND1 pin, INA pin, INB pin, OSFB pin, RDY pin, RT pin, SENSE pin, VCC1 pin) may be concentrated on the first side of the package.

[0157] On the other hand, on the second side of the package (= the side opposite to the first side mentioned above, the right side in this figure), there are arranged, in order from top to bottom, a VEE2 pin, an NC pin, an OUT2 pin, an NC pin, an OUT1L pin, an NC pin, an OUT1H pin, an NC pin, a VCC2 pin, an NC pin, a GND2 pin, a GND2 pin, a SCPIN pin, a PROOUT2 pin, a PROOUT1 pin, an NC pin, an FB pin, an NC pin, and a VEE2 pin.

[0158] In this way, the external terminals of the secondary circuit system 400s (FB pin, GND2 pin, OUT1H pin, OUT1L pin, OUT2 pin, PROOUT1 pin, PROOUT2 pin, SCPIN pin, VCC2 pin, VEE2 pin) may be concentrated on the second side of the package.

[0159] A ground terminal GND1 and a negative power supply terminal VEE2 may be disposed at both ends of each of the first and second sides of the package. That is, two ground terminals GND1 and two negative power supply terminals VEE2 may be provided.

[0160] The signal transmission device 400 can be widely applied to general applications (such as motor drivers or DC / DC converters that handle high voltages) that require signal transmission between the primary circuit system 400p and the secondary circuit system 400s while isolating them from each other.

[0161] Continuing with reference to Fig. 10, the internal configuration of the signal transmission device 400 will be described. The signal transmission device 400 of this embodiment is configured by sealing a controller chip 410 (corresponding to the first chip), a driver chip 420 (corresponding to the second chip), and a transformer chip 430 (corresponding to the third chip) in a single package.

[0162] The controller chip 410 is a semiconductor chip that integrates circuit elements of the primary circuit system 400p that operates upon receiving a supply of power supply voltage VCC1 (for example, up to 7 V relative to GND1). The controller chip 410 also integrates, for example, a logic circuit 411, a UVLO (under-voltage lock out) / OVLO (over-voltage lock out) circuit 412, an internal power supply circuit 413, a switch control circuit 414, and transistors 415 to 41B.

[0163] The transistors 415, 416, 417, 419, and 41B may be, for example, NMOSFETs (N-channel type metal oxide semiconductor field effect transistors), and the transistors 418 and 41A may be, for example, PMOSFETs (P-channel type MOSFETs).

[0164] The logic circuit 411 generates a drive pulse signal PWM for a power transistor (not shown), a type of switching element, in response to the input pulse signals INA and INB. For example, if INB=H (logical level when disabled), PWM=L (fixed value), and if INB=L (logical level when enabled), PWM=INA. The logic circuit 411 also monitors various abnormality detection signals (low voltage, overvoltage, short circuit, open circuit, overheating, load power supply abnormality, etc.) from the signal transmission device 400 and drives transistors 415 and 416 based on the monitoring results to determine the logical levels of the fault signal FLT and the ready signal RDY. The logic circuit 411 also switches the operation of the entire signal transmission device 400 (enable / disable) in response to the enable signal ENA.

[0165] The logic circuit 411 also has the function of performing a self-diagnosis (so-called BIST (built-in self test)) of each part of the signal transmission device 400 in response to the self-diagnosis on signal BISTON, and determining the logic level of the self-diagnosis output signal BISTOUT by driving the transistor 417 based on the results of the self-diagnosis. In other words, the logic circuit 411 functions as part of a self-diagnosis circuit incorporated in the signal transmission device 400 (details will be described later).

[0166] The subject of the self-diagnosis may be a comparator for detecting various abnormal conditions, etc. For example, during the self-diagnosis, a pseudo abnormal signal may be injected into the comparator to be diagnosed, and it may be determined whether or not the abnormal condition is correctly detected.

[0167] Furthermore, the logic circuit 411 also has a function of determining the logic level of the switch state signal OSFB by driving the transistors 418 and 419 based on the on / off state of a power transistor (not shown) to be driven. For example, the switch state signal OSFB may be transmitted from the driver chip 420 to the controller chip 410 via the transformer chip 430. In other words, the driver chip 420 may have a function of generating the switch state signal OSFB according to the logic level of the output pulse signal OUT and feeding it back to the controller chip 410.

[0168] The UVLO / OVLO circuit 412 detects undervoltage and overvoltage of the power supply voltage VCC1, respectively, and outputs the detection results to the logic circuit 411.

[0169] The internal power supply circuit 413 generates an internal power supply voltage VREG1 from the power supply voltage VCC1.

[0170] The switch control circuit 414 is the main controller of the isolated DC / DC converter that generates the power supply voltage VCC2 from the power supply voltage VCC1 while isolating the primary circuit system 400p from the secondary circuit system 400s. Referring to the figure, the switch control circuit 414 drives the transistors 41A and 41B based on a feedback signal FB from the driver chip 420, thereby generating a gate drive signal FETG for a switch output stage (not shown) that is externally connected to an FETG pin. The switch output stage may include, for example, a flyback transformer.

[0171] The switch control circuit 414 has a function of detecting the primary current flowing through the flyback transformer via the SENSE pin. The switch control circuit 414 can also compensate the phase of the feedback loop using the COMP pin. Furthermore, the switch control circuit 414 can adjust the drive frequency of the switch output stage using the RT pin.

[0172] The transistor 415 establishes or breaks conduction between the FLT pin and the ground terminal in response to instructions from the logic circuit 411. For example, when the driver chip 420 detects overheating or an abnormality in the load power supply, the transistor 415 turns on, and the fault signal FLT output from the FLT pin goes low (= the logical level when an abnormality is detected).

[0173] The transistor 416 connects / disconnects the RDY pin and the ground terminal in response to an instruction from the logic circuit 411. For example, when a low voltage or an overvoltage is detected in either the controller chip 410 or the driver chip 420, the transistor 416 is turned on, and the ready signal RDY output from the RDY pin becomes low level (= the logical level when an abnormality is detected).

[0174] The transistor 417 establishes or breaks conduction between the BISTOUT pin and the ground terminal in response to an instruction from the logic circuit 411. For example, when the self-diagnosis result of the signal transmission device 400 is NG, the transistor 417 is turned on, and the self-diagnosis output signal BISTOUT output from the BISTOUT pin becomes low level (= the logical level when an abnormality is detected).

[0175] The source of the transistor 418 is connected to the power supply terminal. The drains of the transistors 418 and 419 are both connected to the OSFB pin. The source of the transistor 419 is connected to the ground terminal. The gates of the transistors 418 and 419 are both connected to the logic circuit 411. The transistors 418 and 419 connected in this manner form a half-bridge output stage for outputting the switch state signal OSFB in response to an instruction from the logic circuit 411.

[0176] The source of the transistor 41A is connected to the power supply terminal. The drains of the transistors 41A and 41B are both connected to the FETG pin. The source of the transistor 41B is connected to the ground terminal. The gates of the transistors 41A and 41B are both connected to the switch control circuit 414. The transistors 41A and 41B connected in this manner form a half-bridge output stage for outputting the gate drive signal FETG in response to an instruction from the switch control circuit 414.

[0177] The driver chip 420 is a semiconductor chip that integrates circuit elements of the secondary circuit system 400s that operates upon receiving a supply of power supply voltage VCC2 (for example, a maximum of 30 V relative to GND2). The driver chip 420 integrates, for example, a logic circuit 421, a UVLO / OVLO circuit 422, an internal power supply circuit 423, a feedback signal generation circuit 424, comparators 425 to 427, a transistor 428, a driver 429, and transistors 42A to 42C.

[0178] The transistors 428, 42A, and 42C may be, for example, NMOSFETs, and the transistor 42B may be, for example, a PMOSFET.

[0179] The logic circuit 421 drives the gates of power transistors (not shown) connected to the OUT1H pin and the OUT1L pin by driving the driver 429 in response to the drive pulse signal PWM input via the transformer chip 430. The OUT1H pin and the OUT1L pin may be connected to the gates of the power transistors outside the signal transmission device 400. The logic circuit 421 also has a function of transmitting various abnormality detection signals (such as a low voltage detection signal UVLO, an over voltage detection signal OV, and a short circuit detection signal SCD) from the driver chip 420 to the controller chip 410 via the transformer chip 430.

[0180] Furthermore, the logic circuit 421 also has a function of transmitting the self-diagnosis result (BIST_result) on the driver chip 420 side to the controller chip 410 via the transformer chip 430. In other words, the logic circuit 421 functions as part of a self-diagnosis circuit incorporated in the signal transmission device 400 (details will be described later).

[0181] The UVLO / OVLO circuit 422 detects undervoltage and overvoltage of the power supply voltage VCC2, respectively, and outputs the detection results to the logic circuit 421.

[0182] The internal power supply circuit 423 generates an internal power supply voltage VREG2 from the power supply voltage VCC2.

[0183] The feedback signal generating circuit 424 generates a feedback signal FB having duty information corresponding to the power supply voltage VCC2 generated by the aforementioned isolated DC / DC converter, and outputs the signal from the secondary circuit system 400s to the primary circuit system 400p. Note that a divided voltage of the power supply voltage VCC2 may be input to the feedback signal generating circuit 424 via the FB pin.

[0184] The comparator 425 compares the terminal voltage of the OUT1H pin with the threshold voltage VOUT2ON to generate a Miller clamp control signal. The logic circuit 421 drives the transistor 428 in response to the Miller clamp control signal.

[0185] A comparator 426 compares the terminal voltage of the SCPIN pin with a threshold voltage VSCDET to detect a short circuit in the power transistor.

[0186] A comparator 427 compares the terminal voltage of the PROOUT1 pin with a threshold voltage Vosfb to detect the switch state (= the on / off state of the power transistor).

[0187] The transistor 428 connects or disconnects the OUT2 pin from the ground terminal in response to an instruction from the logic circuit 421. The OUT2 pin may be directly connected to the gate of the power transistor. For example, when the OUT1H pin is pulled low to turn the power transistor off, the transistor 428 turns on. As a result, the power transistor is reliably maintained in the off state.

[0188] The driver 429 outputs an output pulse signal OUT to the gate of the power transistor in response to an instruction from the logic circuit 421. Referring to this figure, the driver 429 includes a transistor 429H (e.g., a PMOSFET) and a transistor 429L (e.g., an NMOSFET).

[0189] The transistor 429H connects / disconnects the power supply terminal and the OUT1H pin in response to instructions from the logic circuit 421. For example, when the drive pulse signal PWM is at a high level, the transistor 429H is turned on, and the OUT1H pin (and hence the output pulse signal OUT applied to the gate of the power transistor) becomes a high level.

[0190] The transistor 429L establishes or breaks conduction between the OUT1L pin and the ground terminal in response to instructions from the logic circuit 421. For example, when the drive pulse signal PWM is at a low level, the transistor 429L is turned on, and the OUT1L pin (and therefore the output pulse signal OUT applied to the gate of the power transistor) is at a low level.

[0191] Thus, transistors 429H and 429L function as a half-bridge output stage for the gate drive.

[0192] The transistor 42A connects / disconnects the SCPIN pin and the GND2 pin in response to instructions from the logic circuit 421. For example, the transistor 42A is turned off when OUT1H=H, and turned on when OUT1H=L. The transistor 42A functions as a discharge switch that discharges an external capacitor (not shown) connected between SCPIN and GND2 by turning on / off in a complementary manner with a power transistor (not shown).

[0193] The transistor 42B connects / disconnects the PROOUT1 pin and the VEE2 pin in response to an instruction from the logic circuit 421. The PROOUT1 pin may be connected to the gate of the power transistor via an external gate resistor.

[0194] The transistor 42C connects / disconnects the PROOUT2 pin and the VEE2 pin in response to an instruction from the logic circuit 421. The PROOUT2 pin may be connected to the gate of the power transistor via an external gate resistor.

[0195] The transformer chip 430 is a semiconductor chip that integrates a transformer for transmitting signals in both directions while insulating the controller chip 410 and the driver chip 420 from each other.

[0196] The signal transmission device 400 of this configuration example has an independent transformer chip 430 equipped with only a transformer, in addition to the controller chip 410 and the driver chip 420, and these three chips are sealed in a single package.

[0197] With this configuration, the controller chip 410 and the driver chip 420 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby making it possible to reduce manufacturing costs.

[0198] Furthermore, both the controller chip 410 and the driver chip 420 can be manufactured using existing processes with proven results, and there is no need to conduct new reliability tests, which can contribute to shortening development time and reducing development costs.

[0199] Furthermore, even when a DC isolation element other than a transformer (for example, a photocoupler) is used, it is possible to easily accommodate this by simply replacing the transformer chip 430, which eliminates the need to redevelop the controller chip 410 and the driver chip 420, thereby contributing to shortening the development period and reducing development costs.

[0200] 11 is a diagram showing an example of the configuration of an electronic device equipped with a signal transmission device 400. Electronic device A of this example configuration has an upper gate driver IC1H(u / v / w), a lower gate driver IC1L(u / v / w), upper power transistors 2H(u / v / w), lower power transistors 2L(u / v / w), an ECU [electronic control unit] 3, and a motor 4.

[0201] The upper gate driver IC1H(u / v / w) drives the upper power transistor 2H(u / v / w) by generating an upper gate drive signal in response to an upper gate control signal input from the ECU 3 while insulating the ECU 3 from the upper power transistor 2H(u / v / w).

[0202] The lower gate drivers IC1L(u / v / w) drive the lower power transistors 2L(u / v / w) by generating lower gate drive signals in response to lower gate control signals input from the ECU 3 while insulating the ECU 3 from the lower power transistors 2L(u / v / w).

[0203] The signal transmission device 400 described above can be suitably used as the upper gate driver IC1H(u / v / w) and the lower gate driver IC1L(u / v / w).

[0204] The upper power transistors 2H (u / v / w) serve as upper switches forming a three-phase (U-phase / V-phase / W-phase) half-bridge output stage, and are connected between the power system power supply end (= the application end of the load power supply voltage PVDD) and each phase input end of the motor 4.

[0205] The lower power transistors 2L (u / v / w) are connected between each phase input terminal of the motor 4 and the power system ground terminal as lower switches that form a three-phase (U phase / V phase / W phase) half-bridge output stage.

[0206] In this figure, an IGBT (insulated gate bipolar transistor) is used as each of the upper power transistor 2H (u / v / w) and the lower power transistor 2L (u / v / w), but it is also possible to use, for example, a MOSFET instead of the IGBT.

[0207] The ECU 3 drives the upper power transistors 2H (u / v / w) and the lower power transistors 2L (u / v / w) via the upper gate driver IC1H (u / v / w) and the lower gate driver IC1L (u / v / w), respectively, thereby controlling the rotational driving of the motor 4. The ECU 3 also has the function of monitoring the FLT pin and RDY pin of each of the upper gate driver IC1H (u / v / w) and the lower gate driver IC1L (u / v / w), and performing various safety controls based on the monitoring results.

[0208] Furthermore, the ECU 3 uses the self-diagnosis on signal BISTON to output the self-diagnosis results of the signal transmission device 400, and also has the function of checking whether the various protection circuits (low voltage protection, overvoltage protection, overheat protection, and short circuit protection) of the signal transmission device 400 are normal or not based on the logic level of the self-diagnosis output signal BISTOUT.

[0209] The motor 4 is a three-phase motor that is rotationally driven in response to three-phase drive voltages U / V / W input from three-phase (U-phase / V-phase / W-phase) half-bridge output stages.

[0210] 12 is a diagram showing an example of the self-diagnosis operation in the signal transmission device 400. In this diagram, from top to bottom, the power supply voltage VCC1, the self-diagnosis execution signal BIST (OC), the gate drive signal FETG, the power supply voltage VCC2, the self-diagnosis execution signal BIST (UV1 / OV1 / UV2 / OV2 / SCD), the ready signal RDY, the fault signal FLT, the self-diagnosis on signal BISTON, the self-diagnosis output signal BISTOUT, the input pulse signal INA, the enable signal ENA, and the output pulse signal OUT are depicted.

[0211] The self-diagnosis execution signal BIST (OC) is a signal for executing a self-diagnosis of the switch control circuit 414 (particularly, the overcurrent protection function that monitors the primary current of the flyback transformer), which is the main control element of the isolated DC / DC converter. On the other hand, the self-diagnosis execution signals BIST (UV1 / OV1 / UV2 / OV2 / SCD) are signals for executing a self-diagnosis of each of the undervoltage protection function, overvoltage protection function, and short-circuit protection function.

[0212] The input pulse signal INA is a pulse signal input to the INA pin, while the output pulse signal OUT is a pulse signal output from the OUT1H pin and the OUT1L pin to the gates of the power transistors.

[0213] At time t11, when the power supply voltage VCC1 exceeds the undervoltage release threshold VUVLO1H, the self-diagnosis execution signal BIST(OC) rises from low level to high level, so that the self-diagnosis of the overcurrent protection function built into the isolated DC / DC converter is performed first among multiple diagnostic targets.

[0214] If the self-diagnosis result of the overcurrent protection function is OK, switching control of the gate drive signal FETG starts at time t12, and the power supply voltage VCC2 generated by the isolated DC / DC converter rises.

[0215] At time t13, when the power supply voltage VCC2 exceeds the low voltage release threshold VUVLO2H, the ready signal RDY rises from low to high (=the RDY pin is in a high impedance state). Note that the ready signal RDY may also fall from high to low at time t14, which is a predetermined time after time t13.

[0216] At time t13, the rising edge of the ready signal RDY triggers the self-diagnosis execution signal BIST (UV1 / OV1 / UV2 / OV2 / SCD) to rise from low to high, thereby executing self-diagnosis of each of the undervoltage protection function, overvoltage protection function, and short-circuit protection function, among the multiple diagnostic targets.

[0217] In particular, in the driver chip 420, the self-diagnosis execution signal BIST (UV2 / OV2 / SCD) is raised to a high level in response to a self-diagnosis command B_CMD transmitted from the controller chip 410 (details will be described later). This self-diagnosis command B_CMD may not be transmitted from the controller chip 410 unless the self-diagnosis result of the overcurrent protection function described above is OK.

[0218] In the signal transmission device 400, the signal transmission path from the driver chip 420 to the controller chip 410 is also subject to diagnosis.

[0219] During the self-diagnosis operation, the input pulse signals INA and INB and the enable signal ENA may be disabled. That is, during the self-diagnosis operation, the output pulse signal OUT may be fixed to a low level, and the power transistor may be maintained in an off state.

[0220] Furthermore, the self-diagnosis on signal BISTON (and thus the self-diagnosis output signal BISTOUT) may also be disabled during the self-diagnosis operation. For example, the self-diagnosis on signal BISTON may be masked during the self-diagnosis operation. With this masking process, even if the self-diagnosis on signal BISTON is raised to a high level during the self-diagnosis operation, the self-diagnosis output signal BISTOUT remains fixed at a low level.

[0221] Furthermore, during the self-diagnostic operation, the ready signal RDY and the fault signal FLT may not be fixed but may be set to a logic level according to the internal state of the signal transmission device 400. This makes it possible to check from outside the signal transmission device 400 whether the self-diagnostic operation is being executed.

[0222] When a predetermined time has elapsed since the start of the self-diagnosis operation other than the overcurrent protection function, at time t15, the self-diagnosis results obtained up to that point are stored, thereby ending the series of self-diagnosis operations.

[0223] Thereafter, when the self-diagnosis on signal BISTON is raised to high level at any timing, the self-diagnosis result at that time is latched and output as the self-diagnosis output signal BISTOUT. At this time, if the self-diagnosis result is NG, BISTOUT becomes L, and if the self-diagnosis result is OK, BISTOUT becomes HiZ. The signal latch of the self-diagnosis output signal BISTOUT may be reset at the falling edge of the ready signal RDY.

[0224] As described above, in the self-diagnosis sequence shown in the figure, the self-diagnosis of the isolated DC / DC converter (especially the overcurrent protection function) is performed first. If the diagnosis result of the overcurrent protection function is OK, the isolated DC / DC converter is permitted to start up, and self-diagnosis of functions other than the overcurrent protection function (low-voltage protection function, overvoltage protection function, short-circuit protection function, and the signal transmission path from the driver chip 420 to the controller chip 410) is performed in sequence.

[0225] 13 is a diagram showing a first embodiment (corresponding to a comparative example to be compared with the second embodiment described later) of a signal transmission device 400. The signal transmission device 400 of this embodiment includes an isolated signal transmission circuit 500 and a self-diagnosis circuit 600.

[0226] The isolated signal transmission circuit 500 transmits a drive pulse signal PWM (shown in the figure as transmission pulse signals Sr1 and Sf1 and reception pulse signals Sr2 and Sf2) from the primary circuit system 400p to the secondary circuit system 400s while insulating the primary circuit system 400p from the secondary circuit system 400s via transformers 431 and 432 integrated on a transformer chip 430. Referring to the figure, the isolated signal transmission circuit 500 transmits an input pulse signal IN of the primary circuit system 400p as an output pulse signal OUT of the secondary circuit system 400s.

[0227] For example, the isolated signal transmission circuit 500 includes a pulse transmitting circuit 501, a pulse receiving circuit 502, and buffers 503 and 504 in addition to the transformers 431 and 432 described above.

[0228] The pulse transmitting circuit 501 pulse-drives one of the transmission pulse signals Sr1 and Sf1 in accordance with the logic level of the input pulse signal IN. For example, when the pulse transmitting circuit 501 notifies that the input pulse signal IN is at a high level, it pulse-drives (outputs a single or multiple transmission pulses) the transmission pulse signal Sr1 to be applied to the primary winding of the transformer 431. On the other hand, when the pulse transmitting circuit 501 notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal Sf1 to be applied to the primary winding of the transformer 432.

[0229] For example, the pulse transmission circuit 501 generates seven pulses at 10 MHz when the transmission pulse signals Sr1 and Sf1 are pulse-driven.

[0230] The pulse transmitting circuit 501 may be one of the functional blocks included in the aforementioned logic circuit 411. In other words, the pulse transmitting circuit 501 may be integrated into the controller chip 410 of the primary circuit system 400p.

[0231] In addition, the pulse transmitting circuit 501 also has the function of appropriately generating transmission pulse signals Sr1 and Sf1 to re-notify the pulse receiving circuit 502 of the logical level of the input pulse signal IN when the logical levels of the input pulse signal IN and the output pulse signal OUT (and therefore the switch state signal OSFB) do not match.

[0232] For example, consider a case where the switch state signal OSFB is at a low level (= a logical level indicating that the output pulse signal OUT is at a low level) even though the input pulse signal IN is at a high level. In this case, the pulse transmitting circuit 501 generates a transmission pulse signal Sr1 (= a signal indicating that the input pulse signal IN is at a high level) by itself to set the output pulse signal OUT to a high level.

[0233] Conversely, consider a case where the switch state signal OSFB is at a high level (= a logical level indicating that the output pulse signal OUT is at a high level) even though the input pulse signal IN is at a low level. In this case, the pulse transmitting circuit 501 generates a transmission pulse signal Sf1 (= a signal indicating that the input pulse signal IN is at a low level) by itself to set the output pulse signal OUT to a low level.

[0234] The pulse receiving circuit 502 generates an output pulse signal OUT in response to the received pulse signals Sr2 and Sf2 input from the transformers 431 and 432 via buffers 503 and 504, respectively. For example, when the pulse receiving circuit 502 detects an induced pulse of the received pulse signal Sr2 appearing in the secondary winding of the transformer 431 in response to the pulse drive of the transmitted pulse signal Sr1, it raises the output pulse signal OUT to a high level. On the other hand, when the pulse receiving circuit 502 detects an induced pulse of the received pulse signal Sf2 appearing in the secondary winding of the transformer 432 in response to the pulse drive of the transmitted pulse signal Sf1, it lowers the output pulse signal OUT to a low level. In other words, the logic level of the output pulse signal OUT switches in response to the logic level of the input pulse signal IN.

[0235] The pulse receiving circuit 502 may be one of the functional blocks included in the aforementioned logic circuit 421. In other words, the pulse receiving circuit 502 may be integrated into the driver chip 420 of the secondary circuit system 400s.

[0236] The transformer 431 outputs a reception pulse signal Sr2 from a secondary winding in response to a transmission pulse signal Sr1 input to a primary winding, while the transformer 432 outputs a reception pulse signal Sf2 from a secondary winding in response to a transmission pulse signal Sf1 input to a primary winding.

[0237] The transformers 431 and 432 are both integrated into the transformer chip 430. The transformer chip 430 uses the transformers 431 and 432 to insulate the controller chip 410 from the driver chip 420, and outputs the transmission pulse signals Sr1 and Sf1 input from the pulse transmission circuit 501 to the pulse reception circuit 502 as reception pulse signals Sr2 and Sf2, respectively.

[0238] As described above, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals Sr1 and Sf1 (corresponding to a rise signal and a fall signal), and then transmitted from the primary circuit system 400p to the secondary circuit system 400s via two systems of transformers 431 and 432.

[0239] Although not shown in the figure, a noise mask circuit may be incorporated in the subsequent stage of each of the transformers 431 and 432 as a means for suppressing malfunction due to common mode noise.

[0240] The self-diagnosis circuit 600 diagnoses whether each component of the signal transmission device 400 is functioning correctly. The self-diagnosis circuit 600 is provided in both the controller chip 410 and the driver chip 420. In particular, the self-diagnosis circuit 600 shares part of the isolated signal transmission circuit 500 as a means for transmitting a self-diagnosis command B_CMD (= a command instructing the secondary circuit system 400s to start a self-diagnosis operation) from the primary circuit system 400p to the secondary circuit system 400s. Referring to this figure, the self-diagnosis circuit 600 shares the transformer 432 (= a transformer for transmitting the gate-off command G_OFF) as a transformer for transmitting the self-diagnosis command B_CMD.

[0241] By adopting such a configuration, it is not necessary to provide a dedicated signal transmission path (a separate transformer), and therefore it is possible to reduce the size of the transformer chip 430 (and therefore the entire signal transmission device 400).

[0242] However, when the transformer 432 is shared, the driver chip 420 must be able to determine whether the received pulse signal Sf2 transmitted via the transformer 432 is a power transistor gate-off command G_OFF or a self-diagnosis command B_CMD. Therefore, the self-diagnosis circuit 600 transmits the self-diagnosis command B_CMD by driving the transformer 432 at a pulse period different from that during normal operation (= when the gate-off command G_OFF is transmitted).

[0243] For example, when transmitting a normal gate-off command G_OFF via the transformer 432, the isolated signal transmission circuit 500 generates seven pulses at 10 MHz (pulse period T0 = 0.1 μs) in the transmission pulse signal Sf1 (and consequently in the reception pulse signal Sf2 transmitted via the transformer 432) using the falling edge of the input pulse signal IN as a trigger.

[0244] On the other hand, the self-diagnosis circuit 600 generates periodic pulses at 1 MHz (pulse period T1=1 μs) in the transmission pulse signal Sf1 (and consequently in the reception pulse signal Sf2 transmitted via the transformer 432) when transmitting the self-diagnosis command B_CMD via the transformer 432. The periodic pulses generated when transmitting the self-diagnosis command B_CMD may be generated one at a time, or may be generated as a series of pulse groups (for example, a group of seven pulses generated at 10 MHz).

[0245] By such pulse driving, it can be determined whether the received pulse signal Sf2 transmitted via the transformer 432 is a gate-off command G_OFF for the power transistor or a self-diagnosis command B_CMD.

[0246] Referring to this figure, the self-diagnosis circuit 600 of this embodiment includes, for example, an edge detection circuit 610, a pulse transmission circuit 620, and a pulse reception circuit 630.

[0247] The edge detection circuit 610 detects the rising edge of the ready signal RDY and outputs the detection result to the pulse transmission circuit 620 .

[0248] When the edge detection circuit 610 detects the rising edge of the ready signal RDY, the pulse transmission circuit 620 drives the transmission pulse signal Sf1 to be applied to the primary winding of the transformer 432 with a pulse period different from that used during normal operation (i.e., when the gate-off command G_OFF is transmitted). By this pulse driving, the self-diagnosis command B_CMD is transmitted to the secondary circuit system 400s.

[0249] The pulse receiving circuit 630 determines whether the received pulse signal Sf2 transmitted via the transformer 432 is a self-diagnosis command B_CMD and generates a self-diagnosis enable signal B_EN. The self-diagnosis enable signal B_EN can be understood as the aforementioned self-diagnosis execution signal BIST (UV2 / OV2 / SCD). Referring to the figure, the pulse receiving circuit 630 includes signal interval determination circuits 631 and 632, an inverter 633, an AND gate 634, a counter 635, and a latch 636.

[0250] The signal interval determination circuit 631 outputs an internal signal S1 for verifying that the signal interval T2 of the pulse group generated in the received pulse signal Sf2 at a predetermined pulse period T1 (= the period during which the received pulse signal Sf2 is maintained at a low level without being pulse-driven) is shorter than the upper limit time TH (e.g., TH = 2.3 μs). Note that the internal signal S1 goes high when a pulse is generated in the received pulse signal Sf2, and then goes low when the upper limit time TH has elapsed without the next pulse being generated. In other words, the internal signal S1 is maintained at a high level when T2 < TH, and falls to a low level when T2 > TH.

[0251] The signal interval determination circuit 632 outputs an internal signal S2 for verifying that the signal interval T2 of the received pulse signal Sf2 is longer than a lower limit time TL (e.g., TH = 0.45 μs). For example, the internal signal S2 goes low at the pulse generation timing of the received pulse signal Sf2, and then goes high when the lower limit time TL has elapsed without the next pulse being generated. That is, the internal signal S2 is maintained at a low level when T2 < TL, and rises to a high level when T2 > TL. In other words, when T2 > TL, the internal signal S2 is pulse-driven with a pulse period T1.

[0252] The inverter 633 inverts the logic level of the received pulse signal Sr2 (corresponding to the gate-on command G_ON) to generate the internal signal S3. Therefore, the internal signal S3 is at a low level when the received pulse signal Sr2 is at a high level, and is at a high level when the received pulse signal Sr2 is at a low level.

[0253] The AND gate 634 generates an internal signal S4 by performing a logical AND operation on the internal signals S1 and S3. Therefore, the internal signal S4 is at low level when at least one of the internal signals S1 and S3 is at low level, and is at high level when both the internal signals S1 and S3 are at high level. In other words, the internal signal S4 is at low level when the pulse period T of the received pulse signal Sf2 is longer than the upper limit time TH, or when a pulse is generated in the received pulse signal Sr2.

[0254] The counter 635 generates the internal signal S4 by counting the number of pulses of the internal signal S2. For example, the counter 635 raises the internal signal S5 to a high level when the number of pulses of the internal signal S2 reaches a predetermined threshold (e.g., three pulses). The count value of the counter 635 (= the number of pulses of the internal signal S2) is reset to zero when the internal signal S4 falls to a low level.

[0255] The latch 636 receives the internal signal S5 and generates the self-diagnosis enable signal B_EN. For example, the latch 636 may hold the self-diagnosis enable signal B_EN at a high level (= the logic level when enabled) for a predetermined period Tx from the rising timing of the internal signal S5. Furthermore, the latch 636 may return the self-diagnosis enable signal B_EN to a low level (= the logic level when disabled) after the above-mentioned period Tx has elapsed. With this configuration, self-diagnosis of the driver chip 420 is performed only while the self-diagnosis enable signal B_EN is at a high level, without the need for a self-diagnosis cancel signal.

[0256] According to the pulse receiving circuit 630 of this configuration example, when the signal interval T2 of the pulse group generated in the received pulse signal Sf2 during the pulse period T1 falls within a predetermined range (TL<T2<TH) and the same pulse group is detected consecutively over multiple periods (e.g., three or more periods), the received pulse signal Sf2 is determined to be a self-diagnosis command B_CMD. As a result, the self-diagnosis enable signal B_EN is raised to a high level. Note that even when the self-diagnosis command B_CMD is determined based on three pulses, generating seven pulses provides redundancy as a countermeasure against pulse dropouts.

[0257] Furthermore, when the self-diagnosis command B_CMD is transmitted, the transmission pulse signal Sf1 is pulse-driven, just as when the gate of the power transistor is turned off. Therefore, the output pulse signal OUT is pulled down to a low level by the pulse receiving circuit 502 of the isolated signal transmission circuit 500, and the power transistor is turned off. Therefore, the motor 4 does not malfunction during the self-diagnosis of the signal transmission device 400.

[0258] Furthermore, a method of distinguishing between the gate-off command G_OFF and the self-diagnosis command B_CMD based on differences in pulse periods is less likely to result in erroneous discrimination than a method of distinguishing between the two commands based on differences in the number of pulses.

[0259] During normal operation of the signal transmission device 400, the input pulse signal IN may alternate between high and low levels. If the period at which the logic level of the input pulse signal IN is switched is close to the pulse period (e.g., 1 μs) of the transmission pulse signal Sf1 generated by the pulse transmission circuit 620 of the self-diagnosis circuit 600, the signal interval T2 of the reception pulse signal Sf2 generated at each falling edge of the input pulse signal IN may appear to fall within the aforementioned predetermined range (TL<T2<TH), which may result in erroneous determination of the self-diagnosis command B_CMD. Therefore, it is desirable that the counter 635 of the pulse reception circuit 630 be reset each time a pulse of the transmission pulse signal Sr1 (and therefore the reception pulse signal Sr2) is generated, as in this configuration example.

[0260] 14 is a diagram showing the transmission operation of the self-diagnosis command B_CMD. In this diagram, from the top, the received pulse signal Sf2, the internal signals S1, S2, and S5, and the self-diagnosis enable signal B_EN are depicted.

[0261] As shown in this figure, consider the case where the signal interval T2 of the received pulse signal Sf2 falls within a predetermined range (TL<T2<TH). In this case, continuous pulses are generated in the internal signal S2 while the internal signal S1 is maintained at a high level. At this time, the counter 635 continues to count the number of pulses of the internal signal S2 without being reset, and when the count value reaches a predetermined threshold value (three pulses in this figure), the internal signal S5 rises to a high level. As a result, the self-diagnosis enable signal B_EN rises to a high level, and the self-diagnosis operation of the driver chip 420 is performed over a period Tx. Note that after the pulse generation of the received pulse signal Sf2 stops and the upper limit time TH has elapsed, the internal signal S1 falls to a low level, the counter 635 is reset, and the internal signal S5 also falls to a low level.

[0262] On the other hand, consider a case where the signal interval T2 of the received pulse signal Sf2 is shorter than the lower limit time TL. In this case, the internal signal S2 does not rise to a high level (no pulse generation occurs), and the count value of the counter 635 does not reach the predetermined threshold. As a result, the self-diagnosis enable signal B_EN is maintained at a low level. Therefore, the self-diagnosis operation of the driver chip 420 is not performed.

[0263] Also, consider a case where the signal interval T2 of the received pulse signal Sf2 is longer than the upper limit time TH. In this case, the internal signal S2 rises to a high level each time a pulse of the received pulse signal Sf2 is generated, and the count value of the counter 635 is incremented by one. However, if the upper limit time TH elapses before the next pulse generation timing arrives, the internal signal S1 falls to a low level. Therefore, the counter 635 is reset, and the internal signal S5 does not rise to a high level. As a result, the self-diagnosis enable signal B_EN is maintained at a low level. Therefore, the self-diagnosis operation of the driver chip 420 is not performed.

[0264] <Considerations Concerning the Generation of Unintended Self-Diagnosis Commands> Incidentally, if the self-diagnosis command B_CMD is erroneously detected during normal operation of the signal transmission device 400, an abnormality detection will be notified to the outside of the device even though no abnormality has occurred.

[0265] For example, in the signal transmission device 400 of the first embodiment, an unintended self-diagnosis command B_CMD may occur due to noise superimposed on the input pulse signal IN or the output pulse signal OUT. Hereinafter, conditions for malfunction of the self-diagnosis circuit 600 will be considered with reference to the drawings.

[0266] 15 is a diagram showing a first malfunction condition of the self-diagnostic circuit 600. This diagram shows, from top to bottom, the input pulse signal IN, the on signal Son, and the off signal Soff. The on signal Son and the off signal Soff can be understood as received pulse signals Sr2 and Sf2, respectively, that have been filtered to remove common-mode noise.

[0267] As shown by the dashed line frame in the figure, the input pulse signal IN may chatter at a pulse period T1 (e.g., 1 μs) due to noise superposition, etc. In this case, if the high-level period of the input pulse signal IN is equal to or shorter than the filter time (e.g., 60 ns), only the off signal Soff may be pulse-driven, triggered by the falling edge of the input pulse signal IN.

[0268] At this time, the signal interval T2 of the pulse group generated in the off signal Soff with the pulse period T1 can satisfy the discrimination condition for the self-diagnosis command B_CMD (TL<T2<TH). Note that since the on signal Son is not pulse-driven, the counter 625 (see FIG. 13) mentioned above is not reset. Therefore, if the pulse driving of the off signal Soff is repeated three times, the off signal Soff may be erroneously discriminated as the self-diagnosis command B_CMD.

[0269] 16 is a diagram showing the second malfunction condition of the self-diagnostic circuit 600. From top to bottom, the diagram depicts the input pulse signal IN, the output pulse signal OUT, the switch state signal OSFB, the on signal Son, and the off signal Soff. For ease of explanation, the delay time of the switch state signal OSFB is not shown.

[0270] When the input pulse signal IN is at a low level, the output pulse signal OUT should also be at a low level. At this time, the switch state signal OSFB also becomes low level. However, as shown in the dashed line frame in the figure, if noise or the like is superimposed on the output pulse signal OUT, there is a risk that the switch state signal OSFB may accidentally repeat high and low levels in the pulse period T1.

[0271] Referring to this figure, when the output pulse signal OUT is higher than the upper threshold voltage VosfbH, the switch state signal OSFB is at a high level. On the other hand, when the output pulse signal OUT is lower than the lower threshold voltage VosfbL (<VosfbH), the switch state signal OSFB is at a low level.

[0272] In the above situation, a period may occur in which the switch state signal OSFB is at a high level even though the input pulse signal IN is at a low level. During such a period, the off signal Soff is pulse-driven to match the logic levels of the input pulse signal IN and the switch state signal OSFB.

[0273] At this time, the signal interval T2 of the pulse group generated in the off signal Soff with the pulse period T1 can satisfy the discrimination condition for the self-diagnosis command B_CMD (TL<T2<TH). Note that since the on signal Son is not pulse-driven, the counter 625 (see FIG. 13) mentioned above is not reset. Therefore, if the pulse driving of the off signal Soff is repeated three times, the off signal Soff may be erroneously discriminated as the self-diagnosis command B_CMD.

[0274] In view of the above considerations, a second embodiment capable of preventing the unintended start of a self-diagnostic operation will be proposed below.

[0275] <Signal Transmission Device (Second Embodiment)> Fig. 17 is a diagram showing a second embodiment of a signal transmission device 400. The signal transmission device 400 of this embodiment is based on the first embodiment (Fig. 13) described above, and is provided with measures to prevent the unintended start of a self-diagnosis operation.

[0276] As described above, the signal transmission device 400 includes the controller chip 410, the driver chip 420, and the transformer chip 430.

[0277] An input pulse signal IN is input to the controller chip 410. The driver chip 420 performs insulated communication with the controller chip 410 to generate an output pulse signal OUT according to the input pulse signal IN and drive a power transistor (corresponding to a switch element). The transformer chip 430 forms an insulated communication path between the controller chip 410 and the driver chip 420.

[0278] Referring to this figure, the signal transmission device 400 includes a logic circuit 411 as a component of a controller chip 410. The signal transmission device 400 also includes a logic circuit 421, a driver 429, and a self-diagnosis circuit 600 as components of a driver chip 420. The signal transmission device 400 also includes transformers 431 and 432 as components of a transformer chip 430. Of course, the signal transmission device 400 may also include other components (see FIG. 10 ).

[0279] The logic circuit 411 includes a controller 411a, pulse generating circuits 411b, 411c, and 411d, an oscillator 411e, a multiplexer 411f, and buffers 411g and 411h.

[0280] The controller 411a drives the pulse generating circuit 411b using the rising edge and the rising edge of the input pulse signal IN as triggers, respectively. The controller 411a also drives the pulse generating circuit 411b when the logic levels of the input pulse signal IN and the switch state signal OSFB do not match.

[0281] The pulse generating circuit 411b receives an instruction from the controller 411a and generates a first pulse signal CK1 of, for example, 10 MHz (pulse period T11=0.1 μs). The first pulse signal CK1 is used to transmit a gate-on command G_ON and a gate-off command G_OFF of the power transistor, i.e., an on signal Son and an off signal Soff.

[0282] The pulse generating circuit 411c generates a second pulse signal CK2 of, for example, 1 MHz (pulse period T12=1 μs). The second pulse signal CK2 is used when transmitting a self-diagnosis command B_CMD (details will be described later).

[0283] The pulse generating circuit 411d receives an instruction from the controller 411a and generates a third pulse signal CK3 of, for example, 200 kHz (pulse period T13=5 μs). The third pulse signal CK3 is used when transmitting the operating state notification ST.

[0284] The operation state notification ST is a notification signal for notifying the driver chip 420 of the completion of startup of the controller chip 410. For example, the operation state notification ST may be transmitted when (1) UVLO detection of the controller chip 410 is in a released state, (2) a self-diagnosis is in progress (excluding OC) or has been completed, (3) a self-diagnosis command B_CMD is in a non-transmission state, (4) a gate-on command G_ON and a gate-off command G_OFF corresponding to the input pulse signal IN are not being transmitted, and (5) a gate-on command G_ON and a gate-off command G_OFF corresponding to the detection of a mismatch between the input pulse signal IN and the switch state signal OSFB are not being transmitted.

[0285] Note that, due to the transmission conditions (1) and (2) above, the operating state notification ST is not issued from the time the controller chip 410 is started until the time the driver chip 420 is started. Also, the transmission conditions (3) to (5) above correspond to the necessary conditions for sharing the transformer 432 (=transformer for transmitting the off signal Soff) as a means for transmitting the gate off command G_OFF, the self-diagnosis command B_CMD, and the operating state notification ST, respectively.

[0286] The oscillator 411e generates a reference clock signal CK0 of, for example, 200 kHz and outputs it to the pulse generating circuit 411d.

[0287] The multiplexer 411f outputs any one of the first pulse signal CK1, the second pulse signal CK2, and the third pulse signal CK3 to the buffer 411g or 411h.

[0288] For example, when the multiplexer 411f transmits a gate-on command G_ON for the power transistor, it outputs a first pulse signal CK1 to the buffer 411g to drive the transformer 431. On the other hand, when the multiplexer 411f transmits a gate-off command G_OFF for the power transistor, it outputs the first pulse signal CK1 to the buffer 411h to drive the transformer 432.

[0289] That is, the controller chip 410 notifies the driver chip 420 via the transformer 431 (corresponding to the first isolation element) that the input pulse signal IN is at a high level (=a logical level for turning on the power transistor). Also, the controller chip 410 notifies the driver chip 420 via the transformer 432 (corresponding to the second isolation element) that the input pulse signal IN is at a low level (=a logical level for turning off the power transistor).

[0290] Furthermore, when transmitting a self-diagnosis command B_CMD, the multiplexer 411f outputs a second pulse signal CK2 to the buffer 411h to drive the transformer 432. Furthermore, when transmitting an operating state notification ST, the multiplexer 411f outputs a third pulse signal CK3 to the buffer 411h to drive the transformer 432.

[0291] The buffer 411g outputs the output signal (=first pulse signal CK1) of the multiplexer 411f to the transformer 431 as a transmission pulse signal Sr1.

[0292] The buffer 411h outputs the output signal of the multiplexer 411f (=any of the first pulse signal CK1, the second pulse signal CK2, and the third pulse signal CK3) to the transformer 431 as a transmission pulse signal Sf1.

[0293] In this way, the controller chip 410 drives the transformer 432 with a pulse period T11 (e.g., 10 MHz) when transmitting a power transistor gate-off command G_OFF. The controller chip 410 also drives the transformer 432 with a pulse period T12 (e.g., 1 MHz) when transmitting a self-diagnosis command B_CMD. Furthermore, the controller chip 410 also drives the transformer 432 with a pulse period T13 (e.g., 200 kHz) when transmitting its own operating state notification ST.

[0294] The transformers 431 and 432 provide insulation between the controller chip 410 and the driver chip 420, and transmit the transmission pulse signals Sr1 and Sf1 as reception pulse signals Sr2 and Sf2, respectively.

[0295] The logic circuit 421 receives the reception pulse signals Sr2 and Sf2 and generates an on signal Son and an off signal Soff. Referring to the figure, the logic circuit 421 includes receivers 421a and 421b, NOR gates 421c and 421d, and an inverter 421e.

[0296] The receiver 421a generates a reception pulse signal Sa and a mask signal MSKa from the reception pulse signal Sr2. The mask signal MSKa may be generated to have a wider pulse width than the reception pulse signal Sa, for example.

[0297] The receiver 421b generates a reception pulse signal Sb and a mask signal MSKb from the reception pulse signal Sf2. The mask signal MSKb may be generated to have a wider pulse width than the reception pulse signal Sb, for example.

[0298] The NOR gate 421c generates an ON signal Son by performing a NOR operation on the received pulse signal Sa and the mask signal MSKb. The ON signal Son goes low when at least one of the received pulse signal Sa and the mask signal MSKb is high. On the other hand, the ON signal Son goes high when both the received pulse signal Sa and the mask signal MSKb are low.

[0299] The NOR gate 421d generates an off signal Soff by performing a NOR operation on the received pulse signal Sb and the mask signal MSKa. The off signal Soff goes low when at least one of the received pulse signal Sb and the mask signal MSKa is high. On the other hand, the off signal Soff goes high when both the received pulse signal Sb and the mask signal MSKa are low.

[0300] The NOR gates 421c and 421d function as noise cancellers for removing common mode noise superimposed on the received pulse signals Sa and Sb, respectively.

[0301] The inverter 421e inverts the logic level of the mask signal MSKa to generate the internal signal SG. Therefore, the internal signal SG is at a low level when the mask signal MSKa is at a high level. On the other hand, the internal signal SG is at a high level when the mask signal MSKa is at a low level.

[0302] The driver 429 generates an output pulse signal OUT in response to the on signal Son and the off signal Soff. For example, the driver 429 receives the pulse drive of the on signal Son to raise the output pulse signal OUT to a high level (= a logical level for turning on the power transistor). On the other hand, the driver 429 receives the pulse drive of the off signal Soff to lower the output pulse signal OUT to a low level (= a logical level for turning off the power transistor).

[0303] <Self-diagnosis Circuit> The configuration and operation of the self-diagnosis circuit 600 will now be described with reference to Fig. 17. The self-diagnosis circuit 600 diagnoses whether each component of the driver chip 420 is functioning correctly in response to a self-diagnosis command B_CMD transmitted from the controller chip 410.

[0304] In particular, the self-diagnosis circuit 600 shares the transformer 432 (=transformer for transmitting the off signal Soff) as means for transmitting a self-diagnosis command B_CMD (=operation start trigger of the self-diagnosis circuit 600) from the controller chip 410 to the driver chip 420.

[0305] By adopting such a configuration, it is not necessary to provide a dedicated signal transmission path (a separate transformer), and therefore it is possible to reduce the size of the transformer chip 430 (and therefore the entire signal transmission device 400).

[0306] However, when the transformer 432 is shared, the driver chip 420 must be able to determine whether the received pulse signal Sf2 transmitted via the transformer 432 is a power transistor gate-off command G_OFF or a self-diagnosis command B_CMD. Therefore, the controller chip 410 transmits the self-diagnosis command B_CMD by driving the transformer 432 with a pulse period different from that used when transmitting the gate-off command G_OFF.

[0307] For example, when the controller chip 410 transmits a normal gate-off command G_OFF via the transformer 432, it generates seven pulses at 10 MHz (pulse period T11 = 0.1 μs) in the transmission pulse signal Sf1 (and consequently in the reception pulse signal Sf2 transmitted via the transformer 432) using the falling edge of the input pulse signal IN as a trigger.

[0308] On the other hand, when transmitting the self-diagnosis command B_CMD via the transformer 432, the controller chip 410 generates periodic pulses at 1 MHz (pulse period T12=1 μs) in the transmission pulse signal Sf1 (and consequently in the reception pulse signal Sf2 transmitted via the transformer 432). The periodic pulses generated when transmitting the self-diagnosis command B_CMD may be generated one by one, or may be generated as a series of pulse groups (for example, a group of multiple pulses generated at 10 MHz).

[0309] By such pulse driving, the driver chip 420 can determine whether the received pulse signal Sf2 transmitted via the transformer 432 is a gate-off command G_OFF for the power transistor or a self-diagnosis command B_CMD.

[0310] Referring to this figure, the self-diagnosis circuit 600 includes a command discrimination circuit 640 and a discrimination control circuit 650 .

[0311] The command discrimination circuit 640 discriminates whether the received pulse signal Sf2 is the self-diagnosis command B_CMD or not. The command discrimination circuit 640 includes a pulse width expansion circuit 641, signal interval determination circuits 642 and 643, an AND gate 644, a counter 645, and a latch 646.

[0312] The pulse width expansion circuit 641 expands the pulse width of the off signal Soff to generate the internal signal SIN.

[0313] The signal interval determination circuit 642 generates an internal signal SB for verifying that the signal interval T2 of the pulse group generated in the off signal Soff at a predetermined pulse period T1 (=the period during which the off signal Soff is maintained at a low level without being pulse-driven) is shorter than a predetermined upper limit time TH. The upper limit time TH may be set to, for example, 2.3 μs.

[0314] Referring to this figure, the signal interval determination circuit 642 includes a capacitor C1, a current source CS1, transistors N1 and N2 (for example, NMOSFETs), and a resistor R1.

[0315] The gate of transistor N1 is connected to the application terminal of internal signal SIN. The first terminals of current source CS1 and resistor R1 are all connected to a first potential terminal (e.g., an internal power supply terminal). The second terminal of current source CS1, the first terminal of capacitor C1, the drain of transistor N1, and the gate of transistor N2 are all connected to the application terminal of internal signal SA. The second terminal of resistor R1 and the drain of transistor N2 are all connected to the application terminal of internal signal SB. The second terminal of capacitor C1 and the sources of transistors N1 and N2 are all connected to a second potential terminal (e.g., a ground terminal).

[0316] When the internal signal SIN rises to a high level, the transistor N1 turns on. At this time, the capacitor C1 is discharged and the internal signal SA falls to a low level. Therefore, the transistor N2 turns off. As a result, the internal signal SB rises to a high level.

[0317] Thereafter, when the internal signal SIN falls to a low level, the transistor N1 turns off. Therefore, the internal signal SA rises as the capacitor C1 charges. Then, when the upper limit time TH elapses without the next pulse being generated in the internal signal SIN, the internal signal SA reaches the on-threshold value Vth(N2) of the transistor N2. As a result, the transistor N2 turns on, and the internal signal SB falls to a low level.

[0318] That is, the internal signal SB is maintained at a high level when T2<TH, and falls to a low level when T2>TH.

[0319] The signal interval determination circuit 643 generates an internal signal SD for verifying that the signal interval T2 of the pulse group generated in the off signal Soff at a predetermined pulse period T1 is longer than a predetermined lower limit time TL, which may be set to, for example, 0.45 μs.

[0320] Referring to this figure, the signal interval determination circuit 643 includes a capacitor C2, a current source CS2, transistors N3 and N4 (for example, NMOSFETs), a resistor R2, and an inverter INV1.

[0321] The gate of transistor N3 is connected to the application terminal of internal signal SIN. The first terminals of current source CS2 and resistor R2 are all connected to a first potential terminal (e.g., an internal power supply terminal). The second terminal of current source CS2, the first terminal of capacitor C2, the drain of transistor N3, and the gate of transistor N4 are all connected to the application terminal of internal signal SC. The second terminal of resistor R2 and the drain of transistor N4 are all connected to the input terminal of inverter INV1. The output terminal of inverter INV1 is connected to the application terminal of internal signal SD. The second terminal of capacitor C2 and the sources of transistors N3 and N4 are all connected to a second potential terminal (e.g., a ground terminal).

[0322] When the internal signal SIN rises to a high level, the transistor N3 turns on. At this time, the capacitor C2 is discharged and the internal signal SC falls to a low level. Therefore, the transistor N4 turns off. As a result, the internal signal SD falls to a low level.

[0323] After that, when the internal signal SIN falls to a low level, the transistor N3 turns off. Therefore, the internal signal SC rises as the capacitor C2 charges. Then, when the lower limit time TL elapses without the next pulse being generated in the internal signal SIN, the internal signal SC reaches the on-threshold voltage Vth(N4) of the transistor N4. As a result, the transistor N4 turns on, and the internal signal SD falls to a high level.

[0324] That is, the internal signal SD is maintained at a low level when T2<TL, and rises to a high level when T2>TL, i.e., when T2>TL, the internal signal SD is pulse-driven with a pulse period of T1.

[0325] The AND gate 644 generates the internal signal SH by performing a logical AND operation on the internal signals SB, SG, and SS and the UVLO detection signal UV2. The internal signal SH goes low when at least one of the internal signals SB, SG, and SS and the UVLO detection signal UV2 is low. On the other hand, the internal signal SH goes high when all of the internal signals SB, SG, and SS and the UVLO detection signal UV2 are high.

[0326] That is, the internal signal SH becomes low level when the signal interval T2 of the off signal Soff is longer than the upper limit time TH, when a pulse is generated in the mask signal MSKa (and thus the received pulse signal Sr2 corresponding to the gate-on command G_ON), ​​when UVLO is detected in the driver chip 420, or when the invalidation condition of the self-diagnosis command B_CMD (details will be described later) is satisfied in the discrimination control circuit 650.

[0327] The counter 645 generates the internal signal SE by counting the number of pulses of the internal signal SD. Referring to the figure, the counter 645 includes D flip-flops FF1 to FF3.

[0328] The clock terminal (>) of each of the D flip-flops FF1 to FF3 is connected to the terminal to which the internal signal SD is applied. The reset terminal (◯) of each of the D flip-flops FF1 to FF3 is connected to the terminal to which the internal signal SH is applied. The data terminal (D) of the D flip-flop FF1 is connected to the terminal to which a high-level voltage is applied (for example, an internal power supply terminal). The output terminal (Q) of the D flip-flop FF1 is connected to the data terminal (D) of the D flip-flop FF2. The output terminal (Q) of the D flip-flop FF2 is connected to the data terminal (D) of the D flip-flop FF3. The output terminal (Q) of the D flip-flop FF3 is connected to the terminal to which the internal signal SE is applied.

[0329] For example, the counter 645 raises the internal signal SE to a high level when the number of pulses of the internal signal SD reaches a predetermined threshold (three in this figure). The count value of the counter 645 (= the number of pulses of the internal signal SD) is reset to zero when the internal signal SH falls to a low level.

[0330] The latch 646 receives the internal signal SE and generates the self-diagnosis enable signal B_EN. More specifically, the latch 646 holds the self-diagnosis enable signal B_EN at a high level (= the logic level when enabled) for a predetermined period Tx from the rising edge of the internal signal SE. The latch 646 also returns the self-diagnosis enable signal B_EN to a low level (= the logic level when disabled) after the predetermined period Tx has elapsed. This configuration eliminates the need to receive a self-diagnosis termination command from the controller chip 410. The latch 646 also raises the self-diagnosis completion signal F to a high level at the same time as returning the self-diagnosis enable signal B_EN to a low level.

[0331] In the command discrimination circuit 640 of this configuration example, when the signal interval T2 of the pulse group generated in the off signal Soff in the pulse period T1 falls within a predetermined range (TL<T2<TH) and the same pulse group is detected consecutively over multiple periods (e.g., three or more periods), it is determined that the received pulse signal Sf2 (and therefore the off signal Soff) is the self-diagnosis command B_CMD. As a result, the self-diagnosis enable signal B_EN is raised to a high level.

[0332] Furthermore, when the self-diagnosis command B_CMD is transmitted, the received pulse signal Sf2 is pulse-driven, just as when the gate-off command G_OFF is transmitted. Therefore, the logic circuit 421 and the driver 429 cause the output pulse signal OUT to fall to a low level. Therefore, the power transistor is not erroneously turned on during the self-diagnosis of the signal transmission device 400.

[0333] Furthermore, a method for distinguishing between the gate-off command G_OFF and the self-diagnosis command B_CMD based on the difference in pulse period is less likely to result in erroneous determination than a method for distinguishing between the two commands based on the difference in the number of pulses. These advantages are basically the same as those of the first embodiment (FIG. 13).

[0334] The determination control circuit 650 switches the logic level of the internal signal SS depending on whether the invalidation condition of the self-diagnosis command B_CMD is satisfied. Referring to the figure, the determination control circuit 650 includes an OR gate 651, a pulse width expansion circuit 652, an OR gate 653, an operation state determination circuit 654, a NAND gate 655, an inverter 656, a counter 657, an OR gate 658, a latch 659, and an inverter 65A.

[0335] The OR gate 651 generates an internal signal SI by performing a logical OR operation on the on signal Son and the off signal Soff. The internal signal SI is at high level when at least one of the on signal Son and the off signal Soff is at high level. On the other hand, the internal signal SI is at low level when both the on signal Son and the off signal Soff are at low level.

[0336] The pulse width expansion circuit 652 expands the pulse width of the internal signal SI to generate the internal signal SJ.

[0337] The OR gate 653 generates an internal signal SK by performing a logical OR operation on the internal signal SJ and the self-diagnosis enable signal B_EN. The internal signal SK is at a high level when at least one of the internal signal SJ and the self-diagnosis enable signal B_EN is at a high level. On the other hand, the internal signal SK is at a low level when both the internal signal SJ and the self-diagnosis enable signal B_EN are at a low level.

[0338] The operating state determination circuit 654 generates an internal signal SM for determining whether the pulse driving of the internal signal SK (and consequently the pulse driving of the on signal Son and the off signal Soff) has been interrupted for a predetermined determination time T3, which may be set to, for example, 30 μs.

[0339] Referring to this figure, the operating state determination circuit 654 includes a capacitor C3, a current source CS3, transistors N5 and N6 (for example, NMOSFETs), and a resistor R3.

[0340] The gate of transistor N5 is connected to the application terminal of internal signal SK. The first terminals of current source CS3 and resistor R3 are all connected to a first potential terminal (e.g., an internal power supply terminal). The second terminal of current source CS3, the first terminal of capacitor C3, the drain of transistor N5, and the gate of transistor N6 are all connected to the application terminal of internal signal SL. The second terminal of resistor R3 and the drain of transistor N6 are all connected to the application terminal of internal signal SM. The second terminal of capacitor C3 and the sources of transistors N5 and N6 are all connected to a second potential terminal (e.g., a ground terminal).

[0341] When the internal signal SK rises to a high level, the transistor N5 turns on. At this time, the capacitor C3 is discharged and the internal signal SL falls to a low level. Therefore, the transistor N6 turns off. As a result, the internal signal SM rises to a high level.

[0342] After that, when the internal signal SK falls to a low level, the transistor N5 is turned off. Therefore, the internal signal SL rises as the capacitor C3 is charged. Then, when the determination time TK elapses without the next pulse being generated in the internal signal SK, the internal signal SL reaches the on-threshold voltage Vth (N6) of the transistor N6. As a result, the transistor N6 is turned on, and the internal signal SM falls to a low level.

[0343] That is, the internal signal SM falls to a low level when the pulse driving of the internal signal SK is interrupted over the determination time TK.

[0344] The NAND gate 655 generates the internal signal SN by performing a NAND operation on the internal signal SM, the self-diagnosis enable signal B_EN, and the UVLO detection signal UV2. The internal signal SN goes high when at least one of the internal signal SM, the self-diagnosis enable signal B_EN, and the UVLO detection signal UV2 is low. On the other hand, the internal signal SN goes low when all of the internal signal SM, the self-diagnosis enable signal B_EN, and the UVLO detection signal UV2 are high.

[0345] The inverter 656 generates the internal signal SO by inverting the logic level of the internal signal SN. Therefore, the internal signal SO is at a low level when the internal signal SN is at a high level, and is at a high level when the internal signal SN is at a low level.

[0346] The counter 657 generates the internal signal SP by counting the number of pulses of the off signal Soff. For example, the counter 657 raises the internal signal SP to high level when the number of pulses of the off signal Soff reaches six. The count value of the counter 657 (= the number of pulses of the off signal Soff) is reset to zero when the internal signal SO falls to low level.

[0347] The OR gate 658 generates an internal signal SQ by performing a logical OR operation on the self-diagnosis completion signal SF, the internal signal SP, and the output pulse signal OUT. The internal signal SQ goes high when at least one of the self-diagnosis completion signal SF, the internal signal SP, and the output pulse signal OUT is high. On the other hand, the internal signal SQ goes low when all of the self-diagnosis completion signal SF, the internal signal SP, and the output pulse signal OUT are low.

[0348] The latch 659 is a sequential circuit that determines the logic level of the internal signal SR in response to the internal signals SO and SQ. For example, the latch 659 may include an RS flip-flop. Referring to this figure, the latch 659 sets the internal signal SR output from the output terminal (Q) to a high level in response to a rising edge of the internal signal SQ input to the set terminal (S). On the other hand, the latch 659 resets the internal signal SR output from the output terminal (Q) to a low level in response to a falling edge of the internal signal SO input to the reset terminal (S).

[0349] The inverter 65A inverts the logic level of the internal signal SR to generate the internal signal SS. Therefore, the internal signal SS is at a low level when the internal signal SR is at a high level, and is at a high level when the internal signal SR is at a low level.

[0350] The self-diagnosis circuit 600 of this embodiment invalidates the self-diagnosis command B_CMD when any one of a plurality of invalidation conditions is satisfied. More specifically, the self-diagnosis circuit 600 invalidates the self-diagnosis command B_CMD when (1) the self-diagnosis operation of the driver chip 420 is completed, (2) six pulses of the off signal Soff are detected, or (3) the output pulse signal OUT switches from low level to high level.

[0351] Condition (1) is a first invalidation condition that can be met when both the controller chip 410 and the driver chip 420 have completed their startup. Condition (2) is a second invalidation condition that can be met when the driver chip 420 is restarted. Condition (3) is a third invalidation condition that can be met when the power transistor is driven.

[0352] First, a situation in which condition (1) is satisfied will be described. When the driver chip 420 completes its self-diagnosis operation and the self-diagnosis completion signal SF rises to a high level, the internal signal SQ rises to a high level. At this time, the internal signal SR is set to a high level, so the internal signal SS falls to a low level. Therefore, the internal signal SH is fixed to a low level, so the counter 645 is maintained in a reset state. As a result, even if the self-diagnosis command B_CMD is received, the internal signal SE (and hence the self-diagnosis enable signal B_EN) does not rise to a high level.

[0353] In this way, the self-diagnosis circuit 600 invalidates the self-diagnosis command B_CMD when the self-diagnosis operation of the driver chip 420 is completed.

[0354] Next, a situation in which condition (2) is satisfied will be described. Consider the case where only the driver chip 420 is restarted after both the controller chip 410 and the driver chip 420 have completed startup. In this case, the operating controller chip 410 continues to pulse the off signal Soff with a pulse period T13 (e.g., 5 μs) as the operating state notification ST. Therefore, the internal signal SM does not fall to a low level. Therefore, the counter 657 is basically not reset.

[0355] Here, when the number of pulses of the off signal Soff input to the counter 657 reaches six, the internal signal SP rises to a high level, causing the internal signal SQ to rise to a high level. At this time, the internal signal SR is set to a high level, causing the internal signal SS to fall to a low level. Therefore, the internal signal SH is fixed to a low level, and the counter 645 is maintained in a reset state. As a result, even if the self-diagnosis command B_CMD is received, the internal signal SE (and hence the self-diagnosis enable signal B_EN) does not rise to a high level.

[0356] In this way, the self-diagnosis circuit 600 completes the self-diagnosis operation of the driver chip 420 and disables the self-diagnosis command B_CMD, and then disables the self-diagnosis command B_CMD when the driver chip 420 is restarted without the controller chip 410 being restarted.

[0357] Next, a situation in which condition (3) is satisfied will be described. After the self-diagnosis result at startup is OK and the driver chip 420 begins normal operation, when the output pulse signal OUT rises to a high level, the internal signal SQ rises to a high level. At this time, the internal signal SR is set to a high level, so the internal signal SS falls to a low level. Therefore, the internal signal SH is fixed to a low level, so the counter 645 is maintained in a reset state. As a result, even if the self-diagnosis command B_CMD is received, the internal signal SE (and therefore the self-diagnosis enable signal B_EN) does not rise to a high level.

[0358] In this way, the self-diagnosis circuit 600 updates the disabling of the self-diagnosis command B_CMD every time it detects an ON transition of the output pulse signal OUT after completing the self-diagnosis operation of the driver chip 420 and disabling the self-diagnosis command B_CMD. Note that condition (3) is useful from the perspective of safety design (for example, as a measure against high-speed power interruption of the power supply voltage VCC1).

[0359] Furthermore, the self-diagnosis circuit 600 of this embodiment has a function of canceling the invalidation of the self-diagnosis command B_CMD when the controller chip 410 is restarted. This function will be described in detail below.

[0360] In the self-diagnosis circuit 600, an operating state notification ST is constantly transmitted from the operating controller chip 410 to the driver chip 420 so that the driver chip 420 can detect the restart of the controller chip 410. Therefore, the driver chip 420 can determine whether the controller chip 410 has been restarted based on whether the operating state notification ST has been received.

[0361] When the controller chip 410 is restarted, the transmission process of the operation state notification ST, i.e., the continuous pulse driving of the off signal Soff, is temporarily stopped for at least the aforementioned determination time T3 (e.g., 30 μs). At this time, if the driver chip 420 is not in self-diagnosis operation (B_EN=H), the internal signal SK is maintained at a low level for the determination time T3.

[0362] Therefore, the internal signal SM output from the operating state determination circuit 654 falls to low level. As a result, the internal signal SN rises to high level, and the internal signal SO falls to low level. At this time, the internal signal SR is reset to low level, and the internal signal SS rises to high level. Therefore, the internal signal SH is no longer fixed to low level, and the invalidation of the self-diagnosis command B_CMD is released.

[0363] In this way, the self-diagnostic circuit 600 of this embodiment has a robust design that disables the self-diagnostic command B_CMD so that after the self-diagnostic operation is performed at startup, the self-diagnostic operation will not be performed again unless the controller chip 410 is restarted. In other words, the design concept of the self-diagnostic circuit 600 is fundamentally different from the conventional design concept of masking noise that may be superimposed on the input pulse signal IN or the output pulse signal OUT with an appropriate filter.

[0364] 18 is a diagram showing how the self-diagnosis command B_CMD is invalidated when the self-diagnosis operation is completed. This diagram shows, from top to bottom, the power supply voltage VCC1, the power supply voltage VCC2, the self-diagnosis execution signal BIST(OC), the self-diagnosis enable signal B_EN, the self-diagnosis completion signal SF, the on signal Son, the off signal Soff, the ready signal RDY, the internal signal SR, and the internal signal SH.

[0365] As shown in this figure, when the self-diagnosis operation of the driver chip 420 is completed and the self-diagnosis completion signal SF rises to a high level, the internal signal SR is set to a high level. Therefore, the internal signal SH is fixed to a low level, and the counter 645 is maintained in a reset state. As a result, the self-diagnosis enable signal B_EN does not rise to a high level. In this way, when the self-diagnosis operation of the driver chip 420 is completed, the self-diagnosis command B_CMD is invalidated.

[0366] 19 is a diagram showing how the self-diagnosis command B_CMD is disabled when restarting the driver chip 420. In this diagram, from top to bottom, the power supply voltage VCC1, the power supply voltage VCC2, the self-diagnosis completion signal SF, the on signal Son, the off signal Soff, the ready signal RDY, the internal signal SR, the internal signal SO, the input signal 6CNT_IN (=Soff) of the counter 657, the internal signal SP, and the internal signal SH are depicted.

[0367] As shown in this figure, when only the driver chip 420 is restarted due to a momentary interruption of the power supply voltage VCC2, the controller chip 410 continues to pulse the off signal Soff as the operating state notification ST. Therefore, the counter 657 continues to count the number of pulses of the off signal Soff without being reset. Then, when the number of pulses of the off signal Soff reaches six, the internal signal SP rises to a high level, and the internal signal SR is set to a high level. Therefore, the internal signal SH is fixed to a low level, and the counter 645 is reset. As a result, the self-diagnosis enable signal B_EN does not rise to a high level. In this way, the self-diagnosis command B_CMD is disabled when the driver chip 420 is restarted.

[0368] 20 is a diagram showing how the invalidation of the self-diagnosis command B_CMD is canceled when the controller chip 410 is restarted. In this diagram, from top to bottom, the following are depicted: power supply voltage VCC1, power supply voltage VCC2, self-diagnosis execution signal BIST (OC), self-diagnosis enable signal B_EN, self-diagnosis completion signal SF, on signal Son, off signal Soff, ready signal RDY, internal signal SR, internal signal SK, internal signal SM, input signal 6CNT_IN (=Soff) of counter 657, internal signal SP, and internal signal SH.

[0369] As shown in this diagram, when the controller chip 410 is restarted following a momentary interruption of the power supply voltage VCC1, the transmission process of the operating state notification ST (=constant pulse driving of the off signal Soff) is temporarily suspended. At this time, unless the driver chip 420 is in self-diagnosis operation (B_EN=H), the internal signal SK is maintained at a low level for the aforementioned determination time T3. Therefore, the internal signal SM falls to a low level. As a result, the internal signal SR is reset to a low level, and the internal signal SH is released from its low-level fixation. In this way, when the controller chip 410 is restarted, the invalidation of the self-diagnosis command B_CMD is canceled.

[0370] 21 is a diagram showing how the malfunction of the self-diagnosis circuit 600 is resolved when noise is superimposed on the input pulse signal IN. From top to bottom, the diagram depicts the input pulse signal IN, the on signal Son, the off signal Soff, and the self-diagnosis enable signal B_EN. As shown in the diagram, by disabling the self-diagnosis command B_CMD, the self-diagnosis circuit 600 does not malfunction even if noise is superimposed on the input pulse signal IN.

[0371] 22 is a diagram showing how the malfunction of the self-diagnosis circuit 600 is resolved when noise is superimposed on the output pulse signal OUT. From top to bottom, the diagram depicts the input pulse signal IN, the output pulse signal OUT, the switch state signal OSFB, the on signal Son, the off signal Soff, and the self-diagnosis enable signal B_EN. As shown in the diagram, by disabling the self-diagnosis command B_CMD, the malfunction of the self-diagnosis circuit 600 does not occur even if noise is superimposed on the output pulse signal OUT.

[0372] <Application to Vehicles> Fig. 23 is a diagram showing the appearance of a vehicle. Vehicle B of this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0373] Vehicle B includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0374] The signal transmission device 200 or 400 described above can be incorporated into any of the electronic devices installed in the vehicle B.

[0375] <Supplementary Notes> The various embodiments described above will be generally described below.

[0376] For example, a signal transmission device according to the present disclosure includes a first chip configured to receive an input pulse signal, and a second chip configured to generate an output pulse signal corresponding to the input pulse signal by performing insulated communication with the first chip to drive a switch element, the second chip including a self-diagnosis circuit configured to diagnose whether each part of the second chip is functioning correctly in accordance with a self-diagnosis command transmitted from the first chip, and the self-diagnosis circuit is configured to disable the self-diagnosis command when the self-diagnosis operation of the second chip is completed (first configuration).

[0377] In addition, in the signal transmission device having the above-mentioned first configuration, the self-diagnosis circuit may be configured (second configuration) to complete the self-diagnosis operation of the second chip and disable the self-diagnosis command, and then disable the self-diagnosis command again when the second chip is restarted without restarting the first chip.

[0378] In addition, in the signal transmission device having the above-mentioned first or second configuration, the self-diagnosis circuit may be configured (third configuration) to cancel the disablement of the self-diagnosis command when the first chip is restarted.

[0379] Furthermore, in a signal transmission device having any of the first to third configurations described above, the self-diagnosis circuit may be configured (fourth configuration) to update the disabling of the self-diagnosis command each time it detects an ON transition of the output pulse signal after completing the self-diagnosis operation of the second chip and disabling the self-diagnosis command.

[0380] In the signal transmission device according to any one of the first to fourth configurations, the first chip may be configured to notify the second chip, via a first isolation element, that the input pulse signal is at a logic level for turning on the switch element, and to notify the second chip, via a second isolation element, that the input pulse signal is at a logic level for turning off the switch element (fifth configuration).

[0381] Furthermore, in the signal transmission device according to the fifth configuration, the first chip may be configured to drive the second isolation element with a first pulse period when transmitting a gate-off command for the switch element, to drive the second isolation element with a second pulse period when transmitting the self-diagnosis command, and to drive the second isolation element with a third pulse period when transmitting an operating state notification for the first chip (sixth configuration).

[0382] In the signal transmission device of the sixth configuration described above, the self-diagnostic circuit may be configured (seventh configuration) to determine whether the first chip has been restarted depending on whether or not the operating status notification has been received.

[0383] In the signal transmission device according to any one of the first to seventh configurations above, the second chip may be configured to generate a switch state signal corresponding to the logical level of the output pulse signal and feed it back to the first chip, and the first chip may be configured to re-notify the second chip of the logical level of the input pulse signal when the logical levels of the input pulse signal and the switch state signal do not match (eighth configuration).

[0384] Furthermore, for example, an electronic device according to the present disclosure includes a power transistor and a gate driver IC configured to drive a gate of the power transistor, and the gate driver IC is configured to be a signal transmission device having any one of the first to eighth configurations (ninth configuration).

[0385] Also, for example, a vehicle according to the present disclosure is configured (tenth configuration) to include the electronic device according to the ninth configuration.

[0386] With a signal transmission device according to the present disclosure, malfunctions of the self-diagnosis function can be reduced.

[0387] <Others> In addition to the above-described embodiments, various technical features of the present disclosure can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0388] 1H (u / v / w) Upper gate driver IC 1L (u / v / w) Lower gate driver IC 2H (u / v / w) Upper power transistor 2L (u / v / w) Lower power transistor 3 ECU 4 Motor 5 Semiconductor device 11, 11A to 11F Low potential terminal 12, 12A to 12F High potential terminal 21, 21A to 21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 First inner end 25 First outer end 26 First spiral portion 27 Second inner end 28 Second outer end 29 Second spiral portion 31 First low potential wiring 32 Second low potential wiring 33 First high potential wiring 34 Second high potential wiring 41 Semiconductor chip 42 First main surface 43 Second main surface 44A to 44D Chip side wall 45 First functional device 51 Insulating layer 52 Insulating principal surface 53A to 53D Insulating side wall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulating layer 58 First insulating layer 59 Second insulating layer 60 Second functional device 61 Seal conductor 62 Device region 63 Outer region 64 Seal plug conductor 65 Seal via conductor 66 First inner region 67 Second inner region 71 Through wiring 72 Low-potential connecting wiring 73 Lead-out wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 Substrate plug electrode 78 First electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connecting wiring 82 Pad plug electrode 85 Dummy pattern 86 High-potential dummy pattern 87 First high-potential dummy pattern 88 Second high potential dummy pattern 89 First region 90 Second region 91 Third region 92 First connection portion 93 First pattern94 Second pattern 95 Third pattern 96 First outer peripheral line 97 Second outer peripheral line 98 First intermediate line 99 First connecting line 100 Slit 130 Isolation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 First portion 147 Second portion 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p Primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 Buffer 220 Driver chip (second chip) 221, 222 Buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer chip (third chip) 230a First wiring layer (lower layer) 230b Second wiring layer (upper layer) 231, 232 Transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Transformer chip 301 First transformer 302 Second transformer 303 Third transformer 304 Fourth transformer 305 First guard ring 306 Second guard ring 400 Signal transmission device 410 Controller chip (first chip) 411 Logic circuit 411a Controller 411b, 411c, 411d Pulse generation circuit 411e Multiplexer 411f, 411g Buffer 411h Oscillator 412 UVLO / OVLO circuit 413 Internal power supply circuit 414 Switch control circuit 415 to 41B Transistor 420 Driver chip (second chip) 421 Logic circuit 421a, 421b Receiver 421c, 421d NOR gate421e Inverter 422 UVLO / OVLO circuit 423 Internal power supply circuit 424 Feedback signal generation circuit 425 to 427 Comparator 428 Transistor 429 Driver 429H, 429L Transistor 42A, 42B, 42C Transistor 430 Transformer chip (third chip) 431, 432 Transformer 500 Insulated signal transmission circuit 501 Pulse transmission circuit 502 Pulse reception circuit 503, 504 Buffer 600 Self-diagnosis circuit 610 Edge detection circuit 620 Pulse transmission circuit 630 Pulse reception circuit 631, 632 Signal interval judgment circuit 633 Inverter 634 AND gate 635 Counter 636 Latch 640 Command judgment circuit 641 Pulse width expansion circuit 642, 643 Signal interval determination circuit 644 AND gate 645 Counter 646 Latch 650 Discrimination control circuit 651 OR gate 652 Pulse width expansion circuit 653 OR gate 654 Operation state determination circuit 655 NAND gate 656 Inverter 657 Counter 658 OR gate 659 Latch 65A Inverter a1 to a8 Pads (corresponding to first current supply pads) b1 to b8 Pads (corresponding to first voltage measurement pads) c1 to c4 Pads (corresponding to second current supply pads) d1 to d4 Pads (corresponding to second voltage measurement pads) e1, e2 Pads A Electronic device B Vehicle C1 to C3 Capacitors CS1 to CS3 Current source FF1 to FF3 D flip-flop INV1 Inverter L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil N1 to N6 Transistors (NMOSFET) R1 to R3 Resistors T21, T22, T23, T24, T25, T26 External terminalsX First direction X21, X22, X23 Internal terminal Y Second direction Y21, Y22, Y23 Wiring Z Normal direction Z21, Z22, Z23 Via

Claims

1. A first chip configured to receive an input pulse signal, A second chip is configured to drive a switch element by generating an output pulse signal corresponding to the input pulse signal through isolated communication with the first chip, Equipped with, The second chip includes a self-diagnostic circuit configured to diagnose whether each part of the second chip is functioning correctly in response to a self-diagnostic command transmitted from the first chip. The self-diagnosis circuit is a signal transmission device that invalidates the self-diagnosis command when the self-diagnosis operation of the second chip is completed.

2. The signal transmission device according to claim 1, wherein the self-diagnosis circuit, after completing the self-diagnosis operation of the second chip and disabling the self-diagnosis command, disabling the self-diagnosis command again when the second chip is restarted without the first chip being restarted.

3. The signal transmission device according to claim 1, wherein the self-diagnosis circuit releases the deactivation of the self-diagnosis command when the first chip is restarted.

4. The signal transmission device according to claim 1, wherein the self-diagnosis circuit updates the invalidation of the self-diagnosis command each time it detects an ON transition of the output pulse signal after completing the self-diagnosis operation of the second chip and invalidating the self-diagnosis command.

5. The signal transmission device according to claim 1, wherein the first chip notifies the second chip via the first insulating element that the input pulse signal is a logic level for turning on the switch element, and the second chip notifies the second chip via the second insulating element that the input pulse signal is a logic level for turning off the switch element.

6. The signal transmission device according to claim 5, wherein the first chip drives the second insulating element with a first pulse period when transmitting a gate-off command for the switch element, drives the second insulating element with a second pulse period when transmitting a self-diagnosis command, and drives the second insulating element with a third pulse period when transmitting notification of the operating status of the first chip.

7. The signal transmission device according to claim 6, wherein the self-diagnostic circuit determines whether the first chip has been restarted depending on whether or not the operating status notification has been received.

8. The second chip generates a switch state signal corresponding to the logic level of the output pulse signal and feeds it back to the first chip. The signal transmission device according to claim 1, wherein the first chip re-notifies the second chip of the logic level of the input pulse signal when the logic levels of the input pulse signal and the switch state signal are inconsistent.

9. An electronic device comprising a power transistor and a gate driver IC configured to drive the gate of the power transistor, wherein the gate driver IC is a signal transmission device according to any one of claims 1 to 8.

10. A vehicle comprising the electronic equipment described in claim 9.