Linear motor control device

Abstract

In a linear motor control device (100), a plurality of inverters (1) that supply power to a stator winding (20) of a linear motor (200), a plurality of PWM signal generation units (10) for operating each of the plurality of inverters (1), a carrier signal generation circuit (4) that generates a carrier signal (Cw) used for generating a PWM signal (Pw), a clock circuit (6) that outputs a timing signal (Tm) to the plurality of carrier signal generation circuits (4), and a counter circuit (5) and a phase control device (11) composed of the above. By receiving the timing signal (Tm), the carrier signal generation circuit (4) generates carrier signals (Cw) with different phases and supplies them to each of the plurality of PWM signal generation units (10). The plurality of PWM signal generation units (10) generate PWM signals (Pw) with different phases using the carrier signals (Cw), output them to each of the plurality of inverters (1), and operate them.

Description

[Technical field]

[0001] The present disclosure relates to a linear motor control device. [Background technology]

[0002] In a motor control device with an inverter, neutral point potential fluctuations occur with the switching operation of the inverter, and common mode noise currents flow to the reference ground through stray capacitance that inevitably occurs between the power cable or the motor winding and the reference ground. This noise current may flow to the system power supply side and cause damage to other electronic devices that share the same power supply, which is called conducted interference. In addition, the noise current flowing through the power cable may cause damage to other circuit functions in the device, especially communication system circuits, due to electromagnetic coupling, etc., and may cause the devices to malfunction. This phenomenon is sometimes called auto-poisoning. In a motor control device with multiple inverters that are synchronized with each other, when each inverter is switched in phase, the time waveforms of the common mode currents generated in each inverter are also in phase, but when these flow into the same reference ground, etc., a phenomenon occurs in which they reinforce each other. This generates noise currents with large peak values, which increases the risk of conducting interference and auto-poisoning. In order to solve such problems, a method has been proposed in which the phases of function control signals for switching each inverter are shifted so that the switching operations of multiple inverters are not performed in the same phase (see, for example, Patent Documents 1 and 2).

[0003] In Patent Document 1, in order to suppress conducted noise, control signals with a phase difference of 180 degrees are output to multiple inverters, and approximately half of the inverters are operated with the same phase control signal and the remaining half with the opposite phase control signal.

[0004] In Patent Document 2, a phase control unit is provided that determines the phases of N carrier signals supplied to multiple inverters that control each of multiple motors so that the sum of N vectors represented by the amount of noise for each of the N motors becomes zero, thereby suppressing the peak value of the noise current. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 4143833 [Patent Document 2] JP 2022-137360 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, there are the following problems when applying the conventional method to a linear motor control device having multiple stator windings and corresponding inverters for each winding: First, in the method of Patent Document 1, in a motor control device having many inverters, about half of the inverters are in the same phase, so the problem remains unsolved.

[0007] In Patent Document 2, the phase control unit performs calculations so that the sum of N vectors represented by the amounts of noise relating to the N motors becomes zero, and therefore the calculation load increases as the number of motors increases.

[0008] The present disclosure discloses a technology for solving the problems described above, and has an object to enable noise suppression in a linear motor control device having multiple stator windings and multiple inverters corresponding to each of the stator windings by operating the multiple inverters at different phases using a simple phase control device. [Means for solving the problem]

[0009] The linear motor control device of the present disclosure includes: In a linear motor control device for controlling a linear motor having N stator windings (N is a natural number of 2 or more), N inverters each operating based on a PWM signal and supplying power to the corresponding N stator windings; n (n is a natural number smaller than N) carrier signal generating circuits that generate carrier signals used to generate the PWM signals; a phase control unit for controlling a phase of the carrier signal, The phase control unit includes: a clock circuit that outputs a synchronization signal; and n counter circuits that receive the synchronization signal output from the clock circuit and output timing signals to the n corresponding carrier signal generation circuits at a preset time from the time the synchronization signal was received, each of the n carrier signal generating circuits outputs the carrier signal having a preset cycle when receiving a timing signal from the corresponding counter circuit; The times at which timing signals are output from the n counter circuits are set so that the difference between any two of the times is not an integer multiple of the period of the carrier signal. The difference between any two of the times is set to be a half-integer multiple of the period of the carrier signal. , is something. Effect of the Invention

[0010] According to the present disclosure, it is possible to control multiple inverters to operate at different phases, and the generated noise currents also have different phases, making it possible to suppress an increase in noise current due to noise currents overlapping in the same phase. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a configuration of a linear motor system equipped with a linear motor control device according to a first embodiment. [Diagram 2] 1 is a block diagram showing a configuration of a linear motor control device according to a first embodiment. [Diagram 3] FIG. 2 is a diagram for explaining carrier signals having different phases. [Figure 4] 13 is a diagram for explaining the relationship between a carrier signal generating circuit and a PWM signal generating unit in a linear motor control device according to a third embodiment. FIG. [Diagram 5] 13 is a diagram for explaining carrier signals having opposite phases in a linear motor control device according to a fourth embodiment. FIG. [Figure 6] This is a conceptual diagram showing the phase relationship between in-phase PWM signals and noise generated from an inverter, which is a comparative example. In the figure, (a) shows the waveforms of PWM signals 1 and 2, (b) shows the noise current waveform generated from an inverter operated by PWM signals 1 and 2, and (c) shows the combined noise current. [Figure 7] FIG. 11 is a conceptual diagram showing the phase relationship between the opposite-phase PWM signals and the noise generated from the inverter in a linear motor control device according to embodiment 4, in which (a) shows the waveforms of PWM signals 1 and 2, (b) shows the noise current waveform generated from the inverter operated by PWM signals 1 and 2, and (c) shows the combined noise current. [Figure 8] 1A and 1B are diagrams illustrating a state in which a generated noise current flows to a reference ground. [Figure 9] FIG. 2 is a diagram showing an example of a hardware configuration of an inverter control device of the linear motor control device according to the first to fourth embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment of a linear motor control device will be described with reference to the drawings. In each drawing, the same reference numerals indicate the same or corresponding parts. Therefore, detailed descriptions thereof may be omitted to avoid duplication.

[0013] Embodiment 1 The linear motor control device according to the first embodiment will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a linear motor system equipped with a linear motor control device according to a first embodiment, and FIG. 2 is a functional block diagram showing the configuration of the linear motor control device. In FIG. 1, the linear motor system includes a linear motor 200 and a linear motor control device 100 for driving the linear motor 200 .

[0014] <Configuration of Linear Motor 200> First, the configuration of the linear motor 200 will be described. The linear motor 200 generates a magnetic force by passing current through the stator windings 20, and the mover 22 equipped with a permanent magnet is driven along a guide rail 23. Therefore, no power cable is required for the mover 22. The multiple stator windings 20 are housed in a housing 24. Power is supplied to each stator winding 20 from the linear motor control device 100 via a power cable 21. The number of stator windings 20 is N, which is the same as the number of inverters 1 described later.

[0015] <Configuration of the Linear Motor Control Device 100> 1 and 2, a linear motor control device 100 includes a plurality of N inverters 1 (N is a natural number of 2 or more) each supplying power to a stator winding 20 of a linear motor 200 via a power cable 21, a PWM signal generating unit 10 that generates a PWM (Pulse Width Modulation) signal Pw and transmits it to the inverters 1, a carrier signal generating unit 12 that generates a carrier signal Cw and transmits it to the PWM signal generating unit 10, and a phase control unit 11 that generates a timing signal Tm and transmits it to the carrier signal generating unit 12. The PWM signal generating unit 10, the carrier signal generating unit 12, and the phase control unit 11 constitute an inverter control device 101.

[0016] <Inverter 1 Configuration> A plurality of N inverters 1_1, 1_2, ···, 1_N (collectively referred to as inverter 1 when generalized) are single-phase inverter circuits each composed of a circuit that performs power conversion among the components necessary to realize the inverter function, for example, semiconductor switching elements. The N inverters 1 are each supplied with power from a common power supply circuit, but the power supply circuit, rectifier circuit, power cables, etc. are not shown. Examples of semiconductor switching elements include elements typified by MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and IGBT (Insulated-Gate-Bipolar-Transistor). These semiconductor switching elements may be formed of a semiconductor made of silicon (Si), or may be wide-bandgap semiconductors formed of semiconductor materials having a wider bandgap than silicon (Si) such as silicon carbide (SiC) and gallium nitride (GaN). Each of the inverters 1_1, 1_2, ···, 1_N corresponds to each of the stator windings 20 of the linear motor 200 and is electrically connected via a power cable 21.

[0017] <Configuration of PWM Signal Generation Unit 10> In FIGS. 1 and 2, the number of a plurality of PWM signal generation units 10_1, 10_2, ···, 10_N (collectively referred to as PWM signal generation unit 10 when generalized) is also N, the same as the number of inverters 1. PWM signals Pw are respectively transmitted from the PWM signal generation units 10_1, 10_2, ···, 10_N corresponding to the inverters 1_1, 1_2, ···, 1_N. Each PWM signal generation unit 10 includes a command signal generation unit 3 and a comparator 2. Taking the PWM signal generation unit 10_1 as an example, based on the signal from the control unit 7, the command signal generation unit 3_1 generates a command signal Sc and transmits it to the comparator 2_1. The comparator 2_1 compares the carrier signal Cw generated by the carrier signal generation circuit 4_1 with the command signal Sc and generates a PWM signal Pw. The carrier signal Cw is, for example, a triangular wave having a preset period T.

[0018] Here, the control unit 7 determines the value of a current to be passed through each stator winding 20 based on a command from the higher-level device 110. A command signal Sc is generated in the command signal generating unit 3 based on the calculation result in the control unit 7 inside the linear motor control device 100. This command signal Sc is a voltage command signal for setting the switching operation of the inverter 1 corresponding to the stator winding 20. It is not necessary for the control unit 7 to be provided inside the linear motor control device 100.

[0019] <Configuration of Phase Control Unit 11 and Carrier Signal Generation Unit 12> 2, the carrier signal generating unit 12 includes n multiple carrier signal generating circuits 4_1, 4_2, ..., 4_n (collectively referred to as carrier signal generating circuits 4). Here, n is a natural number satisfying 2 ≤ n ≤ N. The phase of each carrier signal Cw generated by the carrier signal generating circuit 4 is determined by a timing signal Tm transmitted from the phase control unit 11.

[0020] Phase control section 11 includes a plurality of n counter circuits 5_1, 5_2, ..., 5_n (collectively referred to as counter circuits 5) and a clock circuit 6. Here, the number of carrier signal generating circuits 4 and the number of counter circuits 5 are the same. When n=1, there is only one counter circuit 5 and it is not possible to generate carrier signals Cw with different phases, so 1 is excluded as the value of n. Therefore, n is 2 or more. Also, when n is larger than the number of inverters N, there will be a surplus of carrier signal generating circuits, so such a case is also excluded. Therefore, candidates for natural number n are limited to 2 or more and N or less.

[0021] Each of the counter circuits 5_1, 5_2, . . . 5_n is a digital circuit having a function of outputting a timing signal Tm after a preset time t1, t2, . . . tn has elapsed from the time t0 when the synchronous signal CLK generated by the clock circuit 6 is received. The synchronous signal CLK is an electric signal having a function of determining the operation start timing of the counter circuit 5 and synchronizing the operation of the counter circuit 5. The specific form of the synchronous signal CLK does not matter, but a repeating electric signal having an arbitrary frequency is generally used. The synchronous signal CLK is common to all the counter circuits 5. The timing signal Tm may be in any form as long as it is an electric signal, but for example, it is a signal that outputs a digital signal fixed to 1 (high) or 0 (low) for a certain period of time. The specific configuration of the clock circuit 6 does not matter either, but it is usually composed of a crystal oscillator and peripheral circuits. There is no need to prepare a clock circuit 6 dedicated to the phase control unit 11, and a clock circuit used in other circuits may be used in combination. The carrier signal generating circuit 4 and counter circuit 5 shown here may be configured as discrete components, but may also be implemented in a programmable logic device such as an FPGA (Field Programmable Gate Array).

[0022] The count circuits 5_1, 5_2, ..., 5_n are connected to the corresponding carrier signal generating circuits 4_1, 4_2, ..., 4_n in a one-to-one relationship, and each supplies a timing signal Tm. The carrier signal generating circuits 4_1, 4_2, ..., 4_n start outputting a carrier signal Cw with a period T when they receive a timing signal Tm from the count circuits 5_1, 5_2, ..., 5_n. In other words, the count circuits 5_1, 5_2, ..., 5_n have a function of determining the relative phases of n different carrier signals Cw.

[0023] Fig. 3 is a diagram showing carrier signals with different phases. Carrier signals generated at two times tk and tl arbitrarily selected in advance after receiving a synchronization signal CLK from a clock circuit 6 are designated as carrier signals Cw_k and Cw_l, respectively. By determining times t1, t2, ... tn such that the value of tk-tl is not an integer multiple (including negative numbers) of the period T of the carrier signal, it is possible to generate carrier signals Cw with up to n different phases. In the following explanation, "having different phases" has the above meaning.

[0024] Here, when the value of tk-tl is an integer multiple of the period T of the carrier signal, although time tk and time tl are different times, the phase difference between the two generated carrier signals Cw_k and Cw_l is an integer multiple of 360°, and there is no substantial phase difference. In other words, the phase difference α is expressed as an angle between 0° and less than 360° (0°≦α<360°), and the relationship with the period T of the carrier signal Cw is clearly stated as follows: tk-tl=T×α / 360×m (m is an integer other than 0) It is written as follows.

[0025] Also, any of the preset times t1, t2,...tn after receiving the synchronization signal CLK from the clock circuit 6 can have the same value, but since the carrier signals Cw are supplied a duplicate number of times at that time, the number of carrier signals Cw with different phases is reduced. Therefore, the times t1, t2,...tn are different by at least two or more.

[0026] When the N inverters 1_1, 1_2, ..., 1_N of the linear motor control device 100 are all operated with different phases, the number n of the counter circuits 5 and the carrier signal generating circuits 4 is set to be the same as the number N of the inverters 1, and the above-mentioned times t1, t2, ..., tn are all set to be different. The timing signal Tm set in this way is transmitted from the counter circuit 5_k, and based on the carrier signal Cw supplied by the carrier signal generating circuit 4_k that has received this timing signal Tm, the PWM signal generating unit 10_k outputs the PWM signal Pw to the inverter 1_k. Since the N inverters 1_1, 1_2, . . . 1_N of the linear motor control device 100 can all be operated with different phases, it is possible to avoid the problem of noise currents occurring at the same time and therefore having large peak values.

[0027] As described above, according to the first embodiment, the linear motor control device is a linear motor control device that controls a linear motor having N (N is a natural number greater than or equal to 2) stator windings, and is equipped with N inverters that supply power to the corresponding N stator windings, N PWM signal generating units that generate PWM signals to operate the inverters and supply them to each of the corresponding N inverters, n (n is a natural number greater than or equal to 2 and less than or equal to N) carrier signal generating circuits that generate carrier signals used to generate the PWM signals, and a phase control unit that controls the phase of the carrier signals. The phase control unit includes a clock circuit that outputs a synchronizing signal, and n counter circuits that receive the synchronizing signal output from the clock circuit and output timing signals to the corresponding n carrier signal generating circuits at at least two or more preset times different from the received time, and each of the n carrier signal generating circuits outputs a carrier signal of a preset period when it receives a timing signal from its corresponding counter circuit, and each of the PWM signal generating units is supplied with the carrier signal from one of the n carrier signal generating circuits, so that a plurality of inverters can operate with PWM signals generated based on carrier signals of different phases, and the problem of noise currents becoming large due to overlapping generation timing can be avoided.

[0028] In this case, the time at which the counter circuit outputs a timing signal is set so that the difference between any two times is not an integer multiple of the period of the carrier signal, making it possible to operate the inverter using a PWM signal generated based on carrier signals of different phases. In addition, when all of the n counter circuits output the timing signal Tm at different times, and when n = N, since all the inverters operate based on PWM signals generated based on carrier signals with different phases, it contributes most to noise suppression.

[0029] By setting the number n of the counter circuit and the carrier signal generation circuit to 2 ≤ n < N, which is less than the number N of the inverters and the PWM signal generation units, the counter circuit and the carrier signal generation circuit can be reduced. Also in this case, by generating a plurality of carrier signals with different phases, it is possible to suppress the overlapping of the generation timings of the noise currents, and avoid the problem that the peak value of the noise current becomes large due to the overlapping of the generation timings of the noise currents.

[0030] Embodiment 2. Hereinafter, the linear motor control device according to Embodiment 2 will be described with reference to the drawings. In Embodiment 1, an example was described in which the number n of the counter circuit 5 and the carrier signal generation circuit 4 was made the same as the number N of the inverters 1, and the N inverters 1_1, 1_2, ··· 1_N of the linear motor control device 100 were operated with different phases. In this Embodiment 2, an example in the case where the number n of the counter circuit 5 and the carrier signal generation circuit 4 is smaller than the number N of the inverters 1 will be described. Note that the configuration and operation of the linear motor control device 100 are the same as those in Embodiment 1.

[0031] When the number n of the counter circuit 5 and the carrier signal generation circuit 4 is smaller than the number N of the inverters 1, the carrier signal generation circuits 4_1, 4_2, ··· 4_n supply the carrier signal Cw with the same phase to the PWM signal generation unit 10 by at least the difference (N - n). Note that a plurality of carrier signals Cw are not supplied to one PWM signal generation unit 10. This is the same in Embodiment 1 as well.

[0032] Here, in the case where Nn=1, if the carrier signal Cw generated by the carrier signal generating circuit 4_1 is transmitted to the PWM signal generating units 10_1 and 10_2, the inverters 1_1 and 1_2 will operate in phase if the command signals are the same. The larger the difference in Nn is, the more the number of inverters operating in phase will increase. If there are many inverters operating in the same phase, the noise currents are superimposed and the peak value becomes large, but even if the difference in Nn becomes large, by distributing the destinations of the same carrier signal as evenly as possible so that many inverters 1 do not operate in the same phase, it is possible to minimize the increase in the peak value due to the superposition of the noise current. For example, if there are 12 inverters and the number of counter circuits and carrier signal generation circuits is 4, the number of inverters operating in the same phase can be reduced to 12 / 4 = 3. Even if it is not possible to operate all inverters in different phases, the number of inverters operating in the same phase can be sufficiently reduced, so the effect of suppressing the peak value of the noise current can be expected.

[0033] On the other hand, in a linear motor system, there are a large number of stator windings 20, and therefore the linear motor control device 100 has a large number of inverters 1 to operate them, and compared to other motor control devices, such as control devices for multi-axis motors, the number of inverters included in one device is much larger. Therefore, if the same number of counter circuits 5 and carrier signal generating circuits 4 as the inverters 1 are prepared, there will be disadvantages in terms of design and manufacturing costs, such as an increase in the number of parts and complicated wiring on the electronic circuit board. Furthermore, when implementing the counter circuits 5 and carrier signal generating circuits 4 in an FPGA, there are cases where it is not possible to implement many counter circuits 5 and carrier signal generating circuits 4 even if one wishes to do so due to limitations in the capacity of the FPGA.

[0034] That is, there is a trade-off between suppressing the influence of noise currents by making the number n of counter circuits 5 and carrier signal generating circuits 4 closer to the number N of inverters 1 and simplifying the design. Therefore, by making the number n of counter circuits 5 and carrier signal generating circuits 4 smaller than the number N of inverters 1, it is possible to simplify the design and reduce costs while operating the inverters 1_1, 1_2, ... 1_N with the maximum possible number of different phases, and it is also possible to obtain the effect of suppressing an increase in peak value due to the superposition of noise currents.

[0035] As described above, according to the second embodiment, by making the number n of counter circuits 5 and carrier signal generating circuits 4 smaller than the number N of inverters 1, it is possible to simplify the design and reduce costs while also achieving the effect of suppressing an increase in the peak value due to the superposition of noise currents.

[0036] Embodiment 3 A linear motor control device according to the third embodiment will be described below with reference to the drawings. In this third embodiment, as in the second embodiment, the number n of counter circuits 5 and carrier signal generating circuits 4 is smaller than the number N of inverters 1, and the same carrier signal Cw is supplied from each carrier signal generating circuit 4 to at least two or more PWM signal generating units 10. The configuration and operation of the linear motor control device 100 are the same as those of the first embodiment.

[0037] 4 is a diagram for explaining the relationship between the carrier signal generating circuit 4 and the PWM signal generating unit 10 in the linear motor control device 100 according to the third embodiment. Although the comparator 2 in the PWM signal generating unit 10 is omitted in FIG. 4, the carrier signal Cw from the carrier signal generating circuit 4 is input to the comparator 2 in the PWM signal generating unit 10.

[0038] 4, the carrier signal Cw of the carrier signal generating circuit 4_1 is supplied to two PWM signal generating units 10_1 and 10_2, the carrier signal Cw of the carrier signal generating circuit 4_2 is supplied to two PWM signal generating units 10_3, 10_4 and 10_5, and the carrier signal Cw of the carrier signal generating circuit 4_n is supplied to two PWM signal generating units 10_N-1 and 10_N. In this way, if the carrier signal Cw is supplied from each carrier signal generating circuit 4 to two PWM signal generating units 10, n=N / 2 is satisfied, and the number of counter circuits 5 and carrier signal generating circuits 4 can be reduced to half the number of inverters 1. In the example shown in FIG. 4, adjacent inverters (e.g., 1_1 and 1_2) operate in phase, but this is not necessarily required. Carrier signal generating circuit 4_1 may be connected to PWM signal generating units 10_1 and 10_3 so that inverters located far apart (e.g., 1_1 and 1_3) operate in phase.

[0039] 4, each carrier signal generating circuit 4 supplies the carrier signal Cw to two PWM signal generating units 10, but this is not limited thereto, and each carrier signal generating circuit 4 may supply the carrier signal Cw to three or more PWM signal generating units 10. However, in any case, the carrier signal Cw is not supplied from multiple carrier signal generating circuits 4 to one PWM signal generating unit 10.

[0040] Regardless of the number n of carrier signal generating circuits 4, if the phases of the carrier signals Cw generated by the n carrier signal generating circuits 4 are all different as described in embodiment 1, the number of inverters 1 operating in the same phase can be reduced. In the example of Fig. 4, the number of inverters 1 operating in the same phase is suppressed to two.

[0041] As described above, according to the third embodiment, each carrier signal generating circuit supplies the same carrier signal Cw to at least two or more PWM signal generating units, so that the number of counter circuits and carrier signal generating circuits can be reduced, and the phase control unit 11 can be simplified and reduced in cost. Furthermore, since the phase control unit generates carrier signals with different phases, it is possible to control the switching operations of the multiple inverters 1 so that they do not overlap, and the timing of noise generation can also be shifted in the same way. This makes it possible to suppress an increase in the peak value of the noise current.

[0042] Embodiment 4 A linear motor control device according to a fourth embodiment will be described below with reference to the drawings. In the fourth embodiment, an example will be described in which the number n of carrier signal generating circuits 4 and counter circuits 5 is an even number. The configuration and operation of the linear motor control device 100 are the same as those in the first embodiment.

[0043] By making the number n of carrier signal generating circuits 4 and counter circuits 5 an even number, it becomes possible to always create a pair of carrier signals Cw that are in opposite phase to a given carrier signal Cw. FIG. 5 is a diagram for explaining carrier signals having opposite phases. Here, the opposite phases refer to a case where the time when any two counter circuits 5_k and 5_l output the timing signal Tm is tk and tl, respectively, and the value of tk-tl is a half integer multiple of the period T of the carrier signal Cw. In other words, this is the case when tk-tl=T / 2×m (m is an integer other than 0) is satisfied. If the phase difference α is expressed as an angle, it is 180° or an odd multiple thereof. As long as the number n of the carrier signal generating circuits 4 and the counter circuits 5 is selected as an even number, it is possible to create all pairs of carrier signals Cw having opposite phases. In FIG. 5, an example is shown in which the phase difference between the carrier signal Cw_k generated by receiving the time tk at which the timing signal Tm is output and the carrier signal Cw_l generated by receiving the time tl at which the timing signal Tm is output is 180°.

[0044] Here, when n=2, it is obvious that the phase angle values ​​of the two carrier signals Cw can be selected as 0° and 180°, and they are in opposite phase to each other. When n=4, the phase angle values ​​of the four carrier signals Cw can be selected as 0°, 90°, 180°, and 270°, with the pairs of 0° and 180°, and 90° and 270° being in opposite phase. When n=6, the phase angle values ​​of the six carrier signals Cw can be selected as 0°, 60°, 120°, 180°, 240°, and 300°, with 0° and 180°, 60° and 240°, and 120° and 300° being opposite-phase pairs, respectively. Of course, any phase can be freely selected for a given number n. For example, when n=4, unlike the above example, the phases may be selected so that pairs with a phase difference of 180° exist, such as 0°, 180°, 100°, and 280°.

[0045] Next, the effect of forming a pair of carrier signals Cw with a phase difference of 180° will be described. 6 and 7 are conceptual diagrams showing the phase relationship between PWM signals and noise generated from inverters operated by the PWM signals. In the figures, (a) shows the waveforms of PWM signals 1 and 2, (b) shows the same-phase noise current waveforms generated from inverters 1_1 and 1_2 operated by PWM signals 1 and 2, and (c) shows the noise current obtained by adding up the noise currents generated from each inverter. As a comparative example, FIG. 6 shows (a) PWM signals 1 and 2 generated by two carrier signals Cw with a phase difference of 0, (b) shows the same-phase noise current waveforms generated from inverters 1_1 and 1_2 by PWM signals 1 and 2, and (c) shows the added noise current. It can be seen that the noise currents generated from inverters operated by carrier signals with a phase difference of 0 are in phase, and the added noise current increases as if the waveforms were superimposed.

[0046] 7 relates to the fourth embodiment, and in the figure (a) shows the PWM signals 1 and 2 of opposite phases due to a pair of carrier signals Cw of opposite phases. As can be seen from the figure (b), the noise currents generated from the inverters 1_1 and 1_2 by the PWM signals 1 and 2 of opposite phases are also of opposite phases, so that the waveforms of the combined noise currents are superimposed as shown in (c) and cancel each other out.

[0047] Fig. 8 is a schematic diagram showing how a noise current flows in a circuit, and is a diagram explaining how the generated noise current flows to a reference ground. In Fig. 8, a system power supply 32 is provided upstream of an inverter 1, and a stator winding 20_1 of a linear motor 200 to which power is supplied from an inverter 1_1 and a stator winding 20_2 to which power is supplied from an inverter 1_2 each have a stray capacitance 30 inevitably generated between the stator winding 20_1 and a reference ground 31. As shown in Fig. 7, when the inverters 1_1 and 1_2 are operated by the PWM signals of opposite phases, the noise currents generated from the inverters 1_1 and 1_2 respectively flow from the stator windings 20_1 and 20_2 to the reference ground 31 via the stray capacitance 30, but the noise currents are of opposite phase and flow in opposite directions. Therefore, as shown in Fig. 7(c), the noise currents flowing to the reference ground 31 cancel each other out.

[0048] As described above, the fourth embodiment provides the same effects as the first to third embodiments. Furthermore, by making the number n of carrier signal generating circuits and counter circuits an even number, it is possible to create a pair of carrier signals Cw with a phase difference of 180°, and as a result, the phase of the noise current generated by the inverter is also in opposite phase, making it possible to suppress the noise current flowing to the reference ground. This further reduces the risk of conductive interference.

[0049] An example of the configuration of the inverter control device 101 in the above-mentioned first to fourth embodiments is shown in Fig. 9. As shown in Fig. 9, the inverter control device 101 includes a processor 1000 and a storage device 1100 as processing circuits, for example. The processor 1000 may include a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), an IC (Integrated Circuit), an FPGA, various logic circuits, various signal processing circuits, etc. Also, the processor 1000 may include a plurality of processors of the same type or different types, and each process may be shared and executed. The storage device 1100 may include a RAM (Random Access Memory) configured to be able to read and write data from the processor 1000, and a ROM (Read Only Memory) configured to be able to read data from the processor 1000, etc. The processor 1000 executes a program input from the storage device 1100 such as a ROM.

[0050] Although an example was shown above in which the carrier signal generating circuit 4 and the counter circuit 5 of the inverter control device 101 are mounted on an FPGA, these may be configured separately or may be integrated into the inverter control device 101 as a hardware configuration.

[0051] Although the present disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not exemplified are assumed within the scope of the technology disclosed in this specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component and combining it with a component of another embodiment. [Explanation of symbols]

[0052] 1: inverter, 2: comparator, 3: command signal generating unit, 4: carrier signal generating circuit, 5: counter circuit, 6: clock circuit, 7: control unit, 10: PWM signal generating unit, 11: phase control unit, 12: carrier signal generating unit, 20: stator winding, 21: power cable, 22: mover, 23: guide rail, 24: housing, 30: stray capacitance, 31: reference ground, 32: system power supply, 100: linear motor control device, 101: inverter control device, 110: higher-level device, 200: linear motor, 1000: processor, 1100: storage device, Pw: PWM signal, Sc: command signal, Cw: carrier signal, Tm: timing signal, CLK: synchronization signal.

Claims

1. In a linear motor control device for controlling a linear motor having N (N is a natural number of 2 or more) stator windings, N inverters that operate based on PWM signals and supply power to the corresponding N stator windings, n (n is a natural number smaller than N) carrier signal generation circuits that generate carrier signals used for generating the PWM signals, A phase control unit that controls the phase of the carrier signal, comprising: The phase control unit A clock circuit that outputs a synchronization signal, and n counter circuits that receive the synchronization signal output from the clock circuit and output timing signals to the corresponding n carrier signal generation circuits at a preset time from the received time, Each of the n carrier signal generation circuits outputs a carrier signal having a preset period when receiving a timing signal from the corresponding counter circuit, A linear motor control device, wherein the times at which the n counter circuits output timing signals are set such that the difference between any two times is not an integer multiple of the period of the carrier signal.

2. The linear motor control device according to claim 1, wherein n, which is the number of the carrier signal generation circuits and the counter circuits, is an even number.

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