Multiprocessor Device

Abstract

The multiprocessor device (1) of the present disclosure has a plurality of processors (11, 12) on a single semiconductor chip, a shared resource (41, 42) that is shared by the plurality of processors (11, 12) and receives a request signal from any one of the plurality of processors (11, 12) and transmits a response signal corresponding to the request signal to the processor that issued the request signal, and a plurality of response control units (21, 22) provided corresponding to each of the plurality of processors, monitoring the request signal and the response signal corresponding to the request signal, and controlling the response to the request signal.

Description

[Technical field]

[0001] The present disclosure relates to a multiprocessor device having multiple processors on a single semiconductor chip. [Background technology]

[0002] In systems that require high reliability, such as infrastructure and industrial equipment, redundancy is implemented to prevent loss of safety due to failure. A known method of redundancy is to multiplex the processors that control the system, and maintain a safe state by having at least one processor continue to operate normally in the event of a failure. In recent years, with the improvement in the integration density of semiconductors, it has become possible to implement multiple processors on a single semiconductor chip, and a method has been proposed to achieve redundancy using a single semiconductor chip, i.e., on-chip redundancy.

[0003] A redundant system may have not only duplicated components but also shared resources that are not duplicated. In this case, if a failure occurs in the shared resource and it becomes unable to respond, and all the duplicated processors access the shared resource, all the processors will continue to wait for a response, and redundancy will be lost. One solution to this problem is to have a mechanism that monitors requests issued by processors and outputs a pseudo response if there is no response for a certain period of time. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-248205 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in a conventional mechanism for outputting a pseudo response, the system controller, which is the mechanism for outputting the pseudo response, itself is a shared resource, and if an abnormality occurs in the system controller, the pseudo response cannot be output.

[0006] The present disclosure has been made in consideration of the above circumstances, and has an object to provide a technique capable of improving the reliability of a multiprocessor device in which multiple processors are mounted on a single semiconductor chip. [Means for solving the problem]

[0007] In order to achieve the above-mentioned objective, the multiprocessor device disclosed herein has a plurality of processors on a single semiconductor chip, a shared resource that is shared by the plurality of processors and receives a request signal from any one of the plurality of processors and transmits a response signal corresponding to the request signal to the processor that issued the request signal, and a plurality of response control units that are provided corresponding to each of the plurality of processors and monitor the request signals and the response signals corresponding to the request signals and control the response to the request signals. Effect of the Invention

[0008] According to the present disclosure, it is possible to provide a technique capable of improving the reliability of a multiprocessor device in which multiple processors are mounted on a single semiconductor chip. [Brief description of the drawings]

[0009] [Figure 1] 1 is a diagram showing an example of a configuration of a multiprocessor device according to an embodiment; [Diagram 2] 1 is a diagram illustrating an example of a request receiving process executed by a response control unit included in the multiprocessor apparatus according to the embodiment; [Diagram 3] FIG. 4 is a diagram showing an example of a history management table according to the embodiment; [Figure 4] 1 is a diagram illustrating an example of a response receiving process executed by a response control unit included in the multiprocessor apparatus according to the embodiment; [Diagram 5]11 is a diagram showing an example of a timeout process executed by a response control unit included in the multiprocessor apparatus according to the embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the additive manufacturing device according to the first embodiment will be described in detail with reference to the drawings. Note that the present invention is not limited to these embodiments.

[0011] Embodiment 1 is a diagram showing a configuration of a multiprocessor device 1 according to an embodiment. The multiprocessor device 1 is, for example, a device in which a plurality of processors are mounted on a single semiconductor chip. The processors are, for example, microprocessors.

[0012] The multiprocessor device 1 includes a processor 11, a processor 12, a response control unit 21, a response control unit 22, an internal bus control unit 31, an internal bus control unit 32, a shared resource 41, a shared resource 42, a signal transmission unit 51, a signal transmission unit 52, an insulation unit 60, a power input unit 71, and a power input unit 72.

[0013] The processor 11 is connected to the shared resource 41 via the response control unit 21 and the internal bus control unit 31. The internal bus control unit 31 is a general component that interconnects the components of a semiconductor chip. The internal bus control unit 31 interconnects, for example, the response control unit 21, the shared resource 41, and the signal transmission unit 51. The processor 12 is connected to the shared resource 42 via the response control unit 22 and the internal bus control unit 32. The internal bus control unit 32 is a general component that interconnects the components of a semiconductor chip. The internal bus control unit 32 interconnects, for example, the response control unit 22, the shared resource 42, and the signal transmission unit 52.

[0014] 1, in the multiprocessor device 1, an area including processor 11 and an area including processor 12 are electrically insulated by an insulating section 60 inside a semiconductor chip included in the multiprocessor device 1. At this time, the internal bus control section 31 and the shared resource 42 are connected across the insulating section 60 by a signal transmission section 51. Also, the internal bus control section 32 and the shared resource 41 are connected across the insulating section 60 by a signal transmission section 52.

[0015] Of the two electrically isolated regions, the region including processor 11 shares power from external power source 101 via power source input unit 71. On the other hand, the region including processor 12 shares power from external power source 102 via power source input unit 72. That is, the region including processor 11 and the region including processor 12 share a power source independently of each other.

[0016] In FIG. 1, the shared resource 41 and the shared resource 42 are components of a semiconductor chip that are shared by a plurality of processors and receive requests from the plurality of processors. For example, the shared resource 41 and the shared resource 42 receive a request signal from the processor 11 or the processor 12 and generate a response signal to the request signal. The shared resource 41 and the shared resource 42 transmit the generated response signal to the processor 11 or the processor 12. The shared resource 41 and / or the shared resource 42 are, for example, an internal memory, an external memory interface, an external input / output interface, an external communication interface, etc. The shared resource 41 and / or the shared resource 42 may be an element that is used in common by a plurality of processors and that performs a part of an internal bus control function. The number of shared resources is not limited to the number shown in FIG. 1, and may be one, or three or more.

[0017] In FIG. 1, signal transmission section 51 and signal transmission section 52 are typical elements within a typical semiconductor chip, and transmit signals across insulated regions.

[0018] 1, each area separated by insulating unit 60 is insulated from each other and is supplied with power independently, so that each component included in each area can operate normally even if an abnormality occurs in the other external power supply. For example, when the supply of external power supply 101 stops and the supply of external power supply 102 is normally provided, the processor 11, response control unit 21, internal bus control unit 31, and shared resource 41 stop operating, but the processor 12, response control unit 22, internal bus control unit 32, and shared resource 42 can continue to operate normally. In other words, it is possible to provide redundancy in the power supply.

[0019] In FIG. 1, the response control unit 21 is provided corresponding to the processor 11, monitors a request signal from the processor 11 and a response signal corresponding to the request signal, and controls a response to the request signal from the processor 11. The response control unit 21 has a history management table 211. The history management table 211 is a table for managing a history of a request signal and a response signal corresponding to the request signal. The history management table 211 manages, for example, a history of a request signal received from the processor 11. The request signal received from the processor 11 is, for example, a request signal transmitted to the shared resource 41 or the shared resource 42. The history management table 211 also manages a history of a response signal received from the shared resource 41 or the shared resource 42 via the internal bus control unit 31. The response control unit 21 also manages the number of response signals requested by a request signal using the history management table 211. The response control unit 21 controls a response to the processor 11, for example, according to the number of response signals actually received with respect to the number of response signals requested.

[0020] In FIG. 1, the response control unit 22 is provided corresponding to the processor 12, monitors a request signal from the processor 12 and a response signal corresponding to the request signal, and controls a response to the request signal from the processor 12. The response control unit 22 has a history management table 221. The history management table 221 is a table for managing the history of request signals or response signals. The history management table 221 manages, for example, the history of request signals received from the processor 12. The request signal received from the processor 12 is, for example, a request signal transmitted to the shared resource 41 or the shared resource 42. The history management table 221 also manages the history of response signals received from the shared resource 41 or the shared resource 42 via the internal bus control unit 32. The response control unit 22 also manages the number of response signals requested by the request signal using the history management table 221. The response control unit 22 controls the response to the processor 12, for example, according to the number of response signals actually received with respect to the number of response signals requested.

[0021] The processing executed by the multiprocessor device 1 configured as above will be described with reference to FIGS. 2, 3, 4 and 5. FIG.

[0022] First, the request reception process will be described. Fig. 2 is a diagram showing an example of the request reception process executed by the response control units 21 and 22 included in the multiprocessor device 1 according to the embodiment. Here, as an example, the request reception process executed by the response control unit 21 will be described with reference to Fig. 2. Note that in this embodiment, the request signal received by the response control unit 21 from the processor 11 includes information indicating the number of transmissions indicating the number of responses required, along with destination information to which the request signal is sent. The number of transmissions is, for example, the number of data transmissions indicating how many transmissions are required to transmit the total amount of data including the response signal corresponding to the request signal. Note that the request signal may include information indicating the transmission size in addition to the information indicating the number of transmissions.

[0023] In FIG. 2, the response control unit 21 receives, for example, a request signal from the processor 11 (step S11).

[0024] When the response control unit 21 receives a request signal from the processor 11, the response control unit 21 refers to information indicating the number of transmissions included in the request signal, and determines the number of response signals corresponding to the received request signal (step S12).

[0025] The response control unit 21 associates the request signal received in step S11 with the number of responses determined in step S12, and registers them in the history management table 211 (step S13). FIG. 3 is a diagram showing an example of the history management table 211 or 221 according to the embodiment. According to FIG. 3, for example, the history management table 211 is composed of a "request signal" item that identifies a request signal, and a "number of responses" item that indicates the number of responses to a request. As shown in FIG. 3, values ​​stored in the "request signal" item are, for example, "A", "B", "C", and "D". Also, values ​​stored in the "number of responses" item are, for example, "1", "5", "3", and "2".

[0026] In FIG. 2, the response control unit 21 outputs the request signal received in step S11 to the internal bus control unit 31 (step S14).

[0027] Next, the response receiving process will be described. Fig. 4 is a diagram showing an example of the response receiving process executed by the response control units 21 and 22 included in the multiprocessor device 1 according to the embodiment. Here, as an example, the response receiving process executed by the response control unit 21 will be described with reference to Fig. 4. Note that in this embodiment, for the response signal received by the response control unit 21 from the internal bus control unit 31, a corresponding record is registered in the history management table 211, and it is assumed that, among the records shown in Fig. 3, the "request signal" field is "B" and the "number of responses" field is "5".

[0028] In FIG. 4, the response control unit 21 receives a response signal that is generated by, for example, the shared resource 41 and transmitted via the internal bus control unit 31 (step S21).

[0029] When the response control unit 21 receives the response signal from the internal bus control unit 31, it refers to the history management table 211 (step S22).

[0030] The response control unit 21 determines whether or not there is a record of the received signal corresponding to the received response signal (step S23).

[0031] Since there is a record in which the "request signal" field is "B" and the "number of responses" field is "5" corresponding to the received response signal (Yes in step S23), the response control unit 21 updates the history management table 211 (step S24). Specifically, the response control unit 21 subtracts 1 from the value "5" of the "number of responses" field for the record in which the "request signal" field is "B" to update it to "4". If the value of the "number of responses" field after the subtraction becomes "0", the record of the request signal in which the value of the "number of responses" field is "0" is deleted from the history management table 211. In this way, the response control unit 21 manages the number of response signals requested by a request signal using the history management table 211. As a result, even if a response signal to a request signal issued by the processor 11 is divided into multiple pieces, for example, the divided data constituting the response signal can be reliably managed and the response signal can be output accurately.

[0032] 4, if there is no record of a received signal corresponding to the received response signal (No in step S23), the response control unit 21 discards the received response signal (step S25). This makes it possible to prevent an abnormal state, such as a state in which the processor becomes inoperable due to an excessive number of response signals being output to the processor 11, for example.

[0033] When the response control unit 21 discards the response signal, the response control unit 21 may transmit an abnormality signal to the processor 11 or the processor 12 to notify that an abnormality has occurred. At this time, the processor 11 or the processor 12 that has received the abnormality signal from the response control unit 21 executes necessary processing to maintain the system in a safe state. The necessary processing to maintain the system in a safe state includes, for example, stopping the entire system by applying an emergency stop, or continuing operation of the entire system using replaceable components. As a result, even if some of the requested number of response signals are not returned, the processor can detect the abnormality and take appropriate measures, thereby preventing the abnormal state from continuing.

[0034] Finally, the timeout process will be described. Fig. 5 is a diagram showing an example of the timeout process executed by the response control units 21 and 22 included in the multiprocessor device 1 according to the embodiment. Here, as an example, the timeout process executed by the response control unit 21 will be described with reference to Fig. 5. In this embodiment, the response control unit 21 monitors the request signals registered in the history management table 211.

[0035] At this time, the response control unit 21 has, for example, a watchdog timer and monitors the request signal using the watchdog timer. The watchdog timer is, for example, a timer equipped with a monitoring function that notifies of an abnormality when a time measurement value exceeds a predetermined time. Note that the timeout process may be realized using a method other than the watchdog timer, and any method that can perform the timeout process may be used. For example, when registering a request signal, the response control unit 21 may register the registration time in the history management table 211, and thereafter, at predetermined intervals, perform the timeout process if the elapsed time from the registration time is equal to or longer than a predetermined time.

[0036] In FIG. 5, the response control unit 21 receives a timeout notification for a specific request signal from the watchdog timer (step S31).

[0037] For example, when the response control unit 21 receives a timeout notification for a specific request signal from a watchdog timer, the response control unit 21 refers to the history management table 211 and extracts the value of the “number of responses” item associated with the specific request signal (step S32).

[0038] The response control unit 21 generates pseudo response signals in the number of values ​​of the "number of responses" extracted in step S32 (step S33). The response control unit 21 generates, for example, three pseudo response signals.

[0039] Next, the response control unit 21 outputs the pseudo response signal generated in step S33 to the processor 11 (step S34). The response control unit 21 outputs, for example, three pseudo response signals that have been generated. This makes it possible to output the correct number of pseudo response signals even if a failure occurs that causes a shortage of multiple response signals.

[0040] Finally, the response control unit 21 updates the history management table 211 (step S35). Specifically, the response control unit 21 deletes from the history management table 211, for example, the record corresponding to the request signal for which the pseudo response signal was output in step S34.

[0041] When the response control unit 21 outputs the pseudo response signal, the response control unit 21 may transmit an abnormality signal to notify the processor 11 or the processor 12 that an abnormality has occurred. At this time, the processor 11 or the processor 12 that receives the abnormality signal from the response control unit 21 executes a necessary process to maintain the system in a safe state.

[0042] According to the above embodiment, the multiprocessor device 1 has processors 11 and 12 on a single semiconductor chip, and has shared resources 41 and 42 that are shared by processors 11 and 12 and receive a request signal from either of processors 11 and 12 and transmit a response signal corresponding to the request signal to the processor that issued the request signal, and response control units 21 and 22 that are provided corresponding to each of processors 11 and 12 and monitor the request signals and the response signals corresponding to the request signals and control the response to the request signals.

[0043] As a result, even if an abnormality occurs in the shared resource 41 or 42 and one of the response control units 21 and 22 also becomes abnormal, the other remains normal, so that the operation of the system that functions the multiprocessor device 1 can be kept safe. In other words, a fault-tolerant system can be realized.

[0044] Therefore, according to this embodiment, it is possible to improve the reliability of a multiprocessor device in which a plurality of processors are mounted on a single semiconductor chip.

[0045] The shared resource 41 and / or the shared resource 42 are not limited to those described in the above embodiment. For example, the shared resource 41 or the shared resource 42 may be a communication control unit that controls a black channel. The black channel is a channel for communicating with an external device by making data redundant over a single physical transmission path. In this case, even if the communication control unit is a single physical element, it is possible to logically duplicate communication.

[0046] In the above embodiment, the multiprocessor device 1 is configured to include two processors, the processor 11 and the processor 12, but is not limited to this. For example, the multiprocessor device 1 may be configured to include three or more processors. In this case, each processor included in the multiprocessor device 1 is electrically insulated from each other. Also, a response control unit, an internal bus control unit, a power input unit, etc. are provided corresponding to each processor included in the multiprocessor device 1.

[0047] Various embodiments and modifications of the present disclosure are possible without departing from the broad spirit and scope of the present disclosure. The above-described embodiments are for explaining the present disclosure and do not limit the scope of the present disclosure. In other words, the scope of the present disclosure is indicated by the claims, not the embodiments. Various modifications made within the scope of the claims and the scope of the disclosure equivalent thereto are considered to be within the scope of the present disclosure. [Industrial Applicability]

[0048] According to the present disclosure, it is possible to provide a multiprocessor device capable of improving the reliability of a multiprocessor device in which multiple processors are mounted on a single semiconductor chip. [Explanation of symbols]

[0049] 1 multiprocessor device, 11,12 processor, 21,22 response control section, 31,32 internal bus control section, 41,42 shared resource, 51,52 signal transmission section, 60 insulation section, 71,72 power supply input section, 211,221 history management table, 101,102 external power supply.

Claims

1. A multiprocessor device having multiple processors on a single semiconductor chip, a shared resource that is shared by the plurality of processors, receives a request signal from any one of the plurality of processors, and transmits a response signal corresponding to the request signal to the processor that issued the request signal; a plurality of response control units provided corresponding to the plurality of processors, each of which monitors the request signal and a response signal corresponding to the request signal, and controls a response to the request signal; and the plurality of processors are electrically isolated from one another and each have a power supply input; Multiprocessor device.

2. A multiprocessor device having multiple processors on a single semiconductor chip, a shared resource that is shared by the plurality of processors, receives a request signal from any one of the plurality of processors, and transmits a response signal corresponding to the request signal to the processor that issued the request signal; a plurality of response control units provided corresponding to the plurality of processors, each of which monitors the request signal and a response signal corresponding to the request signal, and controls a response to the request signal; and the response control unit has a history management table for managing a history of the request signals and the response signals corresponding to the request signals, and manages the number of response signals requested by the request signals using the history management table. Multiprocessor device.

3. 3. The multiprocessor device according to claim 2, wherein the response control unit, if unable to receive the number of response signals required by the request signal within a predetermined time, transmits an abnormality signal indicating an abnormality to the processor that issued the request signal.

4. A multiprocessor device having multiple processors on a single semiconductor chip, a shared resource that is shared by the plurality of processors, receives a request signal from any one of the plurality of processors, and transmits a response signal corresponding to the request signal to the processor that issued the request signal; a plurality of response control units provided corresponding to the plurality of processors, each of which monitors the request signal and a response signal corresponding to the request signal, and controls a response to the request signal; and The shared resource is a communication control unit that controls a black channel for communicating with an external device by making data redundant over a single physical transmission path. Multiprocessor device.

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