Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor in which the amount of lithium (Li) present in an external electrode is set to an appropriate amount and which makes it possible to suppress deterioration of moisture resistance.　A multilayer ceramic capacitor according to the present invention comprises: a stacked body that includes a plurality of stacked dielectric layers and a plurality of stacked internal electrodes, the stacked body having a first surface and a second surface on opposite sides from each other in the stacking direction, a third surface and a fourth surface on opposite sides from each other in a first direction orthogonal to the stacking direction, and a fifth surface and a sixth surface on opposite sides from each other in a second direction orthogonal to the stacking direction and the first direction; a first external electrode that is disposed on the third surface of the stacked body; and a second external electrode that is disposed on the fourth surface of the stacked body. The stacked body includes an inner layer portion and two outer layer portions that are arranged so as to sandwich the inner layer portion in the stacking direction. The inner layer portion has a first internal electrode of which one end is exposed on the third surface, a second internal electrode of which one end is exposed on the fourth surface, and an inner layer dielectric layer where the first internal electrode and the second internal electrode are arranged. The inner layer dielectric layer contains Li and at least Ca, Sr, or Zr as main components. The Li content in the first external electrode and / or the second external electrode is less than the Li content in the inner layer dielectric layer in at least one of a region of the first external electrode within a range of 15 μm in the first direction from the interface between the stacked body and the first external electrode, and a region of the second external electrode within a range of 15 μm or less in the first direction from the interface between the stacked body and the second external electrode.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Known multilayer ceramic capacitors used in electronic devices include high-dielectric-constant multilayer ceramic capacitors and temperature-compensating multilayer ceramic capacitors in which the capacitance changes linearly with temperature changes, as described in Patent Document 1.

[0003] For example, the multilayer ceramic capacitor described in Patent Document 2 uses copper or a copper-containing alloy for the internal electrodes and calcium zirconate as the main component for the dielectric layers. However, when copper is used for the internal electrodes, its low melting point can cause problems such as over-sintering of the internal electrodes during the process of sintering the dielectric, reducing the effective area of ​​the internal electrodes and decreasing the capacitance. Patent Document 2 uses a sintering aid such as lithium or silicon that forms a liquid phase during sintering to lower the sintering temperature of the dielectric and bring it as close as possible to the temperature of copper.

[0004] JP 2018-24542 A JP 2009-7209 A JP 2019-62177 A

[0005] However, as described in Patent Document 3, lithium is easily volatilized, and lithium volatilizes during the process of sintering the dielectric.

[0006] Furthermore, even when copper is used for the external electrodes, lithium in the dielectric material can volatilize and disperse into the external electrodes during the sintering process. When lithium disperses into the external electrodes, it acts as a sintering aid, causing the external electrodes to become excessively dense, which can lead to the formation of blisters and other problems. This can also lead to a deterioration in the moisture resistance of the multilayer ceramic capacitor.

[0007] Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor in which the amount of lithium (Li) present in the external electrodes is appropriate and deterioration of moisture resistance can be suppressed.

[0008] A multilayer ceramic capacitor according to the present invention comprises a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrodes, the laminate having a first surface and a second surface opposing each other in the lamination direction, a third surface and a fourth surface opposing each other in a first direction perpendicular to the lamination direction, and a fifth surface and a sixth surface opposing each other in a second direction perpendicular to the lamination direction and the first direction, a first external electrode disposed on the third surface of the laminate, and a second external electrode disposed on the fourth surface of the laminate, the laminate including an internal layer portion and two external layer portions disposed so as to sandwich the internal layer portion in the lamination direction, the internal layer portion having a first internal electrode having one end exposed on the third surface. a second internal electrode having one end exposed on the fourth surface; and an internal dielectric layer in which the first internal electrode and the second internal electrode are arranged, wherein the internal dielectric layer contains at least Ca, Sr, or Zr as main components, and Li, and the Li content in the first external electrode and / or the second external electrode is less than the Li content in the internal dielectric layer in at least one of a region of the first external electrode within 15 μm square in a first direction from the interface between the laminate and the first external electrode and a region of the second external electrode within 15 μm square in the first direction from the interface between the laminate and the second external electrode.

[0009] According to the multilayer ceramic capacitor of the present invention, the inner dielectric layer contains at least Ca, Sr, or Zr as main components and Li, and in a region within 15 μm square in the first direction from the interface between the laminate and the first external electrode, the Li content in the first external electrode is less than the Li content in the inner dielectric layer, thereby suppressing a decrease in the moisture resistance of the laminate.

[0010] According to the present invention, it is possible to provide a multilayer ceramic capacitor in which the amount of lithium (Li) present in the external electrodes is appropriate and deterioration of moisture resistance can be suppressed.

[0011] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0012] 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. It is a cross-sectional view taken along line II-II in FIG. 1. It is a cross-sectional view taken along line III-III in FIG. 1. It is a cross-sectional view taken along line IV-IV in FIG. 1. It is a cross-sectional view showing a modified example of the first embodiment in the cross-sectional view shown in FIG. 3. It is an external perspective view showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. It is a cross-sectional view taken along line VII-VII in FIG. 6. It is a cross-sectional view taken along line VIII-VIII in FIG. 6. It is a cross-sectional view taken along line IX-IX in FIG. 6. It is a cross-sectional view showing a modified example of the second embodiment in the cross-sectional view shown in FIG. 7. It is an external perspective view showing an example of a multilayer ceramic capacitor according to a third embodiment of the present invention. It is a cross-sectional view taken along line XII-XII in FIG. 11. It is a cross-sectional view taken along line XIII-XIII in FIG. 11. It is a cross-sectional view taken along line XIV-XIV in FIG. 11.

[0013] 1. Multilayer Ceramic Capacitor A. First Embodiment A multilayer ceramic capacitor according to a first embodiment of the present invention will be described.

[0014] Fig. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 1.

[0015] As shown in FIGS. 1 to 3, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped laminate 12 and external electrodes 30 disposed on both ends of the laminate 12 .

[0016] (Laminate) The laminate 12 has a plurality of stacked dielectric layers 14 and a plurality of internal electrodes 20 stacked on the dielectric layers 14. Furthermore, the laminate 12 has a first surface 12a and a second surface 12b facing in a stacking direction x, a third surface 12c and a fourth surface 12d facing in a first direction y perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f facing in a second direction z perpendicular to the stacking direction x and the first direction y.

[0017] Preferably, the first surface 12a and the second surface 12b, or one of them, is flat. If the first surface 12a and the second surface 12b are flat, the stress applied by the nozzle picking up the multilayer ceramic capacitor 10 can be dispersed across the flat surface. As a result, the strength of the multilayer ceramic capacitor can be improved during mounting.

[0018] The surface of the laminate 12 may be roughened.

[0019] The corners and ridges of this laminate 12 may be rounded. The intersection of two of the first surface 12a, the second surface 12b, the third surface 12c, the fourth surface 12d, the fifth surface 12e, and the sixth surface 12f is referred to as a ridge, and the intersection of three surfaces is referred to as a corner. The ridges and corners are preferably rounded and rounded. By rounding the ridges and corners, chipping and cracking can be prevented. When the ridges and corners are rounded, the main surface may be flat on the surfaces excluding the ridges and corners.

[0020] As shown in Figures 2 and 3, the laminate 12 has an inner layer portion 16 formed by alternately stacking dielectric layers 14 and internal electrodes 20 in a stacking direction x connecting the first surface 12a and the second surface 12b, a first surface side outer layer portion 18a formed from a plurality of dielectric layers 14 located between the first surface 12a and the internal electrode 20 located closest to the first surface 12a, and a second surface side outer layer portion 18b formed from a plurality of dielectric layers 14 located between the second surface 12b and the internal electrode 20 located closest to the second surface 12b.

[0021] (Inner Layer Portion) The inner layer portion 16 is constituted by a plurality of inner dielectric layers 14a among the plurality of dielectric layers 14. That is, the inner layer portion 16 is arranged so that a plurality of internal electrodes 20 face each other with the inner dielectric layers 14a interposed therebetween.

[0022] The inner dielectric layer 14a contains at least Ca, Sr, or Zr as its main components, and Li. For example, it contains CaZrO3 or SrZrO3 as its dielectric components, and Li as a sintering aid. In addition, it may contain Mn, Na, Ti, etc.

[0023] The main components of the inner dielectric layer 14a can be observed as follows. That is, the multilayer ceramic capacitor 10 is polished in the second direction z to half the W dimension in the second direction z, and a cross section is exposed. The exposed cross section is then observed under a 30 μm square condition using a TOF.SIM (manufactured by ION-TOF).

[0024] 2 and 3, the internal electrode 20 includes a first internal electrode 20a and a second internal electrode 20b. The first internal electrodes 20a and the second internal electrodes 20b are alternately stacked with the inner dielectric layer 14a interposed therebetween.

[0025] The first internal electrode 20a is disposed on the multiple dielectric layers 14 and is located inside the laminate 12. The first internal electrode 20a has a first opposing electrode portion 22a facing the second internal electrode 20b and a first lead electrode portion 24a located on one end side of the first internal electrode 20a and extending from the first opposing electrode portion 22a to the third surface 12c of the laminate 12. The end of the first lead electrode portion 24a is extended to the surface of the third surface 12c and exposed from the laminate 12. In other words, the end of the first lead electrode portion 24a is not exposed on the first surface 12a, the second surface 12b, the fourth surface 12d, the fifth surface 12e, and the sixth surface 12f. Specifically, the end of the first internal electrode 20a is slightly recessed from the fourth surface 12d.

[0026] The shape of the first opposing electrode portion 22a of the first internal electrode 20a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first opposing electrode portion 22a may be tapered in plan view, with a slope increasing in either direction.

[0027] The shape of the first lead electrode portion 24a of the first internal electrode 20a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first lead electrode portion 24a may be tapered in plan view, with a slope increasing in either direction.

[0028] The width of the first opposing electrode portion 22a of the first internal electrode 20a and the width of the first extraction electrode portion 24a of the first internal electrode 20a may be formed to be the same width, or one of the widths may be formed to be narrower.

[0029] The second internal electrode 20b is disposed on the multiple dielectric layers 14 and is located inside the laminate 12. The second internal electrode 20b has a second opposing electrode portion 22b facing the first internal electrode 20a and a second lead electrode portion 24b located on one end side of the second internal electrode 20b and extending from the second opposing electrode portion 22b to the fourth surface 12d of the laminate 12. The end of the second lead electrode portion 24b is extended to the surface of the fourth surface 12d and exposed from the laminate 12. In other words, the end of the first lead electrode portion 24a is not exposed on the first surface 12a, the second surface 12b, the third surface 12c, or the fifth and sixth surfaces 12e and 12f. Specifically, the end of the second internal electrode 20b is slightly recessed from the third surface 12c.

[0030] The shape of the second opposing electrode portion 22b of the second internal electrode 20b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second opposing electrode portion 22b may be tapered in plan view, with a slope increasing in either direction.

[0031] The shape of the second extraction electrode portion 24b of the second internal electrode 20b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second extraction electrode portion 24b may be tapered in plan view, with a slope increasing in either direction.

[0032] The width of the second opposing electrode portion 22b of the second internal electrode 20b and the width of the second extraction electrode portion 24b of the second internal electrode 20b may be formed to be the same width, or one of the widths may be formed to be narrower.

[0033] The laminate 12 includes a side portion 26a of the laminate 12 formed between one end of the first opposing electrode portion 22a and the second opposing electrode portion 22b in the second direction z and the fifth surface 12e, and a side portion 26b of the laminate 12 formed between the other end of the first opposing electrode portion 22a and the second opposing electrode portion 22b in the second direction z and the sixth surface 12f. Furthermore, the laminate 12 includes an end portion 27a of the laminate 12 formed between an end portion of the first internal electrode 20a opposite to the first extraction electrode portion 24a and the fourth surface 12d, and an end portion 27b of the laminate 12 formed between an end portion of the second internal electrode 20b opposite to the second extraction electrode portion 24b and the third surface 12c.

[0034] The internal electrodes 20 preferably contain, for example, Cu as a main component, which allows the electrical resistance of the internal electrodes 20 to be low and allows the internal electrodes 20 to be formed from an inexpensive material.

[0035] The main components of the internal electrode 20 can be observed as follows. That is, the multilayer ceramic capacitor 10 is polished in the second direction z to half the W dimension in the second direction z, and a cross section is exposed. Then, the exposed cross section is observed under a 30 μm square condition using a TOF.SIM (manufactured by ION-TOF).

[0036] The thickness of the internal electrode 20 is preferably 0.8 μm or more and 3.5 μm or less. The total number of the first internal electrodes 20a and the second internal electrodes 20b is preferably 2 or more and 30 or less.

[0037] (First surface side outer layer portion, second surface side outer layer portion) The first surface side outer layer portion 18a is located on the first surface 12a side of the laminate 12, and is an aggregate of multiple outer dielectric layers 14b that are multiple dielectric layers 14 located between the first surface 12a and the internal electrode 20 closest to the first surface 12a. The second surface side outer layer portion 18b is located on the second surface 12b side of the laminate 12, and is an aggregate of multiple outer dielectric layers 14b that are multiple dielectric layers 14 located between the second surface 12b and the internal electrode 20 closest to the second surface 12b. The region sandwiched between the first surface side outer layer portion 18a and the second surface side outer layer portion 18b is the inner layer portion 16.

[0038] The first surface side outer layer portion 18a and the second surface side outer layer portion 18b are each formed of an insulating material. When the first surface side outer layer portion 18a and the second surface side outer layer portion 18b are formed of the same type of dielectric material as the inner dielectric layer 14a, each outer layer portion 18a, 18b may be formed of multiple outer dielectric layers 14b or a single outer dielectric layer 14b. The outer dielectric layer 14b and the inner dielectric layer 14a may be formed of different components. For example, the inner dielectric layer 14a may be made of a material with a higher dielectric constant than the outer dielectric layer 14b, and the outer dielectric layer 14b may be made of a component with good moisture resistance, weather resistance, or strength resistance.

[0039] The dimensions of the laminate 12 are not particularly limited.

[0040] (External Electrodes) As shown in FIGS. 1 to 3, external electrodes 30 are disposed on the third surface 12c and the fourth surface 12d of the laminate 12.

[0041] The external electrode 30 includes a base electrode layer 32 containing a metal component and glass, and a plating layer 34 disposed on the surface of the base electrode layer 32 .

[0042] The external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0043] The first external electrode 30a is connected to the first internal electrode 20a and is disposed on at least the surface of the third face 12c. The first external electrode 30a also extends from the third face 12c of the laminate 12 and is disposed on a portion of the first face 12a, a portion of the second face 12b, a portion of the fifth face 12e, and a portion of the sixth face 12f. In this case, the first external electrode 30a is electrically connected to the first lead electrode portion 24a of the first internal electrode 20a.

[0044] The second external electrode 30b is connected to the second internal electrode 20b and is disposed on at least the surface of the fourth face 12d. The second external electrode 30b also extends from the fourth face 12d of the laminate 12 and is disposed on a portion of the first face 12a, a portion of the second face 12b, a portion of the fifth face 12e, and a portion of the sixth face 12f. In this case, the second external electrode 30b is electrically connected to the second lead electrode portion 24b of the second internal electrode 20b.

[0045] In the laminate 12, the first opposing electrode portion 22a of the first internal electrode 20a and the second opposing electrode portion 22b of the second internal electrode 20b face each other via the dielectric layer 14, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 30a connected to the first internal electrode 20a and the second external electrode 30b connected to the second internal electrode 20b, thereby realizing the characteristics of a capacitor.

[0046] The base electrode layer 32 includes a first base electrode layer 32a and a second base electrode layer 32b.

[0047] The first base electrode layer 32a is connected to the first internal electrode 20a and is disposed on the surface of the third surface 12c. The first base electrode layer 32a also extends from the third surface 12c and is disposed on a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f. In this case, the first base electrode layer 32a is electrically connected to the first lead electrode portion 24a of the first internal electrode 20a.

[0048] The second base electrode layer 32b is connected to the second internal electrode 20b and is disposed on the surface of the fourth face 12d. The second base electrode layer 32b also extends from the fourth face 12d and is disposed on a part of the first face 12a, a part of the second face 12b, a part of the fifth face 12e, and a part of the sixth face 12f. In this case, the second base electrode layer 32b is electrically connected to the second lead electrode portion 24b of the second internal electrode 20b.

[0049] The base electrode layer 32 is mainly composed of Cu. The base electrode layer 32 contains a glass component in addition to Cu as the main component. By including Cu, which has a low specific resistance, as the main component, the base electrode layer 32 can reduce the ESR of the multilayer ceramic capacitor 10. Furthermore, by including the glass component, the base electrode layer 32 can improve the sinterability of the base electrode layer 32.

[0050] The D50 of Cu particles constituting the Cu contained in the base electrode layer 32 is preferably 0.3 μm or more and 0.6 μm or less. The content of the glass component contained in the base electrode layer 32 is preferably 21 vol% or more and 25 vol% or less. This makes it possible to suppress diffusion of Li into the base electrode layer 32 in the step of forming the base electrode layer, which will be described later, and to suppress the Li content in the base electrode layer 32.

[0051] The thickness of the first base electrode layer 32a located on the third surface 12c in the first direction y connecting the third surface 12c and the fourth surface 12d at the center in the stacking direction x is preferably, for example, approximately 19 μm or more and 24 μm or less.

[0052] The thickness of the second base electrode layer 32b located on the fourth surface 12d in the first direction y connecting the third surface 12c and the fourth surface 12d at the center in the stacking direction x is preferably, for example, approximately 19 μm or more and 24 μm or less.

[0053] In a cross section of the multilayer ceramic capacitor 10 polished in the second direction z to half the W dimension in the second direction z, the base electrode layer 32 located at the center in the stacking direction x is observed using a TOF.SIM (manufactured by ION-TOF) under conditions of 30 μm square and with the interface between the laminate 12 and the base electrode layer 32 at the center of the image. In a region within 15 μm square from the interface between the laminate 12 and the base electrode layer 32, the Li content in the base electrode layer 32 is less than the Li content in the inner dielectric layer 14 a. In this case, the Li content in the base electrode layer 32 may decrease with increasing distance in the first direction y from the interface between the laminate 12 and the base electrode layer 32. This allows the Li content in the base electrode layer 32 to be reduced, thereby suppressing a decrease in the moisture resistance of the multilayer ceramic capacitor 10. More preferably, the Li content in the base electrode layer 32 is less than the Li content in the inner dielectric layer 14a in a region within 5 μm square from the interface between the laminate 12 and the base electrode layer 32. Even more preferably, no Li is present in the base electrode layer 32. This can further suppress a decrease in the moisture resistance of the multilayer ceramic capacitor 10.

[0054] Specifically, in at least one of the regions of the first base electrode layer 32a within 15 μm in the first direction y from the interface between the laminate 12 and the first base electrode layer 32a and the region of the second base electrode layer 32b within 15 μm in the first direction y from the interface between the laminate 12 and the second base electrode layer 32b, the Li content in the first base electrode layer 32a and / or the second base electrode layer 32b is less than the Li content in the inner dielectric layer 14a. In addition, in at least one of a region of the first base electrode layer 32a within 5 μm square in the first direction y from the interface between the laminate 12 and the first base electrode layer 32a and a region of the second base electrode layer 32b within 5 μm square in the first direction y from the interface between the laminate 12 and the second base electrode layer 32b, the Li content in the first base electrode layer 32a and / or the second base electrode layer 32b is preferably less than the Li content in the inner dielectric layer 14a. Furthermore, the Li content in the first base electrode layer 32a may decrease with increasing distance in the first direction y from the interface between the laminate 12 and the first base electrode layer 32a, and the Li content in the second base electrode layer 32b may decrease with increasing distance in the first direction y from the interface between the laminate 12 and the second base electrode layer 32b.

[0055] As described above, the Li content in the base electrode layer 32 and the Li content in the inner dielectric layer 14a can be measured by TOF. SIMS (Time-of-Flight Secondary Ion Mass Spectrometry). The measurement conditions for this TOF. SIMS are as follows: Apparatus name: TOF. SIMS (manufactured by ION-TOF Inc.) Primary ion: Bi + Acceleration voltage: 25 kV Secondary ion polarity: Positive Number of scans: 32 Number of pixels: 256 pixels x 256 pixels Measurement area: □30 μm x 30 μm The Li content is derived by counting the number of pixels in the 256 pixels x 256 pixels where the Li intensity is 1.0 or more.

[0056] Furthermore, in a cross section of the multilayer ceramic capacitor 10 polished in the second direction z to half the W dimension in the second direction z, the base electrode layer 32 located at the center in the stacking direction x was observed using a TOF-SIMS (manufactured by ION-TOF) under conditions of 30 μm square and with the interface between the laminate 12 and the base electrode layer 32 at the center of the observation image. Li was not present in a region of the base electrode layer 32 that was farther from the laminate 12 in the first direction y than 15 μm from the interface between the laminate 12 and the base electrode layer 32. In other words, the distance from the interface between the laminate 12 and the base electrode layer 32 to Li was 15 μm or less. Preferably, the distance from the interface between the laminate 12 and the base electrode layer 32 to Li was 5 μm or less. More preferably, Li is not present in the base electrode layer 32. This reduces the amount of Li scattered from the dielectric layer 14 and reduces the Li content in the base electrode layer 32, thereby suppressing a decrease in the moisture resistance of the multilayer ceramic capacitor 10.

[0057] Specifically, Li is not present in at least one of a region of the first base electrode layer 32a that is 15 μm or more in the first direction y from the interface between the laminate 12 and the first base electrode layer 32a, in a direction away from the laminate 12, and a region of the second base electrode layer 32b that is 15 μm or more in the first direction y from the interface between the laminate 12 and the second base electrode layer 32b, in a direction away from the laminate 12. Furthermore, Li is preferably not present in at least one of a region of the first base electrode layer 32a that is 5 μm or more in the first direction y from the interface between the laminate 12 and the first base electrode layer 32a, in a direction away from the laminate 12, and a region of the second base electrode layer 32b that is 5 μm or more in the first direction y from the interface between the laminate 12 and the second base electrode layer 32b, in a direction away from the laminate 12.

[0058] As described above, the presence or absence of Li in the base electrode layer 32 can be confirmed by TOF. SIMS (Time-of-Flight Secondary Ion Mass Spectrometry). The measurement conditions for this TOF. SIMS are as follows: Apparatus name: TOF. SIMS (manufactured by ION-TOF Inc.) Primary ion: Bi + Acceleration voltage: 25 kV Secondary ion polarity: Positive Number of scans: 32 Number of pixels: 256 pixels x 256 pixels Measurement area: □30 μm x 30 μm The presence or absence of Li is confirmed by the presence or absence of pixels with a Li intensity of 1.0 or more among the 256 pixels x 256 pixels.

[0059] Next, the first plating layer 34a and the second plating layer 34b, which are the plating layers 34 disposed on the base electrode layer 32, will be described with reference to FIGS. 2 and 3. FIG.

[0060] The first plating layer 34a and the second plating layer 34b contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, and the like.

[0061] The first plating layer 34a is disposed so as to completely cover the first base electrode layer 32a, and the second plating layer 34b is disposed so as to completely cover the second base electrode layer 32b.

[0062] The first plating layer 34a and the second plating layer 34b may be formed of multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of a lower plating layer (Ni plating layer) formed on the base electrode layer 32 by Ni plating and an upper plating layer (Sn plating layer) formed on the lower plating layer by Sn plating. That is, in this case, the first plating layer 34a has a first lower plating layer 36a and a first upper plating layer 38a located on the surface of the first lower plating layer 36a. Furthermore, the second plating layer 34b has a second lower plating layer 36b and a second upper plating layer 38b located on the surface of the second lower plating layer 36b.

[0063] The Ni-plated lower layer 36 is used to prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10, and the Sn-plated upper layer 38 is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby facilitating mounting. The thickness of each of the lower layer 36 and the upper layer 38 is preferably 1.0 μm or more and 15.0 μm or less.

[0064] The dimension in the first direction y of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension L, the dimension in the stacking direction x of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension T, and the dimension in the second direction z of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are as follows: L in the first direction y is 0.25 mm or more and 2.0 mm or less, W in the second direction z is 0.125 mm or more and 1.25 mm or less, and T in the stacking direction x is 0.125 mm or more and 1.25 mm or less. The dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0065] In the multilayer ceramic capacitor 10 shown in FIG. 1, in the region within 15 μm square from the interface between the laminate 12 and the base electrode layer 32, the Li content in the base electrode layer 32 is less than the Li content in the inner dielectric layer 14 a, so that a decrease in moisture resistance can be suppressed.

[0066] Furthermore, in the multilayer ceramic capacitor 10 shown in FIG. 1, if the Li content in the base electrode layer 32 in the region within 5 μm square from the interface between the laminate 12 and the base electrode layer 32 is less than the Li content in the inner dielectric layer 14 a, the decrease in moisture resistance can be further suppressed.

[0067] In addition, in the multilayer ceramic capacitor 10 shown in FIG. 1, the oxide film is not present in the region that is farther from the laminate 12 in the first direction y than 15 μm from the interface between the laminate 12 and the base electrode layer 32, so that a decrease in moisture resistance can be suppressed.

[0068] Furthermore, in the multilayer ceramic capacitor 10 shown in FIG. 1, if the distance from the interface between the laminate 12 and the base electrode layer 32 to Li is 5 μm or less, the decrease in moisture resistance can be further suppressed.

[0069] (Modification of the First Embodiment) Next, an example of a multilayer ceramic capacitor 10A according to a modification of the first embodiment of the present invention will be described. Fig. 5 is a schematic cross-sectional view showing an example of a multilayer ceramic capacitor according to a modification of the first embodiment of the present invention. However, the same reference numerals are used to designate the same or corresponding components as those in Figs. 1 to 4, and detailed descriptions thereof will be omitted.

[0070] A multilayer ceramic capacitor 10A according to a modification of the first embodiment includes a rectangular parallelepiped laminate 12A and external electrodes 30 disposed on both ends of the laminate 12A.

[0071] The laminate 12A has a plurality of stacked dielectric layers 14. Furthermore, the laminate 12A has a first surface 12a and a second surface 12b facing in a stacking direction x, a third surface 12c and a fourth surface 12d facing in a first direction y perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f facing in a second direction z perpendicular to the stacking direction x and the first direction y.

[0072] As shown in FIG. 5, the laminate 12A has, as the internal electrodes 20, a pair of first internal electrodes 20A and a pair of second internal electrodes 20B.

[0073] The pair of first internal electrodes 20A is composed of two first internal electrodes 20a that are adjacent to each other in the stacking direction x. The pair of first internal electrodes 20A is electrically connected to the first external electrode 30a. The pair of second internal electrodes 20B is composed of two second internal electrodes 20b that are adjacent to each other in the stacking direction x. The pair of second internal electrodes 20B is electrically connected to the second external electrode 30b. This makes it possible to ensure overall conductivity with multiple internal electrodes even if the thickness dimension of one internal electrode is small.

[0074] The multilayer ceramic capacitor 10A according to the modified example of the first embodiment shown in FIG. 5 has the same effects as the multilayer ceramic capacitor 10 shown in FIG.

[0075] B. Second Embodiment Next, an example of a multilayer ceramic capacitor 110 according to a second embodiment of the present invention will be described. FIG. 6 is an external perspective view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 6. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 6. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 6.

[0076] The multilayer ceramic capacitor 110 according to the second embodiment of the present invention has a laminate 112 having a configuration similar to that of the multilayer ceramic capacitor 10 according to the first embodiment, and external electrodes 30. However, in the multilayer ceramic capacitor 110, the magnitude relationship between the L dimension and the W dimension is reversed compared to the multilayer ceramic capacitor 10 according to the first embodiment, with the W dimension being larger than the L dimension.

[0077] The multilayer ceramic capacitor 110 according to the second embodiment includes a rectangular parallelepiped laminate 112 and external electrodes 30 disposed on both ends of the laminate 112 .

[0078] The laminate 112 has a plurality of stacked dielectric layers 14. Furthermore, the laminate 112 has a first surface 112a and a second surface 112b facing in a stacking direction x, a third surface 112c and a fourth surface 112d facing in a first direction y perpendicular to the stacking direction x, and a fifth surface 112e and a sixth surface 112f facing in a second direction z perpendicular to the stacking direction x and the first direction y.

[0079] In the multilayer ceramic capacitor 110, the magnitude relationship between the L dimension and the W dimension is reversed compared to the multilayer ceramic capacitor 10 of the first embodiment, with the W dimension being larger than the L dimension.

[0080] The multilayer ceramic capacitor 110 according to the second embodiment shown in FIG. 6 provides the same effects as the multilayer ceramic capacitor 10 shown in FIG.

[0081] (Modification of Second Embodiment) Next, an example of a multilayer ceramic capacitor 110A according to a modification of the second embodiment of the present invention will be described. Fig. 10 is a schematic cross-sectional view showing an example of a multilayer ceramic capacitor according to a modification of the second embodiment of the present invention. However, the same reference numerals are used for the same or corresponding components as those in Figs. 6 to 8, and detailed description thereof will be omitted.

[0082] As shown in FIG. 10, a laminate 112A of a multilayer ceramic capacitor 110A according to the modified example of the second embodiment has, as the internal electrodes 20, a pair of first internal electrodes 20A and a pair of second internal electrodes 20B.

[0083] The pair of first internal electrodes 20A is composed of two first internal electrodes 20a that are adjacent to each other in the stacking direction x. The pair of first internal electrodes 20A is electrically connected to the first external electrode 30a. The pair of second internal electrodes 20B is composed of two second internal electrodes 20b that are adjacent to each other in the stacking direction x. The pair of second internal electrodes 20B is electrically connected to the second external electrode 30b. This makes it possible to ensure overall conductivity with multiple internal electrodes even if the thickness dimension of one internal electrode is small.

[0084] The multilayer ceramic capacitor 110A according to the modified example of the second embodiment shown in FIG. 10 provides the same effects as the multilayer ceramic capacitor 10 of FIG.

[0085] C. Third Embodiment Next, an example of a multilayer ceramic capacitor 210 according to a third embodiment of the present invention will be described. Fig. 11 is an external perspective view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. Fig. 12 is a cross-sectional view taken along line XII-XII in Fig. 11. Fig. 13 is a cross-sectional view taken along line XIII-XIII in Fig. 11. Fig. 14 is a cross-sectional view taken along line XIV-XIV in Fig. 11.

[0086] The multilayer ceramic capacitor 210 according to the third embodiment includes a rectangular parallelepiped laminate 212 and external electrodes 30 disposed on both ends of the laminate 212 .

[0087] The laminate 212 has a plurality of stacked dielectric layers 14. Furthermore, the laminate 212 has a first surface 212a and a second surface 212b facing in a stacking direction x, a third surface 212c and a fourth surface 212d facing in a first direction y perpendicular to the stacking direction x, and a fifth surface 212e and a sixth surface 212f facing in a second direction z perpendicular to the stacking direction x and the first direction y.

[0088] As shown in Figures 13 and 14, in the laminate 212, in the inner layer portion 216, the first inner electrode 20a and the second inner electrode 20b are arranged on the same dielectric layer 14 at a predetermined interval.

[0089] The multilayer ceramic capacitor 210 according to the third embodiment shown in FIG. 10 provides the same effects as the multilayer ceramic capacitor 10 shown in FIG.

[0090] 2. Method for Manufacturing the Multilayer Ceramic Capacitor Next, a method for manufacturing the multilayer ceramic capacitor according to the first embodiment will be described as an example.

[0091] (Step of Preparing Ceramic Green Sheets) First, ceramic green sheets for the dielectric layers and conductive paste for the internal electrodes are prepared. The ceramic green sheets and the conductive paste for the internal electrodes contain a binder and a solvent. The binder and solvent may be known.

[0092] In this case, the ceramic green sheets for the inner dielectric layer region are formed from a dielectric paste containing, for example, CaZrO3 and Li. More specifically, this dielectric paste contains at least Ca, Sr, or Zr as the main components, and Li. For example, the dielectric paste contains CaZrO3 or SrZrO3 as the dielectric component, and Li as a sintering aid. In addition, Mn, Na, Ti, etc. may be contained.

[0093] When the dielectric paste for forming the ceramic green sheets for the inner dielectric layer region contains CaZrO3 as the main component, the amount of Li can be 0.06 wt% or more and 0.16 wt% or less relative to CaZrO3.

[0094] Then, a conductive paste for the internal electrodes is printed in a predetermined pattern on the ceramic green sheets for the dielectric layers by, for example, screen printing, gravure printing, etc. In this way, ceramic green sheets on which the patterns of the first internal electrodes are formed and ceramic green sheets on which the patterns of the second internal electrodes are formed are prepared.

[0095] (Process for Obtaining a Laminated Sheet) Next, a predetermined number of ceramic green sheets for outer layers, on which no internal electrode patterns are printed, are stacked to form a portion that will become the second surface side outer layer portion on the second surface side. Then, a ceramic green sheet on which a first internal electrode pattern is printed and a ceramic green sheet on which a second internal electrode pattern is printed are sequentially stacked on top of the portion that will become the second surface side outer layer portion so as to form the structure of the present invention, to form a portion that will become the inner layer portion. A predetermined number of ceramic green sheets for outer layers, on which no internal electrode patterns are printed, are stacked on top of this portion that will become the inner layer portion, to form a portion that will become the first surface side outer layer portion on the first surface side. This completes the production of a laminated sheet.

[0096] (Step of Obtaining a Laminated Block) Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0097] (Step of Obtaining Laminated Chips) The laminated block is then cut to a predetermined size, and laminated chips that will become laminated portions are cut out.

[0098] (Step of Obtaining Sintered Chip) Next, the laminated chip is sintered to produce a sintered chip. Specifically, after heating to 200°C or higher and 300°C or lower, the laminated chip is sintered in a non-oxidizing atmosphere at a temperature rise rate of 3.33°C / min or higher and 200°C / min or lower, and at a maximum sintering temperature of 900°C or higher and 1040°C or lower, to form a sintered chip.

[0099] Next, a conductive paste for the base electrode layer containing a metal component and a glass component is prepared.

[0100] (Process for forming external electrodes) A ​​conductive paste that will become the prepared base electrode layer is applied to the surfaces corresponding to the third and fourth surfaces of the sintered chip, respectively, to form the base electrode layer. The conductive paste can be applied to the surfaces corresponding to the third and fourth surfaces of the sintered chip by, for example, a dipping method. For example, the conductive paste that will become the base electrode layer can contain Cu as the main metal component and a glass component in a content of 21 vol% to 25 vol%. In this case, the Cu particles can be spherical, and the D50 can be 0.3 μm to 0.6 μm.

[0101] Next, the sintered chip coated with the conductive paste is fired to form a sintered chip with a base electrode layer. At this time, it is preferable to adjust the firing conditions so that an appropriate amount of Li is contained in the base electrode layer after firing the conductive paste. Firing under conditions that do not contain Li in the base electrode layer can prevent the base electrode layer from becoming too dense, thereby reducing the porosity within the base electrode layer and improving the moisture resistance of the multilayer ceramic capacitor. Furthermore, by limiting the amount of Li dispersed into the base electrode layer to 15 μm or less from the interface between the laminate (sintered chip) and the base electrode layer, excessive densification can be prevented. Lowering the firing temperature or shortening the firing time can reduce the distance and amount of Li dispersed into the base electrode layer, but this results in insufficient densification of the base electrode layer. Therefore, appropriate firing conditions are selected so that Li constitutes the multilayer ceramic capacitor according to the present invention. For example, the firing can be performed under conditions such as a reducing atmosphere, a temperature of 600° C. to 750° C., and a time of 0.3 to 0.5 hours.

[0102] Next, if necessary, plating is applied to the surface of the base electrode layer to form a plating layer. In this embodiment, two plating layers are formed on the surface of the base electrode layer. Specifically, a Ni plating layer and a Sn plating layer are formed on the base electrode layer. Electrolytic plating is preferably used as the plating process. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0103] In the manner described above, the multilayer ceramic capacitor 10 according to the present embodiment is manufactured.

[0104] 3. Experimental Example Next, in order to confirm the effects of the multilayer ceramic capacitor according to the present invention described above, multilayer ceramic capacitors were fabricated as experimental samples according to the above-described manufacturing method, with the degree of C-axis orientation being varied, and an experiment was conducted to confirm the occurrence of cracks by electrostriction testing.

[0105] (1) Specifications of multilayer ceramic capacitors fabricated as samples of experimental examples Multilayer ceramic capacitors, which are samples of sample numbers 1 to 10, were fabricated using the manufacturing method according to the above embodiment. Dimensions of multilayer ceramic capacitor (design values): L×W×T=400 μm×200 μm×200 μm Ceramic material: CaZrO3 Internal electrode material: Cu Base electrode layer of external electrode: conductive metal (Cu) and glass component Thickness of base electrode layer, which is 1 / 2 of the W dimension in the second direction z of the multilayer ceramic capacitor and is located in the center in the stacking direction x: 20 μm Plating layer Two layers formed of a Ni plating layer and a Sn plating layer Ni plating layer thickness: approximately 3 μm Sn plating layer thickness: approximately 5 μm

[0106] (2) Method for Adjusting the Distance of Li Scattered from the Interface Between the Laminate and the External Electrode The distance of Li scattered from the interface between the laminate and the external electrode was adjusted by adjusting the firing time and firing temperature of the fired chip with conductive paste in the manufacturing method according to the above embodiment. The distance of Li scattered from the interface between the laminate and the external electrode for each sample number is shown in Table 1. Sample number 1 indicates the presence or absence of Li scattered at the interface between the base electrode layer and the plating layer, and sample number 10 indicates that Li was not scattered into the base electrode layer (external electrode).

[0107] (3) Method of Moisture Resistance Test First, the multilayer ceramic capacitor of each sample was mounted on a wiring board using solder, and the insulation resistance value was measured. At this time, the multilayer ceramic capacitor of each sample mounted on the wiring board was placed in a high-temperature, high-humidity chamber, and the humidity test was performed by maintaining the chamber at 85°C and 85% RH for 2000 hours with a direct current of 200 V applied to the external electrodes of the multilayer ceramic capacitor of each sample. The insulation resistance value of each multilayer ceramic capacitor after the humidity test was measured. A sample that showed an insulation resistance value after the humidity test that was one order of magnitude lower than the insulation resistance value before the humidity test was deemed NG. The number of samples was 100.

[0108] (4) Method for Measuring the Distance of Li Scattered The distance of Li scattered from the interface between the laminate and the external electrode was defined as the distance of Li scattered from the interface between the laminate and the external electrode when the cross section of each sample was polished in the second direction z to 1 / 2 of the W dimension in the second direction z of the multilayer ceramic capacitor. The cross section was observed by TOF.SIM (manufactured by ION-TOF) under the conditions of 30 μm square, with the interface between the laminate 12 and the base electrode layer 32 as the center of the image. The presence of Li was confirmed as follows. That is, the presence or absence of Li in the base electrode layer was confirmed by TOF.SIMS (Time-of-Flight Secondary Ion Mass Spectrometry). The measurement conditions for this TOF.SIMS were as follows:・Device name: TOF. SIMS (manufactured by ION-TOF) ・Primary ion: Bi + Acceleration voltage: 25 kV Secondary ion polarity: Positive Number of scans: 32 Number of pixels: 256 pixels × 256 pixels Measurement area: □30 μm × 30 μm The presence or absence of Li was confirmed by the presence or absence of pixels with a Li intensity of 1.0 or more among the 256 pixels × 256 pixels. Furthermore, for each of Sample No. 1 and Sample No. 2, observation was performed by shifting the center of the observation image.

[0109] (5) Results Table 1 shows the distance that Li scattered from the interface between the laminate and the external electrode in each of the multilayer ceramic capacitor samples No. 1 to No. 10, and the results of the moisture resistance test relative to that distance.

[0110]

[0111] According to Table 1, the distance that Li was scattered from the interface between the laminate and the external electrode decreased from sample number 1 to sample number 10, and it was confirmed that as the distance decreased, the number of samples that failed the moisture resistance test also decreased.

[0112] From the above results, it was confirmed that in this invention, the longer the distance that Li is scattered from the interface between the laminate and the external electrode, the more the moisture resistance deteriorates. Therefore, it was suggested that the deterioration of moisture resistance can be suppressed by appropriately arranging lithium (Li) present in the external electrodes of the multilayer ceramic capacitor.

[0113] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited to this.

[0114] In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position or arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0115] <1> A laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrodes, the laminate having a first surface and a second surface opposing each other in a lamination direction, a third surface and a fourth surface opposing each other in a first direction perpendicular to the lamination direction, and a fifth surface and a sixth surface opposing each other in a second direction perpendicular to the lamination direction and the first direction; a first external electrode disposed on the third surface of the laminate; and a second external electrode disposed on the fourth surface of the laminate, the laminate including an internal layer portion and two external layer portions disposed to sandwich the internal layer portion in the lamination direction, the internal layer portion having: a first internal electrode having one end exposed on the third surface; and a second internal electrode having one end exposed on the fourth surface; and an internal dielectric layer in which the first internal electrode and the second internal electrode are disposed, the internal dielectric layer containing at least Ca, Sr or Zr as a main component, and Li, A multilayer ceramic capacitor in which the Li content in the first external electrode and / or the second external electrode is less than the Li content in the inner dielectric layer in at least one of a region of the first external electrode within 15 μm square in the first direction from the interface between the laminate and the first external electrode and a region of the second external electrode within 15 μm square in the first direction from the interface between the laminate and the second external electrode.

[0116] <2> The multilayer ceramic capacitor according to <1>, wherein the Li content in the first external electrode and / or the second external electrode is lower than the Li content in the inner dielectric layer in at least one of a region of the first external electrode within 5 μm square in the first direction from the interface between the laminate and the first external electrode and a region of the second external electrode within 5 μm square in the first direction from the interface between the laminate and the second external electrode.

[0117] <3> A laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrodes, the laminate having a first surface and a second surface opposing each other in a lamination direction, a third surface and a fourth surface opposing each other in a first direction perpendicular to the lamination direction, and a fifth surface and a sixth surface opposing each other in a second direction perpendicular to the lamination direction and the first direction, a first external electrode disposed on the third surface of the laminate, and a second external electrode disposed on the fourth surface of the laminate, wherein the laminate includes an internal layer portion and two external layer portions disposed to sandwich the internal layer portion in the lamination direction, the internal layer portion having: a first internal electrode having one end exposed on the third surface; and a second internal electrode having one end exposed on the fourth surface; and an internal dielectric layer in which the first internal electrode and the second internal electrode are disposed, the internal dielectric layer containing at least Ca, Sr or Zr as a main component, and Li, A multilayer ceramic capacitor in which Li is not present in at least one of a region of the first external electrode that is 15 μm or more away from the interface between the laminate and the first external electrode in the first direction, and a region of the second external electrode that is 15 μm or more away from the interface between the laminate and the second external electrode in the first direction,

[0118] <4> The multilayer ceramic capacitor according to <3>, wherein Li is not present in at least one of a region of the first external electrode that is 5 μm or more away from the interface between the laminate and the first external electrode in the first direction and a region of the second external electrode that is 5 μm or more away from the interface between the laminate and the second external electrode in the first direction and a region of the second external electrode that is 5 μm or more away from the laminate in the first direction.

[0119] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the internal electrodes are made of Cu.

[0120] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the Li content in the first external electrode decreases with increasing distance from the interface between the laminate and the first external electrode in the first direction, and / or the Li content in the second external electrode decreases with increasing distance from the interface between the laminate and the second external electrode in the first direction.

[0121] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein at least one of the first external electrode and the second external electrode contains Cu particles as a main component and a glass component, the Cu particles have a D50 of 0.3 μm or more and 0.6 μm or less, and the content of the glass component is 21 vol% or more and 25 vol% or less.

[0122] <8> The multilayer ceramic capacitor according to any one of <4> to <7>, wherein at least one of the first external electrode and the second external electrode does not contain Li.

[0123] 10, 10A, 110, 110A, 210 Multilayer ceramic capacitor 12, 12A, 112, 112A, 212 Laminate 12a, 112a, 212a First surface 12b, 112b, 212b Second surface 12c, 112c, 212c Third surface 12d, 112d, 212d Fourth surface 12e, 112e, 212e Fifth surface 12f, 112f, 212f Sixth surface 14 Dielectric layer 14a Inner dielectric layer 14b Outer dielectric layer 16 Inner layer portion 18a First surface side outer layer portion 18b Second surface side outer layer portion 20 Internal electrode 20a First internal electrode 20b Second internal electrode 20A Pair of first internal electrodes 20B Pair of second internal electrodes 22 Opposing electrode portion 22a First opposing electrode portion 22b Second opposing electrode portion 24a First lead electrode portion 24b Second lead electrode portion 26a, 26b Side portions 27a, 27b End portions 30 External electrode 30a First external electrode 30b Second external electrode 32 Base electrode layer 32a First base electrode layer 32b Second base electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 36 Base plating layer 36a First base plating layer 36b Second base plating layer 38 Upper plating layer 38a First upper plating layer 38b Second upper plating layer x Stacking direction y First direction z Second direction

Claims

1. A laminate comprising a plurality of stacked dielectric layers and a plurality of stacked internal electrodes, having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, A first external electrode disposed on the third surface of the laminate, A second external electrode disposed on the fourth surface of the laminate, Equipped with, The laminated body comprises an inner layer and Two outer layers are arranged to sandwich the inner layer in the stacking direction, Includes, The aforementioned inner layer is A first internal electrode with one end exposed on the third surface, A second internal electrode, with one end exposed on the fourth surface, An inner dielectric layer on which the first internal electrode and the second internal electrode are arranged, It has, The inner dielectric layer mainly comprises at least Ca, Sr, or Zr, and Li. A multilayer ceramic capacitor in which, in at least one of the regions of the first external electrode within 15 μm in the first direction from the interface between the laminate and the first external electrode, and the region of the second external electrode within 15 μm in the first direction from the interface between the laminate and the second external electrode, the Li content in the first external electrode and / or the Li content in the second external electrode is less than the Li content in the inner dielectric layer.

2. The multilayer ceramic capacitor according to claim 1, wherein in at least one of the regions of the first external electrode within □5 μm in the first direction from the interface between the laminate and the first external electrode, and the region of the second external electrode within □5 μm in the first direction from the interface between the laminate and the second external electrode, the Li content in the first external electrode and / or the second external electrode is less than the Li content in the inner dielectric layer.

3. A laminate comprising a plurality of stacked dielectric layers and a plurality of stacked internal electrodes, having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, A first external electrode disposed on the third surface of the laminate, A second external electrode disposed on the fourth surface of the laminate, Equipped with, The laminated body comprises an inner layer and Two outer layers are arranged to sandwich the inner layer in the stacking direction, Includes, The aforementioned inner layer is A first internal electrode with one end exposed on the third surface, A second internal electrode, with one end exposed on the fourth surface, An inner dielectric layer on which the first internal electrode and the second internal electrode are arranged, It has, The inner dielectric layer mainly comprises at least Ca, Sr, or Zr, and Li. A multilayer ceramic capacitor in which Li is not present in at least one of the following regions: a region of the first external electrode located 15 μm or more away from the laminate in the first direction from the interface between the laminate and the first external electrode, and a region of the second external electrode located 15 μm or more away from the laminate in the first direction from the interface between the laminate and the second external electrode.

4. The multilayer ceramic capacitor according to claim 3, wherein Li is not present in at least one of the following regions: a region of the first external electrode located 5 μm or more away from the laminate in the first direction from the interface between the laminate and the first external electrode, and a region of the second external electrode located 5 μm or more away from the laminate in the first direction from the interface between the laminate and the second external electrode.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the internal electrode is made of Cu.

6. The Li content in the first external electrode decreases as you move away from the interface between the laminate and the first external electrode in the first direction, and / or A multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the Li content in the second external electrode decreases as you move away from the interface between the laminate and the second external electrode in the first direction.

7. At least one of the first external electrode and the second external electrode comprises Cu particles as the main component and a glass component. The D50 of the Cu particles is 0.3 μm or more and 0.6 μm or less. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the content of the glass component is 21 vol% or more and 25 vol% or less.

8. The multilayer ceramic capacitor according to claim 4, wherein at least one of the first external electrode and the second external electrode does not contain Li.