Control device, program, and control method

Abstract

A control device (50) is applied to a power conversion device (10, 210, 310, 410) provided with: a series connection body of upper and lower arm elements (QH, QL); auxiliary capacitors (31H, 31L); a series connection body of first and second voltage dividing capacitors (33H, 33L); and a connection circuit including a reactor (32) and auxiliary switches (Q1, Q2). The control device comprises: a main control unit that performs switching control of a main switch that is one of the upper and lower arm elements; and an auxiliary control unit that performs switching control of the auxiliary switches. A voltage dividing capacitor connected in parallel with the main switch via the connection circuit among the first and second voltage dividing capacitors is set as a target capacitor. The auxiliary control unit performs switching control of the auxiliary switches so that a current flows in a direction in which the target capacitor is charged and then a current flows in a direction in which the target capacitor is discharged.

Description

Control device, program and control method CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Application No. 2024-016662, filed on February 6, 2024, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a control device, a program, and a control method.

[0003] A power conversion device including a switch and an auxiliary circuit has been known. A known control device for the power conversion device performs zero-volt switching (ZVS) to control the switching of the switch while the voltage applied to the switch is zero. An example of such a technique is disclosed in Patent Document 1.

[0004] Japanese Patent Application Publication No. 11-178319

[0005] If the switching state of the switch is changed at a timing when the voltage applied to the switch is shifted from 0, there is a concern that switching loss may increase.

[0006] A primary object of the present disclosure is to provide a control device, a program, and a control method that can reduce switching loss.

[0007] The present disclosure provides a control device applicable to a power conversion device including: a series connection of upper arm elements and lower arm elements; an auxiliary capacitor connected in parallel to the upper arm elements and the lower arm elements; a series connection of first and second voltage dividing capacitors connected in parallel to the series connection of the upper arm elements and the lower arm elements; and a connection circuit connecting a connection point of the upper arm elements and the lower arm elements to a connection point of the first and second voltage dividing capacitors, and including a reactor and an auxiliary switch, the control device including: a main control unit that performs switching control of a main switch that is one of the upper arm elements and the lower arm elements; and an auxiliary control unit that performs switching control of the auxiliary switch, wherein one of the first and second voltage dividing capacitors that is connected in parallel to the main switch via the connection circuit is considered to be a target capacitor, and the auxiliary control unit performs switching control of the auxiliary switch so that a current flows in a direction that charges the target capacitor, and then a current flows in a direction that discharges the target capacitor.

[0008] The connection circuit is equipped with a reactor and an auxiliary switch. The reactor and auxiliary capacitor resonate by switching control of the auxiliary switch. As the reactor and auxiliary capacitor resonate, the voltage applied to the main switch gradually decreases and approaches zero.

[0009] Here, there is a concern that the resonant operation of the reactor and auxiliary capacitor may cause charge to accumulate in the target capacitor, resulting in a deviation of the minimum value of the voltage applied to the main switch from zero. Therefore, in the present disclosure, the switching of the auxiliary switch is controlled so that current flows in a direction that charges the target capacitor, and then in a direction that discharges the target capacitor. This causes the charge accumulated in the target capacitor to be discharged. As a result, it is possible to prevent the minimum value of the voltage applied to the main switch from deviating from zero. Therefore, ZVS of the main switch can be achieved, and the switching loss of the main switch can be reduced.

[0010] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. 1 is an overall configuration diagram of a control system including a DC-DC converter according to a first embodiment; FIG. 2 is a timing chart showing an example of control performed by a control device; FIG. 3 is a diagram showing an example of a current flow path in mode 1; FIG. 4 is a diagram showing an example of a current flow path in mode 2; FIG. 5 is a diagram showing an example of a current flow path in mode 3; FIG. 6 is a diagram showing an example of a current flow path in mode 4; 24 is a diagram showing an example of a current flow path in mode 5; FIG. 25 is a diagram showing an example of a current flow path in mode 6; FIG. 26 is a timing chart showing an example of control performed by the control device; FIG. 27 is a diagram showing an example of a current flow path in mode 1; FIG. 28 is a diagram showing an example of a current flow path in mode 2; FIG. 29 is a diagram showing an example of a current flow path in mode 3;31 is a diagram showing an example of a current flow path in mode 5; FIG. 32 is a diagram showing an example of a current flow path in mode 6; FIG. 33 is an overall configuration diagram of a control system including a single-phase inverter according to a fourth embodiment; FIG. 34 is a diagram showing an example of a current flow path in mode 1; FIG. 35 is a diagram showing an example of a current flow path in mode 2; FIG. 36 is a diagram showing an example of a current flow path in mode 3; and FIG. 37 is a diagram showing an example of a current flow path in mode 4. 38 is a diagram showing an example of a current flow path in mode 5, FIG. 39 is a diagram showing an example of a current flow path in mode 6, FIG. 40 is a diagram showing an example of a current flow path in mode 1, FIG. 41 is a diagram showing an example of a current flow path in mode 2, FIG. 42 is a diagram showing an example of a current flow path in mode 3, FIG. 43 is a diagram showing an example of a current flow path in mode 4, FIG. 44 is a diagram showing an example of a current flow path in mode 5, FIG. 45 is a diagram showing an example of a current flow path in mode 6, and FIG. FIG. 47 is an overall configuration diagram of an auxiliary circuit according to a sixth embodiment, FIG. 48 is an overall configuration diagram of an auxiliary circuit according to a seventh embodiment, FIG. 49 is an overall configuration diagram of an auxiliary circuit according to an eighth embodiment, FIG. 50 is a diagram showing power loss occurring in a DC-DC converter according to a ninth embodiment, FIG. 51 is a flowchart showing the procedure for control performed by a microcomputer, FIG. 52 is a flowchart showing the procedure for control performed by a microcomputer according to a tenth embodiment, FIG. 53 is a time chart showing an example of a current flowing in a first voltage-dividing capacitor according to an eleventh embodiment, FIG. 54 is a time chart showing an example of a voltage applied to the first voltage-dividing capacitor, FIG. 55 is an overall configuration diagram of a control system including a DC-DC converter, FIG. 56 is a time chart for explaining the off timing of a second auxiliary switch, FIG. 57 is a time chart showing an example of a voltage applied to the first voltage-dividing capacitor, FIG. 58 is a flowchart showing the procedure for control performed by a microcomputer according to a twelfth embodiment, and FIG.60 is a diagram comparing the case where the second auxiliary switch is fully on with the case where it is half on; FIG. 61 is a diagram showing the overall configuration of a control system including a DC-DC converter according to a modification of the thirteenth embodiment; and FIG. 62 is a diagram showing the overall configuration of a control system including a DC-DC converter according to a modification of the thirteenth embodiment.

[0011] Several embodiments will be described with reference to the drawings. In several embodiments, functionally and / or structurally corresponding and / or associated parts may be designated by the same reference numerals or reference numerals that differ in the hundredth or more digit. For corresponding and / or associated parts, reference may be made to the descriptions of other embodiments.

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A first embodiment of a power conversion device according to the present disclosure will now be described with reference to the drawings. In this embodiment, the power conversion device is embodied as a DC-DC converter.

[0013] As shown in FIG. 1 , the power conversion system includes a DC-DC converter 10 and a DC power supply 20 .

[0014] The DC-DC converter 10 is a non-isolated boost converter that boosts a voltage input from a first main terminal T1 and a second main terminal T2 and outputs the boosted voltage from a third main terminal T3 and a fourth main terminal T4. In this embodiment, a positive terminal of a DC power supply 20 is connected to the first main terminal T1, and a negative terminal of the DC power supply 20 is connected to the second main terminal T2. The DC power supply 20 is a storage battery or the like. An output voltage Vout, which is a potential difference between the third main terminal T3 and the fourth main terminal T4, is higher than the voltage (e.g., rated voltage) of the DC power supply 20.

[0015] The DC-DC converter 10 includes a first capacitor 11, a first reactor 12, upper and lower arm switches QH and QL, upper and lower arm diodes DH and DL, and a second capacitor 13. In this embodiment, the upper and lower arm switches QH and QL are N-channel MOSFETs. In this case, the drains of the upper and lower arm switches QH and QL correspond to "high potential side terminals," and the sources correspond to "low potential side terminals." Note that the upper and lower arm switches QH and QL are not limited to N-channel MOSFETs and may be, for example, IGBTs with freewheel diodes connected in reverse parallel. In this case, the collectors of the upper and lower arm switches QH and QL correspond to "high potential side terminals," and the emitters correspond to "low potential side terminals."

[0016] A first end of the first reactor 12 is connected to the first main terminal T1 and a first end of the first capacitor 11. A second end of the first reactor 12 is connected to the source of the upper-arm switch QH, the anode of the upper-arm diode DH, the drain of the lower-arm switch QL, and the cathode of the lower-arm diode DL. The upper and lower-arm diodes DH and DL are body diodes of the upper and lower-arm switches QH and QL.

[0017] The drain of the upper arm switch QH is connected to the cathode of the upper arm diode DH, a first end of the second capacitor 13, and the third main terminal T3. The source of the lower arm switch QL is connected to the anode of the lower arm diode DL, a second end of the first capacitor 11, a second end of the second capacitor 13, and the second and fourth main terminals T2 and T4. In this embodiment, the upper arm switch QH corresponds to the "upper arm element," and the lower arm switch QL corresponds to the "lower arm element."

[0018] The DC-DC converter 10 includes an auxiliary circuit 30. The auxiliary circuit 30 includes a second reactor 32, first and second auxiliary capacitors 31H and 31L serving as snubber capacitors, first and second auxiliary switches Q1 and Q2, first and second auxiliary diodes D1 and D2, and first and second voltage-dividing capacitors 33H and 33L. In this embodiment, the first and second auxiliary switches Q1 and Q2 are N-channel MOSFETs. The first and second auxiliary switches Q1 and Q2 are not limited to N-channel MOSFETs and may be, for example, IGBTs with freewheeling diodes connected in anti-parallel. In this embodiment, the second reactor 32 and the first and second auxiliary switches Q1 and Q2 correspond to a "connection circuit."

[0019] The first terminal of the second reactor 32 is connected to the first terminal of the first auxiliary capacitor 31H and the second auxiliary capacitor 31L. The second terminal of the second reactor 32 is connected to the drain of the first auxiliary switch Q1 and the cathode of the first auxiliary diode D1.

[0020] The source of the first auxiliary switch Q1 is connected to the anode of the first auxiliary diode D1, the source of the second auxiliary switch Q2, and the anode of the second auxiliary diode D2. The drain of the second auxiliary switch Q2 is connected to the cathode of the second auxiliary diode D2 and the first ends of the voltage-dividing capacitors 33H and 33L. The first and second auxiliary diodes D1 and D2 are body diodes of the first and second auxiliary switches Q1 and Q2.

[0021] The second end of the first auxiliary capacitor 31H is connected to the second end of the first voltage-dividing capacitor 33H. The second end of the second auxiliary capacitor 31L is connected to the second end of the second voltage-dividing capacitor 33L. In this embodiment, the capacitances of the first voltage-dividing capacitor 33H and the second voltage-dividing capacitor 33L are equal.

[0022] The auxiliary circuit 30 includes first to third auxiliary terminals Tsub1, Tsub2, and Tsub3. The first auxiliary terminal Tsub1 is connected to the connection point of the upper and lower arm switches QH and QL.

[0023] The second auxiliary terminal Tsub2 is connected to the drain of the upper arm switch QH, the first end of the second capacitor 13, and the second end of the first voltage dividing capacitor 33H.

[0024] The third auxiliary terminal Tsub3 is connected to the source of the lower arm switch QL, the second end of the second capacitor 13, and the second end of the second voltage dividing capacitor 33L.

[0025] The DC-DC converter 10 includes a first voltage sensor 40, a second voltage sensor 41, a first current sensor 42, and a second current sensor 43. The first voltage sensor 40 detects the voltage of the first capacitor 11. The second voltage sensor 41 detects the voltage of the second capacitor 13. The first current sensor 42 detects the current flowing through the first reactor 12. The second current sensor 43 detects the current flowing through the second reactor 32. The detected values ​​of the voltage sensors 40, 41 and the detected values ​​of the current sensors 42, 43 are input to a control device 50 included in the DC-DC converter 10.

[0026] The control device 50 is primarily composed of a microcomputer 51, which includes a CPU. The functions provided by the microcomputer 51 can be provided by software stored in a physical memory device and a computer executing the software, software alone, hardware alone, or a combination thereof. For example, if the microcomputer 51 is provided by a hardware electronic circuit, the function can be provided by a digital circuit including multiple logic circuits or an analog circuit. For example, the microcomputer 51 executes a program stored in a non-transitory tangible storage medium serving as a storage unit of the microcomputer 51. The program includes, for example, a program for the process shown in FIG. 9 (described later). Execution of the program results in the execution of a method corresponding to the program. The storage unit is, for example, a non-volatile memory. The program stored in the storage unit can be updated via a communication network such as the Internet, for example, via OTA (Over the Air).

[0027] The DC-DC converter 10 includes a drive circuit 52. The control device 50 generates upper and lower arm switching commands SgQH, SgQL and first and second auxiliary switching commands SgQ1, SgQ2 and outputs them to the drive circuit 52. Specifically, the switching commands SgQH, SgQL, SgQ1, and SgQ2 are PWM signals. The drive circuit 52 turns on and off the upper and lower arm switches QH, QL and the first and second auxiliary switches Q1, Q2 based on the switching commands SgQH, SgQL, SgQ1, and SgQ2.

[0028] In this embodiment, voltage VCi represents the voltage of the first auxiliary capacitor 31H, and voltage VCd represents the voltage of the second auxiliary capacitor 31L. Current IAc represents the current flowing in the upper arm of the DC-DC converter 10, and current IAf represents the current flowing in the lower arm of the DC-DC converter 10.

[0029] The current flowing through the second reactor 32 is referred to as reactor current IL. In this embodiment, the direction of current IAc is positive when it flows from the connection point of the upper and lower arm switches QH and QL to the upper arm switch QH. The direction of current IAf is positive when it flows from the connection point of the upper and lower arm switches QH and QL to the lower arm switch QL. The direction of reactor current IL is positive when it flows from the first auxiliary terminal Tsub1 to the second reactor 32.

[0030] The control device 50 controls the switching of the upper arm switch QH and the lower arm switch QL to boost and output the input voltage input from the first main terminal T1 and the second main terminal T2. The upper arm switch QH and the lower arm switch QL are alternately turned on with a dead time therebetween.

[0031] In order to suppress the switching loss of the lower arm switch QL in the voltage boost control, it is necessary to realize ZVS, in which the lower arm switch QL is turned on when no voltage is applied to the lower arm switch QL. Hereinafter, the voltage boost control for realizing ZVS will be described with reference to FIG.

[0032] 2 shows a timing chart of the boost control process executed by the control device 50. Note that one switching period of the lower arm switch QL is expressed as 1 / fsw using the switching frequency fsw.

[0033] 2, (a) shows the transition of the lower arm switching command SgQL, (b) shows the transition of the first auxiliary switching command SgQ1, (c) shows the transition of the second auxiliary switching command SgQ2, (d) shows the transition of the reactor current IL, (e) shows the transition of the voltage VCi and the voltage VCd, and (f) shows the transition of the current IAc and the current IAf. In FIG. 2(e), the transition of the voltage VCd is indicated by a solid line, and the transition of the voltage VCi is indicated by a dashed line. In FIG. 2(f), the transition of the current IAf is indicated by a solid line, and the transition of the current IAc is indicated by a dashed line.

[0034] In FIG. 2, the period from time t1 to time t8 is referred to as modes 1 to 6 as follows.

[0035] Mode 1: The period from time t1 to time t2. Mode 2: The period from time t2 to time t3. Mode 3: The period from time t3 to time t5. Mode 4: The period from time t5 to time t6. Mode 5: The period from time t6 to time t7. Mode 6: The period from time t7 to time t8. Each mode will now be explained with reference to Figures 2 to 8.

[0036] [Mode 1] At time t1, the logic of the lower-arm switching command SgQL is switched from H to L. As a result, as shown in Fig. 3 , a current flows from the first main terminal T1 to the third main terminal T3 via the first reactor 12 and the upper-arm diode DH. Also, a current flows from the fourth main terminal T4 to the second main terminal T2.

[0037] In this embodiment, the upper arm switch QH is turned on during the period from time t1 to time t2, and turned off during the period from time t2 to time t8. The upper arm switch QH may be turned on during the period from time t1 to the time when the logic of the lower arm switching command SgQL is switched to H, excluding timing t2 when the logic of the first auxiliary switching command SgQ1 is switched from L to H, provided that the upper arm switch QH is not turned on simultaneously with the lower arm switch QL.

[0038] [Mode 2] At time t2, the logic of the first auxiliary switching command SgQ1 is switched from L to H. This turns on the first auxiliary switch Q1, allowing the reactor current IL to flow in the direction of charging the second voltage-dividing capacitor 33L. Specifically, as shown in FIG. 4 , current flows from the first main terminal T1 through the first reactor 12, the second reactor 32, the first auxiliary switch Q1, and the second auxiliary diode D2 to the first and second voltage-dividing capacitors 33H and 33L, causing the reactor current IL to begin to increase. Furthermore, current flows from the first voltage-dividing capacitor 33H to the third main terminal T3, discharging the first voltage-dividing capacitor 33H. Current flows from the second voltage-dividing capacitor 33L to the second main terminal T2, charging the second voltage-dividing capacitor 33L. In this embodiment, the second voltage-dividing capacitor 33L corresponds to the "target capacitor." The first auxiliary switch Q1 corresponds to the "charging switch."

[0039] During the period from time t2 to time t7, LC resonance occurs between the second reactor 32 and at least one of the second auxiliary capacitor 31L and the first and second voltage dividing capacitors 33H, 33L, causing a sinusoidal current to flow through the second reactor 32.

[0040] [Mode 3] At time t3, as shown in Fig. 5, a current flows through a closed circuit including the second reactor 32, the first auxiliary switch Q1, the second auxiliary diode D2, the second voltage dividing capacitor 33L, and the second auxiliary capacitor 31L. This causes the second auxiliary capacitor 31L to discharge, and the voltage VCd of the second auxiliary capacitor 31L begins to decrease. Furthermore, as in mode 2, the first voltage dividing capacitor 33H is discharged, and the second voltage dividing capacitor 33L is charged.

[0041] At time t4, the voltage VCd of the second auxiliary capacitor 31L becomes 0, and the current IAf flowing through the lower arm becomes less than 0. During a main switching period SPm from time t4 to time t5, the logic of the lower arm switching command SgQL is switched from L to H. This makes it possible to achieve ZVS, in which the lower arm switch QL is turned on while the drain-source voltage of the lower arm switch QL is 0, thereby reducing the switching loss of the lower arm switch QL.

[0042] The control device 50 may determine whether or not it is in the main switching period SPm, for example, as follows: The control device 50 counts the elapsed time since the first auxiliary switch Q1 was turned on, and determines that it is in the main switching period SPm when it determines that the counted elapsed time has reached a first determination time Tth1. The first determination time Tth1 is set to a value that allows it to determine that the drain-source voltage of the lower arm switch QL is zero.

[0043] When the control device 50 determines that it is the main switching period SPm, it switches the logic of the lower arm switching command SgQL from L to H. This allows the lower arm switch QL to be turned on when the drain-source voltage of the lower arm switch QL is 0, thereby reducing the switching loss of the lower arm switch QL. In this embodiment, the lower arm switch QL corresponds to the "main switch."

[0044] [Mode 4] After the current IAf flowing through the lower arm becomes zero at time t5, as shown in Fig. 6, a current flows from the first main terminal T1 to the second main terminal T2 via the first reactor 12 and the lower-arm switch QL, causing the current IAf flowing through the lower arm to exceed zero. Also, a current flows from the second reactor 32 to the first and second voltage dividing capacitors 33H, 33L via the first auxiliary switch Q1 and the second auxiliary diode D2. As a result, the first voltage dividing capacitor 33H is discharged and the second voltage dividing capacitor 33L is charged.

[0045] Furthermore, in mode 4, the logic of the second auxiliary switching command SgQ2 is switched from L to H. In this embodiment, the second auxiliary switch Q2 is turned on during the period from time t1 to time t6, and is turned off during the period from time t7 to time t1 of the next switching cycle of the lower arm switch QL. By turning on the second auxiliary switch Q2, the second voltage dividing capacitor 33L can be discharged in mode 5, which will be described later. In other words, by turning on the second auxiliary switch Q2, the reactor current IL is allowed to flow in the discharge direction of the second voltage dividing capacitor 33L. In this embodiment, the first and second auxiliary switches Q1 and Q2 correspond to "auxiliary switches." The second auxiliary switch Q2 corresponds to a "discharge switch."

[0046] For example, the control device 50 turns on the second auxiliary switch Q2 during a period in which the reactor current IL flows in the charging direction of the second voltage dividing capacitor 33L. The control device 50 can determine whether or not the period in which the reactor current IL flows in the charging direction of the second voltage dividing capacitor 33L is as follows. For example, the control device 50 determines that the period in which the reactor current IL flows in the charging direction of the second voltage dividing capacitor 33L is when the detection value of the second current sensor 43 is positive. Furthermore, for example, the control device 50 determines that the period in which the reactor current IL flows in the charging direction of the second voltage dividing capacitor 33L is the period from when the first auxiliary switch Q1 is turned on until a predetermined period has elapsed as the period in which the reactor current IL flows in the charging direction of the second voltage dividing capacitor 33L. The predetermined period is a period determined according to the characteristics of the DC-DC converter 10, such as the capacitance of the first capacitor 11 and the inductance of each reactor 12, 32. In a configuration in which the second auxiliary switch is turned on based on the time that has elapsed since the first auxiliary switch Q1 was turned on, the DC-DC converter 10 does not need to include the second current sensor 43 .

[0047] [Mode 5] At time t6, the reactor current IL falls below 0, and as shown in Fig. 7, a current flows through a closed circuit including the lower arm switch QL, the second voltage dividing capacitor 33L, the second auxiliary switch Q2, the first auxiliary switch Q1, and the second reactor 32, thereby discharging the second voltage dividing capacitor 33L. A current flows from the third main terminal T3 to the first voltage dividing capacitor 33H, thereby charging the first voltage dividing capacitor 33H.

[0048] During the auxiliary switching period SPs, which is the period from time t6 to time t7 when the reactor current IL increases and becomes zero, the logic of the first auxiliary switching command SgQ1 is switched from H to L. In other words, the auxiliary switching period SPs is the period during which the reactor current IL flows in the discharge direction of the second voltage dividing capacitor 33L. During the auxiliary switching period SPs, the voltage VCd of the second auxiliary capacitor 31L is zero and the reactor current IL is less than zero. Furthermore, at time t7, the logic of the second auxiliary switching command SgQ2 is switched from H to L.

[0049] [Mode 6] At time t7, the reactor current IL becomes 0, and a current flows from the first main terminal T1 to the second main terminal T2 via the first reactor 12 and the lower arm switch QL, as shown in Fig. 8. Note that, instead of time t7, the logic of the second auxiliary switching command SgQ2 may be switched from H to L after the auxiliary switching period SPs, during the period in which the lower arm switch QL is on.

[0050] 9 is a flowchart showing the procedure of the switch changeover process in the voltage step-up control. This process is executed by the microcomputer 51. In the following, ZVS is executed in the switching control of the lower arm switch QL.

[0051] In step S10, the first auxiliary switch Q1 is turned on, causing a current to flow from the connection point of the upper and lower arm switches QH and QL through the second reactor 32, the first auxiliary switch Q1, and the second auxiliary diode D2 to the second voltage dividing capacitor 33L, thereby charging the second voltage dividing capacitor 33L.

[0052] In step S11, the lower arm switch QL is turned on during the main switching period SPm. In this embodiment, the process of step S11 corresponds to the "main control unit."

[0053] In step S12, the second auxiliary switch Q2 is turned on, causing a current to flow from the second voltage dividing capacitor 33L to the connection point of the upper and lower arm switches QH and QL via the first and second auxiliary switches Q1 and Q2 and the second reactor 32, thereby discharging the second voltage dividing capacitor 33L.

[0054] In step S13, the first auxiliary switch Q1 is turned off during the auxiliary switching period SPs. In step S14, the second auxiliary switch Q2 is turned off. In this embodiment, the processes of steps S10, S12, S13, and S14 correspond to the "auxiliary control unit."

[0055] The constants of the components of the DC-DC converter 10 (for example, the inductance of the reactor and the capacitance of the capacitor) may vary due to individual differences or deterioration over time of the DC-DC converter 10. In this case, the timing at which the drain-source voltage of the lower arm switch QL becomes zero varies.

[0056] In this embodiment, the drain-source voltage of the lower-arm switch QL is zero throughout the main switching period SPm, so that a margin can be provided for switching on the lower-arm switch QL to achieve ZVS. This margin can be provided because, after the second auxiliary switch Q2 is switched on, the direction of the reactor current IL becomes a direction that allows discharge from the second voltage dividing capacitor 33L.

[0057] In this embodiment, the second voltage-dividing capacitor 33L, which is charged in modes 2 to 4, is discharged in mode 5. This ensures that the voltage of the second voltage-dividing capacitor 33L is always maintained at or below half the output voltage Vout. This allows for ZVS to be achieved when the lower-arm switch QL is turned on, thereby reducing the switching loss of the lower-arm switch QL.

[0058] 10 shows a comparative example in which the control shifts from mode 4 to mode 6 without passing through mode 5. In this case, each time modes 1 to 4 and 6 are repeated, the voltage of the second voltage-dividing capacitor 33L rises to Vout, as shown in FIG.

[0059] 10A, when the lower arm switch QL is turned on at a switching timing Tr when the voltage of the second voltage-dividing capacitor 33L reaches a predetermined voltage Vr, the voltage of the second voltage-dividing capacitor 33L exceeds Vout / 2. In this case, as shown in FIG. 10B, the drain-source voltage of the lower arm switch QL may not be reduced to 0 when the lower arm switch QL is switched on.

[0060] <Modification of First Embodiment> The arrangement order of the second reactor 32, the first auxiliary switch Q1, and the second auxiliary switch Q2 is not limited to the order shown in Fig. 1. Specifically, the second reactor 32 may be located between the first auxiliary switch Q1 and the second auxiliary switch Q2, or between the second auxiliary switch Q2 and the connection point of the first and second voltage dividing capacitors 33H, 33L.

[0061] Second Embodiment A second embodiment will now be described with reference to the drawings, focusing on differences from the first embodiment. In this embodiment, the DC-DC converter 10 is used as a step-down converter.

[0062] As shown in Fig. 11 , the power conversion system includes a DC-DC converter 10 and a DC power supply 120. The DC-DC converter 10 is a non-isolated step-down converter that steps down a voltage input from a third main terminal T3 and a fourth main terminal T4 and outputs the stepped-down voltage from a first main terminal T1 and a second main terminal T2. In this embodiment, a positive terminal of the DC power supply 120 is connected to the third main terminal T3, and a negative terminal of the DC power supply 120 is connected to the fourth main terminal T4. The DC power supply 120 is, for example, a storage battery. An output voltage Vout, which is a potential difference between the first main terminal T1 and the second main terminal T2, is lower than the voltage (for example, a rated voltage) of the DC power supply 120.

[0063] In this embodiment, voltage VCi represents the voltage of the second auxiliary capacitor 31L, and voltage VCd represents the voltage of the first auxiliary capacitor 31H. Current IAc represents the current flowing in the lower arm of the DC-DC converter 10, and current IAf represents the current flowing in the upper arm of the DC-DC converter 10.

[0064] In this embodiment, the direction of current IAf flowing through the upper arm is defined as positive when it flows from the upper arm switch QH to the junction of the upper and lower arm switches QH and QL. The direction of current IAc flowing through the lower arm is defined as positive when it flows from the lower arm switch QL to the junction of the upper and lower arm switches QH and QL. Furthermore, the direction of reactor current IL is defined as positive when it flows from the second reactor 32 to the first auxiliary terminal Tsub1.

[0065] The control device 50 controls the switching of the upper arm switch QH and the lower arm switch QL to step down the input voltage input from the third main terminal T3 and the fourth main terminal T4 and output the output voltage Vout. The upper arm switch QH and the lower arm switch QL are alternately turned on with a dead time therebetween.

[0066] The switching process executed by the control device 50 will be described with reference to Fig. 2. In Fig. 2, (a) shows the transition of the upper arm switching command SgQH, (b) shows the transition of the second auxiliary switching command SgQ2, and (c) shows the transition of the first auxiliary switching command SgQ1.

[0067] In mode 0 before the switch changeover process is executed, the upper arm switch QH is turned on. As a result, as shown in Fig. 12 , a current flows from the third main terminal T3 to the first main terminal T1 via the upper arm switch QH and the first reactor 12, and magnetic energy is stored in the first reactor 12.

[0068] In mode 1, the upper-arm switch QH is turned off. Due to the magnetic energy stored in the first reactor 12, a current flows from the second main terminal T2 to the first main terminal T1 via the lower-arm diode DL and the first reactor 12, as shown in FIG.

[0069] In this embodiment, the lower arm switch QL is turned off from time t1 to time t8. Note that the lower arm switch QL may be turned on during the period from time t1 until the upper arm switch QH is turned on, excluding timing t2 when the second auxiliary switch Q2 is turned on from off, provided that the lower arm switch QL is not turned on simultaneously with the upper arm switch QH.

[0070] In mode 2, the second auxiliary switch Q2 is turned on. This allows the reactor current IL to flow in the direction of charging the first voltage-dividing capacitor 33H. Specifically, as shown in FIG. 14 , current flows from the first and second voltage-dividing capacitors 33H and 33L to the first main terminal T1 via the second auxiliary switch Q2, the first auxiliary diode D1, the second reactor 32, and the first reactor 12, and the reactor current IL begins to increase. Furthermore, current flows from the second main terminal T2 to the second voltage-dividing capacitor 33L, discharging the second voltage-dividing capacitor 33L. Current flows from the third main terminal T3 to the first voltage-dividing capacitor 33H, charging the first voltage-dividing capacitor 33H. In this embodiment, the first voltage-dividing capacitor 33H corresponds to the "target capacitor." The second auxiliary switch Q2 corresponds to the "charging switch."

[0071] 15 , in mode 3, a current flows through a closed circuit including the first auxiliary capacitor 31H, the first voltage-dividing capacitor 33H, the second auxiliary switch Q2, the first auxiliary diode D1, and the second reactor 32. This causes the first auxiliary capacitor 31H to discharge, and the voltage VCd of the first auxiliary capacitor 31H begins to drop. In addition, the first voltage-dividing capacitor 33H is charged. Current flows from the second main terminal T2 and the fourth main terminal T4 to the second voltage-dividing capacitor 33L, causing the second voltage-dividing capacitor 33L to discharge.

[0072] In this embodiment, the main switching period SPm is a period during which the voltage VCd of the first auxiliary capacitor 31H becomes 0 and the current IAf flowing through the upper arm becomes less than 0. During the main switching period SPm, the upper arm switch QH is turned on. This achieves ZVS, in which the upper arm switch QH is turned on when the drain-source voltage of the upper arm switch QH is 0, thereby reducing the switching loss of the upper arm switch QH.

[0073] The control device 50 may determine whether or not it is in the main switching period SPm, for example, as follows: The control device 50 counts the elapsed time since the second auxiliary switch Q2 was turned on, and determines that it is in the main switching period SPm when it determines that the counted elapsed time has reached a first determination time Tth1. The first determination time Tth1 is set to a value that allows it to determine that the drain-source voltage of the upper arm switch QH is zero.

[0074] When the control device 50 determines that it is the main switching period SPm, it turns on the upper arm switch QH. This allows the upper arm switch QH to be turned on in a state where the drain-source voltage of the upper arm switch QH is 0, thereby reducing the switching loss of the upper arm switch QH. In this embodiment, the upper arm switch QH corresponds to the "main switch."

[0075] 16 , in mode 4, a current flows from the third main terminal T3 to the first main terminal T1 via the upper arm switch QH and the first reactor 12, and the current IAf flowing in the upper arm exceeds 0. Also, a current flows from the third main terminal T3 to the first voltage dividing capacitor 33H, charging the first voltage dividing capacitor 33H. A current flows from the second main terminal T2 to the second voltage dividing capacitor 33L, discharging the second voltage dividing capacitor 33L.

[0076] Furthermore, in mode 4, the first auxiliary switch Q1 is turned on. In this embodiment, the first auxiliary switch Q1 is turned on during the period from time t1 to time t6, and is turned off during the period from time t7 to time t1 of the next switching cycle. By turning on the first auxiliary switch Q1, the first voltage dividing capacitor 33H can be discharged in mode 5, which will be described later. In other words, by turning on the first auxiliary switch Q1, the reactor current IL is allowed to flow in the discharge direction of the first voltage dividing capacitor 33H. In this embodiment, the first and second auxiliary switches Q1 and Q2 correspond to "auxiliary switches." The first auxiliary switch Q1 corresponds to a "discharge switch."

[0077] For example, the control device 50 turns on the first auxiliary switch Q1 during a period in which the reactor current IL flows in the charging direction of the first voltage dividing capacitor 33H. In this case, the control device 50 may determine whether or not the period in which the reactor current IL flows in the charging direction of the first voltage dividing capacitor 33H is the same as in the case described in the first embodiment.

[0078] 17 , in mode 5, a current flows through a closed circuit including the upper arm switch QH, the second reactor 32, the first and second auxiliary switches Q1 and Q2, and the first voltage dividing capacitor 33H, the reactor current IL falls below 0, and the first voltage dividing capacitor 33H is discharged. Also, a current flows from the second voltage dividing capacitor 33L to the fourth main terminal T4, and the second voltage dividing capacitor 33L is charged.

[0079] The second auxiliary switch Q2 is turned off during the auxiliary switching period SPs, which is the period from time t6 to time t7 when the reactor current IL increases and becomes zero. In other words, the auxiliary switching period SPs is the period during which the reactor current IL flows in the discharge direction of the first voltage dividing capacitor 33H. During the auxiliary switching period SPs, the voltage VCd of the first auxiliary capacitor 31H is zero and the reactor current IL is less than zero. Also, at time t7, the first auxiliary switch Q1 is turned off.

[0080] In mode 6, the reactor current IL becomes 0, and as shown in Fig. 18, a current flows from the third main terminal T3 to the first main terminal T1 via the upper arm switch QH and the first reactor 12. Also, a current flows from the second main terminal T2 to the fourth main terminal T4. Note that, instead of at time t7, the first auxiliary switch Q1 may be turned off during the period after the auxiliary switching period SPs when the upper arm switch QH is turned on.

[0081] The switch switching process shown in FIG. 9 can also be applied to this embodiment. This process is executed by the microcomputer 51. In the following, ZVS is executed in the switching control of the upper arm switch QH. In this embodiment, the first auxiliary switch Q1 in FIG. 9 is replaced with the second auxiliary switch Q2, and the second auxiliary switch Q2 is replaced with the first auxiliary switch Q1.

[0082] In step S10, the second auxiliary switch Q2 is turned on, causing a current to flow from the first voltage dividing capacitor 33H to the connection point between the upper and lower arm switches QH and QL via the second auxiliary switch Q2, the first auxiliary diode D1, and the second reactor 32, thereby charging the first voltage dividing capacitor 33H.

[0083] In step S11, the upper arm switch QH is turned on during the main switching period SPm. In this embodiment, the process of step S11 corresponds to the "main control unit."

[0084] In step S12, the first auxiliary switch Q1 is turned on, causing a current to flow from the connection point between the upper and lower arm switches QH and QL through the second reactor 32 and the first and second auxiliary switches Q1 and Q2 to the first voltage dividing capacitor 33H, thereby discharging the first voltage dividing capacitor 33H.

[0085] In step S13, the second auxiliary switch Q2 is turned off during the auxiliary switching period SPs. In step S14, the first auxiliary switch Q1 is turned off. In this embodiment, the processes of steps S10, S12, S13, and S14 correspond to the "auxiliary control unit."

[0086] According to the present embodiment described above, it is possible to achieve the same effects as the first embodiment.

[0087] <Modification of Second Embodiment> The DC-DC converter 10 may be used as a step-up / step-down converter.

[0088] Third Embodiment A third embodiment will now be described with reference to the drawings, focusing on differences from the first embodiment. In this embodiment, a power conversion system includes a PFC converter 210 and an AC power supply 220, as shown in FIG.

[0089] An AC power supply 220 is connected to the first main terminal T1 and the second main terminal T2 of the PFC converter 210. The AC output voltage Vac of the AC power supply 220 is considered positive when the voltage on the first main terminal T1 side is higher than the voltage on the second main terminal T2 side.

[0090] The PFC converter 210 includes upper and lower arm rectifier elements 14H and 14L. In this embodiment, the upper arm rectifier element 14H and the lower arm rectifier element 14L are diodes. The cathode of the upper arm rectifier element 14H is connected to the drain of the upper arm switch QH, the cathode of the upper arm diode DH, the second auxiliary terminal Tsub2, the first end of the second capacitor 13, and the third main terminal T3. The anode of the upper arm rectifier element 14H is connected to the second main terminal T2, the second end of the first capacitor 11, and the cathode of the lower arm rectifier element 14L.

[0091] The anode of the lower arm rectifier element 14L is connected to the source of the lower arm switch QL, the anode of the lower arm diode DL, the third auxiliary terminal Tsub3, the second end of the second capacitor 13, and the fourth main terminal T4.

[0092] The control device 50 performs switching control of the upper arm switch QH and the lower arm switch QL, for example, to convert the AC current output from the AC power supply 220 into DC current and improve the power factor. The upper arm switch QH and the lower arm switch QL are alternately turned on with a dead time therebetween.

[0093] When the AC output voltage Vac is positive and the lower arm switch QL is turned on, the timing chart of the switch changeover process is shown in Fig. 2. When the AC output voltage Vac is negative and the upper arm switch QH is turned on, the timing chart of the switch changeover process is shown in Fig. 26.

[0094] 2, a description will be given of the switch changeover process that is executed when the AC output voltage Vac of the AC power supply 220 is positive. In FIG. 2, (a) shows the transition of the lower arm switching command SgQL, (b) shows the transition of the first auxiliary switching command SgQ1, and (c) shows the transition of the second auxiliary switching command SgQ2.

[0095] Note that voltage VCi indicates the voltage of the first auxiliary capacitor 31H, and voltage VCd indicates the voltage of the second auxiliary capacitor 31L. Current IAc indicates the current flowing in the upper arm of the PFC converter 210, and current IAf indicates the current flowing in the lower arm of the PFC converter 210. In the switch changeover process that is executed when the AC output voltage Vac of the AC power supply 220 is positive, the second voltage-dividing capacitor 33L corresponds to the "target capacitor," the first auxiliary switch Q1 corresponds to the "charge switch," and the second auxiliary switch Q2 corresponds to the "discharge switch."

[0096] In mode 1, the lower-arm switch QL is turned off. As a result, as shown in Fig. 20, a current flows from the first main terminal T1 to the third main terminal T3 via the first reactor 12 and the upper-arm diode DH. Also, a current flows from the fourth main terminal T4 to the second main terminal T2 via the lower-arm rectifier element 14L.

[0097] In this embodiment, the upper arm switch QH is turned off from time t1 to time t8. Note that the upper arm switch QH may be turned on during the period from time t1 to when the lower arm switch QL is turned on, excluding timing t2 when the first auxiliary switch Q1 is switched from off to on, provided that the upper arm switch QH is not turned on simultaneously with the lower arm switch QL.

[0098] In mode 2, the first auxiliary switch Q1 is turned on. As a result, as shown in Fig. 21, current flows from the first main terminal T1 through the first reactor 12, the second reactor 32, the first auxiliary switch Q1, and the second auxiliary diode D2 to the first and second voltage dividing capacitors 33H and 33L, and the reactor current IL begins to rise. Here, the first voltage dividing capacitor 33H is discharged and the second voltage dividing capacitor 33L is charged.

[0099] 22, in mode 3, a current flows through a closed circuit including the second reactor 32, the first auxiliary switch Q1, the second auxiliary diode D2, the second voltage dividing capacitor 33L, and the second auxiliary capacitor 31L. This causes the second auxiliary capacitor 31L to discharge, and the voltage VCd of the second auxiliary capacitor 31L begins to drop. Also, as in mode 2, the first voltage dividing capacitor 33H is discharged, and the second voltage dividing capacitor 33L is charged.

[0100] In this embodiment, when the AC output voltage Vac of the AC power supply 220 is positive, the main switching period SPm is a period during which the voltage VCd of the second auxiliary capacitor 31L becomes 0 and the current IAf flowing through the lower arm becomes less than 0. During the main switching period SPm, the lower arm switch QL is turned on. This makes it possible to achieve ZVS, in which the lower arm switch QL is turned on while the drain-source voltage of the lower arm switch QL is 0, thereby reducing the switching loss of the lower arm switch QL.

[0101] 23 , in mode 4, a current flows from the first main terminal T1 to the second main terminal T2 via the first reactor 12, the lower-arm switch QL, and the lower-arm rectifier element 14L, and the current IAf flowing in the lower arm exceeds 0. Also, a current flows from the first main terminal T1 to the first and second voltage dividing capacitors 33H and 33L via the first reactor 12, the second reactor 32, the first auxiliary switch Q1, and the second auxiliary diode D2. As a result, the first voltage dividing capacitor 33H is discharged and the second voltage dividing capacitor 33L is charged.

[0102] Furthermore, the second auxiliary switch Q2 is turned on in mode 4. In this embodiment, the second auxiliary switch Q2 is turned on from time t1 to time t6, and is turned off from time t7 to time t1 of the next switching cycle.

[0103] In mode 5, the reactor current IL falls below 0, and as shown in Fig. 24, a current flows through a closed circuit including the lower arm switch QL, the second voltage dividing capacitor 33L, the first and second auxiliary switches Q1 and Q2, and the second reactor 32, thereby discharging the second voltage dividing capacitor 33L. Also, a current flows from the third main terminal T3 to the first voltage dividing capacitor 33H, thereby charging the first voltage dividing capacitor 33H.

[0104] During the auxiliary switching period SPs, which is the period from time t6 to time t7 when the reactor current IL increases and becomes 0, the first auxiliary switch Q1 is turned off. At time t7, the second auxiliary switch Q2 is turned off.

[0105] In mode 6, the reactor current IL becomes 0, and as shown in FIG. 25, a current flows from the first main terminal T1 to the second main terminal T2 via the first reactor 12, the lower arm switch QL, and the lower arm rectifier element 14L.

[0106] Next, the switching process executed when the AC output voltage Vac of the AC power supply 220 is negative will be described with reference to Fig. 26. In Fig. 26, (a) shows the transition of the upper arm switching command SgQH, (b) shows the transition of the second auxiliary switching command SgQ2, and (c) shows the transition of the first auxiliary switching command SgQ1.

[0107] Note that voltage VCi indicates the voltage of second auxiliary capacitor 31L, and voltage VCd indicates the voltage of first auxiliary capacitor 31H. Current IAc indicates the current flowing in the lower arm of PFC converter 210, and current IAf indicates the current flowing in the upper arm of PFC converter 210.

[0108] Next, each mode will be explained with reference to FIGS.

[0109] [Mode 1] At time t1, the logic of the upper-arm switching command SgQH is switched from H to L. As a result, as shown in Fig. 27 , a current flows from the second main terminal T2 to the third main terminal T3 via the upper-arm rectifier element 14H. Also, a current flows from the fourth main terminal T4 to the first main terminal T1 via the lower-arm diode DL and the first reactor 12.

[0110] In this embodiment, the lower arm switch QL is turned off during the period from time t1 to time t8. The lower arm switch QL may be turned on during the period from time t1 to when the logic of the upper arm switching command SgQH is switched from L to H, excluding timing t2 when the logic of the second auxiliary switching command SgQ2 is switched from L to H.

[0111] [Mode 2] At time t2, the logic of the second auxiliary switching command SgQ2 is switched from L to H. This turns on the second auxiliary switch Q2, allowing the reactor current IL to flow in the direction of charging the first voltage dividing capacitor 33H. Specifically, as shown in FIG. 28 , current flows from the first voltage dividing capacitor 33H through the second auxiliary switch Q2, the first auxiliary diode D1, the second reactor 32, and the first reactor 12 to the first main terminal T1, and the reactor current IL begins to decrease. Here, the first voltage dividing capacitor 33H is charged. Furthermore, current flows from the fourth main terminal T4 to the second voltage dividing capacitor 33L, discharging the second voltage dividing capacitor 33L. During the period from time t2 to time t7, LC resonance occurs between the second reactor 32, the first auxiliary capacitor 31H, and at least one of the first and second voltage dividing capacitors 33H and 33L, causing a sinusoidal current to flow through the second reactor 32. In the switch changeover process that is executed when the AC output voltage Vac of the AC power supply 220 is negative, the first voltage dividing capacitor 33H corresponds to the "target capacitor," and the second auxiliary switch Q2 corresponds to the "charging switch."

[0112] 29 , at time t3, a current flows through a closed circuit including the first auxiliary capacitor 31H, the first voltage-dividing capacitor 33H, the second auxiliary switch Q2, the first auxiliary diode D1, and the second reactor 32. This causes the first auxiliary capacitor 31H to discharge, and the voltage VCd of the first auxiliary capacitor 31H begins to drop. Also, as in mode 2, the first voltage-dividing capacitor 33H is charged, and the second voltage-dividing capacitor 33L is discharged.

[0113] At time t4, the voltage VCd of the first auxiliary capacitor 31H becomes 0, and the current IAf flowing through the upper arm becomes greater than 0. During a main switching period SPm from time t4 to time t5, the logic of the upper arm switching command SgQH is switched from L to H. This makes it possible to achieve ZVS, in which the upper arm switch QH is turned on in a state in which the drain-source voltage of the upper arm switch QH is 0, thereby reducing the switching loss of the upper arm switch QH.

[0114] The control device 50 may determine whether or not it is in the main switching period SPm, for example, as follows: The control device 50 counts the elapsed time since the second auxiliary switch Q2 was turned on, and determines that it is in the main switching period SPm when it determines that the counted elapsed time has reached a first determination time Tth1. The first determination time Tth1 is set to a value that allows it to determine that the drain-source voltage of the upper arm switch QH is zero.

[0115] When the control device 50 determines that it is the main switching period SPm, it switches the logic of the upper arm switching command SgQH from L to H. This allows the upper arm switch QH to be turned on in a state where the drain-source voltage of the upper arm switch QH is 0, thereby reducing the switching loss of the upper arm switch QH.

[0116] [Mode 4] As shown in Fig. 30 , a current flows from the second main terminal T2 to the first main terminal T1 via the upper-arm rectifier element 14H, the upper-arm switch QH, and the first reactor 12. After the current IAf flowing through the upper arm becomes zero at time t5, the current IAf flowing through the upper arm falls below zero. Also, a current flows from the second main terminal T2 to the first voltage dividing capacitor 33H via the upper-arm rectifier element 14H. This charges the first voltage dividing capacitor 33H. A current flows from the fourth main terminal T4 to the second voltage dividing capacitor 33L, discharging the second voltage dividing capacitor 33L.

[0117] Furthermore, in mode 4, the logic of the first auxiliary switching command SgQ1 is switched from L to H. In this embodiment, the first auxiliary switch Q1 is turned on during the period from time t1 to time t6 and turned off during the period from time t7 to time t1 of the next switching cycle. By turning on the first auxiliary switch Q1, the reactor current IL is allowed to flow in the discharging direction of the first voltage dividing capacitor 33H. For example, the control device 50 turns on the first auxiliary switch Q1 during the period in which the reactor current IL flows in the charging direction of the first voltage dividing capacitor 33H. In this case, the control device 50 may determine whether the reactor current IL is flowing in the charging direction of the first voltage dividing capacitor 33H in the same manner as described in the first embodiment. In the switching process executed when the AC output voltage Vac of the AC power supply 220 is negative, the first auxiliary switch Q1 corresponds to the "discharging switch."

[0118] [Mode 5] At time t6, the reactor current IL exceeds zero, and as shown in FIG. 31 , a current flows from the second reactor 32 to the first main terminal T1 via the first auxiliary switch Q1, the second auxiliary switch Q2, the first voltage dividing capacitor 33H, the upper arm switch QH, and the first reactor 12. This causes the first voltage dividing capacitor 33H to discharge. During the auxiliary switching period SPs, which is the period from time t6 to time t7 when the reactor current IL decreases to zero, the logic of the second auxiliary switching command SgQ2 is switched from H to L. In other words, the auxiliary switching period SPs is the period during which the reactor current IL flows in the direction in which the first voltage dividing capacitor 33H is discharged. At time t7, the logic of the first auxiliary switching command SgQ1 is switched from H to L.

[0119] [Mode 6] At time t7, the reactor current IL becomes 0, and as shown in Fig. 32 , a current flows from the second main terminal T2 to the first main terminal T1 via the upper arm rectifier element 14H, the upper arm switch QH, and the first reactor 12. Note that, instead of at time t7, the logic of the first auxiliary switching command SgQ1 may be switched from H to L after the auxiliary switching period SPs, during the period in which the upper arm switch QH is on.

[0120] In this embodiment, the switch changeover process shown in Fig. 9 is also executed. This process is executed by the microcomputer 51.

[0121] According to the present embodiment described above, it is possible to achieve the same effects as the first embodiment.

[0122] <Modification of Third Embodiment> The upper and lower arm rectifying elements 14H and 14L may each be an N-channel MOSFET or an IGBT with a freewheel diode connected in anti-parallel.

[0123] Fourth Embodiment A fourth embodiment will be described below with reference to the drawings, focusing on differences from the first embodiment. In this embodiment, a power conversion system includes a single-phase inverter 310 and a DC power supply 320, as shown in FIG.

[0124] A positive terminal of a DC power supply 320 is connected to a third main terminal T3 of the single-phase inverter 310, and a negative terminal of the DC power supply 320 is connected to a fourth main terminal T4 of the single-phase inverter 310. The DC power supply 320 is, for example, a storage battery or a fuel cell. A first main terminal T1 and a second main terminal T2 of the single-phase inverter 310 are connected by, for example, a reactor that constitutes a motor.

[0125] The single-phase inverter 310 includes a first switch unit 53A, a second switch unit 53B, first and second voltage dividing capacitors 33H and 33L, and the capacitor 13 which is the second capacitor.

[0126] The first switch section 53A includes upper and lower arm switches QH, QL, upper and lower arm diodes DH, DL, a second reactor 32, first and second auxiliary capacitors 31H, 31L, first and second auxiliary switches Q1, Q2, and first and second auxiliary diodes D1, D2. The circuit including the second reactor 32, first and second auxiliary capacitors 31H, 31L, first and second auxiliary switches Q1, Q2, first and second auxiliary diodes D1, D2, and first and second voltage dividing capacitors 33H, 33L is also referred to as an auxiliary circuit 30.

[0127] The second switch unit 53B has the same configuration as the first switch unit 53A, and therefore a detailed description of the second switch unit 53B will be omitted. Note that, in Fig. 33, the signal line of the switching command input to the second switch unit 53B is not shown.

[0128] The first switch section 53A includes a first input terminal Tai, a first output terminal Tao, a first positive terminal Tap, a first negative terminal Tan, a first high potential side terminal Tah, and a first low potential side terminal Tal.

[0129] The first input terminal Tai is connected to the first main terminal T1. The first output terminal Tao is connected to the second switch unit 53B, the second end of the first voltage-dividing capacitor 33H, and the first end of the second voltage-dividing capacitor 33L. The first positive terminal Tap is connected to the second switch unit 53B, the second auxiliary terminal Tsub2, the first end of the capacitor 13, and the third main terminal T3. The first negative terminal Tan is connected to the second switch unit 53B, the third auxiliary terminal Tsub3, the second end of the capacitor 13, and the fourth main terminal T4. The first high-potential terminal Tah is connected to the first end of the first voltage-dividing capacitor 33H. The first low-potential terminal Tal is connected to the second end of the second voltage-dividing capacitor 33L.

[0130] In this embodiment, the first voltage sensor 40 detects the voltage between the first main terminal T1 and the second main terminal T2. The first current sensor 42 detects the current flowing through the path between the first input terminal Tai and the first main terminal T1.

[0131] The control device 50 performs switching control of the upper arm switch QH and the lower arm switch QL, for example, to convert the output voltage of the DC power supply 320 into a square wave. For example, the upper arm switch QH of the first switch unit 53A and the lower arm switch QL of the second switch unit 53B are turned on synchronously. Also, the lower arm switch QL of the first switch unit 53A and the upper arm switch QH of the second switch unit 53B are turned on synchronously. The upper arm switch QH and the lower arm switch QL of each switch unit 53A, 53B are turned on alternately with dead time therebetween.

[0132] In this embodiment, when a current flows from the first main terminal T1 to the outside of the single-phase inverter 310 and the upper arm switch QH is turned on, the timing chart of the switch changeover process is shown in Fig. 2. When a current flows from the outside of the single-phase inverter 310 to the first main terminal T1 and the lower arm switch QL is turned on, the timing chart of the switch changeover process is shown in Fig. 26.

[0133] The following describes the switching process that is executed when a current flows from the first main terminal T1 to the outside of the single-phase inverter 310, with reference to Figures 2 and 34 to 39. Note that in Figures 34 to 39, the components that make up the second switch unit 53B are not shown.

[0134] 2 and 34 to 39, voltage VCi indicates the voltage of second auxiliary capacitor 31L, and voltage VCd indicates the voltage of first auxiliary capacitor 31H. Current IAc indicates the current flowing through the lower arm of first switch unit 53A, and current IAf indicates the current flowing through the upper arm of first switch unit 53A.

[0135] The direction of current IAf flowing through the upper arm is positive when it flows from the upper arm switch QH to the junction of the upper and lower arm switches QH and QL. The direction of current IAc flowing through the lower arm is positive when it flows from the lower arm switch QL to the junction of the upper and lower arm switches QH and QL. The direction of reactor current IL is positive when it flows from the second reactor 32 to the first auxiliary terminal Tsub1.

[0136] In FIG. 2, (a) shows the transition of the upper arm switching command SgQH, (b) shows the transition of the second auxiliary switching command SgQ2, and (c) shows the transition of the first auxiliary switching command SgQ1.

[0137] In mode 1, the upper arm switch QH is turned off. As a result, as shown in Fig. 34, a current flows from the second main terminal T2 to the third main terminal T3 via the second switch unit 53B. Also, a current flows from the fourth main terminal T4 to the first main terminal T1 via the lower arm diode DL.

[0138] In this embodiment, the lower arm switch QL is turned off from time t1 to time t8. Note that the lower arm switch QL may be turned on during the period from time t1 until the upper arm switch QH is turned on, excluding timing t2 when the second auxiliary switch Q2 is switched from off to on, provided that the lower arm switch QL is not turned on simultaneously with the upper arm switch QH.

[0139] In mode 2, the second auxiliary switch Q2 is turned on. This allows the reactor current IL to flow in the direction of charging the first voltage-dividing capacitor 33H. Specifically, as shown in FIG. 35 , a current flows from the first and second voltage-dividing capacitors 33H and 33L to the first main terminal T1 via the second auxiliary switch Q2, the first auxiliary diode D1, and the second reactor 32, and the reactor current IL begins to increase. Furthermore, the first voltage-dividing capacitor 33H is charged, and the second voltage-dividing capacitor 33L is discharged. In the switch-switching process that is executed when a current flows from the first main terminal T1 toward the outside of the single-phase inverter 310, the first voltage-dividing capacitor 33H corresponds to the "target capacitor," and the second auxiliary switch Q2 corresponds to the "charging switch."

[0140] 36, in mode 3, a current flows through a closed circuit including the first auxiliary capacitor 31H, the first voltage-dividing capacitor 33H, the second auxiliary switch Q2, and the first auxiliary diode D1. This causes the first auxiliary capacitor 31H to discharge, and the voltage VCd of the first auxiliary capacitor 31H begins to drop. Furthermore, as in mode 2, the first voltage-dividing capacitor 33H is charged, and the second voltage-dividing capacitor 33L is discharged.

[0141] When a current flows from the first main terminal T1 to the outside of the single-phase inverter 310, the main switching period SPm is a period during which the voltage VCd of the first auxiliary capacitor 31H becomes 0 and the current IAf flowing through the upper arm becomes less than 0. During the main switching period SPm, the upper arm switch QH is turned on. This realizes ZVS, in which the upper arm switch QH is turned on in a state in which the drain-source voltage of the upper arm switch QH is 0, thereby reducing the switching loss of the upper arm switch QH.

[0142] 37 , in mode 4, a current flows from the third main terminal T3 to the first main terminal T1 via the upper arm switch QH, and the current IAf flowing in the upper arm switch QH exceeds 0. Also, a current flows from the third main terminal T3 to the first voltage dividing capacitor 33H, charging the first voltage dividing capacitor 33H. A current flows from the second main terminal T2 to the second voltage dividing capacitor 33L via the second switch unit 53B, discharging the second voltage dividing capacitor 33L.

[0143] Furthermore, in mode 4, the first auxiliary switch Q1 is turned on. In this embodiment, the first auxiliary switch Q1 is turned on during the period from time t1 to time t6, and is turned off during the period from time t7 to time t1 of the next switching cycle. By turning on the first auxiliary switch Q1, the reactor current IL is allowed to flow in the discharge direction of the first voltage dividing capacitor 33H. For example, the control device 50 turns on the first auxiliary switch Q1 in the same manner as described in the second embodiment. Note that in the switch switching process that is executed when a current flows from the first main terminal T1 toward the outside of the single-phase inverter 310, the first auxiliary switch Q1 corresponds to the "discharge switch."

[0144] In mode 5, the reactor current IL falls below 0. As shown in FIG. 38 , a current flows through a closed circuit including the upper arm switch QH, the second reactor 32, the first and second auxiliary switches Q1 and Q2, and the first voltage-dividing capacitor 33H, discharging the first voltage-dividing capacitor 33H. A current flows from the second voltage-dividing capacitor 33L to the fourth main terminal T4, thereby charging the second voltage-dividing capacitor 33L. Furthermore, during the auxiliary switching period SPs, which is the period from time t6 to time t7 when the reactor current IL increases and becomes zero, the second auxiliary switch Q2 is turned off. In other words, the auxiliary switching period SPs is a period during which the reactor current IL flows in the direction in which the first voltage-dividing capacitor 33H is discharged. At time t7, the first auxiliary switch Q1 is turned off.

[0145] In mode 6, the reactor current IL becomes 0, and as shown in Fig. 39, a current flows from the second main terminal T2 to the fourth main terminal T4 via the second switch unit 53B. Also, a current flows from the third main terminal T3 to the first main terminal T1 via the upper arm switch QH. Note that, instead of at time t7, the first auxiliary switch Q1 may be turned off during the period after the auxiliary switching period SPs when the upper arm switch QH is on.

[0146] Next, the switching process executed when a current flows from outside the single-phase inverter 310 toward the first main terminal T1 will be described with reference to Figures 26 and 40 to 45. Note that in Figures 40 to 45, the components that make up the second switch unit 53B are not shown.

[0147] 26 and 40 to 45, voltage VCi indicates the voltage of first auxiliary capacitor 31H, and voltage VCd indicates the voltage of second auxiliary capacitor 31L. Current IAc indicates the current flowing through the upper arm of first switch section 53A, and current IAf indicates the current flowing through the lower arm of first switch section 53A.

[0148] The direction of current IAc flowing through the upper arm is positive when it flows from the upper arm switch QH to the junction of the upper and lower arm switches QH and QL, and the direction of current IAf flowing through the lower arm is positive when it flows from the lower arm switch QL to the junction of the upper and lower arm switches QH and QL.

[0149] In FIG. 26, (a) shows the transition of the lower arm switching command SgQL, (b) shows the transition of the first auxiliary switching command SgQ1, and (c) shows the transition of the second auxiliary switching command SgQ2.

[0150] In mode 1, the lower arm switch QL is turned off. As a result, as shown in Fig. 40, a current flows from the first main terminal T1 to the third main terminal T3 via the upper arm diode DH. Also, a current flows from the fourth main terminal T4 to the second main terminal T2 via the second switch section 53B.

[0151] In this embodiment, the upper arm switch QH is turned off from time t1 to time t8. Note that the upper arm switch QH may be turned on during the period from time t1 to when the lower arm switch QL is turned on, excluding timing t2 when the first auxiliary switch Q1 is switched from off to on, provided that the upper arm switch QH is not turned on simultaneously with the lower arm switch QL.

[0152] In mode 2, the first auxiliary switch Q1 is turned on. As a result, as shown in FIG. 41 , current flows from the first main terminal T1 through the second reactor 32, the first auxiliary switch Q1, and the second auxiliary diode D2 to the first and second voltage-dividing capacitors 33H and 33L, and the reactor current IL begins to decrease. Furthermore, current flows from the first voltage-dividing capacitor 33H to the third main terminal T3, discharging the first voltage-dividing capacitor 33H. Current flows from the second voltage-dividing capacitor 33L to the second switch unit 53B, charging the second voltage-dividing capacitor 33L. In the switching process executed when current flows from outside the single-phase inverter 310 toward the first main terminal T1, the second voltage-dividing capacitor 33L corresponds to the "target capacitor," and the first auxiliary switch Q1 corresponds to the "charging switch."

[0153] 42, in mode 3, a current flows through a closed circuit including the second auxiliary capacitor 31L, the second reactor 32, the first auxiliary switch Q1, the second auxiliary diode D2, and the second voltage-dividing capacitor 33L. As a result, the voltage VCd of the second auxiliary capacitor 31L begins to drop. As in mode 2, the first voltage-dividing capacitor 33H is discharged, and the second voltage-dividing capacitor 33L is charged.

[0154] When a current flows from outside the single-phase inverter 310 toward the first main terminal T1, the main switching period SPm is a period during which the voltage VCd of the second auxiliary capacitor 31L becomes 0 and the current IAf flowing through the lower arm becomes greater than 0. During the main switching period SPm, the lower arm switch QL is turned on. This realizes ZVS, in which the lower arm switch QL is turned on when the drain-source voltage of the lower arm switch QL is 0, thereby reducing the switching loss of the lower arm switch QL.

[0155] 43, in mode 4, a current flows from the first main terminal T1 to the fourth main terminal T4 via the lower arm switch QL, and the current IAf flowing through the lower arm falls below 0. Also, the first voltage dividing capacitor 33H is discharged, and the second voltage dividing capacitor 33L is charged.

[0156] Furthermore, in mode 4, the second auxiliary switch Q2 is turned on. In this embodiment, the second auxiliary switch Q2 is turned on during the period from time t1 to time t6, and is turned off during the period from time t7 to time t1 of the next cycle. By turning on the second auxiliary switch Q2, the reactor current IL is allowed to flow in the discharging direction of the second voltage dividing capacitor 33L. For example, the control device 50 turns on the second auxiliary switch Q2 during the period in which the reactor current IL flows in the charging direction of the second voltage dividing capacitor 33L. Note that in the switch switching process that is executed when a current flows from outside the single-phase inverter 310 toward the first main terminal T1, the second auxiliary switch Q2 corresponds to the "discharging switch."

[0157] In mode 5, the reactor current IL exceeds zero, and as shown in FIG. 44 , a current flows through a closed circuit including the lower arm switch QL, the second voltage dividing capacitor 33L, the first and second auxiliary switches Q1 and Q2, and the second reactor 32, discharging the second voltage dividing capacitor 33L. Furthermore, during the auxiliary switching period SPs, which is the period from time t6 to time t7 when the reactor current IL drops to zero, the first auxiliary switch Q1 is turned off. In other words, the auxiliary switching period SPs is the period during which the reactor current IL flows in the direction of discharging the second voltage dividing capacitor 33L. At time t7, the second auxiliary switch Q2 is turned off.

[0158] In mode 6, the reactor current IL becomes 0, and as shown in Fig. 45, a current flows from the third main terminal T3 to the second main terminal T2 via the second switch unit 53B. Also, a current flows from the first main terminal T1 to the fourth main terminal T4 via the lower arm switch QL. Note that, instead of at time t7, the second auxiliary switch Q2 may be turned off during the period after the auxiliary switching period SPs when the lower arm switch QL is on.

[0159] In this embodiment, the switch changeover process shown in Fig. 9 is executed by the microcomputer 51.

[0160] 9 may be performed on the upper and lower arm switches QH and QL constituting the second switch unit 53B. In this case, the first main terminal T1 is replaced with the second main terminal T2, the second main terminal T2 is replaced with the first main terminal T1, and the second switch unit 53B is replaced with the first switch unit 53A.

[0161] According to the present embodiment described above, it is possible to achieve the same effects as the first embodiment.

[0162] <Modification of Fourth Embodiment> The first switch section 53A and the second switch section 53B may be provided with the first and second voltage dividing capacitors 33H and 33L, respectively.

[0163] Fifth Embodiment Hereinafter, a fifth embodiment will be described with reference to the drawings, focusing on differences from the fourth embodiment. In this embodiment, a power conversion system includes a three-phase inverter 410 and a DC power supply 420, as shown in FIG.

[0164] A positive terminal of a DC power supply 420 is connected to a third main terminal T3 of the three-phase inverter 410, and a negative terminal of the DC power supply 420 is connected to a fourth main terminal T4 of the three-phase inverter 410. The DC power supply 420 is, for example, a storage battery or a fuel cell. The first main terminal T1, the second main terminal T2, and the fifth main terminal T5 of the three-phase inverter 410 are connected to each other by, for example, a reactor that constitutes a motor.

[0165] The three-phase inverter 410 includes a first switch unit 53A, a second switch unit 53B, and a third switch unit 53C. The third switch unit 53C has the same configuration as the first switch unit 53A, so a description of the third switch unit 53C will be omitted. In Fig. 46, the signal lines of the switching commands input to the second and third switch units 53B and 53C are not shown.

[0166] The control device 50 performs switching control of the first to third switch units 53A to 53C to satisfy a first condition and a second condition, for example, in order to convert the output voltage of the DC power supply 420 into a three-phase AC square wave. The first condition is that in each switch unit, the upper arm switch QH and the lower arm switch QL are alternately turned on with a dead time therebetween. The second condition is that the upper arm switch QH of one or two of the switch units 53A to 53C and the lower arm switch QL of one or two of the switch units are turned on in synchronization.

[0167] In this embodiment, the control device 50 executes the switch changeover processes shown in FIGS. 2, 9, 26, and 34 to 45.

[0168] 9 is executed for the upper and lower arm switches QH and QL that constitute the third switch section 53C. In this case, the first main terminal T1 is replaced with the fifth main terminal T5.

[0169] According to the present embodiment described above, it is possible to achieve the same effects as the first embodiment.

[0170] <Modification of Fifth Embodiment> The first to third switch sections 53A to 53C may be provided with the first and second voltage dividing capacitors 33H and 33L, respectively.

[0171] Sixth Embodiment A sixth embodiment will be described below with reference to the drawings, focusing on differences from the first embodiment. In this embodiment, the auxiliary circuit 30 includes third and fourth auxiliary diodes 34H and 34L. The third and fourth auxiliary diodes 34H and 34L are elements provided to prevent the voltage applied to components such as the second reactor 32 from becoming greater than Vout.

[0172] 47, the cathode of the third auxiliary diode 34H is connected to the first end of the first auxiliary capacitor 31H, the first end of the first voltage-dividing capacitor 33H, and the second auxiliary terminal Tsub2. The anode of the third auxiliary diode 34H is connected to the drain of the second auxiliary switch Q2, the cathode of the second auxiliary diode D2, the cathode of the fourth auxiliary diode 34L, the second end of the first voltage-dividing capacitor 33H, and the first end of the second voltage-dividing capacitor 33L.

[0173] The anode of the fourth auxiliary diode 34L is connected to the second end of the second auxiliary capacitor 31L, the second end of the second voltage dividing capacitor 33L, and the third auxiliary terminal Tsub3.

[0174] When LC resonance occurs between the second reactor 32 and at least one of the first and second auxiliary capacitors 31H and 31L and the first and second voltage-dividing capacitors 33H and 33L, the voltages of the first and second voltage-dividing capacitors 33H and 33L fluctuate in a sinusoidal manner. Here, it is assumed that the capacitance of the first voltage-dividing capacitor 33H is equal to the capacitance of the second voltage-dividing capacitor 33L. When LC resonance does not occur, the voltages of the first and second voltage-dividing capacitors 33H and 33L are each ½ Vout.

[0175] On the other hand, when LC resonance occurs, for example, the voltage of the first voltage-dividing capacitor 33H fluctuates sinusoidally with a predetermined width V1 centered around Vout, and the voltage of the second voltage-dividing capacitor 33L fluctuates sinusoidally with a predetermined width V2 centered around 0 V. In this case, a time may occur when the voltage difference between the first voltage-dividing capacitor 33H and the second voltage-dividing capacitor 33L becomes larger than Vout, and the voltage applied to components such as the second reactor 32 may become equal to or greater than Vout. In this case, there is a concern that the load on components such as the second reactor 32 may increase compared to when LC resonance is not occurring.

[0176] In this embodiment, the auxiliary circuit 30 includes the third and fourth auxiliary diodes 34H and 34L, so that even if LC resonance occurs, the voltage of the first voltage-dividing capacitor 33H does not exceed Vout, and the voltage of the second voltage-dividing capacitor 33L does not become less than 0 V. This makes it possible to prevent the voltage applied to components such as the second reactor 32 from becoming greater than Vout.

[0177] According to the present embodiment described above, the load on components such as the second reactor 32 can be reduced.

[0178] <Variation of the sixth embodiment> In FIG. 47, the connection point of the third and fourth auxiliary diodes 34H, 34L may be connected between the first auxiliary switch Q1 and the second auxiliary switch Q2, or may be connected between the second reactor 32 and the first auxiliary switch Q1.

[0179] Seventh Embodiment A seventh embodiment will be described below with reference to the drawings, focusing on differences from the sixth embodiment. In this embodiment, the auxiliary circuit 30 includes a coupling reactor 35 instead of the second reactor 32.

[0180] 48, the coupling reactor 35 includes a first coil 36, a second coil 37, and a core (not shown) around which the first coil 36 and the second coil 37 are wound. The first coil 36 and the second coil 37 are magnetically coupled via the core.

[0181] The anode of the fourth auxiliary diode 34L and the second end of the second voltage dividing capacitor 33L are connected to a first end of the first coil 36. The second end of the first coil 36 is connected to a second end of the second auxiliary capacitor 31L and the third auxiliary terminal Tsub3.

[0182] The second auxiliary terminal Tsub2 and the first terminal of the first auxiliary capacitor 31H are connected to a first terminal of the second coil 37. The second terminal of the second coil 37 is connected to the cathode of the third auxiliary diode 34H and the first terminal of the first voltage dividing capacitor 33H.

[0183] When the potential of the first end of the first coil 36 is higher than that of the second end, an induced voltage is generated in the second coil 37 such that the potential of the first end is higher than that of the second end. On the other hand, when the potential of the second end of the first coil 36 is higher than that of the first end, an induced voltage is generated in the second coil 37 such that the potential of the second end is higher than that of the first end.

[0184] Because the first coil 36 and the second coil 37 are magnetically coupled, the auxiliary circuit 30 is smaller than a reactor that has the same inductance but is not magnetically coupled. Furthermore, the current flowing through the first coil 36 and the second coil 37 is smaller than the current flowing through the second reactor 32, which reduces the power consumption of the auxiliary circuit 30.

[0185] According to the present embodiment described above, the power conversion system can be made smaller and power consumption can be reduced.

[0186] <Variation of the Seventh Embodiment> The cathode of the third auxiliary diode 34H may be connected to the first end of the first coil 36, and the first end of the first voltage dividing capacitor 33H may be connected to the second end of the first coil 36.

[0187] The second end of the first voltage dividing capacitor 33H may be connected to the first end of the first coil 36, and the first end of the second voltage dividing capacitor 33L may be connected to the second end of the first coil 36.

[0188] The auxiliary circuit 30 does not have to include the third and fourth auxiliary diodes 34H and 34L.

[0189] Eighth Embodiment An eighth embodiment will now be described with reference to the drawings, focusing on differences from the sixth embodiment. In this embodiment, the auxiliary circuit 30 includes an auxiliary capacitor 38 instead of the first and second auxiliary capacitors 31H and 31L.

[0190] 49, a first end of the auxiliary capacitor 38 is connected to the first auxiliary terminal Tsub1 and the first end of the second reactor 32. A second end of the auxiliary capacitor 38 is connected to the drain of the second auxiliary switch Q2, the cathode of the second auxiliary diode D2, the connection point of the third and fourth auxiliary diodes 34H and 34L, and the connection point of the first and second voltage-dividing capacitors 33H and 33L.

[0191] According to the present embodiment described above, the auxiliary capacitor 38 is used instead of the first and second auxiliary capacitors 31H and 31L, so that the number of parts in the power conversion system can be reduced.

[0192] Modification of Eighth Embodiment The auxiliary circuit 30 does not have to include the third and fourth auxiliary diodes 34H and 34L.

[0193] Ninth Embodiment A ninth embodiment will be described below with reference to the drawings, focusing on differences from the first embodiment. In this embodiment, the switch changeover process is modified.

[0194] Depending on the operating state of the DC-DC converter 10 , it may be desirable to stop the operation of the auxiliary circuit 30 from the viewpoint of reducing power loss in the DC-DC converter 10 .

[0195] For example, when the lower arm switch QL is turned on and off during boost control, the switching loss of the lower arm switch QL occurs as a power loss in the DC-DC converter 10. When a switch changeover process is performed during boost control, the switching loss of the lower arm switch QL is reduced by realizing ZVS, but power loss due to the operation of the auxiliary circuit 30 occurs as a power loss in the DC-DC converter 10. The power loss due to the operation of the auxiliary circuit 30 includes, for example, the switching loss of each auxiliary switch Q1, Q2 and the conduction loss of the auxiliary circuit 30.

[0196] The switching loss of the lower arm switch QL is reduced when the output power of the DC-DC converter 10 is small compared to when the output power of the DC-DC converter 10 is large. On the other hand, the power loss caused by the operation of the auxiliary circuit 30 occurs at a substantially constant level regardless of the output power of the DC-DC converter 10. Therefore, as shown in Figure 50, depending on the output power of the DC-DC converter 10, the power loss of the DC-DC converter 10 may be smaller when the auxiliary circuit 30 is not operated than when the auxiliary circuit 30 is operated.

[0197] In view of the above, in this embodiment, the switch changeover process shown in Fig. 51 is executed by the microcomputer 51. The switch changeover process in Fig. 51 includes a process of determining whether the auxiliary circuit 30 is operable.

[0198] In step S20, the output power value Pr of the DCDC converter 10 is obtained. For example, the output power value Pr of the DCDC converter 10 may be a value calculated based on at least one of the detection values ​​of the sensors 40, 41, and 42. Alternatively, the output power value Pr of the DCDC converter 10 may be a value calculated based on an output command to the DCDC converter 10. The output command to the DCDC converter 10 is notified to the control device 50 from a higher-level control device, for example.

[0199] In step S21, it is determined whether the output power of the DC-DC converter 10 is high. In this embodiment, if the acquired output power value Pr is higher than a predetermined power judgment value Pa, it is determined that the output power of the DC-DC converter 10 is high. The power judgment value Pa is determined based on, for example, the characteristics of the DC-DC converter 10. The processing of step S21 corresponds to an "output judgment unit."

[0200] If a positive determination is made in step S21, the process proceeds to step S10. On the other hand, if the acquired output power value Pr is equal to or less than a predetermined power determination value Pa, the output power of the DC-DC converter 10 is determined to be low. In this case, the process proceeds to step S22. In step S22, the first and second auxiliary switches Q1 and Q2 are fixed to the off state. This stops the operation of the auxiliary circuit 30. In this embodiment, it is possible to determine whether or not to operate the auxiliary circuit 30 from the perspective of reducing power loss in the DC-DC converter 10. Therefore, it is possible to realize a switch switching process that is suitable for reducing power loss in the DC-DC converter 10. The process in step S22 corresponds to the "auxiliary control unit."

[0201] In step S23, the switching frequency fsw of the lower arm switch QL is reduced so that the direction of current flowing through the first reactor 12 is reversed during the OFF period of the lower arm switch QL. Specifically, in PWM control of the lower arm switch QL, the frequency of the carrier signal is set low to reduce the switching frequency fsw of the lower arm switch QL. The carrier signal is, for example, a sawtooth wave signal or a triangular wave signal. In step S24, switching control of the lower arm switch QL is performed. In this case, although the period during which the drain-source voltage of the lower arm switch QL becomes zero varies compared to when the auxiliary circuit 30 is operating, it is possible to achieve zero voltage suppression of the lower arm switch QL. Therefore, when it is determined that the output of the DC-DC converter 10 is low, the power loss of the DC-DC converter 10 can be accurately reduced. The processes in steps S23 and S24 correspond to the "main control unit."

[0202] <Modification of the ninth embodiment> The process of step S23 in FIG. 51 does not need to be performed.

[0203] In the second to fifth embodiments, a process similar to the switch changeover process shown in Fig. 51 may be executed. For example, in the second embodiment in which the switch changeover process for voltage step-down control is executed, in step S23, the switching frequency fsw of the upper arm switch QH may be lowered so that the direction of the current flowing through the first reactor 12 is reversed during the off period of the upper arm switch QH.

[0204] Tenth Embodiment A tenth embodiment will be described below with reference to the drawings, focusing on differences from the first embodiment. In this embodiment, the switch changeover process is modified.

[0205] If the transformation ratio of the DC-DC converter 10 is low, the auxiliary circuit 30 for achieving ZVS may not function properly. In this case, there is a concern that the operating range of the DC-DC converter 10 capable of achieving ZVS of the lower arm switch QL may be limited.

[0206] Specifically, as the boost ratio in the boost control decreases, the on-period of the lower-arm switch QL within one switching cycle decreases. If the on-period of the lower-arm switch QL is short, the discharge period of the second voltage-dividing capacitor 33L cannot be sufficiently secured, and the voltage of the second voltage-dividing capacitor 33L may increase. In this case, there is a concern that the length of the main switching period SPm cannot be made long enough, and ZVS of the lower-arm switch QL cannot be achieved. In this regard, even when the boost ratio is low, it is conceivable to lengthen the on-period of the lower-arm switch QL as much as possible by reducing the switching frequency of the lower-arm switch QL.

[0207] In view of the above, in this embodiment, the switch changeover process shown in Fig. 52 is executed by the microcomputer 51. The switch changeover process in Fig. 52 includes a process of changing the switching frequency fsw in accordance with the step-up ratio.

[0208] In step S30, the input voltage Vin and output voltage Vout of the DC-DC converter 10 are acquired. For example, the input voltage Vin may be a value detected by the first voltage sensor 40. For example, the output voltage Vout may be a value detected by the second voltage sensor 41 or a command value for the output voltage Vout. The command value for the output voltage Vout is notified to the control device 50 from a higher-level control device, for example.

[0209] In step S31, it is determined whether the transformation ratio is low based on the acquired input voltage Vin and output voltage Vout. In this embodiment, it is determined whether the step-up ratio obtained by dividing the acquired output voltage Vout by the input voltage Vin is lower than a predetermined threshold value α. The threshold value α is determined based on the characteristics of the auxiliary capacitors 31H and 31L, the second reactor 32, the voltage-dividing capacitors 33H and 33L, and the auxiliary switches Q1 and Q2. The threshold value α is, for example, 1.2. The processing of step S31 corresponds to a "transformation ratio determination unit."

[0210] In step S32, the switching frequency fsw of the lower arm switch QL is set to a predetermined first set value fsw1. The first set value fsw1 is determined based on the characteristics of the DC-DC converter 10, for example.

[0211] In step S33, the switching frequency fsw of the lower arm switch QL is set to a second set value fsw2 that is lower than the first set value fsw1. The second set value fsw2 may be, for example, a predetermined fixed value, or may be a variable value that is reduced as the boost ratio decreases. The processes of steps S32 and S33 can be performed by changing the frequency of the carrier signal in the PWM control of the lower arm switch QL. The processes of steps S32 and S33 correspond to the "main control unit."

[0212] In this embodiment, when the step-up ratio is determined to be low, the switching frequency fsw of the lower arm switch QL is set lower than when the step-up ratio is determined to be high. This makes it possible to maximize the on-period of the lower arm switch QL and ensure the discharge period of the second voltage-dividing capacitor 33L even when the step-up ratio is low. This makes it possible to prevent limitations on the operating range of the DC-DC converter 10 that can achieve ZVS for the lower arm switch QL.

[0213] <Modification of Tenth Embodiment> In the second to fifth embodiments, processing similar to the switch changeover processing shown in Fig. 52 may be executed. For example, in the second embodiment in which the switch changeover processing for the step-down control is executed, it may be determined in step S31 whether the step-down ratio is lower than a predetermined threshold value. In step S32, the switching frequency fsw of the upper arm switch QH may be set to a first set value fsw1. In step S33, the switching frequency fsw of the upper arm switch QH may be set to a second set value fsw2.

[0214] Eleventh Embodiment An eleventh embodiment will now be described with reference to the drawings, focusing on differences from the first embodiment. In this embodiment, the circuit configuration of the auxiliary circuit 30 is modified in order to reduce the size of the DC-DC converter 10.

[0215] In order to reduce the size of the DC-DC converter 10, it is conceivable to use capacitors with low capacitance as the voltage-dividing capacitors 33H, 33L. In this regard, the voltage-dividing capacitors 33H, 33L are charged and discharged by the resonant current flowing through the second reactor 32, causing the voltages of the voltage-dividing capacitors 33H, 33L to fluctuate. There is a concern that the large fluctuations in the voltages of the voltage-dividing capacitors 33H, 33L may limit the use of capacitors with low capacitance as the voltage-dividing capacitors 33H, 33L.

[0216] Specifically, if the charging and discharging currents of the voltage-dividing capacitors 33H and 33L are unbalanced in one switching cycle of the switch switching process, the voltages of the voltage-dividing capacitors 33H and 33L may rise excessively as multiple switching cycles pass.

[0217] For example, in one switching cycle of the switch changeover process in the boost control, the current I33H flowing through the first voltage-dividing capacitor 33H becomes unbalanced, as shown in Fig. 53. Accordingly, the amount of charge Qc charged to the first voltage-dividing capacitor 33H becomes higher than the amount of charge Qd discharged from the first voltage-dividing capacitor 33H. In this case, as shown in Fig. 54, the voltage V33H of the first voltage-dividing capacitor 33H rises excessively as multiple switching cycles pass. In Fig. 54, the voltage of the first voltage-dividing capacitor 33H rises above the withstand voltage Va of the first voltage-dividing capacitor 33H.

[0218] Therefore, in this embodiment, in order to reduce the size of the DC-DC converter 10, the auxiliary circuit 30 is configured as follows.

[0219] 55, the arrangement of the second reactor 32 and the auxiliary switches Q1, Q2 has been changed from the arrangement described in the first embodiment. Specifically, the drain of the second auxiliary switch Q2 and the cathode of the second auxiliary diode D2 are connected to a first end of the second reactor 32. The source of the second auxiliary switch Q2 and the anode of the second auxiliary diode D2 are connected to first ends of the auxiliary capacitors 31H, 31L and the first auxiliary terminal Tsub1.

[0220] The drain of the first auxiliary switch Q1 and the cathode of the first auxiliary diode D1 are connected to the second end of the second reactor 32. The source of the first auxiliary switch Q1 and the anode of the first auxiliary diode D1 are connected to first ends of the voltage-dividing capacitors 33H and 33L.

[0221] The auxiliary circuit 30 includes a third auxiliary diode D3 and a fourth auxiliary diode D4. The cathode of the third auxiliary diode D3 is connected to the first end of the second capacitor 13, the drain of the upper arm switch QH, the second auxiliary terminal Tsub2, and the third main terminal T3. The anode of the third auxiliary diode D3 is connected to the first end of the second reactor 32, the drain of the second auxiliary switch Q2, and the cathode of the second auxiliary diode D2.

[0222] The cathode of the fourth auxiliary diode D4 is connected to the second end of the second reactor 32, the drain of the first auxiliary switch Q1, and the cathode of the first auxiliary diode D1. The anode of the fourth auxiliary diode D4 is connected to the second end of the second capacitor 13, the source of the lower arm switch QL, the third auxiliary terminal Tsub3, the second and fourth main terminals T2 and T4, and the second end of the first capacitor 11.

[0223] In this embodiment, a closed circuit including the second capacitor 13 and the third and fourth auxiliary diodes D3 and D4 is formed as a current path that allows current to flow from the second end to the first end of the second reactor 32. This makes it possible to suppress charging and discharging of the voltage-dividing capacitors 33H and 33L compared to a configuration that does not include the third and fourth auxiliary diodes D3 and D4 when a resonant current flows through the second reactor 32. As a result, capacitors with low capacitance can be used as the voltage-dividing capacitors 33H and 33L, and the DC-DC converter 10 can be made smaller.

[0224] For example, in the switching process of the boost control, the control device 50 turns off the second auxiliary switch Q2 at a timing within the auxiliary switching period SPs instead of time t7. Specifically, the control device 50 turns off the second auxiliary switch Q2 at an off timing toff shown in FIG. 56 . The off timing toff is a timing within the auxiliary switching period SPs when the charge Qc stored in the first voltage-dividing capacitor 33H becomes equal to or equivalent to the charge Qd discharged from the first voltage-dividing capacitor 33H. Even when the second auxiliary switch Q2 is turned off and charging of the first voltage-dividing capacitor 33H is stopped, a closed circuit including the second capacitor 13 and the third and fourth auxiliary diodes D3 and D4 is formed, so that current continues to flow from the second terminal to the first terminal of the second reactor 32. This allows the resonant current to continue to flow while eliminating the imbalance between the charging and discharging currents flowing through the first voltage-dividing capacitor 33H. 57, the voltage V33H of the first voltage-dividing capacitor 33H is set to a value less than the withstand voltage Va of the first voltage-dividing capacitor 33H over a period of multiple switching cycles. As a result, capacitors with low capacitance can be used as the voltage-dividing capacitors 33H, 33L, and the DC-DC converter 10 can be made smaller.

[0225] Furthermore, during the period in which current flows from the second terminal to the first terminal of the second reactor 32, current flows through a closed circuit including the second capacitor 13 and the third and fourth auxiliary diodes D3 and D4, charging the second capacitor 13. In this case, power loss in the auxiliary circuit 30 can be reduced compared to a configuration in which energy is consumed within the auxiliary circuit 30 to eliminate the imbalance between the charging and discharging currents flowing through the first voltage dividing capacitor 33H. As a result, a configuration suitable for reducing power loss in the DCDC converter 10 can be realized.

[0226] <Twelfth Embodiment> A twelfth embodiment will be described below with reference to the drawings, focusing on the differences from the first embodiment. In this embodiment, as shown in Figure 58, in the switch changeover process, after the process of step S11, the process proceeds to step S40. In step S40, the second auxiliary switch Q2 is half-on. After the process of step S40, the process proceeds to step S13.

[0227] Half-on is a state in which the gate voltage of a switch is a voltage that turns the switch on in the saturation region. The saturation region is a region in which the drain current is approximately constant regardless of the magnitude of the drain-source voltage in the output characteristics that relate the drain-source voltage and the drain current of the switch. The voltage drop across a half-on switch is greater than the voltage drop across a fully-on switch.

[0228] Full-on is a state in which the gate voltage of the switch is a voltage that turns the switch on in the non-saturation region. The non-saturation region is the region in which the drain current increases as the drain-source voltage increases in the output characteristics that relate the drain-source voltage and the drain current of the switch. In full-on, the on-resistance of the switch is close to zero.

[0229] In this embodiment, the second auxiliary switch Q2 is half-on during the switching process of the boost control. In this case, the on-resistance of the second auxiliary switch Q2 is increased compared to when the second auxiliary switch Q2 is fully on. As a result, as shown in FIG. 59 , the charging current of the first voltage-dividing capacitor 33H is reduced compared to when the second auxiliary switch Q2 is fully on. This eliminates imbalances in the charging and discharging currents of the first voltage-dividing capacitor 33H during one switching cycle of the switching process. As a result, capacitors with low capacitance can be used as the voltage-dividing capacitors 33H, 33L, allowing for a reduction in the size of the DC-DC converter 10.

[0230] <Modification of Twelfth Embodiment> In the second to fifth embodiments, a process similar to the switch changeover process shown in Fig. 58 may be executed. For example, in the second embodiment in which the switch changeover process for voltage step-down control is executed, the first auxiliary switch Q1 may be half-on in place of the second auxiliary switch Q2 in step S40.

[0231] Thirteenth Embodiment A thirteenth embodiment will be described below with reference to the drawings, focusing on differences from the first embodiment. In this embodiment, in addition to the configuration of the first embodiment, the DC-DC converter 10 includes a resistor as a component for suppressing heat generation from the second capacitor 13 serving as a smoothing capacitor. The resistance value of the resistor is determined according to the characteristics of the DC-DC converter 10 and is, for example, 50 mΩ or more.

[0232] 60, the DC-DC converter 10 includes a first resistor 74 and a second resistor 75. The following describes the positional relationship between the resistors 74, 75 and the configuration described in the first embodiment.

[0233] 60 , the DC-DC converter 10 includes a high-potential side path 60H, a low-potential side path 60L, first and second auxiliary paths 61 and 62, and first to third connection paths 71 to 73. The high-potential side path 60H connects the drain of the upper arm switch QH, the first end of the second capacitor 13, the third main terminal T3, and the second auxiliary terminal Tsub2. The low-potential side path 60L connects the source of the lower arm switch QL, the second end of the first capacitor 11, the second end of the second capacitor 13, the second and fourth main terminals T2 and T4, and the third auxiliary terminal Tsub3.

[0234] The first auxiliary path 61 connects the second auxiliary terminal Tsub2 and the second end of the first auxiliary capacitor 31H. The second auxiliary path 62 connects the third auxiliary terminal Tsub3 and the second end of the second auxiliary capacitor 31L.

[0235] The first connection path 71 connects a first end of the first voltage-dividing capacitor 33H, a first end of the second voltage-dividing capacitor 33L, and the drain of the second auxiliary switch Q2. The second connection path 72 connects a second end of the first voltage-dividing capacitor 33H and an intermediate portion of the first auxiliary path 61. The third connection path 73 connects a second end of the second voltage-dividing capacitor 33L and an intermediate portion of the second auxiliary path 62.

[0236] The first resistor 74 is provided in the second connection path 72. The second resistor 75 is provided in the third connection path 73. In this embodiment, the second capacitor 13, the voltage-dividing capacitors 33H and 33L, and the resistors 74 and 75 form a closed circuit. In this case, the resonant current flowing between the second capacitor 13 and the voltage-dividing capacitors 33H and 33L is reduced compared to a configuration in which the resistors 74 and 75 are not provided. This makes it possible to suppress heat generation in the second capacitor 13, and ultimately to reduce the size of a cooling device for cooling the second capacitor 13.

[0237] In this embodiment, part of the energy consumed in the auxiliary circuit 30 is consumed in the resistors 74 and 75. This allows components with low rated values ​​(e.g., rated current) to be used for the second reactor 32 and the auxiliary switches Q1 and Q2, for example, and allows the auxiliary circuit 30 to be made smaller.

[0238] In the present embodiment described above, it is possible to reduce the size of the cooling device for cooling the second capacitor 13 and the auxiliary circuit 30. As a result, it is possible to reduce the size of the DC-DC converter 10.

[0239] Modifications of the Thirteenth Embodiment The DC-DC converter 10 may include only one of the resistors 74, 75. For example, when the DC-DC converter 10 is used as a step-up converter, the DC-DC converter 10 may include only the first resistor 74 of the resistors 74, 75. Furthermore, when the DC-DC converter 10 is used as a step-down converter, the DC-DC converter 10 may include only the second resistor 75 of the resistors 74, 75.

[0240] The resistor may be provided in the first connection path 71. For example, the resistor may be provided in the first connection path 71 between the first end of the first voltage dividing capacitor 33H and the connection point between the drain of the second auxiliary switch Q2. For example, the resistor may be provided in the first connection path 71 between the first end of the second voltage dividing capacitor 33L and the connection point between the drain of the second auxiliary switch Q2. This embodiment can also achieve the same effects as the above-described embodiments.

[0241] The resistor may be provided in a path other than the first to third connection paths 71 to 73 among paths forming a closed circuit including the second capacitor 13 and the voltage dividing capacitors 33H, 33L.

[0242] 61, the DC-DC converter 10 may include a resistor 76. The resistor 76 is provided in a path connecting the first end of the second capacitor 13 and the high-potential side path 60H.

[0243] 62 , the DC-DC converter 10 may include a first resistor 77 and a second resistor 78. The first resistor 77 is provided in a portion of the high-potential-side path 60H between a connection with the second auxiliary terminal Tsub2 and a connection with the first end of the second capacitor 13. The second resistor 78 is provided in a portion of the low-potential-side path 60L between a connection with the third auxiliary terminal Tsub3 and a connection with the second end of the second capacitor 13.

[0244] In this embodiment, too, it is possible to reduce the resonant current flowing through the second capacitor 13. This allows the DC-DC converter 10 to be miniaturized. However, in the configurations shown in FIGS. 61 and 62, the added resistors 76 to 78 prevent the flow of not only the resonant current flowing through the second capacitor 13 but also the boost current that flows as a result of the execution of boost control. Specifically, the boost current is a current that flows through a closed circuit including the DC power supply 20, the upper arm diode DH, the high-potential side path 60H, the second capacitor 13, and the low-potential side path 60L during the off period of the lower arm switch QL. There is a concern that the power loss of the DC-DC converter 10 may increase due to the prevention of the flow of the boost current.

[0245] On the other hand, in the configuration in which resistors are provided in the first to third connection paths 71 to 73, of the flow of the resonant current flowing through the second capacitor 13 and the flow of the boost current flowing in conjunction with the execution of boost control, only the flow of the resonant current is blocked by the resistors. Therefore, compared to the configurations shown in Figures 61 and 62, it is possible to suppress heat generation in the second capacitor 13 while suppressing an increase in power loss in the DC-DC converter 10.

[0246] Other Embodiments In the first embodiment, the DC-DC converter 10 may include an upper arm diode instead of the upper arm switch QH. In this case, the upper arm diode corresponds to the "upper arm element." The cathode of the upper arm diode corresponds to the "high potential side terminal."

[0247] In the second embodiment, when the DC-DC converter 10 is used as a step-down converter, the DC-DC converter 10 may include a lower-arm diode instead of the lower-arm switch QL. In this case, the lower-arm diode corresponds to the "lower-arm element." The anode of the lower-arm diode corresponds to the "low-potential side terminal."

[0248] The capacitances of the first voltage dividing capacitor 33H and the second voltage dividing capacitor 33L may be different.

[0249] The power conversion device may include a current sensor that detects the reactor current IL. In this case, the control device 50 can estimate the voltage of the target capacitor based on the reactor current IL. This is because the voltage of the target capacitor corresponds to the reactor current IL. Specifically, in mode 5, when the voltage of the target capacitor decreases, the reactor current IL decreases.

[0250] The configurations of the sixth to thirteenth embodiments may be applied to the second to fifth embodiments.

[0251] The control device and method described herein may be implemented by a special-purpose computer configured with a processor and memory programmed to execute one or more functions embodied in a computer program. Alternatively, the control device and method described herein may be implemented by a special-purpose computer configured with a processor comprising one or more dedicated hardware logic circuits. Alternatively, the control device and method described herein may be implemented by one or more special-purpose computers configured with a combination of a processor and memory programmed to execute one or more functions and a processor configured with one or more hardware logic circuits. Furthermore, the computer program may be stored in a computer-readable non-transitory tangible recording medium as instructions to be executed by a computer.

[0252] The following describes characteristic configurations extracted from the above-described embodiments. [Configuration 1] A control device (50) applicable to a power conversion device (10, 210, 310, 410) including: a series connection of an upper arm element (QH) and a lower arm element (QL); auxiliary capacitors (31H, 31L) connected in parallel to the upper arm element and the lower arm element; a series connection of a first voltage dividing capacitor (33H) and a second voltage dividing capacitor (33L) connected in parallel to the series connection of the upper arm element and the lower arm element; and a connection circuit connecting a connection point of the upper arm element and the lower arm element to a connection point of the first voltage dividing capacitor and the second voltage dividing capacitor, and including a reactor (32) and an auxiliary switch (Q1, Q2). The control device (50) comprises: a main control unit that controls switching of a main switch that is one of the upper arm element and the lower arm element; and an auxiliary control unit that controls switching of the auxiliary switch; The auxiliary control unit controls the switching of the auxiliary switch so that a current flows in a direction in which the target capacitor is charged, and then a current flows in a direction in which the target capacitor is discharged.[Configuration 2] The auxiliary switches comprise: a first auxiliary switch (Q1) having a first auxiliary diode (D1) connected in anti-parallel; and a second auxiliary switch (Q2) having a second auxiliary diode (D2) connected in anti-parallel; the first auxiliary diode blocks current flowing from a connection point between the upper arm element and the lower arm element to a connection point between the first voltage dividing capacitor and the second voltage dividing capacitor; and the second auxiliary diode blocks current flowing from a connection point between the first voltage dividing capacitor and the second voltage dividing capacitor to a connection point between the upper arm element and the lower arm element; and the auxiliary control unit, in switching control of the first auxiliary switch and the second auxiliary switch, turns on a charging switch of the first auxiliary switch or the second auxiliary switch that allows current to flow in a charging direction of the target capacitor during a period when the main switch is turned off; and turns on a discharging switch of the first auxiliary switch or the second auxiliary switch that is not the charging switch and allows current to flow in a discharging direction of the target capacitor during a period when the reactor is conducting in the charging direction. The control device according to configuration 1, wherein the charge switch is turned off during a period in which the reactor is conducting in the discharging direction, and the discharge switch is turned off during a period in which the main switch is on after the period in which the reactor is conducting in the discharging direction. [Configuration 3] The control device according to configuration 1 or 2, wherein a lower arm switch that is the lower arm element is provided as the main switch, the target capacitor is the second voltage dividing capacitor, and the auxiliary control unit performs switching control of the auxiliary switch so that a current flows from a connection point of the upper arm element and the lower arm element through the connection circuit toward the second voltage dividing capacitor, and then a current flows from the second voltage dividing capacitor through the connection circuit toward the connection point of the upper arm element and the lower arm element.[Configuration 4] The control device according to any one of Configurations 1 to 3, wherein the main switch is provided with an upper arm switch that is the upper arm element, the target capacitor is the first voltage-dividing capacitor, and the auxiliary control unit controls the switching of the auxiliary switch so that a current flows from the first voltage-dividing capacitor through the connection circuit to a connection point between the upper arm element and the lower arm element, and then flows from the connection point between the upper arm element and the lower arm element to the first voltage-dividing capacitor through the connection circuit. [Configuration 5] The control device according to any one of Configurations 1 to 4, wherein the auxiliary control unit controls the switching of the auxiliary switch so that a voltage of the target capacitor when the main switch is switched on in a next switching cycle of the main switch after being switched off in a current switching cycle of the main switch is equal to or less than half the voltage of a series connection of the first voltage-dividing capacitor and the second voltage-dividing capacitor. [Configuration 6] The control device according to any one of configurations 1 to 5, further comprising an output determination unit that determines whether the output power of the power conversion device is high, wherein the auxiliary control unit performs switching control of the auxiliary switch when the determination unit determines that the output power is high, and fixes the auxiliary switch to off when the determination unit determines that the output power is low. [Configuration 7] The control device according to configuration 6, further comprising: the main control unit, when it is determined that the output power is low, lowers the switching frequency of the main switch so that the direction of current flowing through the reactor is reversed during an off period of the main switch. [Configuration 8] The control device according to any one of configurations 1 to 5, further comprising: a transformation ratio determination unit that determines whether the transformation ratio of the power conversion device is low, wherein the main control unit, when it is determined that the transformation ratio is low, lowers the switching frequency of the main switch compared to when it is determined that the transformation ratio is high.[Configuration 9] The auxiliary switches include: a first auxiliary switch (Q1) to which a first auxiliary diode (D1) is connected in anti-parallel; and a second auxiliary switch (Q2) to which a second auxiliary diode (D2) is connected in anti-parallel; a first end of the reactor is connected to the cathode of the second auxiliary diode; a second end of the reactor is connected to the cathode of the first auxiliary diode; a connection point of the first voltage dividing capacitor and the second voltage dividing capacitor is connected to the anode of the first auxiliary diode; and a connection point of the upper arm element and the lower arm element is connected to the anode of the second auxiliary diode; and the power conversion device includes: a smoothing capacitor (13) connected in parallel to the series connection of the upper arm element and the lower arm element; a third auxiliary diode (D3); and a fourth auxiliary diode (D4); a cathode of the third auxiliary diode is connected to the first end of the smoothing capacitor; and an anode of the third auxiliary diode is connected to the first end of the reactor. The control device according to any one of configurations 1 to 5, wherein a cathode of the fourth auxiliary diode is connected to the second end of the reactor, and an anode of the fourth auxiliary diode is connected to the second end of the smoothing capacitor. [Configuration 10] The control device according to any one of configurations 1 to 5, wherein the auxiliary control unit half-on the auxiliary switch while executing switching control of the auxiliary switch. [Configuration 11] The control device according to any one of configurations 1 to 5, wherein the power conversion device comprises: a smoothing capacitor (13) connected in parallel to the series connection of the upper arm element and the lower arm element; and resistors (74, 75, 76, 77, 78), and the first voltage dividing capacitor, the second voltage dividing capacitor, the smoothing capacitor, and the resistors form a closed circuit.[Configuration 12] The control device according to Configuration 11, comprising: a high-potential-side path (60H) connecting a high-potential-side terminal of the upper arm element and a first end of the smoothing capacitor; a low-potential-side path (60L) connecting a low-potential-side terminal of the lower arm element and a second end of the smoothing capacitor; a first connection path (71) connecting a first end of the first voltage-dividing capacitor and a first end of the second voltage-dividing capacitor; a second connection path (72) connecting a second end of the first voltage-dividing capacitor and the high-potential-side path; and a third connection path (73) connecting a second end of the second voltage-dividing capacitor and the low-potential-side path, wherein the closed circuit is a circuit including the first connection path, the second connection path, and the third connection path, and the resistor (74, 75) is provided in at least one of the first connection path, the second connection path, and the third connection path.

[0253] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

Claims

1. A control device (50) for use in a power conversion device (10, 210, 310, 410) comprising: a series connection of an upper arm element (QH) and a lower arm element (QL); auxiliary capacitors (31H, 31L) connected in parallel to the upper arm element and the lower arm element; a series connection of a first voltage dividing capacitor (33H) and a second voltage dividing capacitor (33L) connected in parallel to the series connection of the upper arm element and the lower arm element; and a connection circuit connecting a connection point of the upper arm element and the lower arm element to a connection point of the first voltage dividing capacitor and the second voltage dividing capacitor, and including a reactor (32) and an auxiliary switch (Q1, Q2). The control device (50) comprises: a main control unit that controls switching of a main switch that is one of the upper arm element and the lower arm element; and an auxiliary control unit that controls switching of the auxiliary switch; The auxiliary control unit controls the switching of the auxiliary switch so that a current flows in a direction in which the target capacitor is charged, and then a current flows in a direction in which the target capacitor is discharged.

2. The auxiliary switches comprise: a first auxiliary switch (Q1) having a first auxiliary diode (D1) connected in anti-parallel; and a second auxiliary switch (Q2) having a second auxiliary diode (D2) connected in anti-parallel; the first auxiliary diode blocks current flowing from the connection point of the upper arm element and the lower arm element to the connection point of the first voltage dividing capacitor and the second voltage dividing capacitor; and the second auxiliary diode blocks current flowing from the connection point of the first voltage dividing capacitor and the second voltage dividing capacitor to the connection point of the upper arm element and the lower arm element; and the auxiliary control unit, in controlling the switching of the first auxiliary switch and the second auxiliary switch, turns on a charging switch of the first auxiliary switch or the second auxiliary switch that allows current to flow in the charging direction of the target capacitor during a period when the main switch is off; and turns on a discharging switch of the first auxiliary switch or the second auxiliary switch that is not the charging switch and allows current to flow in the discharging direction of the target capacitor during a period when the reactor is conducting in the charging direction.

2. The control device according to claim 1, wherein the charge switch is turned off during a period in which the reactor is conducting in the discharging direction, and the discharge switch is turned off during a period in which the main switch is on after the period in which the reactor is conducting in the discharging direction.

3. The control device according to claim 1, wherein the main switch is a lower arm switch that is the lower arm element, the target capacitor is the second voltage dividing capacitor, and the auxiliary control unit controls the switching of the auxiliary switch so that current flows from the connection point of the upper arm element and the lower arm element via the connection circuit toward the second voltage dividing capacitor, and then flows from the second voltage dividing capacitor via the connection circuit toward the connection point of the upper arm element and the lower arm element.

4. The control device according to claim 1, wherein the main switch is an upper arm switch that is the upper arm element, the target capacitor is the first voltage dividing capacitor, and the auxiliary control unit controls the switching of the auxiliary switch so that current flows from the first voltage dividing capacitor via the connection circuit toward the connection point of the upper arm element and the lower arm element, and then flows from the connection point of the upper arm element and the lower arm element via the connection circuit toward the first voltage dividing capacitor.

5. A control device as described in any one of claims 1 to 4, wherein the auxiliary control unit controls the switching of the auxiliary switch so that the voltage of the target capacitor when the main switch is switched on in the next switching cycle of the main switch after the main switch is switched off in the current switching cycle of the main switch is not more than half the voltage of the series connection of the first voltage dividing capacitor and the second voltage dividing capacitor.

6. A control device according to any one of claims 1 to 4, comprising an output determination unit that determines whether the output power of the power conversion device is high, wherein the auxiliary control unit performs switching control of the auxiliary switch when the determination unit determines that the output power is high, and fixes the auxiliary switch to off when the determination unit determines that the output power is low.

7. The control device according to claim 6, wherein the main control unit, when it is determined that the output power is low, lowers the switching frequency of the main switch so that the direction of the current flowing through the reactor is reversed during the off period of the main switch.

8. A control device according to any one of claims 1 to 4, further comprising a transformation ratio determination unit that determines whether the transformation ratio of the power conversion device is low, and wherein the main control unit reduces the switching frequency of the main switch when it is determined that the transformation ratio is low compared to when it is determined that the transformation ratio is high.

9. The auxiliary switches include a first auxiliary switch (Q1) to which a first auxiliary diode (D1) is connected in anti-parallel, and a second auxiliary switch (Q2) to which a second auxiliary diode (D2) is connected in anti-parallel, a first end of the reactor is connected to the cathode of the second auxiliary diode, a second end of the reactor is connected to the cathode of the first auxiliary diode, a connection point of the first voltage dividing capacitor and the second voltage dividing capacitor is connected to the anode of the first auxiliary diode, and a connection point of the upper arm element and the lower arm element is connected to the anode of the second auxiliary diode, and the power conversion device includes a smoothing capacitor (13) connected in parallel to the series connection of the upper arm element and the lower arm element, a third auxiliary diode (D3), and a fourth auxiliary diode (D4), a cathode of the third auxiliary diode is connected to the first end of the smoothing capacitor, and an anode of the third auxiliary diode is connected to the first end of the reactor, 5. The control device according to claim 1, wherein a cathode of the fourth auxiliary diode is connected to a second end of the reactor, and an anode of the fourth auxiliary diode is connected to a second end of the smoothing capacitor.

10. The control device according to any one of claims 1 to 4, wherein the auxiliary control unit half-on the auxiliary switch while executing switching control of the auxiliary switch.

11. The control device according to any one of claims 1 to 4, wherein the power conversion device comprises a smoothing capacitor (13) connected in parallel to the series connection of the upper arm element and the lower arm element, and resistors (74, 75, 76, 77, 78), and the first voltage dividing capacitor, the second voltage dividing capacitor, the smoothing capacitor, and the resistors form a closed circuit.

12. A control device according to claim 11, comprising: a high-potential side path (60H) connecting a high-potential side terminal of the upper arm element and a first end of the smoothing capacitor; a low-potential side path (60L) connecting a low-potential side terminal of the lower arm element and a second end of the smoothing capacitor; a first connection path (71) connecting a first end of the first voltage-dividing capacitor and a first end of the second voltage-dividing capacitor; a second connection path (72) connecting a second end of the first voltage-dividing capacitor and the high-potential side path; and a third connection path (73) connecting a second end of the second voltage-dividing capacitor and the low-potential side path, wherein the closed circuit is a circuit including the first connection path, the second connection path, and the third connection path, and the resistors (74, 75) are provided in at least one of the first connection path, the second connection path, and the third connection path.

13. A program applied to a power conversion device (10, 210, 310, 410) comprising: a series connection of an upper arm element (QH) and a lower arm element (QL); auxiliary capacitors (31H, 31L) connected in parallel to the upper arm element and the lower arm element; a series connection of a first voltage dividing capacitor (33H) and a second voltage dividing capacitor (33L) connected in parallel to the series connection of the upper arm element and the lower arm element; and a connection circuit connecting a connection point of the upper arm element and the lower arm element to a connection point of the first voltage dividing capacitor and the second voltage dividing capacitor, and including a reactor (32) and auxiliary switches (Q1, Q2), the program causing a computer (51) to execute a main control process for controlling switching of a main switch which is one of the upper arm element and the lower arm element; and an auxiliary control process for controlling switching of the auxiliary switch, a voltage dividing capacitor connected in parallel to the main switch via the connection circuit out of the first voltage dividing capacitor and the second voltage dividing capacitor is set as a target capacitor, and the auxiliary control process is a process of controlling the switching of the auxiliary switch so that a current flows in a direction in which the target capacitor is charged, and then a current flows in a direction in which the target capacitor is discharged.

14. A control method applicable to a power conversion device (10, 210, 310, 410) comprising: a series connection of an upper arm element (QH) and a lower arm element (QL); auxiliary capacitors (31H, 31L) connected in parallel to the upper arm element and the lower arm element; a series connection of a first voltage dividing capacitor (33H) and a second voltage dividing capacitor (33L) connected in parallel to the series connection of the upper arm element and the lower arm element; and a connection circuit connecting a connection point of the upper arm element and the lower arm element to a connection point of the first voltage dividing capacitor and the second voltage dividing capacitor, and including a reactor (32) and an auxiliary switch (Q1, Q2), the control method comprising: a main control step of controlling switching of a main switch which is one of the upper arm element and the lower arm element; and an auxiliary control step of controlling switching of the auxiliary switch, wherein the voltage dividing capacitor connected in parallel to the main switch via the connection circuit is selected as a target capacitor from among the first voltage dividing capacitor and the second voltage dividing capacitor, In the auxiliary control step, switching control of the auxiliary switch is performed so that a current flows in a direction in which the target capacitor is charged, and then a current flows in a direction in which the target capacitor is discharged.