PROGRAM EXECUTION DEVICE AND PROGRAM EXECUTION METHOD

Abstract

The program execution device (1000) includes a task switching unit (1324) that transfers execution rights from the second calculation task (1312) to the first calculation task (1311) if the second calculation task (1312) is being executed, and a task modification unit (1323) that suspends execution of the second calculation task (1312) when a request for transferring execution rights to the first calculation task (1311) is made during execution of the second calculation task (1312), modifies the second calculation task (1312) on the secondary storage device (1300) to call the task switching unit (1324) for the next checkpoint, and resumes execution of the second calculation task (1312) from the interrupted point in the second calculation task (1312).

Description

[Technical field]

[0001] The present disclosure relates to a program execution device and a program execution method. [Background technology]

[0002] In computer systems, the exclusive control function provided by the operating system (OS) can be used as a method for exclusive control of multiple threads or tasks including critical sections on a single core. For example, when using the exclusive control function provided by the OS from a user program, a system call is issued to call the exclusive control function of the kernel. Therefore, in addition to the cost of the exclusive process itself, there is a cost for switching from userland to the kernel, and the overhead accumulates each time a critical section is executed, resulting in performance degradation.

[0003] Therefore, in Patent Document 1, a userland process sets a flag indicating preemption inhibition in a preemption inhibition variable possessed by the process to 1, and the process calls a setting process to set the address information where the preemption inhibition variable is located in the OS. The OS then references the preemption inhibition variable using a pre-set preemption inhibition variable address in response to a periodically occurring timer interrupt, and if the value of the preemption inhibition flag is 1 and the time elapsed since the start time of preemption inhibition is less than the duration threshold, the process continues to execute without performing preemption. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2016 / 063511 Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 1, from the perspective of a userland process, preemption can be suppressed simply by setting a value in its own preemption-prohibited variable just before the critical section is executed. From the assembly level, this can be achieved by adding instructions to load a value into a register and store the register value in memory, and the degree of degradation in process execution performance is thought to be small, but not zero. However, in Patent Document 1, if preemption execution is blocked during execution of a critical section, there is no function to re-execute the blocked preemption after the critical section is executed, and the process must wait for the next preemption opportunity. This can result in long response times.

[0006] In addition, when multiple threads or tasks that contain many critical sections at high density are mutually exclusive controlled on a single core, overhead due to the processing time of the mutual exclusive control itself accumulates, resulting in a problem of significant performance degradation that cannot be ignored. In addition, there is a problem that the side effect of the mutual exclusive control causes an extension of the response time of the threads or tasks. It is difficult for Patent Document 1 to solve both of these problems.

[0007] The present disclosure has been made in consideration of the above, and aims to provide a program execution device that is capable of performing exclusive control while suppressing performance degradation and extension of response time, even when multiple threads or tasks that include a large number of critical sections at a high density are exclusively controlled on a single processor core. [Means for solving the problem]

[0008] In order to solve the above problems and achieve the object, a program execution device according to the present disclosure includes a storage device that stores an operation program and a system program, and a microprocessor that includes one or more processor cores and executes the operation program and the system program. The operation program includes a first operation task and a second operation task that has a scheduling priority lower than that of the first operation task, and is executed on a single processor core in the microprocessor. The second operation task includes a plurality of critical sections and a checkpoint located at the beginning of each critical section. The program execution device includes a task switching unit that transfers execution rights from the second operation task to the first operation task if the second operation task is being executed, and a task correction unit that suspends execution of the second operation task when a request for transferring execution rights to the first operation task is received during execution of the second operation task, corrects the second operation task to call the task switching unit for the next checkpoint in the second operation task on the storage device, and resumes execution of the second operation task from the interruption point in the second operation task. Effect of the Invention

[0009] According to the program execution device disclosed herein, even when multiple threads or tasks that contain a large number of critical sections at a high density are exclusively controlled on a single processor core, it is possible to perform exclusive control that minimizes performance degradation and increase in response time. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing an example of a configuration of a program execution device according to a first embodiment; [Diagram 2] 1 is a time chart showing an example of an operation during execution of a computing program in the first embodiment; [Diagram 3] FIG. 1 is a diagram showing an example of a C language description of a second calculation task including a critical section in the first embodiment; [Figure 4] FIG. 1 is a diagram showing an example of an assembly description of a second operation task including a critical section in the first embodiment; [Diagram 5] FIG. 1 is a diagram illustrating an example of a configuration of a system program address calculation unit of a program execution device according to a first embodiment; [Figure 6] FIG. 1 is a diagram showing an example of a configuration of an address table of an address calculation unit of a system program of the program execution device according to the first embodiment; [Figure 7] FIG. 1 is a diagram illustrating an example of a configuration of a checkpoint information holding register of a system program of the program execution device according to the first embodiment; [Figure 8] 1 is a flowchart showing an example of an operation of a task correction unit of a system program of the program execution device according to the first embodiment. [Figure 9] 1 is a flowchart showing an example of an operation of a task switching unit of a system program of the program execution device according to the first embodiment; [Figure 10] FIG. 1 is a sequence diagram showing an example of a series of operations of each component of the program execution device according to the first embodiment; [Figure 11] FIG. 11 is a block diagram showing an example of a configuration of a system program of a program execution device according to a second embodiment; [Figure 12] FIG. 13 is a diagram showing an example of a C language description of a second calculation task including a critical section in the second embodiment. [Figure 13] 11 is a flowchart showing an example of an operation of a task correction unit of a system program of a program execution device according to a second embodiment. [Figure 14] 11 is a flowchart showing an example of an operation of a task switching unit of a system program of a program execution device according to a second embodiment. [Figure 15] FIG. 11 is a block diagram showing an example of a configuration of an arithmetic program of a program execution device according to a third embodiment; [Figure 16] 11 is a time chart showing an example of an operation during execution of a computing program in the third embodiment; [Figure 17] FIG. 13 is a diagram showing an example of a C language description of an h-th operation task including a critical section in the third embodiment. [Figure 18]FIG. 13 is a diagram showing an example of a C language description of an i-th operation task including a critical section in the third embodiment. [Figure 19] 11 is a flowchart showing an example of an operation of a task correction unit of a system program of the program execution device according to the third embodiment. [Figure 20] 11 is a flowchart showing an example of an operation of a task switching unit of a system program of a program execution device according to a third embodiment. [Figure 21] FIG. 11 is a sequence diagram showing an example of a series of operations of each component of the program execution device according to the third embodiment. [Figure 22] FIG. 13 is a diagram showing an example of a C language description of an h-th operation task including a critical section in the fourth embodiment. [Diagram 23] FIG. 13 is a diagram showing an example of a C language description of an i-th operation task including a critical section in the fourth embodiment. [Figure 24] 13 is a flowchart showing an example of an operation of a task correction unit of a system program of the program execution device according to the fourth embodiment. [Diagram 25] 13 is a flowchart showing an example of an operation of a task switching unit of a system program of a program execution device according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a program execution device and a program execution method according to embodiments will be described in detail with reference to the accompanying drawings.

[0012] It is possible to reduce performance degradation caused by the overhead of exclusive control processing by reducing the frequency of use of the exclusive control functions provided by the OS according to the execution status of the user program, or by executing the exclusive control processing in userland instead.However, when targeting multiple threads or tasks that contain many critical sections at a high density and executing them on a single processor core with exclusive control, problems with execution performance and response performance may still occur even if the above-mentioned technology is used.

[0013] As an example of multiple threads or tasks that contain many high-density critical sections, consider the case where a target machine equipped with a dedicated hardware engine and shared memory, such as a PLC (Programmable Logic Controller), is emulated on a single processor core of a host machine, such as an industrial PC (Personal Computer). Incidentally, in embedded devices such as PLCs and industrial PCs, it is common to group similar or interdependent functions and assign them to the same processor core.

[0014] The emulator is composed of multiple dedicated hardware engine models and a shared memory model. The dedicated hardware engine model simulates the instruction operation of the dedicated hardware engine with instructions from the host machine's processor. If the instruction to be simulated is a load or store instruction, it will access the shared memory model, so basically the processing of one instruction in the dedicated hardware engine needs to be exclusively controlled as an indivisible process (critical section).

[0015] Generally speaking, the performance of an emulator is required to be equal to or greater than the specs of the target machine. For example, if the processor frequency of the target machine is 100 MHz, the time required to execute one instruction must be 10 ns or less. It is easy to imagine that if even a few host machine instructions are added to simulate one target machine instruction for mutual exclusion purposes, the performance of the emulator as a whole will be significantly degraded.

[0016] In addition, when using exclusive control for critical sections, it is also necessary to take care to ensure that the side effect of exclusive control does not result in unintentionally long waiting times. In the case of the PLC emulator mentioned above, each task that corresponds to a dedicated hardware engine must be able to calculate and send control commands to devices such as servos or motors periodically and in real time. For example, if an interrupt is used to switch the execution of a task for each dedicated hardware engine model, it is important that the response time to the interrupt is short and that response performance is good.

[0017] Furthermore, when multiple threads or tasks that contain many critical sections at high density are mutually exclusive controlled on a single core, overhead due to the processing time of the mutual exclusive control itself accumulates, resulting in a problem of significant performance degradation that cannot be ignored. In addition, there is a problem that the side effect of the mutual exclusive control causes an extension of the response time of the threads or tasks. The program execution device according to the embodiment described below solves both of these problems.

[0018] Embodiment 1 Hereinafter, a program execution device and a program execution method according to the embodiment 1 will be described. In the embodiment 1, an example will be described in which two computation tasks having an execution period and a scheduling priority are prioritized by the OS, but the embodiment 1 can also be applied to a computation task that does not have an execution period or is not prioritized.

[0019] 1 is a block diagram showing an example of a configuration of a program execution device 1000 according to the first embodiment. The program execution device 1000 according to the first embodiment can be constructed by, for example, an embedded controller, but is not limited to this.

[0020] The program execution device 1000 includes a microprocessor 1100, a main memory device 1200, and a secondary memory device 1300 as a memory device.

[0021] The microprocessor 1100 includes one or more processor cores 1100-1 to 1100-4 and executes various programs. Although FIG. 1 illustrates an example of a configuration including four processor cores 1100-1 to 1100-4, the number of processor cores is not limited to this. The primary storage device 1200 stores programs and data required for the execution of the programs. The primary storage device 1200 is, for example, a cache memory or a RAM (Random Access Memory). The secondary storage device 1300 stores and holds programs and data required for the execution of the programs. The secondary storage device 1300 is, for example, a Flash memory or an eMMC (embedded Multi-Media Card). The secondary storage device 1300 includes an arithmetic program 1310 and a system program 1320. The arithmetic program 1310 includes a first arithmetic task 1311 and a second arithmetic task 1312. The system program 1320 includes an address calculation unit 1321 , a checkpoint information holding register 1322 , a task correction unit 1323 , and a task switching unit 1324 .

[0022] The task correction unit 1323 uses the address calculation unit 1321 to identify the checkpoint to be executed next for the second operation task 1312 being executed, and performs correction. At this time, a pair of the address of the checkpoint where correction was performed and the instruction at the position pointed to by the address is stored in the checkpoint information holding register 1322. As will be described later, the checkpoint is merely a mark for identifying a critical section, and no processing is performed by the processor cores 1100-1 to 1100-4. The task switching unit 1324 performs restoration of the checkpoint in the second operation task 1312 corrected by the task correction unit 1323, and switches the execution of the task between the first operation task 1311 and the second operation task 1312.

[0023] FIG. 2 is a time chart showing an example of the operation of the operation program 1310 during execution in the first embodiment. The first operation task 1311 and the second operation task 1312 are threads or tasks that are the smallest unit of processing executed by the OS. The first operation task 1311 and the second operation task 1312 share an address space with each other and do not have their own independent address space. In addition, the first operation task 1311 and the second operation task 1312 are not interrupt processing or exception processing. In the following, a case where the first operation task 1311 and the second operation task 1312 are tasks will be described as an example.

[0024] The first calculation task 1311 has a first execution period 2110 and a first scheduling priority 2120. The second calculation task 1312 has a second execution period 2210 and a second scheduling priority 2220 that is lower than the first scheduling priority 2120. The first calculation task 1311 and the second calculation task 1312 are allocated to a single processor core 1100-n provided in the microprocessor 1100 and executed by the OS scheduler based on their respective scheduling priorities.

[0025] When the second calculation task 1312 is being executed, a timer interrupt or the like occurs at the start of the first execution cycle 2110 of the first calculation task 1311. Then, the execution of the second calculation task 1312 is suspended, and since the first scheduling priority 2120 is higher than the second scheduling priority 2220, the OS starts the execution of the first calculation task 1311. When the execution of the first calculation task 1311 ends, the execution of the second calculation task 1312 is resumed from the point where it was interrupted.

[0026] FIG. 3 is a diagram showing an example of a C language description of the second operation task 1312 including a critical section 3400-n in the first embodiment. n is 1, 2, 3, . . . In FIG. 3, a running variable 3100 is defined to indicate whether the second operation task 1312 is running or not. If the value of the running variable 3100 is "true", it indicates that the second operation task 1312 is running, and if the value is "false", it indicates that the second operation task 1312 is not running. In addition, a task2() function 3200 is defined as a routine executed by the second operation task 1312, and it is assumed that an entry point of this routine is linked to the second operation task 1312 when the second operation task 1312 is generated. In FIG. 3, an example is shown in which a code block including many critical sections densely is repeatedly processed in a while statement as an implementation of the task2() function 3200. The waitUntilDispatched() function is used at the beginning of the while statement block to wait until the execution right is given by the OS and the state becomes running. Note that the waitUntilDispatched() function is written to clearly show the example in Figure 3, and in practice a function that acquires a semaphore or the like provided by the OS may be used. When the wait is released, the running variable 3100 is set to "true", and at the end of the while block, the running variable 3100 is set to "false".

[0027] At the beginning of each critical section 3400-n, a label is written as a checkpoint 3300-n. In the first embodiment, the checkpoint 3300-n is merely a mark or label for identifying the critical section 3400-n, and no processing is executed by the processor cores 1100-1 to 1100-4. However, since each critical section 3400-n includes at its beginning a checkpoint 3300-n that is modified by the task modification unit 1323, care must be taken to ensure that the two consecutive critical sections 3400-n and 3400-(n+1) are optimized together at the time of compilation so that the boundary between them is not removed. Therefore, for example, as shown in FIG. 3, it is appropriate to write a label equivalent to the checkpoint 3300-n using an inline assembler with a volatile qualifier.

[0028] Also, the position where the checkpoint 3300-n is inserted in the second computation task 1312 does not necessarily have to be before or after each critical section 3400-n. For example, a checkpoint may be inserted every third or every fourth critical section. There is a trade-off: the wider the interval at which the checkpoint 3300-n is inserted, the smaller the degree of degradation of the execution performance but the larger the response time (poor responsiveness), and the narrower the interval, the larger the degree of degradation of the execution performance but the smaller the response time (good responsiveness). Therefore, the insertion interval of the checkpoint 3300-n may be used as a parameter to adjust the insertion interval of the checkpoint 3300-n based on the degree of degradation of the execution performance and the estimated or actual value of the response time.

[0029] Fig. 4 is a diagram showing an example of an assembly description of the second operation task 1312 including a critical section in the first embodiment. Fig. 4 shows a simplified assembly description generated as a result of compiling the C language description of the second operation task 1312 shown in Fig. 3. Checkpoints 4100-n in Fig. 4 correspond to checkpoints 3300-n in Fig. 3, respectively.

[0030] 5 is a diagram showing an example of the configuration of the address calculation unit 1321 of the system program 1320 of the program execution device 1000 according to the first embodiment. The address calculation unit 1321 receives a program counter value as an input, and calculates an address of the checkpoint 3300-n to be executed next in the second computation task 1312 from the program counter value. The address calculation unit 1321 includes an address table 5100.

[0031] 6 is a diagram showing an example of the configuration of the address table 5100 of the address calculation unit 1321 of the system program 1320 of the program execution device 1000 according to the first embodiment. The address table 5100 is an array of addresses on the main memory device 1200 where the checkpoint 3300-n inserted in the second operation task 1312 is placed. The entry 6100-n represents the state in which the addresses of the checkpoint 3300-n in FIG. 3 and the checkpoint 4100-n in FIG. 4 are stored (the addresses of the checkpoints in FIG. 3 and FIG. 4 are the same). As a method for acquiring the address of the checkpoint 3300-n of the second operation task 1312, for example, a variable corresponding to the label equivalent to the checkpoint 3300-n is declared as extern in the second operation task 1312, and the address of each checkpoint 3300-n can be acquired by referring to each variable at the time of execution. The series of operations up to loading the acquired addresses into each entry 6100-n need only be performed once after the second calculation task 1312 is loaded into the main memory 1200, and may be performed during the initialization process of the second calculation task 1312.

[0032] 7 is a diagram showing an example of a configuration of the checkpoint information holding register 1322 of the system program 1320 of the program execution device 1000 according to the first embodiment. The checkpoint information holding register 1322 includes an address field 7100 for holding the address of a checkpoint, and an instruction field 7200 for holding an instruction at a position indicated by the address of the checkpoint.

[0033] 8 is a flowchart showing an example of the operation of the task corrector 1323 of the system program 1320 of the program execution device 1000 according to the first embodiment. The task corrector 1323 is called when an execution right transfer request occurs, and corrects the checkpoint 3300-n in the second calculation task 1312 as necessary. Here, the execution right transfer request can be notified to the second calculation task 1312 from a task assigned to a processor core 1100-m other than the processor core 1100-n to which the calculation program 1310 is assigned, using, for example, an interrupt or a semaphore. When an interrupt is used, the task corrector 1323 may be implemented as an interrupt handler. When a semaphore is used, the task corrector 1323 may be implemented as a task.

[0034] In step S8101, it is determined whether the second calculation task 1312 is being executed by checking whether the value of the running variable 3100 in the second calculation task 1312 is "true" or "false." If the second calculation task is being executed, step S8102 is processed next, and if the second calculation task is not being executed, step S8201 is processed next.

[0035] In step S8102, the program counter (PC) value (return address) at the time when the execution of the second computation task 1312 was interrupted due to the task modification unit 1323 being started by the execution right transfer request is acquired. When the task modification unit 1323 is implemented as an interrupt handler, for example, if the architecture of the microprocessor 1100 is Armv8, the PC value is saved in a link register when an interrupt occurs, so the PC value is acquired by accessing the link register from the interrupt handler. When the task modification unit 1323 is implemented as a task, the register state (context) is usually saved in a save area on the main memory device 1200 when the OS switches the execution of a task, so the PC value is acquired by accessing the save area.

[0036] In step S8103, the PC value acquired in step S8102 is passed to the address calculation unit 1321, and the address of the checkpoint 3300-n to be executed next in the second calculation task 1312 is acquired.

[0037] In step S8104, next checkpoint information, which is a pair of the address of the next checkpoint 3300-n obtained in step S8103 and the instruction placed at the position pointed to by the address of the checkpoint 3300-n, is stored in the checkpoint information holding register 1322. These are stored in the address field 7100 and the instruction field 7200, respectively.

[0038] In step S8105, the location indicated by the address of the next checkpoint 3300-n obtained in step S8103 is rewritten to an instruction to call the entry point of the task switching unit 1324. This is nothing but rewriting an instruction in the text area of ​​the executable format loaded on the main memory device 1200. For example, if the executable format is ELF (Executable and Linkage Format), the load segment (called the text area) including the text section in which the instruction is stored is rewritten. Therefore, the computation program 1310 needs to give a writable attribute to the text area at the time of compilation. In step S8106, the execution of the task correction unit 1323 ends, and the execution of the second computation task 1312 is resumed.

[0039] In step S8201, since it is determined in step S8101 that the second calculation task 1312 is not being executed, the task correcting section 1323 directly calls the task switching section 1324, and the first calculation task 1311 is started.

[0040] 9 is a flowchart showing an example of the operation of the task switching unit 1324 of the system program 1320 of the program execution device 1000 according to the first embodiment. The task switching unit 1324 performs restoration for the checkpoint in the second calculation task 1312 corrected by the task correction unit 1323, and transfers execution rights from a task with a low scheduling priority to a task with a high scheduling priority by using the function of the OS. The task switching unit 1324 may be implemented as, for example, a function.

[0041] In step S9101, it is determined whether the second calculation task 1312 is running. For example, this determination may be made by referring to whether the value of the running variable 3100 in the second calculation task 1312 is "true" or "false." If the second calculation task 1312 is running, step S9102 is processed next, and if the second calculation task 1312 is not running, step S9104 is processed next.

[0042] In step S9102, a pair of the address of the checkpoint 3300-n corrected by the task corrector 1323 and the instruction located at the position pointed to by the address of the checkpoint 3300-n is obtained from the checkpoint information holding register 1322.

[0043] In step S9103, the location pointed to by the address obtained in step S9102 is rewritten to the command obtained in step S9102.

[0044] In step S9104, the second calculation task 1312 having the lower second scheduling priority 2220 transfers the execution right to the first calculation task 1311 having the higher first scheduling priority 2120. For example, a method of using a binary semaphore is used for transferring the execution right. In the first calculation task 1311 and the second calculation task 1312 allocated to a single processor core 1100-n, the second calculation task 1312 starts execution by acquiring a binary semaphore (P operation). During the execution of the second calculation task 1312, when the task switching unit 1324 is called from the checkpoint in the second calculation task 1312 through steps S8101 to S8106 of the task correction unit 1323 described above, and when the task switching unit 1324 is called from the task correction unit 1323 through steps S8101 to S8201, the task switching unit 1324 releases the binary semaphore (V operation). As a result, the OS determines that the first computation task 1311 has the highest scheduling priority among the computation tasks being executed or executable on the processor core 1100-n, and the execution is switched from the second computation task 1312 to the first computation task 1311.

[0045] In step S9105, the process waits until the execution of the first calculation task 1311 is completed.

[0046] In step S9106, the process returns to the address acquired in step S9102, and the execution of the second operation task 1312 is resumed. Assuming that the task switching unit 1324 is implemented as a function, the address of the instruction next to the jump instruction to the entry point of the function is usually held in a dedicated register as a return address when the function is called, and is used when returning from the function to the caller. In the first embodiment, the position of the first instruction at the beginning of each critical section 3400-n in the second operation task 1312 is set as the checkpoint 3300-n. When a request for transfer of execution rights is made, the next checkpoint 3300-(n+1) of the critical section 3400-n that was being executed is rewritten by the task modification unit 1323 to an instruction that calls the task switching unit 1324. When the task switching unit 1324 is called from the checkpoint 3300-(n+1) and returns from the task switching unit 1324 to the second operation task 1312, if the task switching unit 1324 returns to the return address held in the dedicated register, the task will return to the position of the second instruction from the beginning of the critical section 3400-n, and the first instruction at the beginning will not be executed. To avoid this, when the task switching unit 1324 returns to the second operation task 1312, it is necessary to return to the address obtained from the checkpoint information holding register 1322.

[0047] Fig. 10 is a sequence diagram showing an example of a series of operations of each component of the program execution device 1000 according to the first embodiment. Fig. 10 shows how the first operation task 1311, the second operation task 1312, the task correction unit 1323, and the task switching unit 1324 interact with each other when an execution right transfer request occurs during execution of the critical section 3400-2 in the second operation task 1312.

[0048] First, when an execution right transfer request occurs during execution of the critical section 3400-2 in the second operation task 1312, the task correction unit 1323 is started and performs correction so that the task switching unit 1324 is called from the checkpoint 3300-3 located at the beginning of the next critical section 3400-3. The execution of the task correction unit 1323 ends, and the unexecuted part of the critical section 3400-2 that was being executed in the second operation task 1312 is executed. The execution reaches the checkpoint 3300-3 at the beginning of the next critical section 3400-3, and the task switching unit 1324 is called. The task switching unit 1324 performs correction so that the task switching unit 1324 is not called from the checkpoint 3300-3, and the execution right is transferred from the second operation task 1312 to the first operation task 1311, and the first operation task 1311 is executed.

[0049] When the execution of the first calculation task 1311 is completed, the execution right is returned to the task switching unit 1324 and returned to the second calculation task 1312, and the execution of the second calculation task 1312 is resumed from the beginning of the critical section 3400-3.

[0050] <Advantages of the First Embodiment> In the first embodiment, when two threads or tasks that include many critical sections at high density are executed on a single processor core 1100-n, when an execution right transfer request occurs, the task correction unit 1323 corrects the task being executed so that the task switching unit 1324 is called from a checkpoint in the task being executed, and the execution is switched to another task starting from the corrected checkpoint, thereby realizing exclusive control. When no execution right transfer request occurs, the task correction unit 1323 does not make any correction to the task being executed, and the original task is merely inserted with a checkpoint (label) that is not processed by the processor core 1100-n, so that in principle there is no degradation in performance during execution. In addition, because task execution is always switched starting from a checkpoint, there is an effect of preventing an extension of response time that is not intended by the user.

[0051] Embodiment 2 A program execution device and a program execution method according to the second embodiment will be described below. In the following description, components similar to those described in the first embodiment will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. In the second embodiment, an example will be described in which two computation tasks having an execution period and a scheduling priority are prioritized by the OS, but the second embodiment can also be applied to computation tasks that do not have an execution period or are not prioritized.

[0052] In the first embodiment, when an execution right transfer request occurs, the task correction unit 1323 rewrites the checkpoint in the task being executed. That is, an operation is performed to rewrite the executable text area loaded on the main storage device 1200. Generally, a compiler sets a readable attribute and an executable attribute for the text area, and the text area cannot be rewritten when the text area is executed. If a text area intended to be read and executed is rewritten at execution time, a malicious code block can be inserted and executed, so this is suppressed from the viewpoint of security. Therefore, in the second embodiment, a program execution device and a program execution method that do not require an operation to rewrite the text area at execution time will be described.

[0053] 11 is a block diagram showing an example of a configuration of a system program 11000 of the program execution device 1000 according to the second embodiment. The system program 11000 includes a task correction unit 11100 and a task switching unit 11200.

[0054] FIG. 12 is a diagram showing an example of a C language description of the second calculation task 1312 including a critical section 12400-n in the second embodiment. In FIG. 12, a function pointer 12200 is defined as a checkpoint and initialized with "0". The function pointer 12200 will be described in detail in the explanation of the operation flow of the task correction unit 11100, and this is a difference from the first embodiment. The address of the entry point of the task switching unit 11200 is assigned to the function pointer 12200 by the task correction unit 11100. FIG. 12 shows an example of the implementation of the task2() function 12300, in which a code block including many critical sections 12400-n at high density is repeatedly processed in a while statement. The waitUntilDispatched() function is used at the beginning of the while statement block to wait until the execution right is given by the OS and the state becomes running. When the wait is released, the running variable 12100 is set to "true", and at the end of the while block, the running variable 12100 is set to "false".

[0055] At the beginning of each critical section 12400-n, code is written as checkpoints 12200-1 to 12200-3 to check that the value of the function pointer is not "0" and to call the task switching unit 11200 by referring to the function pointer. Thus, in the second embodiment, the checkpoints 12200-1 to 12200-3 are codes to call the task switching unit 11200 by referring to the function pointer, and overhead is generated for conditional branching according to the value of the function pointer at the checkpoint during execution. According to the code for checking the value of the function pointer and calling the function by the function pointer, overhead is generated for processing the conditional branch compared to the first embodiment in which the second calculation task 1312 does not include any extra code. Note that the label corresponding to the checkpoint 3300-n in FIG. 3 is not processed during execution. Therefore, in order to reduce overhead, hint information on whether the probability of the conditional branch being taken or not taken may be given to the compiler. For example, if GCC (GNU Compiler Collection) is used as the compiler and there is a high probability that the conditional branch of the if statement at checkpoint 12200-n will not be satisfied, checkpoint 12200-n can be written as "if(__builtin_expect(!!(checkpoint)、0))checkpoint();" using the built-in function provided by GCC.

[0056] FIG. 13 is a flowchart showing an example of the operation of the task corrector 11100 of the system program 11000 of the program execution device 1000 according to the second embodiment. The task corrector 11100 is called when an execution right transfer request occurs, and corrects the checkpoint 12200-n in the second calculation task 1312 as necessary. Here, the execution right transfer request can be made by using, for example, an interrupt or a semaphore, and a notification can be made to the second calculation task 1312 from a task assigned to a processor core 1100-m other than the processor core 1100-n to which the calculation program 1310 is assigned. When an interrupt is used, the task corrector 11100 may be implemented as an interrupt handler. When a semaphore is used, the task corrector 11100 may be implemented as a task.

[0057] In step S13101, it is determined whether the second calculation task is being executed by checking whether the value of the running variable 12100 in the second calculation task 1312 is "true" or "false." If the second calculation task is being executed, step S13102 is processed next, and if the second calculation task is not being executed, step S13201 is processed next.

[0058] In step S13102, the address of the entry point of the task switching unit 11200 is cast to the function pointer corresponding to the checkpoint 12200-n and assigned to the function pointer. Unlike the first embodiment, the task correction unit 11100 does not need to specify the position of the correction target, and only needs to rewrite the value of the function pointer.

[0059] In step S13103, the execution of the task modifier 11100 ends, and the execution of the second calculation task 1312 is resumed.

[0060] In step S 13201 , since it is determined that the second calculation task 1312 is not being executed, the task corrector 11100 directly calls the task switcher 11200 and starts up the first calculation task 1311 .

[0061] 14 is a flowchart showing an example of the operation of the task switching unit 11200 of the system program 11000 of the program execution device 1000 according to the second embodiment. The task switching unit 11200 performs restoration of the checkpoint 12200-n in the second computation task 1312 corrected by the task correction unit 11100, and transfers the execution right from a task with a low scheduling priority to a task with a high scheduling priority by using the function of the OS. The task switching unit 11200 may be implemented as, for example, a function.

[0062] In step S14101, it is determined whether the second calculation task 1312 is running. For example, this determination may be made by referring to whether the value of the running variable 12100 in the second calculation task 1312 is "true" or "false." If the second calculation task 1312 is running, step S14102 is processed next, and if the second calculation task 1312 is not running, step S14103 is processed next.

[0063] In step S14102, the task corrector 11100 assigns an invalid value "0" to the function pointer corresponding to the checkpoint 12200-n corrected by the task corrector 11100.

[0064] In step S14103, the second computation task 1312 having the lower second scheduling priority 2220 transfers the execution right to the first computation task 1311 having the higher first scheduling priority 2120.

[0065] In step S14104, the process waits until the execution of the first calculation task 1311 is completed.

[0066] In step S14105, the process returns to the checkpoint 12200-n in the second calculation task 1312, and resumes the execution of the second calculation task 1312. When the task switching unit 11200 is implemented as a function, this step is a return operation from a normal function.

[0067] <Advantages of the second embodiment> In the second embodiment, as in the first embodiment, when two threads or tasks including many critical sections 12400-n densely are executed on a single processor core 1100-n, the task corrector 11100 corrects the task being executed so that the task switching unit 11200 is called from a checkpoint in the task being executed when a request for transfer of execution rights occurs, and executes another task starting from the corrected checkpoint, thereby realizing exclusive control. In the second embodiment, compared to the first embodiment, there is overhead during execution due to conditional branching according to the value of a function pointer at a checkpoint, but performance degradation is minimized by providing a hint of the conditional branching direction to the compiler, etc. According to the second embodiment, the extension of response time has the same effect as the first embodiment. In addition, in the second embodiment, the task corrector 11100 does not rewrite the text area loaded on the main memory device 1200, so that there is an effect of closing a security hole in which a malicious code block may be inserted and executed during execution.

[0068] Embodiment 3 A program execution device and a program execution method according to the third embodiment will be described below. In the following description, components similar to those described in the first and second embodiments will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. In the third embodiment, an example will be described in which three or more computation tasks having an execution period and a scheduling priority are prioritized by the OS, but the third embodiment can also be applied to computation tasks that do not have an execution period or are not prioritized.

[0069] In the first and second embodiments, a program execution device in which an arithmetic program includes two arithmetic tasks, all of which are assigned to a single processor core for execution, has been described. In the third embodiment, a program execution device and a program execution method in which an arithmetic program includes three or more tasks, all of which are assigned to a single processor core for execution, will be described. In particular, the third embodiment is based on the first embodiment and is a program execution device in which the number of arithmetic tasks is expanded to three or more. In the third embodiment, checkpoints are simply marks or labels for identifying critical sections, as in the first embodiment, and no processing is performed by the processor cores 1100-1 to 1100-4.

[0070] First, the basic idea of ​​the third embodiment will be described. In the first embodiment, the number of computation tasks is two, so one (the second computation task 1312) is an interrupted computation task, and the other (the first computation task 1311) is an interrupting computation task. Therefore, the number of simultaneous occurrences of execution right transfer requests during the execution of the second computation task 1312 is at most one. In contrast, in the third embodiment, the number of computation tasks is three or more, so there are two or more interrupting computation tasks. In other words, a case is assumed in which the number of simultaneous occurrences of execution right transfer requests during the execution of a certain computation task is two or more.

[0071] When the above-mentioned case where multiple execution right transfer requests may occur is examined in detail, in FIG. 10 of the first embodiment, if another execution right transfer request occurs during the period from the time when the execution right transfer request occurs to the time when the first operation task 1311 starts executing, a problem occurs. During this period, the checkpoint in the second operation task 1312 that was originally being executed is rewritten to an instruction to jump to the entry point of the task switching unit 1324. If another execution right transfer request occurs during this period, the same checkpoint in the second operation task 1312 may be rewritten twice, or the address of the checkpoint to be rewritten may not be obtained. In order to avoid these cases, a mechanism is provided that does not accept another execution right transfer request during this period.

[0072] FIG. 15 is a block diagram showing an example of the configuration of an arithmetic program 15000 of the program execution apparatus 1000 according to Embodiment 3. The arithmetic program 15000 includes N tasks, and includes a first arithmetic task 15100, an h-th arithmetic task 15200, and an i-th arithmetic task 15300 (1 < h < i ≦ N). The h-th arithmetic task 15200 corresponds to the second arithmetic task in the claims, and the i-th arithmetic task 15300 corresponds to the third arithmetic task in the claims.

[0073] FIG. 16 is a time chart showing an example of the operation at the time of execution of the arithmetic program 15000 in Embodiment 3. The first arithmetic task 15100 has a first execution period 16110 and a first scheduling priority 16120. The h-th arithmetic task 15200 has an h-th execution period 16210 and an h-th scheduling priority 16220 lower than the first scheduling priority 16120. The i-th arithmetic task 15300 has an i-th execution period 16310 and an i-th scheduling priority 16320 lower than the h-th scheduling priority 16220. The first arithmetic task 15100, the h-th arithmetic task 15200, and the i-th arithmetic task 15300 are assumed to be assigned to and executed by a single processor core 1100-n provided in the microprocessor 1100 based on their respective scheduling priorities by the scheduler of the OS.

[0074] When the i-th arithmetic task 15300 is being executed, a timer interrupt or the like occurs at the start of the h-th execution period 16210 of the h-th arithmetic task 15200. Then, the execution of the i-th arithmetic task 15300 is interrupted, and since the h-th scheduling priority 16220 is higher than the i-th scheduling priority 16320, the h-th arithmetic task 15200 is executed by the OS. When the execution of the h-th arithmetic task 15200 ends, the execution of the i-th arithmetic task 15300 resumes from the point where it was interrupted.

[0075] When the h-th arithmetic task 15200 is being executed, a timer interrupt or the like occurs at the start of the first execution cycle 16110 of the first arithmetic task 15100. Then, the execution of the h-th arithmetic task 15200 is interrupted, and since the first scheduling priority 16120 is higher than the h-th scheduling priority 16220, the first arithmetic task 15100 is executed by the OS. When the execution of the first arithmetic task 15100 ends, the execution of the h-th arithmetic task 15200 resumes from the point where it was interrupted.

[0076] FIG. 17 is a diagram showing an example of a C language description of the h-th arithmetic task 15200 including the critical section 17400-n in Embodiment 3 (1 ≦ h < i ≦ N). In FIG. 17, a running_h variable 17100 is defined to indicate whether the h-th arithmetic task 15200 is being executed. If the value of the running_h variable 17100 is "true", it indicates that it is being executed, and if it is "false", it indicates that it is not being executed. Also, a task_h() function 17200 is defined as a routine executed by the h-th arithmetic task 15200, and it is assumed that the entry point of this routine is associated with the h-th arithmetic task 15200 when the h-th arithmetic task 15200 is generated. In FIG. 17, as an implementation of the task_h() function 17200, an example is shown in which a code block containing a large number of critical sections 17400-n densely is repeatedly processed in a while statement. At the beginning of the block of the while statement, the waitUntilDispatched() function is used to wait until the execution right is given from the task switching unit 1324 and it enters the executing state. When the waiting is released, "true" is set in the running_h variable 17100, acceptance of the execution right transfer request is permitted, and "false" is set in the running_h variable 17100 at the end of the block of the while statement.

[0077] At the beginning of each critical section 17400-n, a label is described as a checkpoint 17300-n.

[0078] FIG. 18 is a diagram showing an example of a C language description of the i-th arithmetic task 15300 including the critical section 18400-n in the third embodiment (1 ≦ h < i ≦ N). In FIG. 18, a running_i variable 18100 indicating whether the i-th arithmetic task 15300 is being executed is defined. If the value of the running_i variable 18100 is "true", it indicates that it is being executed, and if it is "false", it indicates that it is not being executed. Also, a task_i() function 18200 is defined as a routine executed by the i-th arithmetic task 15300, and it is assumed that the entry point of this routine is associated with the i-th arithmetic task 15300 when the i-th arithmetic task 15300 is generated. In FIG. 18, as an implementation of the task_i() function 18200, an example is shown in which a code block containing a large number of critical sections 18400-n densely is repeatedly processed in a while statement. At the beginning of the block of the while statement, the waitUntilDispatched() function is used to wait until execution permission is given by the OS and it enters the execution state. When the waiting is released, "true" is set in the running_i variable 18100, acceptance of an execution right transfer request is permitted, and "false" is set in the running_i variable 18100 at the end of the block of the while statement.

[0079] At the beginning of each critical section 18400-n, a label is described as a checkpoint 18300-n.

[0080] FIG. 19 is a flowchart showing an example of the operation of the task correction unit 1323 of the system program 1320 of the program execution device 1000 according to the third embodiment. The task correction unit 1323 is called when an execution right transfer request occurs, and performs correction as necessary for a checkpoint in the calculation task that was being executed. Here, for example, an interrupt or a semaphore is used for the execution right transfer request, and a notification can be made to the i-th calculation task 15300 from a task assigned to a processor core 1100-m other than the processor core 1100-n to which the calculation program 15000 is assigned. When an interrupt is used, the task correction unit 1323 may be implemented as an interrupt handler. When a semaphore is used, the task correction unit 1323 may be implemented as a task.

[0081] In step S19101, the processor core 1100-n to which the computing program 15000 is assigned is prohibited from accepting a request to transfer execution rights. When an interrupt is used for the request to transfer execution rights, an interrupt with a specific ID (Identification) can be masked, or all interrupts can be prohibited. When a semaphore is used for the request to transfer execution rights, a similar measure can be taken. This is because when a specific task is started by releasing a semaphore, the OS usually issues an interrupt to the processor core to switch the execution of the task.

[0082] In step S19102, the task modification unit 1323 identifies the task ID of the computation task to be executed next after the computation task that was being executed immediately before being called. Here, it is assumed that the execution right transfer request corresponds one-to-one to the computation task to be executed next. When an interrupt is used, one interrupt ID is associated with one task. When a semaphore is used, one semaphore is associated with one task. In this way, the task modification unit 1323 can identify the task ID of the computation task to be executed next by referring to the interrupt ID or the semaphore.

[0083] In step S19103, the value of the running variable of all the calculation tasks is checked to see if it is "true" or "false" to determine whether any calculation task is running. If it is running, step S19104 is processed next, and if it is not running, step S19201 is processed next.

[0084] In step S19104, the PC value at the time when the execution of the i-th calculation task 15300 was interrupted due to the task modifier 1323 being started in response to a request to transfer the execution right is obtained.

[0085] In step S19105, the PC value acquired in step S19104 is passed to the address calculation unit 1321, and the address of the checkpoint 18300-n to be executed next in the computation task that was being executed is acquired. Note that the address table 5100 provided in the address calculation unit 1321 may acquire the address of the checkpoint in the initialization process of each computation task by using the method described in the explanation of Fig. 6, for example, and load the acquired address into each entry 6100-n.

[0086] In step S19106, next checkpoint information, which is a pair of the address of the next checkpoint 18300-n acquired in step S19105 and the instruction placed at the position pointed to by the address of the checkpoint 18300-n, is stored in the checkpoint information holding register 1322.

[0087] In step S19107, the location indicated by the address of the next checkpoint 18300-n acquired in step S19106 is rewritten to a command for calling the entry point of the task switching unit 1324.

[0088] In step S19108, the execution of the task corrector 1323 ends, and the execution of the i-th calculation task 15300 that was being executed is resumed.

[0089] In step S19201, since it is determined in step S19103 that no arbitrary computation task is being executed, the task corrector 1323 directly calls the task switcher 1324, and starts the computation task designated by the task ID.

[0090] 20 is a flowchart showing an example of the operation of the task switching unit 1324 of the system program 1320 of the program execution device 1000 according to the third embodiment. The task switching unit 1324 performs restoration for a checkpoint in an active computation task that has been corrected by the task correction unit 1323. In addition, the task switching unit 1324 transfers execution rights from a task with a low scheduling priority to a task with a high scheduling priority by utilizing the functions of the OS. Note that the task switching unit 1324 is assumed to receive the task ID of the computation task from the task correction unit 1323.

[0091] In step S20101, it is determined whether any calculation task is running. For example, it may be determined by referring to whether the value of the running variable of all calculation tasks is "true" or "false". If any calculation task is running, step S20102 is processed next, and if not, step S20104 is processed next.

[0092] In step S20102, a pair of the checkpoint address corrected by the task corrector 1323 and the instruction located at the position pointed to by the checkpoint address is obtained from the checkpoint information holding register 1322.

[0093] In step S20103, the location pointed to by the address obtained in step S20102 is rewritten to the command obtained in step S20102.

[0094] In step S20104, the execution right is transferred from the currently running computation task to the computation task specified by the task ID. For example, the execution right is transferred from the i-th computation task 15300 having the lower i-th scheduling priority 16320 to the h-th computation task 15200 having the higher h-th scheduling priority 16220.

[0095] In step S20105, the process waits until the execution of the calculation task specified by the task ID is completed.

[0096] In step S20106, the process returns to the address obtained in step S20102, and the execution of the previously executed calculation task is resumed.

[0097] Fig. 21 is a sequence diagram showing an example of a series of operations of each component of the program execution device 1000 according to the third embodiment. Fig. 21 shows how the first operation task 15100, the hth operation task 15200, the ith operation task 15300, the task correction unit 1323, and the task switching unit 1324 interact with each other when an execution right transfer request to the hth operation task 15200 occurs during execution of the critical section 18400-2 in the ith operation task 15300, and then an execution right transfer request to the first operation task 15100 occurs during execution of the critical section 17400-1 in the hth operation task 15200.

[0098] First, when a request for transferring execution rights to the h-th operation task 15200 occurs during the execution of the critical section 18400-2 in the i-th operation task 15300, the task corrector 1323 starts up and prohibits the acceptance of the execution rights transfer request at the beginning of the critical section, and then corrects the task so that the task switcher 1324 is called from the checkpoint 18300-3 located at the beginning of the next critical section 18400-3. The execution of the task corrector 1323 ends, and the unexecuted part of the critical section 18400-2 that was being executed in the i-th operation task 15300 is executed. The execution reaches the checkpoint 18300-3 at the beginning of the next critical section 18400-3, and the task switcher 1324 is called. The task switching unit 1324 is modified so as not to call the task switching unit 1324 from the checkpoint 18300-3, and the execution right is transferred from the i-th computation task 15300 to the h-th computation task 15200. The h-th computation task 15200 is executed, and the acceptance of the execution right transfer request is permitted at the beginning of the h-th computation task.

[0099] Next, when a request for transferring execution rights to the first operation task 15100 occurs during the execution of the critical section 17400-1 in the h-th operation task 15200, the task corrector 1323 starts up, prohibits the acceptance of the execution rights transfer request at the beginning of the critical section, and then corrects the task so that the task switcher 1324 is called from the checkpoint 17300-2 located at the beginning of the next critical section 17400-2. The execution of the task corrector 1323 ends, and the unexecuted part of the critical section 17400-1 that was being executed in the h-th operation task 15200 is executed. The execution reaches the checkpoint 17300-2 at the beginning of the next critical section 17400-2, and the task switcher 1324 is called. The task switching unit 1324 is modified so as not to call the task switching unit 1324 from the checkpoint 17300-2, and the execution right is transferred from the h-th calculation task 15200 to the first calculation task 15100. The h-th calculation task 15200 is executed, and after the acceptance of the execution right transfer request is permitted at the beginning of the h-th calculation task, the subsequent processing is executed.

[0100] When the execution of the first operation task 15100 is completed, the execution right is returned to the task switching unit 1324, and the execution is returned to the h-th operation task 15200, and the execution of the h-th operation task 15200 is resumed from the beginning of the critical section 17400-2. When the execution of the h-th operation task 15200 is completed, the execution is returned to the i-th operation task 15300, and the execution of the i-th operation task 15300 is resumed from the beginning of the critical section 18400-3.

[0101] <Advantages of the Third Embodiment> In the third embodiment, when three or more threads or tasks including many critical sections densely are executed on a single processor core 1100-n, when an execution right transfer request occurs, the task correction unit 1323 corrects the task being executed so that the task switching unit 1324 is called from a checkpoint in the task being executed, and the execution is switched to another task starting from the corrected checkpoint, thereby realizing exclusive control. When no execution right transfer request occurs, the task correction unit 1323 does not make any correction to the task being executed, and the original task is merely inserted with a checkpoint (label) that is not processed by the processor core 1100-n, so that in principle there is no degradation in performance during execution. In addition, because task execution is always switched starting from a checkpoint, there is an effect of preventing an extension of response time that is not intended by the user.

[0102] Embodiment 4 A program execution device and a program execution method according to the fourth embodiment will be described below. In the following description, components similar to those described in the first to third embodiments will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. In the fourth embodiment, an example will be described in which three or more computation tasks each having an execution period and a scheduling priority are prioritized by the OS, but the fourth embodiment can also be applied to computation tasks that do not have an execution period or are not prioritized.

[0103] In the fourth embodiment, similarly to the third embodiment, a program execution device and a program execution method will be described in the case where a computing program includes three or more computing tasks, all of which are assigned to a single processor core and executed. In particular, the fourth embodiment is a program execution device in which the number of computing tasks is expanded to three or more, based on the second embodiment.

[0104] FIG. 22 is a diagram showing an example of a C language description of the h-th computation task 15200 including the critical section 22400-n in the fourth embodiment. In FIG. 22, a function pointer 22200 is defined as a checkpoint and initialized with "0". The address of the entry point of the task switching unit 11200 is assigned to the function pointer 22200 by the task correction unit 11100. FIG. 22 shows an example of the implementation of the task_h() function 22300, in which a code block including many critical sections 22400-n densely is repeatedly processed in a while statement. The waitUntilDispatched() function is used at the beginning of the while statement block to wait until the execution right is given by the task switching unit 11200 and the task is in an executing state. When the wait is released, the running_h variable 22100 is set to "true", the acceptance of the execution right transfer request is permitted, and the running_h variable 22100 is set to "false" at the end of the while statement block.

[0105] At the beginning of each critical section 22400-n, code is written as checkpoints 22200-1 to 3 for checking that the value of the function pointer 22200 is not "0" and for calling the task switching unit 11200 by referencing the function pointer 22200. In this way, in the fourth embodiment, checkpoints 22200-1 to 3 are codes for calling the task switching unit 11200 by referencing the function pointer, similar to the second embodiment, and during execution, overhead is generated for conditional branching according to the value of the function pointer at the checkpoint.

[0106] FIG. 23 is a diagram showing an example of a C language description of the i-th operation task 15300 including the critical section 23400-n in the fourth embodiment. In FIG. 23, a function pointer 23200 is defined as a checkpoint and initialized with "0". The address of the entry point of the task switching unit 11200 is assigned to the function pointer 23200 by the task correction unit 11100. FIG. 23 shows an example of the implementation of the task_i() function 23300, in which a code block including many critical sections densely is repeatedly processed in a while statement. The waitUntilDispatched() function is used at the beginning of the while statement block to wait until the OS gives the execution right and the task is in an executing state. When the wait is released, the running_i variable 23100 is set to "true", the acceptance of the execution right transfer request is permitted, and the running_i variable 23100 is set to "false" at the end of the while statement block.

[0107] At the beginning of each critical section 23400-n, code is written as checkpoints 23200-1 to 3 to check that the value of the function pointer 23200 is not "0" and to call the task switching unit 11200 by referencing the function pointer 23200.

[0108] 24 is a flowchart showing an example of the operation of the task correction unit 11100 of the system program 11000 of the program execution device 1000 according to the fourth embodiment. The task correction unit 11100 is called when an execution right transfer request occurs, and performs correction, as necessary, for a checkpoint in the computation task that was being executed.

[0109] In step S24101, the processor core 1100-n to which the arithmetic program 16000 is allocated is prohibited from accepting an execution right transfer request.

[0110] In step S24102, the task modification unit 11100 identifies the task ID of the computation task to be executed next after the computation task that was being executed immediately before being called. Here, it is assumed that the execution right transfer request corresponds one-to-one to the computation task to be executed next. When an interrupt is used, one interrupt ID is associated with one task. When a semaphore is used, one semaphore is associated with one task. In this way, the task modification unit 11100 can identify the task ID of the computation task to be executed next by referring to the interrupt ID or the semaphore.

[0111] In step S24103, the value of the running variable of all the calculation tasks is checked to see if it is "true" or "false" to determine whether any calculation task is running. If it is running, step S24104 is processed next, and if it is not running, step S24201 is processed next.

[0112] In step S24104, the address of the entry point of the task switching unit 11200 is cast to the function pointer corresponding to the checkpoint in the computation task that was being executed, and assigned to the function pointer. Unlike the first and third embodiments, the task correction unit 11100 does not need to specify the position of the correction target, and only needs to rewrite the value of the function pointer.

[0113] In step S24105, the execution of the task modifier 11100 ends, and the execution of the computation task that was being executed is resumed.

[0114] In step S24201, since it is determined in step S24103 that no arbitrary computation task is being executed, the task corrector 11100 directly calls the task switcher 11200, and starts the computation task designated by the task ID.

[0115] 25 is a flowchart showing an example of the operation of the task switching unit 11200 of the system program 11000 of the program execution device 1000 according to the fourth embodiment. The task switching unit 11200 performs restoration for a checkpoint in an active computation task corrected by the task correction unit 11100, and transfers execution rights from a task with a low scheduling priority to a task with a high scheduling priority by using an OS function. The task switching unit 11200 may be implemented as, for example, a function.

[0116] In step S25101, it is determined whether any calculation task is running. For example, it may be determined by referring to whether the value of the running variable of all calculation tasks is "true" or "false". If any calculation task is running, step S25102 is processed next, and if not, step S25103 is processed next.

[0117] In step S25102, the function pointer corresponding to the checkpoint corrected by the task corrector 11100 is substituted with "0".

[0118] In step S25103, the execution right is transferred from the currently running computation task to the computation task specified by the task ID. For example, the execution right is transferred from the i-th computation task 15300 having the lower i-th scheduling priority 16320 to the h-th computation task 15200 having the higher h-th scheduling priority 16220.

[0119] In step S25104, the process waits until the execution of the calculation task designated by the task ID is completed.

[0120] In step S25105, the process returns to the checkpoint in the previously executed computation task, and the execution of the computation task is resumed. When the task switching unit 11200 is implemented as a function, this step is a return operation from a normal function.

[0121] <Advantages of the Fourth Embodiment> In the fourth embodiment, when three or more threads or tasks including many critical sections densely are executed on a single processor core 1100-n, the task correction unit 11100 corrects the task being executed so that the task switching unit 11200 is called from a checkpoint in the task being executed when a request for transfer of execution rights occurs, and the execution is switched to another task from the corrected checkpoint, thereby realizing exclusive control. In the fourth embodiment, compared to the third embodiment, there is overhead during execution due to conditional branching according to the value of a function pointer at a checkpoint, but performance degradation is minimized by providing a hint of the conditional branching direction to the compiler, etc. In the fourth embodiment, the response time is extended in the same way as in the third embodiment. In addition, in the fourth embodiment, the task correction unit 11100 does not rewrite the text area loaded on the main memory device 1200, so that there is an effect of closing a security hole in which a malicious code block may be inserted and executed during execution.

[0122] It should be noted that, within the scope of the present disclosure, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted. Although the present disclosure has been described in detail, the above description is illustrative in all respects and is not limiting. It is understood that countless variations not illustrated can be envisioned.

[0123] The configurations shown in the above embodiments are examples of the contents of the present disclosure, and may be combined with other known technologies, or the embodiments may be combined with each other. Also, parts of the configurations may be omitted or modified without departing from the gist of the present disclosure. [Explanation of symbols]

[0124] 1000 program execution device, 1100 microprocessor, 1100-1 to 1100-4, 1100-n, 1100-m processor core, 1200 main memory device, 1300 secondary memory device, 1310, 15000 operation program, 1311, 15100 first operation task, 1312 second operation task, 1320, 11000 system program, 1321 address calculation unit, 1322 checkpoint information holding register, 1323, 11100 task correction unit, 1324, 11200 task switching unit, 3100, 12100 running variable, 3200, 12300 task2() function, 3300-n, 4100-n, 12200-n, 17300-n, 18300-n, 22200-n, 23200-n Checkpoint, 3400-n,12400-n,17400-n,18400-n,22400-n,23400-n critical section, 5100 address table, 6100-n entry, 7100 address field, 7200 instruction field, 12200,22200,23200 function pointer, 15200 hth calculation task, 15300 ith calculation task, 17100,22100 running_h variable, 17200,22300 task_h() function, 18100,23100 running_i variable, 18200,22300,23300 task_i() function.

Claims

1. A program execution device comprising: a storage device that stores an arithmetic program and a system program; and a microprocessor that has one or more processor cores and executes the arithmetic program and the system program, the computing program includes a first computing task and a second computing task having a scheduling priority lower than that of the first computing task, and is executed on a single processor core in the microprocessor; the second computation task includes a plurality of critical sections and a checkpoint located at the beginning of each critical section; a task switching unit that transfers an execution right from the second computation task to the first computation task if the second computation task is being executed; a task modification unit that, when a request for transferring execution rights to the first computation task is received during the execution of the second computation task, suspends the execution of the second computation task, modifies the second computation task on the storage device to call the task switching unit at the next checkpoint in the second computation task, and resumes the execution of the second computation task from the interruption point in the second computation task; A program execution device comprising:

2. the system program includes an address calculation unit that calculates an address of the next checkpoint from a program counter value, and a checkpoint information holding register; When the execution right transfer request is made during the execution of the second calculation task, the task modification unit interrupts the execution of the second calculation task, acquires a program counter value at the interruption point, acquires the address of the next checkpoint from the address calculation unit, stores a pair of the checkpoint address and an instruction at the position pointed to by the address in the checkpoint information holding register, and rewrites the checkpoint on the storage device to an instruction that calls the task switching unit.

2. The program execution device according to claim 1.

3. the address calculation unit has an address table for storing the address of the checkpoint included in the second computation task, The address table is searched by the program counter value to calculate the address of the next checkpoint in the second computing task.

3. The program execution device according to claim 2.

4. the task switching unit acquires a pair of an address and an instruction of the checkpoint from the checkpoint information holding register before transferring execution right from the second calculation task to the first calculation task; Rewriting the location pointed to by the address in the second computation task on the storage device to the instruction.

3. The program execution device according to claim 2.

5. the checkpoint in the second computation task is a pointer capable of referencing the task switching unit inserted at the beginning of the critical section, The task modification unit interrupts the execution of the second calculation task when the execution right transfer request is made during the execution of the second calculation task, and sets an address of an entry point of the task switching unit to the checkpoint next to the interruption point in the second calculation task.

2. The program execution device according to claim 1.

6. The task switching unit sets an invalid value to the checkpoint in the second computation task, and then transfers execution rights from the second computation task to the first computation task.

6. The program execution device according to claim 5.

7. the computing program includes a third computing task having a lower scheduling priority than the second computing task and having a plurality of critical sections and a checkpoint located at the beginning of each critical section; the task switching unit, if the third computation task is being executed, transfers execution rights to the first computation task or the second computation task; the task modification unit, when a request for transfer of execution rights to the first or second computation task is made during the execution of the third computation task, prohibits acceptance of the request for transfer of execution rights in a single processor core, interrupts the execution of the third computation task, modifies the third computation task on the storage device to call the task switching unit for the next checkpoint, and resumes the execution of the third computation task from the interruption point in the third computation task; The task switching unit permits acceptance of an execution right transfer request in a single processor core at the head of processing when the first computation task or the second computation task is in an execution state.

7. A program execution device according to claim 1.

8. A program execution method using a storage device that stores an arithmetic program and a system program, and a microprocessor that has one or more processor cores and executes the arithmetic program and the system program, comprising: the computing program includes a first computing task and a second computing task having a scheduling priority lower than that of the first computing task, and is executed on a single processor core in the microprocessor; the second computation task includes a plurality of critical sections and a checkpoint located at the beginning of each critical section; a task switching step of transferring execution rights from the second computation task to the first computation task if the second computation task is being executed; a task modification step of suspending the execution of the second calculation task when a request for transferring execution rights to the first calculation task is received during the execution of the second calculation task, modifying the second calculation task on the storage device so as to call the task switching step for the next checkpoint in the second calculation task, and resuming the execution of the second calculation task from the interruption point in the second calculation task; A program execution method comprising: