semiconductor device

Abstract

A semiconductor device comprising a transistor of a fine size is provided. It includes a first transistor and a second transistor, a first insulating layer and a second insulating layer. Both transistors are vertical transistors, and a second transistor is provided superimposed on the first transistor. One of the source electrode and drain electrode of the first transistor (a first conductive layer), a first insulating layer, and the other of the source electrode and drain electrode of the first transistor (a second conductive layer) are provided in this order and include an overlapping region. An opening extending to the first conductive layer is provided in the second conductive layer and the first insulating layer, and a semiconductor layer, a gate insulating layer, and a gate electrode are provided in this order in contact with the sidewall and bottom surface of the opening. The second insulating layer is provided to fill a recess of the gate electrode of the first transistor, and one of the source electrode and drain electrode of the second transistor is provided in contact with the gate electrode.

Description

Technology Field

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, a display device, a display module, and an electronic device. One embodiment of the present invention relates to a method for manufacturing a transistor, a method for manufacturing a semiconductor device, and a method for manufacturing a display device.

[0002] Furthermore, one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, capacitor devices, memory devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), electronic devices including the same, methods for driving the same, or methods for manufacturing the same.

[0003] Furthermore, in this specification and others, the term "semiconductor device" refers to a device utilizing semiconductor characteristics, and includes circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.) and devices containing such circuits. It also refers to devices in general that can function by utilizing semiconductor characteristics. For example, integrated circuits, chips containing integrated circuits, and electronic components housing chips in packages are examples of semiconductor devices. Additionally, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and each may include a semiconductor device. Background Technology

[0004] Semiconductor devices, including transistors, are widely applied in display devices and electronic equipment, and there is a demand for higher integration and speed of these devices. For example, when applying semiconductor devices to high-resolution display devices, high-integration semiconductor devices are required. As one means of increasing the integration density of transistors, the development of finer transistors is underway.

[0005] In recent years, there has been a demand for display devices applicable to Virtual Reality (VR), Augmented Reality (AR), Substitutional Reality (SR), or Mixed Reality (MR). VR, AR, SR, and MR are collectively referred to as Extended Reality (XR). Display devices for XR are required to have high resolution and color reproduction capabilities to enhance realism and immersion. Examples of devices applicable to the above display devices include liquid crystal displays, organic EL (Electro-Luminescence) devices, or light-emitting devices (also called light-emitting elements) such as light-emitting diodes (LEDs).

[0006] Patent Document 1 discloses a display device for VR using an organic EL device (also called an organic EL element). Prior art literature

[0007] International Publication WO2018 / 087625 The problem to be solved

[0008] One embodiment of the present invention has as its objective to provide a semiconductor device including a transistor of fine size and a method for manufacturing the same. Alternatively, one embodiment of the present invention has as its objective to provide a compact semiconductor device and a method for manufacturing the same. Alternatively, one embodiment of the present invention has as its objective to provide a semiconductor device including a transistor with high on-current and a method for manufacturing the same. Alternatively, one embodiment of the present invention has as its objective to provide a semiconductor device with good electrical characteristics and a method for manufacturing the same. Alternatively, one embodiment of the present invention has as its objective to provide a semiconductor device with high reliability and a method for manufacturing the same. Alternatively, one embodiment of the present invention has as its objective to provide a method for manufacturing a semiconductor device with high productivity. Alternatively, one embodiment of the present invention has as its objective to provide a novel semiconductor device and a method for manufacturing the same.

[0009] Furthermore, the description of these problems does not prevent the existence of other problems. One embodiment of the present invention is not necessarily required to solve all of these problems. Problems other than these can be derived from the description in the specification, drawings, and claims. means of solving the problem

[0010] To further increase the integration of a semiconductor device, it is effective to miniaturize the transistors included in the semiconductor device while simultaneously adjusting the layout of the transistors. For example, it is effective to stack multiple transistors included in the semiconductor device in a direction perpendicular to the substrate surface rather than arranging them on the same plane. By doing so, the high integration of the semiconductor device can be promoted without increasing the area occupied by the transistors within the substrate surface. Meanwhile, when stacking transistors, if the lower transistor has a shape with large irregularities, the surface to be formed of the transistor formed thereon will also have irregularities, making it difficult to stack and form fine transistors. Therefore, it is desirable for the surface to be formed to be as flat as possible. Accordingly, one embodiment of the present invention provides a semiconductor device including a transistor in which the irregularities on the upper surface are flattened by an insulating layer, and a method for manufacturing the same.

[0011] One embodiment of the present invention functions as part of a sequential circuit, wherein the sequential circuit comprises a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer; the first transistor comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a gate insulating layer, and a gate electrode; the second transistor comprises a second semiconductor layer, a third conductive layer, and a fourth conductive layer; the first insulating layer is provided on the first conductive layer, and the second conductive layer is provided on the first insulating layer; the first insulating layer and the second conductive layer each comprise a first opening extending to the first conductive layer; within the first opening, the first semiconductor layer is provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer; the gate insulating layer is provided in contact with the upper surface of the first semiconductor layer; and the gate electrode is provided in contact with the upper surface of the gate insulating layer to include a region overlapping with the first opening; and the second An insulating layer is provided on a gate electrode to fill a first opening, a third conductive layer is provided in contact with the second insulating layer and the gate electrode, the third insulating layer is provided on the third conductive layer, a fourth conductive layer is provided on the third insulating layer, the third insulating layer and the fourth conductive layer each include a second opening extending to the third conductive layer, and within the second opening, a second semiconductor layer is provided in contact with the upper surface of the third conductive layer, the side surface of the third insulating layer, and the side surface of the fourth conductive layer, and the second insulating layer is a semiconductor device comprising an organic insulating material.

[0012] In addition, above, a fourth insulating layer is provided in an area on the gate insulating layer that does not overlap with the first opening, and a third insulating layer is provided on the fourth insulating layer, and it is preferable that the fourth insulating layer comprises the same material as the second insulating layer.

[0013] In addition, the second insulating layer preferably comprises one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins.

[0014] In addition, the first transistor includes a back gate electrode, and the back gate electrode is provided between the first conductive layer and the second conductive layer to include a region that overlaps with each of the first conductive layer and the second conductive layer, and it is preferable that one side of the first semiconductor layer faces the gate electrode within the first opening, and the other side of the first semiconductor layer faces the back gate electrode.

[0015] In addition, in the above, at least one of the first semiconductor layer and the second semiconductor layer comprises a metal oxide, and the metal oxide comprises two or three types selected from indium, element M, and zinc, and element M comprises one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium, and at least one of the first insulating layer and the third insulating layer comprises silicon oxide or silicon nitride.

[0016] In addition, the first insulating layer comprises a fifth insulating layer, a sixth insulating layer above the fifth insulating layer, and a seventh insulating layer above the sixth insulating layer, and the third insulating layer comprises an eighth insulating layer, a ninth insulating layer above the eighth insulating layer, and a tenth insulating layer above the ninth insulating layer, and the fifth insulating layer, the seventh insulating layer, the eighth insulating layer, and the tenth insulating layer each comprise silicon nitride, silicon nitride oxide, hafnium oxide, or aluminum oxide, and the sixth insulating layer and the ninth insulating layer each comprise silicon oxide or silicon nitride oxide.

[0017] In addition, one embodiment of the present invention comprises a first transistor, a second transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, wherein the first transistor comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a first gate insulating layer, and a first gate electrode, and the second transistor comprises a second semiconductor layer, a third conductive layer, a fourth conductive layer, a second gate insulating layer, and a second gate electrode, wherein the first insulating layer is provided on the first conductive layer and the second conductive layer is provided on the first insulating layer, and the first insulating layer and the second conductive layer each comprise a first opening extending to the first conductive layer, wherein within the first opening, the first semiconductor layer is provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer, and the first gate insulating layer is provided in contact with the upper surface of the first semiconductor layer, and the first gate electrode is the A first gate insulating layer is provided in contact with the upper surface of the first gate insulating layer to include an area overlapping with the first opening, a second insulating layer is provided on the first gate electrode to fill the first opening, a third insulating layer is provided in contact with the upper surface of the second insulating layer, a side of the first gate electrode, and the upper surface of the first gate insulating layer, a third conductive layer is provided in contact with the upper surface of the third insulating layer, a fourth insulating layer is provided on the third conductive layer, a fourth conductive layer is provided on the fourth insulating layer, the fourth insulating layer and the fourth conductive layer each include a second opening extending to the third conductive layer, within the second opening a second semiconductor layer is provided in contact with the upper surface of the third conductive layer, a side of the fourth insulating layer, and a side of the fourth conductive layer, a second gate insulating layer is provided in contact with the upper surface of the second semiconductor layer, a second gate electrode is provided in contact with the upper surface of the second gate insulating layer to include an area overlapping with the second opening, and the second insulating layer is a semiconductor comprising an organic insulating material. It is a device.

[0018] In addition, above, it is preferable that the first conductive layer and the third conductive layer are connected, the second conductive layer and the fourth conductive layer are connected, and the first gate electrode and the second gate electrode are connected.

[0019] In addition, as described above, it is preferable that the second conductive layer and the third conductive layer are connected, and the first gate electrode and the second gate electrode are connected.

[0020] In addition, above, a fifth insulating layer is provided in an area on the first gate insulating layer that does not overlap with the first opening, and a fourth insulating layer is provided on the fifth insulating layer, and it is preferable that the fifth insulating layer comprises the same material as the second insulating layer.

[0021] In addition, the second insulating layer preferably comprises one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins.

[0022] In addition, in the above, at least one of the first semiconductor layer and the second semiconductor layer comprises a metal oxide, and the metal oxide comprises two or three types selected from indium, element M, and zinc, and element M comprises one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium, and at least one of the first insulating layer and the fourth insulating layer comprises silicon oxide or silicon nitride.

[0023] In addition, the first insulating layer comprises a sixth insulating layer, a seventh insulating layer above the sixth insulating layer, and an eighth insulating layer above the seventh insulating layer, and the fourth insulating layer comprises a ninth insulating layer, a tenth insulating layer above the ninth insulating layer, and an eleventh insulating layer above the tenth insulating layer, and the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each comprise silicon nitride, silicon nitride oxide, hafnium oxide, or aluminum oxide, and the seventh insulating layer and the tenth insulating layer each comprise silicon oxide or silicon nitride oxide. Effects of the invention

[0024] According to one embodiment of the present invention, a semiconductor device including a transistor of fine size and a method for manufacturing the same may be provided. Alternatively, according to one embodiment of the present invention, a compact semiconductor device and a method for manufacturing the same may be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device including a transistor with high on-current and a method for manufacturing the same may be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics and a method for manufacturing the same may be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high reliability and a method for manufacturing the same may be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity may be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device and a method for manufacturing the same may be provided.

[0025] Furthermore, the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be derived from the description in the specification, drawings, and claims. Brief explanation of the drawing

[0026] Figure 1 (A) is a plan view showing an example of a semiconductor device. Figure 1 (B) is a cross-sectional view showing an example of a semiconductor device. Figure 2 (A) is a cross-sectional view showing an example of a semiconductor device. Figure 2 (B) is a circuit diagram explaining the semiconductor device. Figure 3 is a cross-sectional view showing an example of a semiconductor device. Figure 4 is a cross-sectional view showing an example of a semiconductor device. Figure 5 is a cross-sectional view showing an example of a semiconductor device. Figure 6 is a cross-sectional view showing an example of a semiconductor device. Figure 7 (A) is a cross-sectional view showing an example of a semiconductor device. Figure 7 (B) is a circuit diagram explaining the semiconductor device. Figure 8 (A) is a cross-sectional view showing an example of a semiconductor device. Figure 8 (B) is a circuit diagram explaining the semiconductor device. FIG. 9 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 9 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 10 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 10 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 11 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 11 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 12 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 12 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 13 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 13 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 14 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 14 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 15 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 15 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 16 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 16 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 17 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 17 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 18 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 18 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 19 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 19 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 20 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 20 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 21 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 21 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 22 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 22 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 23 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 23 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 24 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 24 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 25 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 25 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 26 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 26 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 27 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 27 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 28 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 28 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 29 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 29 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 30 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 30 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 31 (A) is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 31 (B) and (C) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 32 (A) is a diagram showing an example of a sequence circuit configuration. Figure 32 (B) is a circuit diagram of a shift register. Figure 32 (C) is a timing chart. Figures 33 (A) and (B) are diagrams showing examples of sequential circuit configurations. Figures 34 (A) and (B) are diagrams showing examples of sequential circuit configurations. FIG. 35 is a circuit diagram showing an example of a stacked configuration of transistors including a sequential circuit. FIG. 36 is a cross-sectional view showing an example of a stacked configuration of transistors including a sequential circuit. Figures 37 (A) to (D) are drawings showing examples of electronic devices. Figures 38 (A) to (F) are drawings showing examples of electronic devices. Figures 39 (A) to (G) are drawings showing examples of electronic devices. Specific details for implementing the invention

[0027] Embodiments are described in detail using drawings. However, the present invention is not limited to the description below, and it is readily understood by those skilled in the art that various changes to its form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention is not to be interpreted as being limited to the description of the embodiments below.

[0028] Furthermore, in the configuration of the invention described below, the same reference numerals are commonly used across different drawings for identical parts or parts having the same function, and redundant descriptions thereof are omitted. Additionally, when referring to parts having the same function, the same hatch pattern is used, and in some cases, no specific reference numeral is assigned.

[0029] The actual location, size, and range of each component shown in the drawings may not be indicated to facilitate understanding. Therefore, the disclosed invention is not necessarily limited to the location, size, and range disclosed in the drawings.

[0030] In addition, the terms "film" and "layer" can be interchanged depending on the case or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0031] A transistor is a type of semiconductor device capable of realizing functions such as amplifying current or voltage, and switching operations that control conduction or non-conduction. Transistors in this specification include Insulated Gate Field Effect Transistors (IGFETs) and Thin Film Transistors (TFTs).

[0032] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification and other documents, the terms "source" and "drain" may be used interchangeably. Furthermore, regarding the designations of the source and drain of a transistor, they may be appropriately changed depending on the situation, such as the source terminal and drain terminal, or the source electrode and drain electrode.

[0033] "Gate" and "back gate" are interchangeable. Therefore, in this specification and others, the terms "gate" and "back gate" may be used interchangeably. Furthermore, the designations "gate" and "back gate" of a transistor may be appropriately changed to "gate electrode" and "back gate electrode" depending on the situation.

[0034] In this specification, "connection" includes, by way of example, "electrical connection." Additionally, the term "electrical connection" may be used to define the connection relationship of circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without any circuit elements (e.g., transistors, switches, etc.; wiring is not a circuit element) in between. On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements.

[0035] For example, assuming that a circuit including A and B is in operation, if there is a timing during the operation period of the circuit where the exchange of electrical signals or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected" as an object. Furthermore, even if there is a timing during the operation period of the circuit where the exchange of electrical signals or potential interaction does not occur between A and B, if there is a timing during the operation period where the exchange of electrical signals or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected".

[0036] An example of a case where "A and B are indirectly connected" is when A and B are connected through the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are indirectly connected" is when an insulator exists in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, or where a gate insulating film of a transistor exists between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0037] Another example of a case where it cannot be said that "A and B are indirectly connected" is that multiple transistors are connected through sources and drains in the path from A to B, and a constant potential (V) is applied from a power source, GND, etc. to the node between the transistors.

[0038] In the present specification and others, a light-emitting device includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Here, the layers included in the EL layer (also called functional layers) may include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier blocking layer (hole blocking layer and electron blocking layer).

[0039] In the present specification and others, "substantially matching upper surface shapes" refers to a situation where at least a portion of the contours overlaps between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or partially identical mask patterns. However, strictly speaking, there are cases where the contours do not overlap and the upper layer is located inside the lower layer or the upper layer is located outside the lower layer; in such cases, it may also be referred to as "substantially matching upper surface shapes."

[0040] Furthermore, in this specification and others, the upper surface shape of a component refers to the contour shape of said component when viewed from a planar view. Additionally, "when viewed from a planar view" refers to viewing from the normal direction of the surface to be formed of said component, or the surface of the support (e.g., a substrate) on which said component is formed.

[0041] Furthermore, in this specification and others, the term "heights substantially match" refers to a configuration in which the heights from a reference plane (e.g., a flat surface such as a substrate surface) are substantially equal when viewed from a cross-section. For example, when a planarization treatment (typically Chemical Mechanical Polishing (CMP) treatment) is performed, the heights of the treated surfaces are substantially equal. However, even if a planarization treatment is performed, the heights may not strictly match depending on the film material, but in this specification and others, it is also referred to as "heights substantially match" in such cases.

[0042] (Embodiment 1)

[0043] In this embodiment, a transistor of one form of the present invention, a method for manufacturing the transistor, etc., is described.

[0044] One embodiment of the present invention is a semiconductor device comprising a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer.

[0045] Both the first transistor and the second transistor are vertical transistors in which the source electrode and the drain electrode are provided overlapping at different heights relative to the substrate surface, and the drain current flows in the height direction (vertical direction). Therefore, they can be miniaturized more than planar transistors in which the source electrode and the drain electrode are provided on the same plane, and the area occupied by the transistor can be further reduced. By having the first transistor and the second transistor have the structure described above, the miniaturization and high integration of the semiconductor device can be achieved.

[0046] In addition, by providing a configuration in which the first transistor and the second transistor are stacked, the miniaturization and high integration of the semiconductor device can be further promoted.

[0047] However, because vertical transistors have a configuration where the source electrode, channel formation region, and drain electrode are provided at different heights, they are prone to larger height differences or irregularities compared to planar transistors. Therefore, stacking vertical transistors on top of each other is much more difficult to fabricate than stacking planar transistors on top of each other.

[0048] A vertical transistor of one embodiment of the present invention has a configuration in which a step or irregularity occurring in the height direction is embedded in a layer having a flattening function. Accordingly, since a plurality of vertical transistors can be stacked, the miniaturization and high integration of semiconductor devices can be promoted.

[0049] In a semiconductor device of one embodiment of the present invention, the first transistor and the second transistor are provided superimposed in this order.

[0050] The first insulating layer is provided above one of the source electrode and the drain electrode of the first transistor. The other of the source electrode and the drain electrode of the first transistor is provided above the first insulating layer. That is, the first insulating layer includes a region sandwiched between the source electrode and the drain electrode of the first transistor.

[0051] The other side of the first insulating layer and the source electrode and drain electrode of the first transistor each include a first opening extending to one side of the source electrode and drain electrode of the first transistor. A semiconductor layer of the first transistor is provided to be in contact with a side of the first insulating layer within the first opening, a side of the other side of the source electrode and drain electrode of the first transistor within the first opening, and an upper surface of one of the source electrode and drain electrode of the first transistor within the first opening. A gate insulating layer of the first transistor is provided to be in contact with the upper surface of the semiconductor layer. A gate electrode of the first transistor is provided to be in contact with the upper surface of the gate insulating layer and to include a region that overlaps with the first opening. The gate electrode has a shape that follows the shape of the first opening. That is, the gate electrode includes a concave portion on its upper surface corresponding to the shape of the first opening.

[0052] The second insulating layer is a layer having the planarization function described above. The second insulating layer is provided to fill a depression formed in the gate electrode of the first transistor. The upper surface of the second insulating layer has a substantially flat shape. The height of the upper surface of the second insulating layer and the upper surface of the highest region when viewed from the substrate surface of the gate electrode of the first transistor substantially coincide.

[0053] One of the source electrode and drain electrode of the second transistor is provided so as to be in contact with a portion of the upper surface of the gate electrode of the first transistor.

[0054] A third insulating layer is provided above one of the source electrode and drain electrode of the second transistor. The other of the source electrode and drain electrode of the second transistor is provided above the third insulating layer. That is, the third insulating layer includes a region sandwiched between the source electrode and drain electrode of the second transistor.

[0055] The other side of the third insulating layer and the source electrode and drain electrode of the second transistor each include a second opening extending to one side of the source electrode and drain electrode of the second transistor. A semiconductor layer of the second transistor is provided to be in contact with a side of the third insulating layer within the second opening, a side of the other side of the source electrode and drain electrode of the second transistor within the second opening, and an upper surface of one side of the source electrode and drain electrode of the second transistor within the second opening. A gate insulating layer of the second transistor is provided to be in contact with the upper surface of the semiconductor layer. A gate electrode of the second transistor is provided to be in contact with the upper surface of the gate insulating layer and to include a region that overlaps with the second opening.

[0056] As such, a semiconductor device of one embodiment of the present invention comprises two vertical transistors, and at least one of the vertical transistors has a configuration in which a step or irregularity in the height direction, more specifically a concave portion formed in the gate electrode, is filled with a layer having a flattening function. Therefore, it becomes easy to form another vertical transistor by overlapping it on top of the vertical transistor. For example, when a semiconductor device of one embodiment of the present invention is used in a scan line driving circuit (also called a gate line driving circuit or gate driver) of a display device, a vertical transistor is used as each of the plurality of transistors constituting the scan line driving circuit, and the transistors are stacked such that their electrodes (source electrode, drain electrode, or gate electrode) are connected to each other. By doing so, the area occupied by the scan line driving circuit can be reduced, thereby narrowing the bezel of the display device.

[0057] Hereinafter, a specific configuration example of a semiconductor device of one form of the present invention will be described with reference to the drawings.

[0058] <Example of Semiconductor Device Configuration 1>

[0059] Figure 1 (A) shows a plan view (also called a top view) of a semiconductor device (100). Figure 1 (B) shows a cross-sectional view along the dotted line A1-A2 of Figure 1 (A), and Figure 2 (A) shows a cross-sectional view along the dotted line B1-B2 of Figure 1 (A). Figure 2 (B) shows a circuit diagram explaining the configuration of the semiconductor device (100). In addition, in Figure 1 (A), some components (such as an insulating layer) of the semiconductor device (100) are omitted. In the plan view of the semiconductor device, etc., some components are omitted in the drawings referenced below, just as in Figure 1 (A).

[0060] A semiconductor device (100) is provided on a substrate (102). Additionally, although not shown in (B) of FIG. 1, an insulating layer functioning as a film may be provided between the substrate (102) and the semiconductor device (100). The semiconductor device (100) includes a transistor (10_1), a transistor (10_2), an insulating layer (110_1) (insulating layer (110a1), insulating layer (110b1), and insulating layer (110c1)), an insulating layer (110_2) (insulating layer (110a2), insulating layer (110b2), and insulating layer (110c2)), an insulating layer (192), an insulating layer (193), and an insulating layer (194). The transistor (10_1) and the transistor (10_2) are provided superimposed in this order.

[0061] The transistor (10_1) includes a conductive layer (104_1), an insulating layer (106_1), a semiconductor layer (108_1), a conductive layer (112a1), and a conductive layer (112b1). The conductive layer (104_1) functions as a gate electrode. A portion of the insulating layer (106_1) functions as a gate insulating layer. The conductive layer (112a1) functions as either a source electrode or a drain electrode. The conductive layer (112b1) functions as either a source electrode or a drain electrode. In the semiconductor layer (108_1), the entire region overlapping with the gate electrode functions as a channel forming region by interposing a gate insulating layer between the source electrode and the drain electrode. Additionally, in the semiconductor layer (108_1), the region in contact with the source electrode functions as a source region, and the region in contact with the drain electrode functions as a drain region.

[0062] For the transistor (10_2), the description of the transistor (10_1) described above can be applied by replacing the conductive layer (104_1), insulating layer (106_1), semiconductor layer (108_1), conductive layer (112a1), and conductive layer (112b1) with the conductive layer (104_2), insulating layer (106_2), semiconductor layer (108_2), conductive layer (112a2), and conductive layer (112b2), respectively.

[0063] The detailed configuration of the semiconductor device (100) is described.

[0064] A conductive layer (112a1) is provided on the substrate (102). An insulating layer (110a1) is provided on the conductive layer (112a1) and on the substrate (102). An insulating layer (110b1) is provided on the insulating layer (110a1). An insulating layer (110c1) is provided on the insulating layer (110b1). A conductive layer (112b1) is provided on the insulating layer (110c1). Additionally, the insulating layer (110a1), the insulating layer (110b1), and the insulating layer (110c1) are collectively referred to as the insulating layer (110_1).

[0065] The conductive layer (112a1), the insulating layer (110_1), and the conductive layer (112b1) include an overlapping region. In the region, the insulating layer (110_1) is provided to be sandwiched between the conductive layer (112a1) and the conductive layer (112b1).

[0066] The insulating layer (110_1) and the conductive layer (112b1) include an opening (143) extending to the conductive layer (112a1).

[0067] The upper surface shape of the opening (143) may be, for example, circular or elliptical. The upper surface shape of the opening (143) may be a polygon such as a triangle, a square (including a rectangle, a rhombus, and a square), or a pentagon, or a shape with rounded corners of such polygons. As shown in (A) of FIG. 1, etc., it is preferable that the upper surface shape of the opening (143) be circular. By making the upper surface shape of the opening (143) circular, the machining precision when forming the opening (143) can be increased, allowing for the formation of a fine-sized opening (143). Furthermore, in this specification, the circular shape is not limited to a perfect circle.

[0068] Additionally, in FIG. 1 (B) and FIG. 2 (A), the film thickness of the region overlapping with the opening (143) in the conductive layer (112a1) is shown to be substantially equal to the film thickness of the region not overlapping with the opening (143), but is not limited thereto. The film thickness of the region overlapping with the opening (143) in the conductive layer (112a1) may be thinner than the film thickness of the region not overlapping with the opening (143). In this case, the electric field from the conductive layer (104_1) (i.e., the gate electric field of the transistor (10_1)) can be applied to the channel forming region near the conductive layer (112a1). Therefore, there are cases where the effect of the gate electric field on carriers in the channel forming region can be made stronger than when the film thickness of the conductive layer (112a1) is uniform.

[0069] A semiconductor layer (108_1) is provided in contact with the upper surface of the conductive layer (112a1) in the opening (143), the side surface of the insulating layer (110_1) in the opening (143), the side surface of the conductive layer (112b1) in the opening (143), and the upper surface of the conductive layer (112b1).

[0070] Additionally, Figure 1 (B) and Figure 2 (A) show a configuration in which the semiconductor layer (108_1) includes an area in contact with the upper surface of the conductive layer (112b1), but is not limited thereto. The semiconductor layer (108_1) may include an area in contact with the side of the conductive layer (112b1) at least within the opening (143).

[0071] For example, by configuring the entire area of ​​the semiconductor layer (108_1) to be located within the opening (143) and the end of the semiconductor layer (108_1) to be in contact only with the side of the conductive layer (112b1) within the opening (143), it is possible to suppress the formation of a step difference on the conductive layer (112b1) due to the end of the semiconductor layer (108_1). By doing so, the coverage of the film formed on the upper surface of the conductive layer (112b1) can be increased.

[0072] Meanwhile, as shown in (B) of FIG. 1 and (A) of FIG. 2, the end of the semiconductor layer (108_1) extends to the outside of the opening (143), and the semiconductor layer (108_1) is configured to come into contact not only with the side of the conductive layer (112b1) within the opening (143) but also with the upper surface of the conductive layer (112b1), thereby increasing the contact area between the semiconductor layer (108_1) and the conductive layer (112b1). This allows for the suppression of film peeling of the conductive layer (108_1). Additionally, the contact resistance between the semiconductor layer (108_1) and the conductive layer (112b1) is lowered, which may increase the on-current of the transistor (10_1).

[0073] Here, among the insulating layers (110_1), it is preferable that the insulating layer (110b1) is an insulating layer containing oxygen. It is also preferable that it is an insulating layer that releases oxygen upon heating. Accordingly, for example, when a metal oxide is used in the semiconductor layer (108_1), the oxygen contained in the insulating layer (110b1) can be supplied to the metal oxide. As a result, the oxygen deficiency within the metal oxide can be repaired, thereby improving the electrical characteristics and reliability of the transistor (10_1).

[0074] Meanwhile, among the insulating layers (110_1), insulating layer (110a1) and insulating layer (110c1) are preferably insulating layers that have a barrier property against gases such as oxygen and hydrogen. By doing so, oxygen contained in the insulating layer (110b1) can be suppressed from being released to the outside through the insulating layer (110a1) or insulating layer (110c1). In addition, hydrogen can be suppressed from the outside of the insulating layer (110_1) through the insulating layer (110a1) or insulating layer (110c1) into the insulating layer (110b1) and from diffusing said hydrogen into the semiconductor layer (108_1). For example, if a metal oxide is used in the semiconductor layer (108_1), hydrogen within the semiconductor layer (108_1) can be a factor in the deterioration of the electrical characteristics and reliability of the transistor (10_1).

[0075] An insulating layer (106_1) is provided on the semiconductor layer (108_1). The insulating layer (106_1) includes an area in contact with the upper and side surfaces of the semiconductor layer (108_1), the upper surface of the conductive layer (112b1), and the upper surface of the insulating layer (110c1).

[0076] A conductive layer (104_1) is provided on top of an insulating layer (106_1). The conductive layer (104_1) is provided to include an area that overlaps with the opening (143) when viewed in a planar view. The conductive layer (104_1) has a shape that follows the shape of the semiconductor layer (108_1) and the insulating layer (106_1) within the opening (143). That is, the conductive layer (104_1) includes a concave portion on its upper surface that corresponds to the shape of the opening (143). The conductive layer (104_1) includes an area facing the semiconductor layer (108_1) through the insulating layer (106_1) within the opening (143).

[0077] An insulating layer (192) is provided on the conductive layer (104_1) to fill the opening (143). The upper surface of the insulating layer (192) has a substantially flat shape. It is preferable to use, for example, an organic insulating material for the insulating layer (192). By doing so, the concave portion formed in the conductive layer (104_1) can be easily flattened with good productivity. It is preferable that the height of the upper surface of the insulating layer (192) and the upper surface of the highest region when viewed from the substrate surface of the conductive layer (104_1) substantially coincide. By doing so, the surface to be formed of the layer (e.g., conductive layer (112a2)) provided on the insulating layer (192) and on the conductive layer (104_1) can be made substantially flat, thereby increasing the coverage of the layer.

[0078] A conductive layer (112a2) is provided over the insulating layer (192) and over the conductive layer (104_1). The conductive layer (112a2) is provided to include an area that overlaps with the opening (143). The end of the conductive layer (112a2) and the end of the conductive layer (104_1) substantially coincide when viewed in a plane. The conductive layer (112a2) includes an area that contacts the upper surface of the insulating layer (192) and a portion of the upper surface of the conductive layer (104_1).

[0079] That is, as shown in (B) of FIG. 2, the gate electrode (conductive layer (104_1)) of the transistor (10_1) and one of the source electrode and drain electrode (conductive layer (112a2)) of the transistor (10_2) can be said to be connected.

[0080] An insulating layer (193) is provided over the transistor (10_1) and the conductive layer (112a2) to cover them. It is preferable to use a material for the insulating layer (193) such as the insulating layer (110a1) and the insulating layer (110c1) described above. By doing so, the diffusion of impurities, such as hydrogen, from the outside of the transistor (10_1) into the transistor (10_1) through the insulating layer (193) can be suppressed.

[0081] An insulating layer (194) is provided on the insulating layer (193) in an area that does not overlap with the opening (143). The insulating layer (194) has the function of flattening the step or irregularity caused by the transistor (10_1) by filling it. Therefore, it is preferable to use a material for the insulating layer (194) such as the insulating layer (192) described above. For example, it is preferable to use an organic insulating material. This allows the step or irregularity caused by the transistor (10_1) to be easily flattened with good productivity. It is preferable that the height of the upper surface of the insulating layer (194) and a portion of the upper surface of the insulating layer (193) (specifically, the upper surface of the area overlapping with the conductive layer (112a2)) substantially match. This allows the surface to be formed of the layer (e.g., insulating layer (110_2)) provided on the insulating layer (194) and on the insulating layer (193) to be substantially flat, thereby increasing the coverage of the layer.

[0082] An insulating layer (110a2) is provided on the insulating layer (194) and on the insulating layer (193). An insulating layer (110b2) is provided on the insulating layer (110a2). An insulating layer (110c2) is provided on the insulating layer (110b2). A conductive layer (112b2) is provided on the insulating layer (110c2). Additionally, the insulating layer (110a2), the insulating layer (110b2), and the insulating layer (110c2) are collectively referred to as the insulating layer (110_2).

[0083] It is preferable to use the same material as the aforementioned insulating layer (110a1), insulating layer (110b1), and insulating layer (110c1) for the insulating layer (110a2), insulating layer (110b2), and insulating layer (110c2), respectively. By doing so, for example, when a metal oxide is used in the semiconductor layer (108_2), oxygen contained in the insulating layer (110b2) can be supplied to the metal oxide. Additionally, the release of oxygen contained in the insulating layer (110b2) to the outside through the insulating layer (110a2) or the insulating layer (110c2) can be suppressed. Furthermore, hydrogen can diffuse from the outside of the insulating layer (110_2) into the insulating layer (110b2) through the insulating layer (110a2) or the insulating layer (110c2), and the diffusion of said hydrogen into the semiconductor layer (108_2) can be suppressed.

[0084] The conductive layer (112a2), insulating layer (193), insulating layer (110_2), and conductive layer (112b2) include regions that overlap each other. In the said regions, the insulating layer (193) and the insulating layer (110_2) are provided to be fitted between the conductive layer (112a2) and the conductive layer (112b2).

[0085] The insulating layer (193), the insulating layer (110_2), and the conductive layer (112b2) each include an opening (144) extending to the conductive layer (112a2).

[0086] Regarding the shape of the upper surface of the opening (144), one may refer to the description of the shape of the upper surface of the opening (143) described above. As shown in (A) of FIG. 1, etc., the shape of the upper surface of the opening (144) is preferably circular.

[0087] In addition, Figure 1 (B) and Figure 2 (A) show a configuration in which the film thickness of the region overlapping with the opening (144) in the conductive layer (112a2) is substantially equal to the film thickness of the region not overlapping with the opening (144), but is not limited thereto. As with the description of the conductive layer (112a1) and the opening (143) described above, the conductive layer (112a2) can also be configured such that the film thickness of the region overlapping with the opening (144) is thinner than the film thickness of the region not overlapping with the opening (144).

[0088] A semiconductor layer (108_2) is provided in contact with the upper surface of the conductive layer (112a2) in the opening (144), the side surface of the insulating layer (193) in the opening (144), the side surface of the insulating layer (110_2) in the opening (144), the side surface of the conductive layer (112b2) in the opening (144), and the upper surface of the conductive layer (112b2).

[0089] In addition, Figure 1 (B) and Figure 2 (A) show a configuration in which the semiconductor layer (108_2) includes an area in contact with the upper surface of the conductive layer (112b2), but is not limited thereto. As with the description of the semiconductor layer (108_1) and the conductive layer (112b1) described above, the semiconductor layer (108_2) may also include an area in contact with the side of the conductive layer (112b2) at least within the opening (144).

[0090] An insulating layer (106_2) is provided on the semiconductor layer (108_2). The insulating layer (106_2) includes an area in contact with the upper and side surfaces of the semiconductor layer (108_2), the upper surface of the conductive layer (112b2), and the upper surface of the insulating layer (110c2).

[0091] A conductive layer (104_2) is provided on top of an insulating layer (106_2). The conductive layer (104_2) is provided to include an area that overlaps with the opening (144) when viewed in a planar view. The conductive layer (104_2) has a shape that follows the shape of the semiconductor layer (108_2) and the insulating layer (106_2) within the opening (144). That is, the conductive layer (104_2) includes a concave portion on its upper surface that corresponds to the shape of the opening (144). The conductive layer (104_2) includes an area facing the semiconductor layer (108_2) through the insulating layer (106_2) within the opening (144).

[0092] Additionally, the conductive layer (104_2) may be formed to embed the opening (144). For example, depending on the diameter of the opening (144) when viewed from a planar view, the conductive layer (104_2) may be formed to embed the opening (144). In this case, it is desirable because the step or irregularity formed on the upper surface of the conductive layer (104_2) in the area overlapping with the opening (144) is reduced, thereby increasing the coverage of the layer formed thereon.

[0093] In the transistor (10_1), the source electrode and the drain electrode are positioned at different heights relative to the surface of the substrate (102), which is the surface to be formed, and the drain current flows in a direction perpendicular to the surface of the substrate (102) or substantially perpendicular. Similarly, in the transistor (10_2), the source electrode and the drain electrode are positioned at different heights relative to the surface of the insulating layer (192), which is the surface to be formed, and the drain current flows in a direction perpendicular to the surface of the insulating layer (192) or substantially perpendicular. That is, it can be said that the drain current flows in a vertical direction or substantially perpendicularly in the transistor (10_1) and the transistor (10_2), respectively. Therefore, one form of the transistor of the present invention can be described as a vertical transistor, a vertical channel transistor, or a VFET (Vertical Field Effect Transistor).

[0094] Since both transistors (10_1) and (10_2) can be provided with the source electrode and drain electrode overlapping, the transistors can be miniaturized compared to so-called planar transistors in which the source electrode and drain electrode are arranged on the same plane. In addition, the area occupied by the transistors within the substrate surface can be significantly reduced.

[0095] In addition, a semiconductor device (100) of one embodiment of the present invention has a configuration in which a transistor (10_2) is provided so as to overlap a transistor (10_1) in which a concave portion formed in the gate electrode by an insulating layer (192) and an insulating layer (194) is substantially flattened. Therefore, compared to a configuration in which these two transistors are arranged on the same plane, the area occupied by the transistor within the substrate surface can be significantly reduced, thereby promoting miniaturization and high integration of the semiconductor device. For example, when using a semiconductor device of one embodiment of the present invention in a scan line driving circuit of a display device, a vertical transistor can be used as each of the plurality of transistors constituting the scan line driving circuit, and a configuration can be made in which transistors with electrodes (source electrode, drain electrode, or gate electrode) connected to each other, such as transistor (10_1) and transistor (10_2), are stacked. As a result, the area occupied by the scan line driving circuit can be reduced, thereby enabling the realization of a display device with a very narrow bezel.

[0096] The channel length and channel width of transistors (10_1) and (10_2) will be described. Additionally, although the channel length and channel width will be described below using transistor (10_2), the same description can be applied to transistor (10_1), which is a vertical transistor, by substituting each component of the transistor (for example, by substituting the number "2" at the end of each code with "1").

[0097] In the semiconductor layer (108_2), the region in contact with the conductive layer (112a2) functions as one of the source region and the drain region, the region in contact with the conductive layer (112b2) functions as the other of the source region and the drain region, and the region between the source region and the drain region functions as a channel forming region.

[0098] The channel length of the transistor (10_2) is the distance between the source region and the drain region. In FIG. 2 (A), the channel length L10_2 of the transistor (10_2) is indicated by dashed left and right arrows. In FIG. 2 (A), the distance along the semiconductor layer (108_2) in the region between the conductive layer (112a2) and the conductive layer (112b2) is indicated as the channel length L10_2 of the transistor (10_2).

[0099] In addition, as the channel length L10_2 of the transistor (10_2), the sum of the thickness of the insulating layer (193) in the region fitted between the upper surface of the conductive layer (112a2) and the lower surface of the conductive layer (112b2) and the thickness of the insulating layer (110_2) (in the case of the channel length of the transistor (10_1), the thickness of the insulating layer (110_1)) may be used. Alternatively, as the channel length L10_2 of the transistor (10_2), the thickness of the insulating layer (110b2) (in the case of the channel length of the transistor (10_1), the thickness of the insulating layer (110b1)) may be used. Alternatively, as the channel length L10_2 of the transistor (10_2), the sum of the thickness of the insulating layer (193), the thickness of the insulating layer (110_2), and the thickness of the conductive layer (112b2) (in the case of the channel length of the transistor (10_1), the sum of the thickness of the insulating layer (110_1) and the thickness of the conductive layer (112b1)) may be used.

[0100] Here, the channel length L10_2 of the transistor (10_2) is determined by the thickness of the insulating layer (193), the thickness of the insulating layer (110_2), the thickness of the conductive layer (112b2), the angle (θ110_2) formed by the surface to be formed of the semiconductor layer (108_2) within the opening (144) (here, the side of the insulating layer (193), the side of the insulating layer (110_2), and the side of the conductive layer (112b2)) and the surface to be formed of the insulating layer (193) (here, the upper surface of the conductive layer (112a2)), and is not affected by the performance of the exposure device used to manufacture the transistor. Therefore, since the channel length L10_2 can be made smaller than the limit resolution of the exposure device, a transistor of fine size can be realized.

[0101] The channel length L10_2 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and less than 2.5 μm, 10 nm or more and less than 2 μm, 10 nm or more and less than 1.5 μm, 10 nm or more and less than 1.2 μm, 10 nm or more and less than 1 μm, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm. For example, the channel length L10_2 can be 100 nm or more and less than 1 μm. By shortening the channel length L10_2, the on-current of the transistor (10_2) can be increased.

[0102] The thickness of the insulating layer (110_2) (or the sum of the thickness of the insulating layer (193) and the thickness of the insulating layer (110_2)) can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and less than 2.5 μm, 10 nm or more and less than 2 μm, 10 nm or more and less than 1.5 μm, 10 nm or more and less than 1.2 μm, 10 nm or more and less than 1 μm, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm.

[0103] The angle (θ110_2) can be, for example, 30° or more and less than 90°, 35° or more and less than 85°, 40° or more and less than 80°, 45° or more and less than 80°, 50° or more and less than 80°, 55° or more and less than 80°, 60° or more and less than 80°, 65° or more and less than 80°, or 70° or more and less than 80°. Additionally, the angle (θ110_2) can be 90°. It is preferable that the angle (θ110_2) is smaller, as this increases the coverage of the layer (semiconductor layer (108_2), etc.) formed along the side wall of the opening (144). On the other hand, it is preferable that the angle (θ110_2) is closer to 90°, as this reduces the area occupied by the transistor relative to the substrate surface.

[0104] The channel width of the transistor (10_2) is the length of the source region or the length of the drain region when viewed from a plane ((A) of FIG. 1). That is, the channel width of the transistor (10_2) is the length of the region where the semiconductor layer (108_2) and the conductive layer (112a2) meet when viewed from a plane, or the length of the region where the semiconductor layer (108_2) and the conductive layer (112b2) meet when viewed from a plane. Alternatively, as the channel width of the transistor (10_2), the average value of the length of the region where the semiconductor layer (108_2) and the conductive layer (112a2) meet when viewed from a plane and the length of the region where the semiconductor layer (108_2) and the conductive layer (112b2) meet when viewed from a plane may be used.

[0105] Here, the channel width of the transistor (10_2) is described as the perimeter length in the area where the semiconductor layer (108_2) and the side of the opening (144) of the conductive layer (112b2) meet. In FIG. 1 (A) and FIG. 2 (A), the channel width W10_2 of the transistor (10_2) is indicated by dashed left and right arrows. The channel width W10_2 may be the perimeter length of the opening (144) when viewed from a plane (in the case of the channel width of the transistor (10_1), the perimeter length of the opening (143) when viewed from a plane).

[0106] The channel width W10_2 is determined by the shape of the upper surface of the opening (144), etc. In FIG. 1 (A) and FIG. 2 (A), the width D144 of the opening (144) is indicated by the left and right arrows of the dotted line. The width D144 refers to the short side of the smallest rectangle that circumscribes the opening (144) when viewed from a plane. When the opening (144) is formed using a photolithography method, the width D144 of the opening (144) is greater than the limit resolution of the exposure device. For example, the width D144 is 0.20 μm or more and less than 5.0 μm. Also, if the shape of the upper surface of the opening (144) is circular, the width D144 corresponds to the diameter of the opening (144), and the channel width W10_2 can be calculated as "D144 × π".

[0107] [Semiconductor layer (108_1), Semiconductor layer (108_2)]

[0108] The semiconductor materials that can be used in the semiconductor layer (108_1) and semiconductor layer (108_2) are not particularly limited. For example, a single semiconductor or a compound semiconductor may be used. As a single semiconductor, for example, silicon or germanium may be used. As a compound semiconductor, for example, gallium arsenide and silicon germanium may be used. As a compound semiconductor, an organic material having semiconductor properties or a metal oxide having semiconductor properties (also called an oxide semiconductor) may be used. In addition, these semiconductor materials may contain impurities that function as dopants (for example, when silicon is used as a semiconductor material, representative examples include elements such as phosphorus and boron).

[0109] The crystallinity of the semiconductor material used in the semiconductor layer (108_1) and semiconductor layer (108_2) is not particularly limited, and any of an amorphous semiconductor and a crystalline semiconductor (single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or a semiconductor including a crystalline region in part) may be used. Using a crystalline semiconductor is preferable because it can suppress the degradation of transistor characteristics.

[0110] Silicon can be used for the semiconductor layer (108_1) and semiconductor layer (108_2). Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0111] A transistor using amorphous silicon for the semiconductor layer (108_1) and semiconductor layer (108_2) can be formed on a large glass substrate and manufactured at a low cost. A transistor using polycrystalline silicon for the semiconductor layer (108_1) and semiconductor layer (108_2) has a high field-effect mobility, enabling high-speed operation. Additionally, a transistor using microcrystalline silicon for the semiconductor layer (108_1) and semiconductor layer (108_2) has a higher field-effect mobility than a transistor using amorphous silicon, enabling high-speed operation.

[0112] It is preferable that the semiconductor layer (108_1) and the semiconductor layer (108_2) include a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the semiconductor layer (108_1) and the semiconductor layer (108_2) include indium oxide, gallium oxide, and zinc oxide. It is preferable that the metal oxide includes at least indium (In) or zinc (Zn). In addition, it is preferable that the metal oxide includes two or three types selected from indium, element M, and zinc. In addition, element M is one or more types selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, it is preferable that element M is one or more types selected from aluminum, gallium, yttrium, and tin. It is more desirable that element M be gallium.

[0113] For example, indium oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc., may be used in the semiconductor layer (108_1) and semiconductor layer (108_2). Alternatively, indium tin oxide containing silicon, etc., may be used.

[0114] Sputtering or atomic layer deposition (ALD) can be suitably used for the formation of metal oxides. In addition, when metal oxides are formed by sputtering, there may be cases where the ratio of atoms in the target and the ratio of atoms in the metal oxide differ. In particular, zinc may have a lower ratio of atoms in the metal oxide than in the target. Specifically, there may be cases where the ratio of zinc atoms contained in the target is between 40% and 90%.

[0115] When forming the semiconductor layer (108_1) and semiconductor layer (108_2) using the ALD method, it is preferable to use a film deposition method such as the thermal ALD method or the PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferred because it offers very high step coverage. Additionally, the PEALD method is preferred because, in addition to offering high step coverage, it enables low-temperature film deposition.

[0116] The composition of the metal oxide included in the semiconductor layer (108_1) and the semiconductor layer (108_2) significantly affects the electrical characteristics and reliability of the transistor (10_1) and the transistor (10_2), respectively.

[0117] For example, a transistor with a high on-current can be realized by increasing the indium content of the metal oxide. In addition, for example, by using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer (108_1) and semiconductor layer (108_2), a transistor with high reliability for positive bias application can be made. In addition, for example, by applying a metal oxide with a low content of element M to the semiconductor layer (108_1) and semiconductor layer (108_2), a transistor with high reliability for positive bias application can be made. In addition, for example, by increasing the element M content of the metal oxide, a transistor with high reliability for light can be made.

[0118] Details regarding the composition of the metal oxide included in the semiconductor layer (108_1) and semiconductor layer (108_2) will be described later.

[0119] It is preferable to use a crystalline metal oxide layer as the semiconductor layer (108_1) and semiconductor layer (108_2). For example, a metal oxide layer having a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline structure, or a nanocrystalline (nc: nano-crystal) structure may be used. By using a crystalline metal oxide layer as the semiconductor layer (108_1) and semiconductor layer (108_2), the defect level density in the semiconductor layer (108_1) and semiconductor layer (108_2) can be reduced, thereby enabling the realization of a highly reliable transistor. Furthermore, the CAAC structure is a crystal structure in which a plurality of nanocrystallines (typically a plurality of IGZO nanocrystallines) have a c-axis orientation, and the plurality of nanocrystallines are connected without orientation in the ab plane. Since the grain boundaries in the CAAC structure are not clearly visible in the ab plane compared to the polycrystalline structure, a highly reliable transistor can be realized.

[0120] The higher the crystallinity of the metal oxide layer used as the semiconductor layer (108_1) and semiconductor layer (108_2), the lower the defect level density in the semiconductor layer (108_1) and semiconductor layer (108_2). On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of carrying a large current can be realized.

[0121] The semiconductor layer (108_1) and the semiconductor layer (108_2) may have a stacked structure of two or more metal oxide layers with different crystallinities. For example, the structure may be a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, and the second metal oxide layer may be configured to include a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may be configured to include a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer (108_1) and the semiconductor layer (108_2) may have the same or substantially the same composition. By forming a stacked structure of metal oxide layers with the same composition, manufacturing costs can be reduced because, for example, they can be formed using the same sputtering target. For example, by using the same sputtering target and varying the ratio of the oxygen gas flow rate to the total film-forming gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), a stacked structure of two or more metal oxide layers with different crystallinities can be formed. In addition, the two or more metal oxide layers included in the semiconductor layer (108_1) and the semiconductor layer (108_2) may have different compositions.

[0122] The thickness of each of the semiconductor layer (108_1) and the semiconductor layer (108_2) (film thickness relative to the surface to be formed) is preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, more preferably 20 nm or more and 50 nm or less, more preferably 20 nm or more and 40 nm or less, and more preferably 25 nm or more and 40 nm or less.

[0123] Here, oxygen vacancies that may be formed within the semiconductor layer (108_1) and the semiconductor layer (108_2) are described.

[0124] When an oxide semiconductor is used in the semiconductor layer (108_1) and semiconductor layer (108_2), hydrogen contained in the oxide semiconductor reacts with oxygen that combines with metal atoms to form water, resulting in oxygen vacancies (V) within the oxide semiconductor. O There are cases where an oxygen vacancy is formed. In addition, defects in which hydrogen enters the oxygen vacancy (hereinafter V) O Hydrogen (referred to as H) functions as a donor, and there are cases where carrier electrons are generated. Additionally, some hydrogen may combine with oxygen that bonds to metal atoms to generate carrier electrons. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen are prone to exhibiting normaly-on characteristics. Furthermore, since hydrogen within oxide semiconductors is prone to migration due to stresses such as heat and electric fields, there is a concern that the reliability of the transistor may deteriorate if the oxide semiconductor contains a large amount of hydrogen.

[0125] V O H can function as a donor for oxide semiconductors. However, it is difficult to quantitatively evaluate the above defect. Therefore, oxide semiconductors are sometimes evaluated based on carrier concentration rather than donor concentration. Accordingly, in this specification and others, carrier concentration, which assumes a state where no electric field is applied, is sometimes used as a parameter of oxide semiconductors instead of donor concentration. That is, "carrier concentration" described in this specification and others may be replaced with "donor concentration."

[0126] From the above, when an oxide semiconductor is used in the semiconductor layer (108_1) and the semiconductor layer (108_2), V in the semiconductor layer (108_1) and in the semiconductor layer (108_2) O It is desirable to reduce H as much as possible to achieve high-purity authenticity or substantially high-purity authenticity. In this way, V OIn order to obtain an oxide semiconductor with sufficiently reduced H, impurities such as water and hydrogen within the oxide semiconductor are removed (sometimes described as dehydration or dehydrogenation treatment), and oxygen is supplied to the oxide semiconductor to address oxygen deficiency (V O It is important to restore ). V O By using an oxide semiconductor in which defects such as H are sufficiently reduced in the channel formation region of a transistor, stable electrical characteristics can be imparted. In addition, by supplying oxygen to the oxide semiconductor, oxygen vacancies (V) O There are cases where restoring ) is described as oxidization treatment.

[0127] When oxide semiconductors are used in the semiconductor layer (108_1) and semiconductor layer (108_2), the carrier concentration of the oxide semiconductor in the region functioning as a channel forming region is 1×10 18 cm -3 It is desirable that it be less than or equal to 1×10 17 cm -3 It is more desirable to be less than 1×10 16 cm -3 It is more desirable to be less than 1×10 13 cm -3 It is more desirable to be less than 1×10 12 cm -3 It is more preferable that it be less than. In addition, the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel-forming region is not particularly limited, but, for example, 1×10⁻⁶ -9 cm -3 It can be done as.

[0128] Transistors using oxide semiconductors (hereinafter referred to as OS transistors) have a much higher field-effect mobility than transistors using amorphous silicon. In addition, since OS transistors have a very low source-drain leakage current (hereinafter also referred to as off-current) in the off state, the charge accumulated in a capacitive element connected in series with said transistor can be maintained over a long period. Furthermore, by applying OS transistors to semiconductor devices, the power consumption of the semiconductor device can be reduced.

[0129] OS transistors can be applied to display devices. When increasing the luminous brightness of a light-emitting device included in the pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of the driving transistor included in the pixel circuit. Since OS transistors have a higher source-drain voltage rating than silicon transistors (hereinafter referred to as Si transistors), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by applying an OS transistor to the driving transistor of the pixel circuit, the amount of current flowing through the light-emitting device can be increased, thereby increasing the luminous brightness of the light-emitting device.

[0130] When a transistor operates in the saturation region, OS transistors can reduce the change in source-drain current relative to the change in gate-source voltage compared to Si transistors. Therefore, by applying OS transistors as driving transistors in the pixel circuit, the current flowing between the source and drain can be precisely set according to the change in gate-source voltage, thereby allowing for precise control of the amount of current flowing to the light-emitting device. Consequently, the number of grayscale levels in the pixel circuit can be increased.

[0131] Regarding the saturation characteristics of the current flowing when the transistor operates in the saturation region, the OS transistor can flow a more stable current (saturation current) than the Si transistor even when the voltage between the source and drain is gradually increased. Therefore, by using the OS transistor as a driving transistor, a stable current can be flowed to the light-emitting device, for example, even when there is a deviation in the current-voltage characteristics of the light-emitting device. In other words, when the OS transistor operates in the saturation region, the current between the source and drain hardly changes even when the voltage between the source and drain is increased, so the luminous brightness of the light-emitting device can be stabilized.

[0132] As described above, by using an OS transistor as a driving transistor included in the pixel circuit, for example, it is possible to suppress the black display area from being displayed brightly, increase the luminous brightness, increase the gradation, or suppress deviations in the light-emitting device.

[0133] In addition, OS transistors can be applied, for example, to scanline driving circuits of display devices. As mentioned above, OS transistors have a much higher field-effect mobility than transistors using amorphous silicon. Therefore, by applying OS transistors to the scanline driving circuits of display devices, it is possible to realize a scanline driving circuit capable of high-speed operation.

[0134] Furthermore, OS transistors exhibit minimal fluctuations in electrical characteristics due to radiation exposure—in other words, they possess high resistance to radiation—making them suitable for use even in environments where radiation may be incident. OS transistors can also be described as having high reliability against radiation. For example, OS transistors can be appropriately used in the pixel circuits of X-ray flat-panel detectors. Additionally, OS transistors are suitable for use in semiconductor devices operated in space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, and proton rays).

[0135] [Insulation layer]

[0136] In a transistor of one embodiment of the present invention, and in a semiconductor device, display device, etc. to which a transistor of one embodiment of the present invention is applied, an inorganic insulating material or an organic insulating material may be used for the insulating layer (insulating layer (110_1), insulating layer (110_2), insulating layer (106_1), insulating layer (106_2), insulating layer (192), insulating layer (193), and insulating layer (194)). Additionally, a laminated structure of an inorganic insulating material and an organic insulating material may be used as the insulating layer.

[0137] One or more of oxides, nitride oxides, nitride oxides, and nitrides may be used as inorganic insulating materials.

[0138] In addition, in this specification and others, the term "nitride oxide" refers to a material having a higher oxygen content than nitrogen in its composition. The term "nitride oxide" refers to a material having a higher nitrogen content than oxygen in its composition. For example, silicon nitride oxide refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0139] For the analysis of oxygen and nitrogen content, methods such as Secondary Ion Mass Spectrometry (SIMS) or X-ray Photoelectron Spectrometry (XPS) may be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic%, or less than 1 atomic%). When comparing elemental content, it is more desirable to perform a combined analysis using both SIMS and XPS analytical methods.

[0140] In addition, for evaluating the film density of insulating layers, methods such as Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR) can be used. Furthermore, differences in film density can sometimes be evaluated using cross-sectional Transmission Electron Microscopy (TEM) images. In TEM observation, if the film density is high, the transmission electron (TE) image becomes darker, and if the film density is low, the transmission electron (TE) image becomes lighter. Also, even when the same material is applied to the insulating layer, if the film densities differ, the boundary between them can sometimes be observed as a difference in contrast in the cross-sectional TEM image.

[0141] The nitrogen content of the insulating layer can be determined, for example, by Energy Dispersive X-ray Spectrometry (EDX). For instance, when silicon nitride, silicon oxynitride, etc., are used in the insulating layer, the nitrogen content can be evaluated by using the ratio of the height of the nitrogen peak to the height of the silicon peak. Furthermore, in EDX, a peak of a specific element refers to the point where the count of the element reaches a maximum value in a spectrum where the horizontal axis represents the energy of the characteristic X-ray and the vertical axis represents the count of the characteristic X-ray (detection value). Alternatively, the count at the characteristic X-ray energy unique to the element may be used, and the difference in nitrogen content may be determined by the ratio of the count of nitrogen to the count of silicon. For example, the count at 1.739 keV (Si-Kα) can be used for silicon, and the count at 0.392 keV (N-Kα) can be used for nitrogen.

[0142] The hydrogen concentration of the insulating layer can be evaluated, for example, using SIMS.

[0143] When hydrogen diffuses into the semiconductor layer (108_1) and semiconductor layer (108_2), it reacts with oxygen atoms contained in the oxide semiconductor to become water, and oxygen vacancies (V) within the semiconductor layer (108_1) and semiconductor layer (108_2) O There are cases where ) is formed. Also, V within the semiconductor layer (108_1) and semiconductor layer (108_2). O There are cases where H is formed, causing the carrier concentration within the semiconductor layer (108_1) and semiconductor layer (108_2) to increase. By using a barrier film that suppresses hydrogen diffusion as an insulating layer in contact with the semiconductor layer (108_1) and semiconductor layer (108_2), or as an insulating layer located around the semiconductor layer (108_1) and semiconductor layer (108_2), the oxygen deficiency (V) within the semiconductor layer (108_1) and semiconductor layer (108_2) is reduced. O ) and V OSince H can be reduced, it can be made into a transistor with good electrical characteristics and high reliability.

[0144] Oxygen vacancy (V) in the channel formation region of transistor (10_1) and transistor (10_2) O ) and V O It is desirable for H to be low. Particularly when the channel length is short, oxygen deficiency (V) in the channel-forming region. O ) and V O The influence of H on the electrical characteristics and reliability of transistors (10_1) and (10_2) increases. For example, V from the source region or drain region to the channel forming region O As H diffuses, the carrier concentration in the channel-forming region increases, which may cause the threshold voltage of transistors (10_1) and (10_2) to fluctuate or reduce reliability. Such V O The effect of H diffusion on the electrical characteristics and reliability of transistors (10_1) and (10_2) increases as the channel length becomes shorter. The oxygen vacancy (V) in the semiconductor layer (108_1), semiconductor layer (108_2), particularly in the channel forming region. O ) and V O By reducing H, it is possible to realize a transistor with good electrical characteristics, high reliability, and a short channel length.

[0145] By using an insulating layer that emits oxygen as an insulating layer in contact with the semiconductor layer (108_1) and an insulating layer in contact with the semiconductor layer (108_2) (e.g., insulating layer (106_1), insulating layer (106_2), insulating layer (110b1), insulating layer (110b2)), oxygen can be supplied from the insulating layer to the semiconductor layer (108_1) and the semiconductor layer (108_2). By supplying oxygen to the channel forming region of the semiconductor layer (108_1) and the semiconductor layer (108_2), oxygen deficiency (V) within the semiconductor layer (108_1) and the semiconductor layer (108_2) can be reduced. O ) and V OSince H can be reduced, it can be made into a transistor with good electrical characteristics and high reliability. In addition, as a process for supplying oxygen to the semiconductor layer (108_1) and semiconductor layer (108_2), other methods include heating in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere.

[0146] It is desirable that the insulating layer in contact with the semiconductor layer (108_1), the insulating layer in contact with the semiconductor layer (108_2), or the insulating layer located around the semiconductor layer (108_1) and the semiconductor layer (108_2) have low levels of impurities (e.g., water and hydrogen) emitted from themselves. Furthermore, the impurities referred to herein are oxygen deficiencies (V) that occur within the semiconductor layer (108_1) and the semiconductor layer (108_2) by diffusing into the semiconductor layer (108_1) and the semiconductor layer (108_2). O ) and V O It refers to a substance that can adversely affect the electrical characteristics of a transistor by generating H, etc. If the emission of impurities is low, the diffusion of the impurities into the semiconductor layer (108_1) and semiconductor layer (108_2) is suppressed, so the transistor can be made with good electrical characteristics and high reliability.

[0147] There are cases where oxygen is lost from the semiconductor layer (108_1) and the semiconductor layer (108_2) due to heat applied in a process later than the formation of the semiconductor layer (108_1) and the semiconductor layer (108_2). However, as oxygen is supplied to the semiconductor layer (108_1) and the semiconductor layer (108_2) from the insulating layer in contact with the semiconductor layer (108_1) and the insulating layer in contact with the semiconductor layer (108_2), the oxygen deficiency (V) within the semiconductor layer (108_1) and the semiconductor layer (108_2) is reduced. O ) and V OThe increase in H can be suppressed. Additionally, the degree of freedom for the processing temperature can be increased in processes later than the formation of the semiconductor layer (108_1) and the semiconductor layer (108_2). Specifically, the processing temperature can be increased even in processes later than the formation of the semiconductor layer (108_1) and the semiconductor layer (108_2). Therefore, a transistor with good electrical characteristics and high reliability can be formed.

[0148] [Insulating layer (110_1), insulating layer (110_2)]

[0149] Inorganic insulating materials or organic insulating materials may be used in the insulating layer (110_1) (insulating layer (110a1), insulating layer (110b1), and insulating layer (110c1)) and insulating layer (110_2) (insulating layer (110a2), insulating layer (110b2), and insulating layer (110c2)). The insulating layer (110_1) and insulating layer (110_2) may have a laminated structure of an inorganic insulating material and an organic insulating material.

[0150] Inorganic insulating materials may be suitably used in the insulating layer (110_1) and insulating layer (110_2). One or more of oxides, nitride oxides, nitride oxides, and nitrides may be used as inorganic insulating materials. In the insulating layer (110_1) and insulating layer (110_2), for example, one or more of silicon oxide, silicon nitride oxide, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon nitride oxide, and aluminum nitride may be used.

[0151] The insulating layer (110_1) and insulating layer (110_2) may have a stacked structure of two or more layers. In Fig. 1 (B), etc., the insulating layer (110_1) has a stacked structure of insulating layer (110a1), insulating layer (110b1) above insulating layer (110a1), and insulating layer (110c1) above insulating layer (110b1), and the insulating layer (110_2) has a stacked structure of insulating layer (110a2), insulating layer (110b2) above insulating layer (110a2), and insulating layer (110c2) above insulating layer (110b2). In addition, the insulating layer (110a1), insulating layer (110b1), insulating layer (110c1), insulating layer (110a2), insulating layer (110b2), and insulating layer (110c2) may use the same material or different materials.

[0152] It is desirable that the insulating layer (110_1) and insulating layer (110_2) have little impurity (e.g., water and hydrogen) emitted from themselves.

[0153] The film thickness of the insulating layer (110b1) and insulating layer (110b2) can be made thicker than the film thickness of the insulating layer (110a1) and insulating layer (110a2), and the film thickness of the insulating layer (110c1) and insulating layer (110c2). As described above, the insulating layer (110b1) and insulating layer (110b2) are insulating layers containing oxygen to supply to the semiconductor layer (108_1) and semiconductor layer (108_2), respectively. Accordingly, among the three insulating layers (insulating layer (110a1), insulating layer (110b1), and insulating layer (110c1)) constituting the insulating layer (110_1) and the three insulating layers (insulating layer (110a2), insulating layer (110b2), and insulating layer (110c2)) constituting the insulating layer (110_2), the film thickness of insulating layer (110b1) and insulating layer (110b2) is made the thickest, thereby increasing the amount of oxygen that can be contained in the entire insulating layer (110_1) and the entire insulating layer (110_2). It is preferable that the film formation rate of insulating layer (110b1) and insulating layer (110b2) be faster than the film formation rate of insulating layer (110a1) and insulating layer (110a2) and the film formation rate of insulating layer (110c1) and insulating layer (110c2). Productivity can be increased by accelerating the film formation speed of thick films.

[0154] Insulating layer (110a1) and insulating layer (110c1), and insulating layer (110a2) and insulating layer (110c2) each function as a barrier that prevents gas from escaping from insulating layer (110b1) and insulating layer (110b2). It is preferable to use a material that is difficult to diffuse gas in each of insulating layer (110a1) and insulating layer (110c1), and insulating layer (110a2) and insulating layer (110c2). It is preferable that insulating layer (110a1) and insulating layer (110c1), and insulating layer (110a2) and insulating layer (110c2) each include a region with a higher film density than insulating layer (110b1) and insulating layer (110b2). By increasing the film density of the insulating layer, the barrier performance against gas can be increased. By slowing down the film formation speed of the insulating layer, the film density increases, thereby increasing the barrier performance against gas.

[0155] It is preferable to use an oxide or an oxynitride in the insulating layer (110b1) and insulating layer (110b2). It is preferable to use a film that releases oxygen upon heating in the insulating layer (110b1) and insulating layer (110b2). For example, silicon oxide or silicon oxynitride may be suitably used in the insulating layer (110b1) and insulating layer (110b2).

[0156] By releasing oxygen from the insulating layer (110b1) and the insulating layer (110b2), oxygen can be supplied from the insulating layer (110b1) to the semiconductor layer (108_1) and from the insulating layer (110b2) to the semiconductor layer (108_2). It is desirable for the insulating layer (110b1) and the insulating layer (110b2) to have a high oxygen diffusion coefficient. By increasing the oxygen diffusion coefficient, oxygen becomes easier to diffuse within the insulating layer (110b1) and the insulating layer (110b2), allowing oxygen to be efficiently supplied to the semiconductor layer (108_1) and the semiconductor layer (108_2), respectively. In addition, as described above, by making the film thickness of the insulating layer (110b1) and insulating layer (110b2) thicker than the film thickness of the insulating layer (110a1) and insulating layer (110c1), and the film thickness of the insulating layer (110a2) and insulating layer (110c2), respectively, more oxygen can be supplied to the semiconductor layer (108_1) and semiconductor layer (108_2).

[0157] It is preferable that the insulating layer (110_1) and insulating layer (110_2) be formed by a film formation method such as sputtering, ALD, or plasma CVD.

[0158] In particular, by using a sputtering method and performing the film deposition using a method that does not use a gas containing hydrogen as the film deposition gas, it is possible to produce a film with a very low hydrogen content. Therefore, by suppressing the supply of hydrogen to the semiconductor layer (108_1) and semiconductor layer (108_2), the stabilization of the electrical characteristics of the transistor (10_1) and transistor (10_2) can be promoted. When depositing silicon oxide by the sputtering method, the film can be deposited using a silicon target in an atmosphere containing oxygen gas, for example. Also, when depositing silicon nitride by the sputtering method, the film can be deposited using a silicon target in an atmosphere containing nitrogen gas, for example. Also, when depositing aluminum oxide by the sputtering method, the film can be deposited using an aluminum target in an atmosphere containing oxidizing gas, for example.

[0159] In addition, silicon oxide and silicon nitride can be deposited using, for example, the PEALD method. Furthermore, aluminum oxide and hafnium oxide can be deposited using, for example, the thermal ALD method. Since a dense insulating film can be formed by depositing an insulating layer using the PEALD and thermal ALD methods, the barrier properties against oxygen and hydrogen can be enhanced.

[0160] In the insulating layer (110a1) and insulating layer (110c1), and in the insulating layer (110a2) and insulating layer (110c2), a material having a higher nitrogen content than the insulating layer (110b1) and insulating layer (110b2) can be used, respectively. By increasing the nitrogen content of the insulating layer, the barrier properties against oxygen and hydrogen can be increased.

[0161] Additionally, the insulating layer (110a1) and insulating layer (110c1), and the insulating layer (110a2) and insulating layer (110c2) may each include a region in which the hydrogen concentration within the film is lower than that of the insulating layer (110b1) and insulating layer (110b2).

[0162] It is preferable that the insulating layer (110a1) and the insulating layer (110c1), and the insulating layer (110a2) and the insulating layer (110c2) each have difficulty permeating oxygen. Additionally, it is preferable that the insulating layer (110a1) and the insulating layer (110c1), and the insulating layer (110a2) and the insulating layer (110c2) each have difficulty permeating hydrogen. The insulating layer (110a1) and the insulating layer (110c1), and the insulating layer (110a2) and the insulating layer (110c2) each function as a barrier to suppress the diffusion of hydrogen from the outside of the transistor to the semiconductor layer (108_1) and the semiconductor layer (108_2) through the insulating layer (110a1) and the insulating layer (110c1), and the insulating layer (110a2) and the insulating layer (110c2). It is preferable that the film density of the insulating layer (110a1) and insulating layer (110c1), and the insulating layer (110a2) and insulating layer (110c2) be higher than the film density of the insulating layer (110b1) and insulating layer (110b2), respectively. By increasing the film density of the insulating layer, the barrier properties of oxygen and hydrogen can be increased. When silicon oxide or silicon nitride is used in the insulating layer (110b1) and insulating layer (110b2), silicon nitride or silicon nitride oxide may be used in the insulating layer (110a1), insulating layer (110c1), insulating layer (110a2), and insulating layer (110c2), respectively. Additionally, hafnium oxide or aluminum oxide may be suitably used in the insulating layer (110a1), insulating layer (110c1), insulating layer (110a2), and insulating layer (110c2).

[0163] In addition, a structure in which two or more materials selected from silicon nitride, silicon nitride oxide, hafnium oxide, and aluminum oxide are stacked can be used as insulating layers (110a1), insulating layers (110c1), insulating layers (110a2), and insulating layers (110c2), respectively.

[0164] If oxygen contained in the insulating layer (110b1) and insulating layer (110b2) diffuses downward from the insulating layer (110b1) and insulating layer (110b2) (towards the substrate (102)), there may be a case where the amount of oxygen supplied from the insulating layer (110b1) and insulating layer (110b2) to the semiconductor layer (108_1) and semiconductor layer (108_2), respectively, decreases. By providing insulating layer (110a1) and insulating layer (110a2), respectively, below the insulating layer (110b1) and insulating layer (110b2), the diffusion of oxygen contained in the insulating layer (110b1) and insulating layer (110b2) downward from the insulating layer (110b1) and insulating layer (110b2) can be suppressed. Additionally, by providing an insulating layer (110c1) and an insulating layer (110c2) respectively on top of the insulating layer (110b1) and the insulating layer (110b2), the diffusion of oxygen contained in the insulating layer (110b1) and the insulating layer (110b2) upwards can be suppressed. Accordingly, the amount of oxygen supplied from the insulating layer (110b1) and the insulating layer (110b2) to the semiconductor layer (108_1) and the semiconductor layer (108_2), respectively, is increased, thereby reducing the oxygen deficiency (V) within the semiconductor layer (108_1) and the semiconductor layer (108_2). O ) and V O H can be reduced.

[0165] In addition, by providing insulating layers (110a1) and (110c1), and insulating layers (110a2) and (110c2), hydrogen is suppressed from diffusing into the semiconductor layer (108_1) and semiconductor layer (108_2), respectively, thereby reducing the oxygen deficiency (V) within the semiconductor layer (108_1) and semiconductor layer (108_2). O ) and V O H can be reduced.

[0166] It is preferable that the insulating layer (110a1) and insulating layer (110c1), and the insulating layer (110a2) and insulating layer (110c2) each have a film thickness that functions as a barrier against oxygen and hydrogen. If the film thickness is thin, the function as a barrier may be reduced. On the other hand, if the film thickness is thick, the region of the semiconductor layer (108_1) and semiconductor layer (108_2) in contact with the insulating layer (110b1) and insulating layer (110b2), respectively, becomes narrower, and the amount of oxygen supplied to the semiconductor layer (108_1) and semiconductor layer (108_2) may be reduced. It is preferable that the film thickness (film thickness relative to the surface to be formed) of the insulating layer (110a1), insulating layer (110c1), insulating layer (110a2), and insulating layer (110c2) be 1 nm or more and 200 nm or less, 1 nm or more and 100 nm or less, 1 nm or more and 60 nm or less, 1 nm or more and 50 nm or less, 1 nm or more and 40 nm or less, 1 nm or more and 30 nm or less, 1 nm or more and 20 nm or less, 1 nm or more and 10 nm or less, 1 nm or more and 5 nm or less, or 2 nm or more and 5 nm or less.

[0167] [Insulating layer (106_1), insulating layer (106_2)]

[0168] It is desirable that the insulating layer (106_1) and insulating layer (106_2), which function as gate insulating layers, have a low defect density. If the insulating layer (106_1) and insulating layer (106_2) have a low defect density, the transistor can be made with good electrical characteristics. In addition, it is desirable that the insulating layer (106_1) and insulating layer (106_2) have a high dielectric breakdown voltage. If the insulating layer (106_1) and insulating layer (106_2) have a high dielectric breakdown voltage, the transistor can be made with high reliability.

[0169] Additionally, it is preferable that the insulating layer (106_1) and the insulating layer (106_2) are insulating layers containing oxygen. It is also preferable that they are insulating layers that release oxygen upon heating. Accordingly, for example, when a metal oxide is used in the semiconductor layer (108_1) and the semiconductor layer (108_2), the oxygen contained in the insulating layer (106_1) and the insulating layer (106_2) can be supplied to the metal oxide, respectively. As a result, the oxygen deficiency within the metal oxide can be restored, thereby improving the electrical characteristics and reliability of the transistor (10_1) and the transistor (10_2).

[0170] In the insulating layer (106_1) and insulating layer (106_2), one or more of oxides, nitride oxides, nitride oxides, and nitrides having insulating properties may be used, for example. In the insulating layer (106_1) and insulating layer (106_2), one or more of silicon oxide, silicon nitride oxide, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum nitride oxide, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium nitride oxide, gallium oxide, gallium nitride oxide, yttrium oxide, yttrium nitride oxide, and Ga-Zn oxide may be used. The insulating layer (106_1) and insulating layer (106_2) may be a single layer or a stacked layer. The insulating layer (106_1) and insulating layer (106_2) may have a stacked structure of oxides and nitrides, for example.

[0171] In addition, in microtransistors, leakage current may increase when the thickness of the gate insulating layer is reduced. By using a material with a high dielectric constant (also called a high-k material) in the gate insulating layer, it is possible to achieve low voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, aluminum, oxides containing hafnium, nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0172] It is desirable that the insulating layer (106_1) and the insulating layer (106_2) have low levels of impurities (e.g., water and hydrogen) emitted from themselves. If the levels of impurities emitted from the insulating layer (106_1) and the insulating layer (106_2) are low, the diffusion of said impurities into the semiconductor layer (108_1) and the semiconductor layer (108_2), respectively, is suppressed, thereby enabling the formation of a transistor with good electrical characteristics and high reliability.

[0173] Since the insulating layer (106_1) and the insulating layer (106_2) are formed on the semiconductor layer (108_1) and the semiconductor layer (108_2), respectively, it is desirable that the film be formed under conditions where there is minimal damage to the semiconductor layer (108_1) and the semiconductor layer (108_2). For example, it is desirable that the film be formed under conditions where the film deposition rate (also called the film deposition rate) is sufficiently slow. For example, when forming the insulating layer (106_1) and the insulating layer (106_2) using the plasma CVD method, the damage to the semiconductor layer (108_1) and the semiconductor layer (108_2) can be minimized by forming them under conditions of low power.

[0174] Here, the insulating layer (106_1) and insulating layer (106_2) are described in detail, using a configuration in which a metal oxide is used in the semiconductor layer (108_1) and semiconductor layer (108_2).

[0175] In order to improve the interface characteristics with the semiconductor layer (108_1) and the semiconductor layer (108_2), it is preferable to use at least one of an oxide and a nitride oxide on the side of the insulating layer (106_1) that contacts the semiconductor layer (108_1) and at least one of the insulating layer (106_2) that contacts the semiconductor layer (108_2). For example, at least one of silicon oxide and silicon nitride oxide may be suitably used for the insulating layer (106_1) and the insulating layer (106_2). Furthermore, it is more preferable to use a film that releases oxygen upon heating as the insulating layer (106_1) and the insulating layer (106_2).

[0176] Additionally, the insulating layer (106_1) and the insulating layer (106_2) may have a stacked structure. The insulating layer (106_1) and the insulating layer (106_2) may each have a stacked structure of an oxide film or an oxynitride film on the side in contact with the semiconductor layer (108_1) and the semiconductor layer (108_2), and a nitride film on the side in contact with the conductive layer (104_1) and the conductive layer (104_2), respectively. For example, one or more of silicon oxide and silicon oxynitride may be suitably used for the oxide film or oxynitride film. For example, silicon nitride may be suitably used as the nitride film.

[0177] It is more preferable that the film thickness (film thickness relative to the surface to be formed) of the insulating layer (106_1) and insulating layer (106_2) be 1 nm or more and 100 nm or less. It is also preferable that the insulating layer (106_1) and insulating layer (106_2) include a region of such film thickness in at least a portion.

[0178] [Challenge layer(112a1), Challenge layer(112b1), Challenge layer(112a2), Challenge layer(112b2)]

[0179] The conductive layer (112a1) and conductive layer (112b1), and the conductive layer (112a2) and conductive layer (112b2), which function as source electrode and drain electrode, respectively, can each be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy having one or more of the aforementioned metals as a component. For the conductive layer (112a1) and conductive layer (112b1), and the conductive layer (112a2) and conductive layer (112b2), a low-resistance conductive material comprising one or more of copper, silver, gold, and aluminum can be suitably used. In particular, copper or aluminum is preferred because of their excellent mass producibility.

[0180] For the conductive layer (112a1) and conductive layer (112b1), and for the conductive layer (112a2) and conductive layer (112b2), a metal oxide film (also called an oxide conductor) can be used, respectively. Examples of oxide conductors (OC: Oxide Conductor) include In-Sn oxide (ITO), In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide (ITSO), and In-Ga-Zn oxide.

[0181] Here, oxide conductors (OC) are described. For example, if oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to these oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and acts as a conductor. A metal oxide that has become a conductor can be referred to as an oxide conductor.

[0182] The conductive layer (112a1) and the conductive layer (112b1), and the conductive layer (112a2) and the conductive layer (112b2) may each have a stacked structure of a conductive film comprising the oxide conductor (metal oxide) described above and a conductive film comprising a metal or an alloy. By using a conductive film comprising a metal or an alloy, the wiring resistance can be reduced.

[0183] A Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied to each of the conductive layer (112a1) and the conductive layer (112b1), and the conductive layer (112a2) and the conductive layer (112b2). By using a Cu-X alloy film, the manufacturing cost can be reduced because it can be processed by a wet etching method.

[0184] In addition, the same material may be used for the conductive layer (112a1) and the conductive layer (112b1), or different materials may be used. The same applies to the conductive layer (112a2) and the conductive layer (112b2).

[0185] Here, the conductive layer (112a1) and conductive layer (112b1), and the conductive layer (112a2) and conductive layer (112b2) are specifically described by using a configuration in which a metal oxide is used in the semiconductor layer (108_1) and semiconductor layer (108_2).

[0186] When oxide semiconductors are used in the semiconductor layer (108_1) and semiconductor layer (108_2), the conductive layer (112a1), conductive layer (112b1), conductive layer (112a2), and conductive layer (112b2) may be oxidized by oxygen contained in the semiconductor layer (108_1) and semiconductor layer (108_2), thereby increasing the resistance. There are also cases where the conductive layer (112a1), conductive layer (112b1), conductive layer (112a2), and conductive layer (112b2) may be oxidized by oxygen contained in the insulating layer (110_1) and insulating layer (110_2), thereby increasing the resistance. In addition, the conductive layer (112a1) and the conductive layer (112b1), and the conductive layer (112a2) and the conductive layer (112b2) are oxidized by oxygen contained in the semiconductor layer (108_1) and the semiconductor layer (108_2), thereby causing oxygen deficiency (V) in the semiconductor layer (108_1) and the semiconductor layer (108_2). O There are cases where the amount of oxygen supplied from the insulating layer (110_1) and insulating layer (110_2) to the semiconductor layer (108_1) and semiconductor layer (108_2), respectively, is reduced.

[0187] It is preferable to use a material that is resistant to oxidation for the conductive layer (112a1) and the conductive layer (112b1), and for the conductive layer (112a2) and the conductive layer (112b2), respectively. It is preferable to use an oxide conductor for the conductive layer (112a1) and the conductive layer (112b1), and for the conductive layer (112a2) and the conductive layer (112b2), respectively. For example, In-Sn oxide (ITO) or In-Sn-Si oxide (ITSO) may be suitably used. Nitride conductors may also be used for the conductive layer (112a1) and the conductive layer (112b1), and for the conductive layer (112a2) and the conductive layer (112b2), respectively. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layer (112a1) and the conductive layer (112b1), and the conductive layer (112a2) and the conductive layer (112b2) may each have a laminated structure of the material described above.

[0188] By using materials that are resistant to oxidation in the conductive layer (112a1) and conductive layer (112b1), and the conductive layer (112a2) and conductive layer (112b2), it is possible to suppress the increase in resistance caused by oxidation due to oxygen contained in the semiconductor layer (108_1) and semiconductor layer (108_2), or oxygen contained in the insulating layer (110_1) and insulating layer (110_2). In addition, oxygen deficiency (V) within the semiconductor layer (108_1) and semiconductor layer (108_2) O Along with suppressing the increase of ), the amount of oxygen supplied from the insulating layer (110_1) and insulating layer (110_2) to the semiconductor layer (108_1) and semiconductor layer (108_2), respectively, can be increased.

[0189] [Challenge Floor (104_1), Challenge Floor (104_2)]

[0190] The conductive layer (104_1) and the conductive layer (104_2), which function as gate electrodes, can each be formed using one or more of, for example, chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy having one or more of the aforementioned metals as components. Additionally, materials that can be used for the conductive layer (112a1) and the conductive layer (112b1), and the conductive layer (112a2) and the conductive layer (112b2) may be applied to the conductive layer (104_1) and the conductive layer (104_2).

[0191] In addition, in Fig. 1 (B), etc., the conductive layer (104_1) and the conductive layer (104_2) are shown as a single-layer structure, but are not limited thereto. For example, the conductive layer (104_1) and the conductive layer (104_2) may be formed as a stacked structure of two or more layers. For example, when the conductive layer (104_1) and the conductive layer (104_2) are formed as a two-layer stacked structure, a nitride or an oxide may be used for the first layer of the conductive layer (the conductive layer on the side of the insulating layer (106_1) and the insulating layer (106_2), respectively), and for the second layer of the conductive layer, one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy having one or more of the aforementioned metals as components may be used. In addition, for example, when the conductive layer (104_1) and the conductive layer (104_2) are formed as a three-layer stacked structure, an alloy having one or more of the metals described above as components, or a nitride of the metal or the alloy may be used in the first layer's conductive layer (the conductive layer on the insulating layer (106_1) side and the insulating layer (106_2) side, respectively), an alloy having one or more of the metals described above as components may be used in the second layer's conductive layer, and an alloy having one or more of the metals described above as components, or a nitride of the metal or the alloy may be used in the third layer's conductive layer.

[0192] [Insulating layer (192), insulating layer (194)]

[0193] In the insulating layer (192) that fills the opening (143) and the insulating layer (194) that flattens the upper surface of the transistor (10_1), either one or both of organic insulating materials and inorganic insulating materials may be used, respectively. It is preferable to use organic insulating materials for the insulating layer (192) and the insulating layer (194), respectively. For example, by using organic insulating materials for the insulating layer (192) and the insulating layer (194), a film with excellent flatness can be easily formed at a relatively low temperature on a surface to be formed that has a step.

[0194] Specific examples of organic insulating materials that can be used for the insulating layer (192) and the insulating layer (194) include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins. Photosensitive materials may also be used as organic materials. Here, photosensitivity refers to the property of responding to ultraviolet rays, far ultraviolet rays, electron beams, X-rays, etc. A resist pattern is formed by exposure using this property. Ultraviolet rays, preferably far ultraviolet rays, are mainly used for the exposure of the silicon-containing resist. The raw monomer used at this time may be aromatic, but to increase sensitivity, it is more desirable to have a structure that does not contain aromatic rings. For example, it is desirable to use polyimide resin for the insulating layer (192) and the insulating layer (194).

[0195] Inorganic insulating materials may be used for the insulating layer (192) and the insulating layer (194). Specific examples of inorganic insulating materials that can be used for the insulating layer (192) and the insulating layer (194) include the inorganic insulating materials that can be used for the insulating layer (110_1) and the insulating layer (110_2) described above. For example, it is preferable to use silicon oxide, silicon nitride, silicon nitride, silicon nitride, etc., for the insulating layer (192) and the insulating layer (194).

[0196] [Insulating layer (193)]

[0197] It is preferable to use an insulating material that is resistant to the diffusion of impurities in the insulating layer (193) provided to cover the transistor (10_1). By providing the insulating layer (193), the diffusion of impurities from the outside into the transistor (10_1) can be effectively suppressed, thereby increasing the reliability of the transistor (10_1). Examples of impurities include water and hydrogen. The insulating layer (193) may be an insulating layer containing an inorganic insulating material or an insulating layer containing an organic material. It is preferable to use an inorganic insulating material for the insulating layer (193). Specific examples of inorganic insulating materials that can be used for the insulating layer (193) include the inorganic insulating materials that can be used for the insulating layer (110a1), insulating layer (110c1), insulating layer (110a2), and insulating layer (110c2) described above. For example, it is preferable to use silicon nitride, silicon nitride oxide, hafnium oxide, aluminum oxide, etc., for the insulating layer (193).

[0198] [Board (102)]

[0199] There are no major restrictions on the material of the substrate (102), but it needs to have at least enough heat resistance to withstand subsequent heat treatment. For example, a single-crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate (102). Additionally, a semiconductor device provided on these substrates may be used as the substrate (102). Furthermore, the shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.

[0200] A flexible substrate may be used as the substrate (102), and a semiconductor device (100), etc. may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate (102) and the semiconductor device (100), etc. The release layer may be used to separate the semiconductor device from the substrate (102) and transfer it to another substrate after the semiconductor device is partially or entirely completed on it. At that time, the semiconductor device (100), etc. may be transferred to a substrate with low heat resistance or a flexible substrate.

[0201] [Composition of metal oxide containing semiconductor layer (108_1) and semiconductor layer (108_2)]

[0202] The composition of the metal oxide included in the semiconductor layer (108_1) and semiconductor layer (108_2) is described below.

[0203] The composition of the metal oxide included in the semiconductor layer (108_1) and the semiconductor layer (108_2) significantly affects the electrical characteristics and reliability of the transistor (10_1) and the transistor (10_2), respectively.

[0204] For example, by increasing the indium content of the metal oxide, a transistor with a high on-current can be realized.

[0205] When using In-Zn oxide in the semiconductor layer (108_1) and semiconductor layer (108_2), it is preferable to use a metal oxide in which the ratio of the number of indium atoms is greater than or equal to the ratio of the number of zinc atoms. For example, a metal oxide with an atomic ratio of metal elements In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, In:Zn=10:1, or a ratio close to these may be used.

[0206] When using In-Sn oxide in the semiconductor layer (108_1) and semiconductor layer (108_2), it is preferable to use a metal oxide in which the ratio of the number of indium atoms is greater than or equal to the ratio of the number of tin atoms. For example, a metal oxide with an atomic ratio of metal elements In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, In:Sn=10:1, or a ratio close to these may be used.

[0207] When using In-M-Zn oxide in the semiconductor layer (108_1) and semiconductor layer (108_2), a metal oxide in which the ratio of the number of indium atoms to the number of metal atoms is higher than the ratio of the number of atoms of element M can be applied. Additionally, it is more preferable to use a metal oxide in which the ratio of the number of zinc atoms is higher than the ratio of the number of atoms of element M. For example, in the semiconductor layer (108_1) and semiconductor layer (108_2), the atomic number ratio of metal elements is In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides with a ratio close to these can be used.

[0208] In addition, when element M includes multiple metal elements, the sum of the ratios of the atomic numbers of said metal elements can be defined as the ratio of the atomic number of element M. For example, in the case of an In-Ga-Al-Zn oxide containing gallium and aluminum as element M, the sum of the ratio of the atomic number of gallium and the ratio of the atomic number of aluminum can be defined as the ratio of the atomic number of element M. Furthermore, it is preferable that the ratio of the atomic numbers of indium, element M, and zinc falls within the range described above. For example, in the case of an In-Ga-Sn-Zn oxide containing gallium and tin as element M, the sum of the ratio of the atomic number of gallium and the ratio of the atomic number of tin can be defined as the ratio of the atomic number of element M. Furthermore, it is preferable that the ratio of the atomic numbers of indium, element M, and zinc falls within the range described above.

[0209] It is preferable to use a metal oxide in which the ratio of the number of atoms of indium to the number of atoms of metal elements contained in the metal oxide is 30 atomic% or more and 100 atomic% or less, preferably 30 atomic% or more and 95 atomic% or less, more preferably 35 atomic% or more and 95 atomic% or less, more preferably 35 atomic% or more and 90 atomic% or less, more preferably 40 atomic% or more and 90 atomic% or less, more preferably 45 atomic% or more and 90 atomic% or less, more preferably 50 atomic% or more and 80 atomic% or less, more preferably 60 atomic% or more and 80 atomic% or less, and more preferably 70 atomic% or more and 80 atomic% or less. For example, when using In-Ga-Zn oxide in the semiconductor layer (108_1) and semiconductor layer (108_2), it is preferable that the ratio of the number of atoms of indium to the sum of the number of atoms of indium, gallium, and zinc is within the range described above.

[0210] In the present specification and other documents, the ratio of the number of indium atoms to the number of atoms of the contained metal elements is sometimes described as the indium content. The same applies to other metal elements.

[0211] By increasing the indium content of the metal oxide, a transistor with a high on-current can be produced. By applying the above transistor as a transistor requiring a high on-current, a semiconductor device with excellent electrical characteristics can be provided.

[0212] For the analysis of the composition of metal oxides, methods such as EDX, XPS, Inductively Coupled Plasma-Mass Spectrometry (ICP-MS), or Inductively Coupled Plasma-Atomic Emission Spectrometry (ICP-AES) may be used. Alternatively, analysis may be performed by combining multiple of these methods. Furthermore, for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical precision. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, difficult to quantify, or not detected at all.

[0213] In the present specification, etc., the composition of the vicinity includes a range of ±30% of the ratio of the desired number of atoms. For example, when the ratio of the number of atoms is described as In:M:Zn=4:2:3 or a composition of the vicinity thereof, if the ratio of the number of atoms of indium is 4, it includes cases where the ratio of the number of atoms of M is 1 or more and 3 or less, and the ratio of the number of atoms of zinc is 2 or more and 4 or less. Also, when the ratio of the number of atoms is described as In:M:Zn=5:1:6 or a composition of the vicinity thereof, if the ratio of the number of atoms of indium is 5, it includes cases where the ratio of the number of atoms of M is greater than 0.1 and 2 or less, and the ratio of the number of atoms of zinc is 5 or more and 7 or less. Also, when the ratio of the number of atoms is described as In:M:Zn=1:1:1 or a composition of the vicinity thereof, if the ratio of the number of atoms of indium is 1, it includes cases where the ratio of the number of atoms of M is greater than 0.1 and 2 or less, and the ratio of the number of atoms of zinc is greater than 0.1 and 2 or less.

[0214] Here, the reliability of transistors is explained. As one of the indicators for evaluating transistor reliability, there is the Gate Bias Temperature (GBT) stress test, which involves maintaining the device at a high temperature while applying an electric field to the gate. Specifically, the test in which a positive potential (positive bias) is applied to the gate with respect to the source and drain potentials while maintaining the device at a high temperature is called the Positive Bias Temperature Stress (PBTS) test, and the test in which a negative potential (negative bias) is applied to the gate while maintaining the device at a high temperature is called the Negative Bias Temperature Stress (NBTS) test. Additionally, the PBTS and NBTS tests performed under light irradiation are called the Positive Bias Temperature Illumination Stress (PBTIS) test and the Negative Bias Temperature Illumination Stress (NBTIS) test, respectively.

[0215] In n-channel transistors, since a positive potential is applied to the gate when the transistor is turned on (current flows), the amount of variation in the threshold voltage during the PBTS test is one of the important factors to consider as an indicator of the transistor's reliability.

[0216] By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer (108_1) and semiconductor layer (108_2), a transistor with high reliability for positive bias application can be made. That is, a transistor with a small variation in threshold voltage during PBTS testing can be made. In addition, when using a metal oxide containing gallium, it is preferable to lower the gallium content compared to the indium content. By doing so, a transistor with high reliability can be realized.

[0217] One of the factors causing variation in threshold voltage during a PBTS test is carrier traps caused by defect levels at or near the interface between the semiconductor layer and the gate insulating layer. As the defect level density increases, the amount of carrier traps caused by defect levels increases, which leads to significant degradation during the PBTS test. By lowering the gallium content in the region of the semiconductor layer in contact with the gate insulating layer, the generation of the defect levels can be suppressed.

[0218] The reason why fluctuations in the threshold voltage during the PBTS test can be suppressed by using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer is thought to be, for example, as follows. Gallium contained in the metal oxide has a property of easily attracting oxygen compared to other metal elements (e.g., indium or zinc). Therefore, it is inferred that at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, carrier (here, electron) trap sites are easily formed as gallium combines with excess oxygen in the gate insulating layer. Therefore, it is thought that when a positive potential is applied to the gate, the threshold voltage fluctuates as carriers are trapped at the interface between the semiconductor layer and the gate insulating layer.

[0219] More specifically, when using In-Ga-Zn oxide in the semiconductor layer (108_1) and semiconductor layer (108_2), a metal oxide in which the ratio of the number of indium atoms is higher than the ratio of the number of gallium atoms can be applied to the semiconductor layer (108_1) and semiconductor layer (108_2). Additionally, it is more preferable to use a metal oxide in which the ratio of the number of zinc atoms is higher than the ratio of the number of gallium atoms. In other words, it is preferable to apply a metal oxide in which the ratio of the number of metal elements satisfies In > Ga and Zn > Ga to the semiconductor layer (108_1) and semiconductor layer (108_2).

[0220] In the semiconductor layer (108_1) and semiconductor layer (108_2), it is preferable to use a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is higher than 0 atomic% and is 50 atomic% or less, preferably 0.1 atomic% or more and 40 atomic% or less, more preferably 0.1 atomic% or more and 35 atomic% or less, more preferably 0.1 atomic% or more and 30 atomic% or less, more preferably 0.1 atomic% or more and 25 atomic% or less, more preferably 0.1 atomic% or more and 20 atomic% or less, more preferably 0.1 atomic% or more and 15 atomic% or less, and more preferably 0.1 atomic% or more and 10 atomic% or less. By lowering the gallium content in the semiconductor layer, it is possible to make a transistor with high resistance to PBTS testing. In addition, by incorporating gallium into the metal oxide, oxygen vacancies (V) in the metal oxide are created. O The effect is that it becomes difficult for ) to occur.

[0221] For the semiconductor layer (108_1) and semiconductor layer (108_2), a metal oxide that does not contain gallium may be applied. For example, an In-Zn oxide may be applied to the semiconductor layer (108_1) and semiconductor layer (108_2). In this case, by increasing the ratio of the number of indium atoms to the number of metal element atoms included in the metal oxide, the field-effect mobility of the transistor can be increased. On the other hand, by increasing the ratio of the number of zinc atoms to the number of metal element atoms included in the metal oxide, the metal oxide becomes highly crystalline, thereby suppressing fluctuations in the electrical characteristics of the transistor and increasing reliability. Additionally, for the semiconductor layer (108_1) and semiconductor layer (108_2), a metal oxide that does not contain gallium and zinc, such as indium oxide, may be applied. By using a metal oxide that does not contain gallium, the fluctuation of the threshold voltage, particularly in the PBTS test, can be made very small.

[0222] For example, in the semiconductor layer (108_1) and semiconductor layer (108_2), an oxide containing indium and zinc may be used. In this case, a metal oxide in which the atomic ratio of the metal elements is, for example, In:Zn=2:3 or close to these may be used.

[0223] In addition, although gallium was used as a representative example, it can also be applied when using element M instead of gallium. For the semiconductor layer (108_1) and semiconductor layer (108_2), it is preferable to apply a metal oxide in which the ratio of the number of indium atoms is higher than the ratio of the number of indium atoms. It is also preferable to apply a metal oxide in which the ratio of the number of zinc atoms is higher than the ratio of the number of indium atoms.

[0224] By applying a metal oxide with a low content of element M to the semiconductor layer (108_1) and semiconductor layer (108_2), a transistor with high reliability for positive bias application can be made. By applying the above transistor as a transistor requiring high reliability for positive bias application, a semiconductor device with high reliability can be made.

[0225] Next, the reliability of the transistor with respect to light is explained.

[0226] There are cases where the electrical characteristics of a transistor fluctuate due to the incidence of light. In particular, for transistors applied to regions where light can be incident, it is desirable that the fluctuation in electrical characteristics under light irradiation conditions be small and that the reliability against light is high. Reliability against light can be evaluated, for example, by the amount of variation in threshold voltage during the NBTIS test.

[0227] By increasing the element M content of the metal oxide, it is possible to make a transistor with high reliability against light. That is, it is possible to make a transistor with a small variation in threshold voltage during the NBTIS test. Specifically, a metal oxide in which the ratio of the number of atoms of element M is greater than the ratio of the number of atoms of indium has a larger band gap, and the variation in threshold voltage during the NBTIS test of the transistor can be reduced. The band gap of the metal oxide included in the semiconductor layer (108_1) and the semiconductor layer (108_2) is preferably 2.0 eV or more, more preferably 2.5 eV or more, more preferably 3.0 eV or more, more preferably 3.2 eV or more, more preferably 3.3 eV or more, more preferably 3.4 eV or more, and more preferably 3.5 eV or more.

[0228] For example, in the semiconductor layer (108_1) and semiconductor layer (108_2), metal oxides with an atomic ratio of metal elements In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a range thereof may be used.

[0229] In the semiconductor layer (108_1) and semiconductor layer (108_2), a metal oxide in which the ratio of the number of atoms of element M to the number of atoms of the metal element contained is 20 atomic% or more and 70 atomic% or less, preferably 30 atomic% or more and 70 atomic% or less, more preferably 30 atomic% or more and 60 atomic% or less, more preferably 40 atomic% or more and 60 atomic% or less, more preferably 50 atomic% or more and 60 atomic% or less can be particularly suitably used.

[0230] When using In-Ga-Zn oxide in the semiconductor layer (108_1) and semiconductor layer (108_2), a metal oxide can be applied in which the ratio of the number of indium atoms to the number of metal elements is less than or equal to the ratio of the number of gallium atoms. For example, a metal oxide in which the ratio of the number of metal elements is In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, or a range thereof can be used.

[0231] In the semiconductor layer (108_1) and semiconductor layer (108_2), a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the metal elements contained is 20 atomic% or more and 60 atomic% or less, preferably 30 atomic% or more and 60 atomic% or less, more preferably 40 atomic% or more and 60 atomic% or less, more preferably 50 atomic% or more and 60 atomic% or less can be particularly suitablely used.

[0232] By applying a metal oxide with a high content of element M to the semiconductor layer (108_1) and semiconductor layer (108_2), a transistor with high reliability against light can be made. By applying the above transistor as a transistor requiring high reliability against light, a semiconductor device with high reliability can be made.

[0233] As described above, the electrical characteristics and reliability of the transistor differ depending on the composition of the metal oxide applied to the semiconductor layer (108_1) and the semiconductor layer (108_2). Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, it is possible to create a semiconductor device that combines excellent electrical characteristics and high reliability.

[0234] The semiconductor layer (108_1) and the semiconductor layer (108_2) may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer (108_1) and the semiconductor layer (108_2) may have the same or substantially the same composition. By making the stacked structure of metal oxide layers with the same composition, manufacturing costs can be reduced because, for example, they can be formed using the same sputtering target.

[0235] Two or more metal oxide layers comprising the semiconductor layer (108_1) and the semiconductor layer (108_2) may have different compositions. For example, a stacked structure may suitably be used, comprising a first metal oxide layer having a composition of In:M:Zn=1:3:4 [atomic ratio] or a similar composition, and a second metal oxide layer provided on the first metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or a similar composition. Additionally, it is particularly preferable to use gallium or aluminum as the element M. For example, a stacked structure may be used that is selected from indium oxide, indium gallium oxide, and IGZO, and selected from IAZO, IAGZO, and ITZO (registered trademark).

[0236] <Example of Semiconductor Device Configuration 2>

[0237] Figure 3 shows an example of a configuration of a semiconductor device (100A) that is different from the semiconductor device (100) shown in Figures 1 (A) to 2 (B). Figure 3 is a cross-sectional view along the dotted line A1-A2 in the plan view of the semiconductor device (100) shown in Figure 1 (A).

[0238] The semiconductor device (100A) shown in FIG. 3 is mainly different from the semiconductor device (100) shown in FIG. 1 (A) to FIG. 2 (B) in that the transistor (10_1) includes a conductive layer (114_1) that functions as a second gate electrode (also called a back gate electrode) and an insulating layer (110s1) that functions as a second gate insulating layer (also called a back gate insulating layer), and the insulating layer (110_1) is composed of six layers: an insulating layer (110d1), an insulating layer (110e1), an insulating layer (110f1), an insulating layer (110g1), an insulating layer (110h1), and an insulating layer (110i1).

[0239] In the semiconductor device (100A), the insulating layer (110_1) is composed of six layers: an insulating layer (110d1) on the conductive layer (112a1) and the substrate (102), an insulating layer (110e1) on the insulating layer (110d1), an insulating layer (110f1) on the insulating layer (110e1), an insulating layer (110g1) on the insulating layer (110f1), an insulating layer (110h1) on the insulating layer (110g1), and an insulating layer (110i1) on the insulating layer (110h1). Additionally, a conductive layer (114_1) is provided between the insulating layer (110f1) and the insulating layer (110g1). The conductive layer (112a1), insulating layer (110d1), insulating layer (110e1), insulating layer (110f1), conductive layer (114_1), insulating layer (110g1), insulating layer (110h1), insulating layer (110i1), and insulating layer (112b1) include regions that overlap each other.

[0240] In a semiconductor device (100A), an opening (143) extending to a conductive layer (112a1) is provided in an insulating layer (110d1), an insulating layer (110e1), an insulating layer (110f1), a conductive layer (114_1), an insulating layer (110g1), an insulating layer (110h1), an insulating layer (110i1), and an insulating layer (112b1).

[0241] An insulating layer (110s1) is provided in contact with the upper surface of the conductive layer (112a1), the side surface of the insulating layer (110d1), the side surface of the insulating layer (110e1), the side surface of the insulating layer (110f1), the side surface of the conductive layer (114_1), the side surface of the insulating layer (110g1), the side surface of the insulating layer (110h1), the side surface of the insulating layer (110i1), and the side surface of the conductive layer (112b1) within the opening (143). The insulating layer (110s1) has a curved shape at its upper end.

[0242] A semiconductor layer (108_1) is provided in contact with the upper surface of the conductive layer (112a1) in the opening (143), the side of the insulating layer (110s1) in the opening (143), the curved portion of the insulating layer (110s1), and the upper surface of the conductive layer (112b1).

[0243] In the transistor (10_1) included in the semiconductor device (100A), one side within the opening (143) of the semiconductor layer (108_1) faces the conductive layer (104_1) through an insulating layer (106_1), and the other side within the opening (143) of the semiconductor layer (108_1) faces the conductive layer (114_1) through an insulating layer (110s1). As described above, the conductive layer (114_1) functions as the second gate electrode of the transistor (10_1). Additionally, the insulating layer (110s1) functions as the second gate insulating layer of the transistor (10_1).

[0244] A transistor (10_1) included in a semiconductor device (100A) includes two gate electrodes provided to accommodate a semiconductor layer (108_1), thereby allowing a gate electric field to be applied to carriers in a channel-forming region from both sides of the semiconductor layer (108_1). Thus, a higher on-current can be realized than that of a transistor (10_1) included in a semiconductor device (100) that includes only one gate electrode (conductive layer (104_1)). A lower off-current can also be realized. Additionally, the threshold voltage can be shifted to the normal off side. Furthermore, the saturation characteristics of the current flowing when operating in the saturation region can be improved (i.e., the magnitude of the drain current hardly changes with increasing drain voltage).

[0245] The insulating layer (110s1), which functions as the second gate insulating layer of the transistor (10_1), is preferably formed from a material that contains oxygen and releases oxygen through heat treatment or the like. For example, the insulating layer (110s1) may use a material that can be used for the insulating layer (110b1) and insulating layer (110b2) described above. Accordingly, for example, when a metal oxide is used in the semiconductor layer (108_1), the oxygen contained in the insulating layer (110s1) can be supplied to the metal oxide. As a result, the oxygen deficiency within the metal oxide can be restored, thereby improving the electrical characteristics and reliability of the transistor (10_1).

[0246] The conductive layer (114_1) functioning as the second gate electrode of the transistor (10_1) may use a material that can be used for the conductive layer (104_1) and the conductive layer (104_2) described above.

[0247] Among the six insulating layers constituting the insulating layer (110_1), the insulating layer (110d1), insulating layer (110f1), insulating layer (110g1), and insulating layer (110i1) may use materials that can be used for the insulating layer (110a1), insulating layer (110c1), insulating layer (110a2), and insulating layer (110c2) described above. Additionally, the insulating film (110e1) and insulating film (110h1) may use materials that can be used for the insulating layer (110b1) and insulating layer (110b2) described above.

[0248] Accordingly, for example, when a metal oxide is used in the semiconductor layer (108_1), oxygen contained in the insulating layer (110e1) and the insulating layer (110h1) can be supplied to the semiconductor layer (108_1) through the insulating layer (110s1). Since oxygen deficiency within the metal oxide can be restored, the electrical characteristics and reliability of the transistor (10_1) can be improved. In addition, the diffusion of oxygen contained in the insulating layer (110e1) to the conductive layer (112a1) through the insulating layer (110d1) and to the conductive layer (114_1) through the insulating layer (110f1) can be suppressed, respectively. Similarly, the diffusion of oxygen contained in the insulating layer (110h1) to the conductive layer (114_1) through the insulating layer (110g1) and to the conductive layer (112b1) through the insulating layer (110i1) can be suppressed, respectively.

[0249] For configurations of the semiconductor device (100A) other than those mentioned above, you may refer to the description of the semiconductor device (100).

[0250] <Example of Semiconductor Device Configuration 3>

[0251] FIG. 4 shows an example of a configuration of a semiconductor device (100B) that is different from the configuration of the semiconductor device (100A) shown in FIG. 3. FIG. 4 is a cross-sectional view along the dotted line A1-A2 in the plan view of the semiconductor device (100) shown in (A) of FIG. 1.

[0252] The semiconductor device (100B) shown in FIG. 4 is mainly different from the semiconductor device (100A) shown in FIG. 3 in that the transistor (10_1) includes an insulating layer (116) that covers a conductive layer (114_1) and functions as a barrier against oxygen and hydrogen, and the insulating layer (110_1) is composed of three layers: an insulating layer (110a1), an insulating layer (110b1), and an insulating layer (110c1). In addition, the shape of the insulating layer (110a1) is different from the semiconductor device (100) shown in FIG. 1 (B).

[0253] The transistor (10_1) included in the semiconductor device (100B) has a shape in which the end at the opening (143) side of the insulating layer (110a1) protrudes more than the side at the opening (143) side of the insulating layer (110b1), the side at the opening (143) side of the insulating layer (110c1), and the side at the opening (143) side of the conductive layer (112b1).

[0254] Additionally, a conductive layer (114_1) is provided on the insulating layer (110a1) so as to overlap with the insulating layer (110b1), the insulating layer (110c1), and the conductive layer (112b1). An insulating layer (116) is provided in contact with the upper surface and side surface of the conductive layer (114_1). An insulating layer (110s1) is provided in contact with the upper surface of the insulating layer (110a1) within the opening (143), the side surface of the insulating layer (116) on the side of the opening (143), the side surface of the insulating layer (110b1) on the side of the opening (143), the side surface of the insulating layer (110c1) on the side of the opening (143), and the side surface of the conductive layer (112b1) on the side of the opening (143). The insulating layer (110s1) has a shape with a curved upper portion.

[0255] Unlike the transistor (10_1) included in the semiconductor device (100A), the transistor (10_1) included in the semiconductor device (100B) has a configuration in which the insulating layer (110s1) does not come into contact with the conductive layer (112a1). Therefore, it is possible to suppress problems such as the reduction of the on-current of the transistor (10_1) caused by the oxygen contained in the insulating layer (110s1) diffusing toward the conductive layer (112a1) and the conductive layer (112a1) becoming oxidized and high-resistance.

[0256] A semiconductor layer (108_1) is provided in contact with the upper surface of the conductive layer (112a1) in the opening (143), the side of the insulating layer (110a1) on the side of the opening (143), the side of the insulating layer (110s1) on the side of the opening (143), the curved portion of the insulating layer (110s1), and the upper surface of the conductive layer (112b1).

[0257] In the transistor (10_1) included in the semiconductor device (100B), one side within the opening (143) of the semiconductor layer (108_1) faces the conductive layer (104_1) through an insulating layer (106_1), and the other side within the opening (143) of the semiconductor layer (108_1) faces the conductive layer (114_1) through an insulating layer (110s1) and an insulating layer (116). As described above, the conductive layer (114_1) functions as a second gate electrode. Additionally, the insulating layer (110s1) functions as a second gate insulating layer. The insulating layer (116) in the region sandwiched between the conductive layer (114_1) and the insulating layer (110s1) can also function as a second gate insulating layer.

[0258] It is preferable that the insulating layer (116) be formed from a material that functions as a barrier against oxygen and hydrogen. For example, the insulating layer (116) may use a material that can be used for the insulating layer (110a1), insulating layer (110c1), insulating layer (110a2), and insulating layer (110c2) described above. As shown in FIG. 4, by covering the upper and side surfaces of the conductive layer (114_1) with the insulating layer (116) formed from the above material, problems such as oxygen contained in, for example, the insulating layer (110s1) and insulating layer (110b1) diffusing into the conductive layer (114_1) and causing a decrease in the conductivity of the conductive layer (114_1) can be suppressed.

[0259] Here, the insulating layer (116) may be formed by a film deposition method such as plasma CVD or sputtering, but, for example, the surface of the conductive layer (114_1) may be oxidized by plasma treatment performed in an oxygen atmosphere to form an insulating layer (116) covering the upper and side surfaces of the conductive layer (114_1). In this case, since an insulating layer (116) having the same function as the insulating layer (110a1) and the insulating layer (110c1) can be formed without using a film deposition method such as plasma CVD or sputtering, the number of times the above film deposition method is applied can be reduced, and thus productivity can be increased. For example, productivity can be increased compared to a semiconductor device (100A) that includes six insulating layers constituting the insulating layer (110_1). In addition, in this case, it is preferable to use a material that is easily oxidized by plasma treatment in an oxygen atmosphere for the conductive layer (114_1). For example, it is preferable to use aluminum. In addition, in this case, the insulating layer (116) becomes an insulating layer made of an oxide of an element included in the conductive layer (114_1). For example, if aluminum is used as the material for the conductive layer (114_1), the insulating layer (116) becomes aluminum oxide.

[0260] For configurations of the semiconductor device (100B) other than those mentioned above, you may refer to the description of the semiconductor device (100) and the semiconductor device (100A).

[0261] In addition, the semiconductor device (100B) and the semiconductor device (100A) shown in <Configuration Example 2 of a semiconductor device> both show a configuration in which the transistor (10_1) includes two gate electrodes and the transistor (10_2) includes only one gate electrode, but are not limited thereto. For example, the configuration may be such that the transistor (10_1) includes only one gate electrode and the transistor (10_2) includes two gate electrodes.

[0262] <Example of Semiconductor Device Configuration 4>

[0263] Figure 5 shows an example of a configuration of a semiconductor device (100C) that is different from the semiconductor device (100) shown in Figures 1 (A) to 2 (B). Figure 5 is a cross-sectional view along the dotted line A1-A2 in the plan view of the semiconductor device (100) shown in Figure 1 (A).

[0264] The semiconductor device (100C) shown in FIG. 5 is mainly different from the semiconductor device (100) shown in FIG. 1 (A) to FIG. 2 (B) in that it includes a conductive layer (114_2) instead of a conductive layer (104_2) as a conductive layer functioning as a gate electrode of a transistor (10_2), includes an insulating layer (110s2) functioning as a gate insulating layer, and the insulating layer (110_2) is composed of six layers: an insulating layer (110d2), an insulating layer (110e2), an insulating layer (110f2), an insulating layer (110g2), an insulating layer (110h2), and an insulating layer (110i2).

[0265] In the semiconductor device (100C), the insulating layer (110_2) is composed of six layers: an insulating layer (110d2) on top of the insulating layer (193) and insulating layer (194), an insulating layer (110e2) on top of the insulating layer (110d2), an insulating layer (110f2) on top of the insulating layer (110e2), an insulating layer (110g2) on top of the insulating layer (110f2), an insulating layer (110h2) on top of the insulating layer (110g2), and an insulating layer (110i2) on top of the insulating layer (110h2). Additionally, a conductive layer (114_2) is provided between the insulating layer (110f2) and the insulating layer (110g2). The conductive layer (112a2), insulating layer (110d2), insulating layer (110e2), insulating layer (110f2), conductive layer (114_2), insulating layer (110g2), insulating layer (110h2), insulating layer (110i2), and insulating layer (112b2) include regions that overlap each other.

[0266] In a semiconductor device (100C), an opening (144) extending to a conductive layer (112a2) is provided in an insulating layer (193), an insulating layer (110d2), an insulating layer (110e2), an insulating layer (110f2), a conductive layer (114_2), an insulating layer (110g2), an insulating layer (110h2), an insulating layer (110i2), and an insulating layer (112b2).

[0267] An insulating layer (110s2) is provided in contact with the upper surface of the conductive layer (112a2), the side surface of the insulating layer (193), the side surface of the insulating layer (110d2), the side surface of the insulating layer (110e2), the side surface of the insulating layer (110f2), the side surface of the conductive layer (114_2), the side surface of the insulating layer (110g2), the side surface of the insulating layer (110h2), the side surface of the insulating layer (110i2), and the side surface of the conductive layer (112b2) within the opening (144). The insulating layer (110s2) has a curved shape at its upper end.

[0268] A semiconductor layer (108_2) is provided in contact with the upper surface of the conductive layer (112a2) in the opening (144), the side of the insulating layer (110s2) in the opening (144), the curved portion of the insulating layer (110s2), and the upper surface of the conductive layer (112b2).

[0269] In the transistor (10_2) included in the semiconductor device (100C), the semiconductor layer (108_2) faces the conductive layer (114_2) through an insulating layer (110s2) within the opening (144).

[0270] For materials that can be used for the insulating layer (110s2) and the conductive layer (114_2), reference may be made to the descriptions regarding the insulating layer (110s1) and the conductive layer (114_1) in the semiconductor device (100A) of <Example of the configuration of a semiconductor device 2>, respectively. Additionally, for materials that can be used for the insulating layer (110d2), insulating layer (110e2), insulating layer (110f2), insulating layer (110g2), insulating layer (110h2), and insulating layer (110i2), reference may be made to the descriptions regarding the insulating layer (110d1), insulating layer (110e1), insulating layer (110f1), insulating layer (110g1), insulating layer (110h1), and insulating layer (110i1) in the semiconductor device (100A) of <Example of the configuration of a semiconductor device 2>, respectively.

[0271] Here, the semiconductor device (100) shown in (A) of FIG. 1 to (B) of FIG. 2 has a configuration in which the semiconductor layer (108_2) of the transistor (10_2) surrounds the gate electrode (conductive layer (104_2)) when viewed from a planar view, whereas the semiconductor device (100C) shown in FIG. 5 has a configuration in which the gate electrode (conductive layer (114_2)) of the transistor (10_2) surrounds the semiconductor layer (108_2) when viewed from a planar view.

[0272] In the semiconductor device (100C) containing the transistor (10_2), the side on which the channel of the semiconductor layer (108_2) is formed is the side facing the conductive layer (114_2). Therefore, the side can be suppressed from being directly affected by film formation damage, etc., of the layer (e.g., insulating layer (106_2)) formed on the semiconductor layer (108_2). Thus, there may be cases where the semiconductor layer (108_2) (especially the channel formation region) has fewer defects than the transistor (10_2) containing the semiconductor device (100). Meanwhile, in the semiconductor device (100), the gate electrode (conductive layer (104_2)) of the transistor (10_2) is provided to cover the opening (144), so that the step or irregularity of the transistor (10_2) can be made smaller than that of the transistor (10_2) containing the semiconductor device (100C), which is preferable.

[0273] For configurations of the semiconductor device (100C) other than those mentioned above, you may refer to the description of the semiconductor device (100).

[0274] <Example of Semiconductor Device Configuration 5>

[0275] Figure 6 shows an example of a configuration of a semiconductor device (100D) that is different from the semiconductor device (100) shown in Figures 1 (A) to 2 (B). Figure 6 is a cross-sectional view along the dotted line A1-A2 in the plan view of the semiconductor device (100) shown in Figure 1 (A).

[0276] The semiconductor device (100D) shown in FIG. 6 is mainly different from the semiconductor device (100) shown in FIG. 1 (A) to FIG. 2 (B) in that both transistor (10_1) and transistor (10_2) include a second gate electrode.

[0277] In the semiconductor device (100D), regarding the transistor (10_1), one may refer to the description of the transistor (10_1) included in the semiconductor device (100A) shown in <Example of the configuration of the semiconductor device 2>.

[0278] In the semiconductor device (100D), the transistor (10_2) may be configured to have a conductive layer (104_2) added to the transistor (10_2) included in the semiconductor device (100C) shown in <Configuration Example 4 of a semiconductor device>. The conductive layer (104_2) is provided to include an area that is in contact with the upper surface of the insulating layer (106_2) and overlaps with the opening (144).

[0279] In the transistor (10_2) included in the semiconductor device (100D), one side within the opening (144) of the semiconductor layer (108_2) faces the conductive layer (104_2) through an insulating layer (106_2), and the other side within the opening (144) of the semiconductor layer (108_2) faces the conductive layer (114_2) through an insulating layer (110s2).

[0280] In the transistor (10_2), the conductive layer (104_2) functions as a gate electrode, and a portion of the insulating layer (106_2) functions as a gate insulating layer. Additionally, the conductive layer (114_2) functions as a second gate electrode, and a portion of the insulating layer (110s2) functions as a second gate insulating layer. For the configuration other than the conductive layer (104_2) in the transistor (10_2), one may refer to the description of the transistor (10_2) included in the semiconductor device (100C) shown in <Configuration Example 4 of a Semiconductor Device>.

[0281] In the semiconductor device (100D), since both the transistor (10_1) and the transistor (10_2) have a configuration including two gate electrodes, a higher overall on-current can be realized compared to a semiconductor device in which either one or both transistors have a configuration including one gate electrode. Additionally, a lower overall off-current can be realized. Furthermore, the threshold voltage of each transistor can be shifted to the normal off side. Additionally, the saturation characteristics of the current flowing when each transistor operates in the saturation region can be improved.

[0282] For configurations of the semiconductor device (100D) other than those mentioned above, you may refer to the description of the semiconductor device (100).

[0283] <Example of Semiconductor Device Configuration 6>

[0284] Examples of configurations of a semiconductor device (200) that are different from the semiconductor device (100) shown in FIG. 1 (A) to FIG. 2 (B) are shown in FIG. 7 (A) and (B). FIG. 7 (A) is a cross-sectional view along the dotted line A1-A2 in the plan view of the semiconductor device (100) shown in FIG. 1 (A). FIG. 7 (B) is a circuit diagram explaining the configuration of the semiconductor device (200).

[0285] In the semiconductor device (200), the configuration of the transistor (10_1) and the transistor (10_2) is the same as that of the transistor (10_1) and the transistor (10_2) included in the semiconductor device (100), but the method of connecting the two transistors is different from that of the semiconductor device (100).

[0286] Specifically, the semiconductor device (100) has a configuration in which the gate electrode (conductive layer (104_1)) of the transistor (10_1) and one of the source electrode and drain electrode (conductive layer (112a2)) of the transistor (10_2) are connected, as shown in (B) of FIG. 2.

[0287] Meanwhile, as shown in (B) of FIG. 7, the semiconductor device (200) has a configuration in which one of the source electrodes and drain electrodes of the transistor (10_1) and transistor (10_2) (conductive layer (112a1) and conductive layer (112a2)) are connected to one another of the source electrodes and drain electrodes (conductive layer (112b1) and conductive layer (112b2)) and the gate electrodes (conductive layer (104_1) and conductive layer (104_2)) are connected to one another. That is, the transistor (10_1) and transistor (10_2) have a configuration in which they are connected in parallel.

[0288] Therefore, in the cross-sectional view along the dotted line A1-A2 of the semiconductor device (200) (Fig. 7 (A)), the insulating layer (193) is provided to be sandwiched between the conductive layer (104_1) and the conductive layer (112a2), and the conductive layer (104_1) and the conductive layer (112a2) do not come into contact with each other. In the semiconductor device (200), the insulating layer (193) is provided in contact with the upper surface of the insulating layer (192), the side surface of the conductive layer (104_1), and the upper surface of the insulating layer (106_1), and the conductive layer (112a2) is provided in contact with the upper surface of the insulating layer (193).

[0289] As such, a semiconductor device of one form of the present invention may be configured to stack two transistors having a different connection relationship with the semiconductor device (100). For example, it may be configured to have a stacked structure in which a transistor (10_1) and a transistor (10_2) connected in parallel are stacked, as in the semiconductor device (200) described above. By doing so, a semiconductor device with a high on-current can be realized without increasing the area occupied.

[0290] Additionally, FIG. 7 (A) and (B) illustrate a configuration example in which two transistors (transistor (10_1) and transistor (10_2)) are stacked in parallel, but is not limited thereto. A semiconductor device of one embodiment of the present invention may be configured to stack three or more transistors connected in parallel. This is preferable because increasing the number of parallel connections of transistors can increase the on-current of the semiconductor device as a whole.

[0291] For configurations of the semiconductor device (200) other than those mentioned above, you may refer to the description of the semiconductor device (100).

[0292] <Example of Semiconductor Device Configuration 7>

[0293] Examples of configurations of a semiconductor device (300) that are different from the semiconductor device (100) shown in FIG. 1 (A) to FIG. 2 (B) are shown in FIG. 8 (A) and (B). FIG. 8 (A) is a cross-sectional view along the dotted line A1-A2 in the plan view of the semiconductor device (100) shown in FIG. 1 (A). FIG. 8 (B) is a circuit diagram explaining the configuration of the semiconductor device (300).

[0294] In the semiconductor device (300), the configuration of the transistor (10_1) and the transistor (10_2) is the same as that of the transistor (10_1) and the transistor (10_2) included in the semiconductor device (100), but the method of connecting the two transistors is different from that of the semiconductor device (100).

[0295] Specifically, the semiconductor device (100) has a configuration in which the gate electrode (conductive layer (104_1)) of the transistor (10_1) and one of the source electrode and drain electrode (conductive layer (112a2)) of the transistor (10_2) are connected, as shown in (B) of FIG. 2.

[0296] Meanwhile, as shown in (B) of FIG. 8, the semiconductor device (300) has a configuration in which the other side (conductive layer (112b1)) of the source electrode and drain electrode of the transistor (10_1) is connected to one side (conductive layer (112a2)) of the source electrode and drain electrode of the transistor (10_2), and the gate electrode (conductive layer (104_1)) of the transistor (10_1) is connected to the gate electrode (conductive layer (104_2)) of the transistor (10_2). That is, the transistor (10_1) and the transistor (10_2) have a configuration in which they are connected in series.

[0297] Therefore, in the cross-sectional view along the dotted line A1-A2 of the semiconductor device (300) (Fig. 8 (A)), the insulating layer (193) is provided to be sandwiched between the conductive layer (104_1) and the conductive layer (112a2), and the conductive layer (104_1) and the conductive layer (112a2) do not come into contact with each other. In the semiconductor device (300), the insulating layer (193) is provided in contact with the upper surface of the insulating layer (192), the side surface of the conductive layer (104_1), and the upper surface of the insulating layer (106_1), and the conductive layer (112a2) is provided in contact with the upper surface of the insulating layer (193).

[0298] As such, a semiconductor device of one form of the present invention may be configured to stack two transistors having a different connection relationship with the semiconductor device (100). For example, it may be configured to have a stacked structure in which a transistor (10_1) and a transistor (10_2) connected in series are stacked, as in the semiconductor device (300) described above. By doing so, a semiconductor device with low off-current can be realized without increasing the area occupied.

[0299] In addition, two transistors connected in series can be regarded as a single transistor with a large channel length. Therefore, by connecting two transistors in series, the source-drain breakdown voltage can be increased compared to a single transistor (10_1) or a single transistor (10_2).

[0300] Additionally, FIG. 8 (A) and (B) illustrate a configuration example in which two series-connected transistors (transistor (10_1) and transistor (10_2)) are stacked, but is not limited thereto. A semiconductor device of one embodiment of the present invention may be configured to stack three or more series-connected transistors. It is preferable to increase the number of series-connected transistors because it can lower the off-current of the semiconductor device as a whole. It is also preferable to consider the semiconductor device as a single transistor because it can increase the voltage withstand between the source and the drain.

[0301] For configurations of the semiconductor device (300) other than those mentioned above, you may refer to the description of the semiconductor device (100).

[0302] Example of a semiconductor device manufacturing method

[0303] Hereinafter, an example of a method for manufacturing a semiconductor device of one form of the present invention will be described with reference to the drawings. Here, the semiconductor device (100) shown in FIG. 1 (A) to FIG. 2 (B) will be described as an example.

[0304] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), etc.

[0305] Sputtering methods include RF sputtering, which uses a high-frequency power source for sputtering; DC sputtering, which uses a direct current power source; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. It is preferable to use RF sputtering for film deposition using insulating targets. DC sputtering is mainly used when film deposition using conductive targets. In addition, DC sputtering allows for the formation of insulating films not only through the formation of conductive films but also through reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0306] CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCVD), which utilizes heat; and photo CVD, which utilizes light. Additionally, depending on the source gas used, they can be classified into metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0307] High-quality films can be obtained at relatively low temperatures using the plasma CVD method. Furthermore, since the thermal CVD method does not use plasma, it is a film deposition method that minimizes plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitive elements, etc.) included in semiconductor devices may become charged by receiving charges from the plasma. In such cases, the accumulated charge can cause the wiring, electrodes, or components within the semiconductor device to be destroyed. On the other hand, in the case of the thermal CVD method, which does not use plasma, such plasma damage does not occur, thereby increasing the yield of semiconductor devices. Additionally, because plasma damage does not occur during film deposition in the thermal CVD method, films with fewer defects can be obtained.

[0308] As an ALD method, thermal ALD, which carries out the reaction between the precursor and the reactant using only thermal energy, and PEALD, which uses a plasma-excited reactant, can be used.

[0309] CVD and ALD methods differ from sputtering methods, where particles emitted from a target are deposited. Therefore, they are film deposition methods that are less affected by the shape of the workpiece and offer excellent step coverage. In particular, because ALD possesses excellent step coverage and thickness uniformity, it is suitable for applications such as coating the surface of an opening with a high aspect ratio. However, since the deposition rate of ALD is relatively slow, it is sometimes advisable to use it in combination with other methods, such as CVD, which have a faster deposition rate.

[0310] Furthermore, the CVD method can form films with arbitrary compositions by varying the flow rate ratio of the source gas. For example, the CVD method can deposit films with continuously changing compositions by varying the flow rate ratio of the source gas during deposition. Since time required for transport or pressure adjustment is eliminated when deposition is performed while varying the flow rate ratio of the source gas, the deposition time can be shortened compared to using multiple deposition chambers. Consequently, it is possible to increase the productivity of semiconductor devices.

[0311] In addition, the ALD method can form a film of any composition by simultaneously introducing multiple types of different precursors. Alternatively, when introducing multiple types of different precursors, a film of any composition can be formed by controlling the number of cycles for each precursor.

[0312] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, knife coating, etc.

[0313] When processing thin films constituting semiconductor devices, methods such as photolithography may be used. In addition, thin films may be processed using methods such as nanoimprinting, sandblasting, or lift-off. Furthermore, island-shaped thin films may be directly formed using a film deposition method that utilizes a shielding mask, such as a metal mask.

[0314] There are two representative methods of photolithography. One is a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is removed. The other is a method in which a thin film having photosensitivity is formed, and then exposure and development are performed to process the thin film into a desired shape.

[0315] In photolithography, light used for exposure may include, for example, i-lines (wavelength 365 nm), g-lines (wavelength 436 nm), h-lines (wavelength 405 nm), or a mixture thereof. In addition, ultraviolet light, KrF laser light, or ArF laser light may be used. Furthermore, exposure may be performed using immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as light for exposure. Furthermore, an electron beam may be used instead of light for exposure. Using EUV light, X-rays, or an electron beam is preferable because it allows for very fine processing. Additionally, when exposure is performed by scanning a beam such as an electron beam, a photomask is unnecessary.

[0316] For etching thin films, for example, dry etching, wet etching, or sandblasting methods can be used.

[0317] For the planarization treatment of thin films, polishing methods such as CMP can be suitably used. Additionally, the reflow method, which involves performing a heat treatment on the conductive layer to induce fluidization, can be suitably used. Furthermore, a combination of the reflow method and the CMP method may also be performed.

[0318] In addition, a process may be used to form a film with a flat upper surface by forming a planarization film on the surface of a film with irregularities and performing highly anisotropic etching (e.g., dry etching) on ​​the planarization film, or a process may be used to flatten the entire upper surface by forming a planarization film and a photoresist in this order on the surface of a film with irregularities and performing highly anisotropic etching on the planarization film and the photoresist to fill only the planarization film in the concave areas (these processes are sometimes referred to as etch-back processes). When performing an etch-back process, high-temperature heating (e.g., about 800°C) such as the reflow method is not required, so there is no need to worry about damage to the device during fabrication caused by the heating process. Furthermore, the etch-back process is desirable because it can be applied to devices on large substrates that are difficult to process with the CMP method due to effects such as warping.

[0319] In addition, dry etching and plasma treatment may be used as thin film planarization treatments. Furthermore, polishing, dry etching, and plasma treatment may be performed multiple times, or they may be performed in combination. Also, when performing them in combination, the process sequence is not particularly limited and can be set appropriately according to the surface roughness of the workpiece.

[0320] To process a thin film with high precision so that its thickness reaches a desired level, for example, the CMP method is used. In this case, polishing is first performed at a constant processing speed until a portion of the upper surface of the thin film is exposed. Subsequently, polishing is performed under conditions with a slower processing speed until the thin film reaches the desired thickness, thereby enabling high-precision processing.

[0321] Methods for detecting the end point of polishing include an optical method of irradiating light onto the surface of the workpiece and detecting a change in the reflected light, a physical method of detecting a change in polishing resistance received by the processing device from the workpiece, and a method of irradiating magnetic field lines onto the workpiece and using a change in magnetic field lines caused by eddy currents.

[0322] After the upper surface of the thin film is exposed, the thickness of the thin film can be controlled with high precision by performing a polishing process under conditions of slow processing speed while monitoring the thickness of the thin film using an optical method such as a laser interferometer. Additionally, if necessary, the polishing process may be performed multiple times until the thin film reaches a desired thickness.

[0323] Each of the drawings in FIG. 9 (A) to FIG. 31 (C) is a drawing that explains the method of manufacturing a semiconductor device (100). (A) of each drawing is a plan view corresponding to (A) of FIG. 1. (B) of each drawing is a cross-sectional view along the dotted line A1-A2 of the plan view shown in FIG. 1 (A). (C) of each drawing is a cross-sectional view along the dotted line B1-B2 of the plan view shown in FIG. 1 (A).

[0324] First, a conductive film that becomes a conductive layer (112a1) is formed on a substrate (102), and the conductive layer (112a1) is formed by removing a portion of the conductive film ((A) to (C) of FIG. 9). For example, a sputtering method may be used to form the conductive film. In addition, one or both of a wet etching method and a dry etching method may be used to process the conductive film.

[0325] Next, insulating films (110a1f), insulating films (110b1f), and insulating films (110c1f) are formed in this order on the conductive layer (112a1) and on the substrate (102).

[0326] In the insulating film (110a1f), a material that can be used for the insulating layer (110a1) described above can be appropriately used.

[0327] As an insulating film (110a1f), for example, silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide can be suitably used.

[0328] Specifically, silicon nitride can be deposited as an insulating film (110a1f) using, for example, a sputtering method. Alternatively, silicon nitride can be deposited using, for example, a PEALD method. Alternatively, aluminum oxide can be deposited using, for example, a sputtering method.

[0329] In addition, a stacked configuration of aluminum oxide and silicon nitride can be used, for example. For instance, aluminum oxide deposited using the sputtering method and silicon nitride deposited using the PEALD method can be stacked and used.

[0330] In the insulating film (110b1f), a material that can be used for the insulating layer (110b1) described above can be appropriately used.

[0331] As an insulating film (110b1f), for example, silicon oxide, silicon nitride, etc. can be suitably used.

[0332] Specifically, silicon oxide can be deposited as an insulating film (110b1f) using, for example, a sputtering method. Or, silicon oxide can be deposited using, for example, a PECVD method. Or, silicon nitride can be deposited using, for example, a PECVD method.

[0333] In addition, for example, silicon oxide deposited using the sputtering method and silicon oxide or silicon nitride deposited using the PECVD method can be stacked and used.

[0334] After forming the insulating film (110b1f), a heat treatment may be performed. By performing the heat treatment, water and hydrogen can be removed from the surface and film of the insulating film (110b1f).

[0335] The temperature of the heat treatment is preferably 150°C or higher and below the deformation point of the substrate, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, and more preferably 350°C or higher and 400°C or lower. The heat treatment may be performed in an atmosphere containing one or more of an inert gas, nitrogen, and oxygen. Clean dry air (CDA) may be used as an atmosphere containing nitrogen or oxygen. In addition, it is preferable that the content of hydrogen, water, etc. in the atmosphere be as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower. By using an atmosphere with as low a content of hydrogen, water, etc. as possible, it is possible to prevent hydrogen, water, etc. from entering the insulating film (110b1f) as much as possible. For heat treatment, for example, an oven or a Rapid Thermal Annealing (RTA) device can be used. By using an RTA device, the heat treatment time can be reduced.

[0336] After performing the above heat treatment, a process of supplying oxygen to the insulating film (110b1f) may be performed. For example, oxygen may be supplied to the insulating film (110b1f) by forming a metal oxide layer on the insulating film (110b1f) after forming the insulating film (110b1f). Additionally, a heat treatment may be performed after forming the metal oxide layer. By performing a heat treatment after forming the metal oxide layer, oxygen can be effectively supplied from the metal oxide layer to the insulating film (110b1f), thereby allowing oxygen to be contained within the insulating film (110b1f). As the oxygen supplied to the insulating film (110b1f) is supplied to the semiconductor layer (108_1) in a later process, the oxygen deficiency (V) within the semiconductor layer (108_1) O ) and V O H can be reduced.

[0337] After forming the metal oxide layer or after performing the heat treatment described above, oxygen may be further supplied to the insulating film (110b1f) through the metal oxide layer. As a method of supplying oxygen, for example, ion implantation, ion doping, plasma infiltration ion implantation, or plasma treatment may be used. In the plasma treatment, a device that plasmaizes oxygen gas with high-frequency power may be suitably used. Examples of devices that plasmaize gas with high-frequency power include plasma etching devices and plasma ashing devices.

[0338] The metal oxide layer may be an insulating layer or a conductive layer. For example, the metal oxide layer may use aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO).

[0339] It is preferable to use an oxide material containing one or more elements identical to those of the semiconductor layer (108_1) for the metal oxide layer. In particular, it is preferable to use an oxide semiconductor material that can be applied to the semiconductor layer (108_1). By doing so, the manufacturing cost can be reduced because the metal oxide layer can be formed using a sputtering target similar to that of the semiconductor layer (108_1).

[0340] When a metal oxide material containing indium and gallium is used in the metal oxide layer, a material with a higher gallium composition (content) than that of the semiconductor layer (108_1) can be used. By using a material with a higher gallium composition (content) in the metal oxide layer, the barrier properties against oxygen can be further enhanced. This is desirable because it can suppress the escape of oxygen contained in the insulating film (110b1f) to the outside.

[0341] It is preferable to form the metal oxide layer in an atmosphere containing oxygen, for example. In particular, it is preferable to form it by sputtering in an atmosphere containing oxygen. By doing so, oxygen can be suitably supplied to the insulating film (110b1f) when forming the metal oxide layer.

[0342] Next, the metal oxide layer is removed. For example, a wet etching method can be suitably used to remove the metal oxide layer.

[0343] The method of supplying oxygen to the insulating film (110b1f) is not limited to that described above. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc., may be supplied to the insulating film (110b1f) by ion doping, ion implantation, plasma treatment, etc. Additionally, after forming a film that inhibits the escape of oxygen on the insulating film (110b1f), oxygen may be supplied to the insulating film (110b1f) through said film. It is preferable that said film be removed after oxygen is supplied. As the aforementioned film that inhibits the escape of oxygen, a conductive film or semiconductor film comprising one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten may be used.

[0344] In the insulating film (110c1f), a material that can be used for the insulating layer (110c1) described above can be appropriately used.

[0345] For materials and film formation methods that can be used for the insulating film (110c1f), one may refer to the description regarding materials and film formation methods that can be used for the insulating film (110a1f) described above.

[0346] Next, a conductive film (112b1f) is formed on the insulating film (110c1f) (Fig. 10 (A) to (C)). For the conductive film (112b1f), a material suitable for use in the conductive layer (112b1) described above can be appropriately used. In addition, for example, a sputtering method can be used to form the conductive film (112b1f).

[0347] Next, a conductive layer (112b1e) is formed by removing a portion of the conductive film (112b1f) (Fig. 11 (A) to (C)). For forming the conductive layer (112b1e), either or both of the wet etching method and the dry etching method may be used. The conductive layer (112b1e) is formed to include an area that overlaps with the conductive layer (112a1).

[0348] Next, a process is performed to remove a portion of each of the conductive layer (112b1e), insulating film (110c1f), insulating film (110b1f), and insulating film (110a1f) to form an opening (143) extending to the conductive layer (112a1). For example, a dry etching method may be suitably used for the above process. By the above process, the conductive layer (112b1), insulating layer (110c1), insulating layer (110b1), and insulating layer (110a1), each containing an opening, are formed ((A) to (C) of FIG. 12).

[0349] Next, a semiconductor film is formed to become a semiconductor layer (108_1) by contacting the upper surface of the conductive layer (112a1) within the opening (143), the side surface of the insulating layer (110_1) (insulating layer (110a1), insulating layer (110b1), and insulating layer (110c1)) within the opening (143), the side surface of the conductive layer (112b1) within the opening (143), and the upper surface of the conductive layer (112b1). After that, a portion of the semiconductor film is removed by etching to form the semiconductor layer (108_1) (Fig. 13 (A) to (C)). The semiconductor layer (108_1) is provided to include an area that overlaps with the opening (143). Additionally, the semiconductor layer (108_1) is provided to include an area where the end contacts the conductive layer (112b1).

[0350] For the semiconductor film that becomes the semiconductor layer (108_1), a material that can be used for the semiconductor layer (108_1) described above can be appropriately used.

[0351] For example, a sputtering method can be used to form the semiconductor film that becomes the conductive layer (108_1). For example, if a metal oxide is used for the semiconductor layer (108_1), it can be formed by a sputtering method using a metal oxide target. It is preferable to use a sputtering method because it allows for the relatively easy formation of a film with a low hydrogen content.

[0352] In addition, when using a metal oxide in the semiconductor layer (108_1), it may be formed by the ALD method using a precursor containing a constituent metal element and an oxidizing agent.

[0353] For example, when forming an In-Ga-Zn oxide, three precursors may be used: a precursor containing indium, a precursor containing gallium, and a precursor containing zinc. Alternatively, two precursors may be used: a precursor containing indium and precursors containing gallium and zinc.

[0354] As a precursor containing indium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanediionic acid)indium, cyclopentadienylindium, indium chloride(III), etc. may be used.

[0355] In addition, as a gallium-containing precursor, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium(III), gallium(III)acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanediionic acid)gallium, dimethylchlorogallium, diethylchlorogallium, etc. may be used.

[0356] In addition, as a zinc-containing precursor, dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5-heptanediionic acid) zinc, zinc chloride, etc. can be used.

[0357] For example, ozone, oxygen, water, etc., can be used as oxidizing agents.

[0358] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gas, the time for flowing the source gas, and the order in which the source gas is flowed. Furthermore, by adjusting these factors, it is possible to deposit a film with a continuously changing composition. Additionally, it is possible to continuously deposit films with different compositions.

[0359] It is desirable to use the ALD method to form a semiconductor film that becomes a semiconductor layer (108_1) so that the semiconductor layer (108_1) can be formed with a uniform thickness on the side of the insulating layer (110_1).

[0360] Heat treatment may be performed after forming a semiconductor film that becomes the semiconductor layer (108_1). By heat treatment, water and hydrogen contained in the semiconductor film can be reduced, and oxygen can also be supplied to the semiconductor film from the insulating layer (110_1). Additionally, heat treatment may be performed after processing the semiconductor film.

[0361] When forming the semiconductor layer (108_1), the substrate temperature (stage temperature) is preferably above room temperature (25°C) and below 200°C, and more preferably above room temperature and below 130°C. If the substrate temperature is within the above-described range, warping or deformation of the substrate can be suppressed when using a large-area glass substrate.

[0362] The higher the substrate temperature during the formation of the metal oxide layer, the more crystallinity a metal oxide layer can be formed. Additionally, the higher the oxygen flow ratio, the more crystallinity a metal oxide layer can be formed.

[0363] Next, the semiconductor layer (108_1), the conductive layer (112b1), and the insulating layer (110c1) are covered to form an insulating layer (106_1) ((A) to (C) of FIG. 14). The insulating layer (106_1) includes an area in contact with the upper and side surfaces of the semiconductor layer (108_1), the upper and side surfaces of the conductive layer (112b1), and the upper surface of the insulating layer (110c1).

[0364] The insulating layer (106_1) may appropriately use the material described above.

[0365] For example, the ALD method can be used to form the insulating layer (106_1). It is preferable to use the ALD method because it allows the insulating layer (106_1) to be formed with good coverage over the semiconductor layer (108_1) formed over the opening (143). Additionally, if the semiconductor layer (108_1) can be sufficiently covered, a method other than the ALD method may be used to form the insulating layer (106_1). For example, the PECVD method, sputtering method, etc., may be used. By doing so, the deposition speed of the insulating layer (106_1) can be increased compared to when the ALD method is used, thereby increasing productivity.

[0366] Next, a conductive film (104_1f) is formed on the insulating layer (106_1) (Fig. 15 (A) to (C)). The conductive film (104_1f) may be made of a material suitable for use in the conductive layer (104_1) described above. Additionally, the conductive film (104_1f) may be formed using a sputtering method, CVD method, MBE method, PLD method, ALD method, etc. Here, it is preferable that the conductive film (104_1f) be formed by contacting the insulating layer (106_1) facing the side of the insulating layer (110_1) within the opening (143). Therefore, it is preferable to use a film formation method with good covering or embedding properties for the formation of the conductive film (104_1f), and it is even more preferable to use the CVD method or ALD method.

[0367] Next, an insulating film (192f) is formed on the conductive film (104_1f). The insulating film (192f) may be appropriately made of a material that can be used for the insulating layer (192) described above. The insulating film (192f) is formed to fill the opening (143). Additionally, the insulating film (192f) is formed such that the height of the upper surface is higher than the height of the upper surface of any region of the conductive film (104_1f). For example, when an organic insulating material such as polyimide resin is used as the insulating film (192f), an insulating film (192f) with a substantially flat upper surface can be easily formed by methods such as spin coating.

[0368] Next, light (139) (e.g., visible light or ultraviolet light) is irradiated onto the insulating film (192f) through the mask (136) to sensitize the area of ​​the insulating film (192f) that does not overlap with the mask (136) ((A) to (C) of FIG. 16). Here, if a positive photosensitive resin composition such as polyimide resin is used for the insulating film (192f), light (139) is irradiated through the mask (136) onto the area where the insulating layer (192) is not formed in a later process.

[0369] Next, an insulating layer (192e) is formed by removing the exposed area from the insulating film (192f) by performing development ((A) to (C) of FIG. 17). The insulating layer (192e) is formed in an area that overlaps with the opening (143). In addition, in the area where the insulating film (192f) is removed by development, the upper surface of the conductive film (104_1f) is exposed. Here, when a polyimide resin is used for the insulating film (192f), it is preferable to use an alkaline solution as the developer, and, for example, an aqueous solution of tetramethylammonium hydroxide (TMAH) can be used.

[0370] In addition, after development, a process to remove residue (so-called residue) from the development process may be performed. For example, residue can be removed by performing ashing using oxygen plasma. After each of the development processes described below, a process to remove residue may also be performed.

[0371] Next, an etch-back treatment is performed on the insulating layer (192e). Through this treatment, an insulating layer (192) is formed with a flat upper surface and embedded throughout the opening (143) ((A) to (C) of FIG. 18).

[0372] Additionally, in FIGS. 16 (A) to FIGS. 18 (C), a method of performing an etch-back treatment to form an insulating layer (192) has been described, but is not limited thereto. In one embodiment of the present invention, an insulating layer (192) may be formed without performing an etch-back treatment.

[0373] For example, after forming the conductive film (104_1f) shown in (A) to (C) of FIG. 15, the insulating film (192f) described above is formed on the conductive film (104_1f). However, the insulating film (192f) is formed such that its thickness becomes thinner than in the case where the etch-back treatment described above is assumed to be performed.

[0374] Next, as described above, light (139) is irradiated onto the insulating film (192f) through the mask (136) to sensitize the area of ​​the insulating film (192f) that does not overlap with the mask (136) ((A) to (C) of FIG. 19).

[0375] Next, by performing a development to remove the exposed area from the insulating film (192f), the insulating layer (192) is formed only in the area overlapping with the opening (143), and the upper surface of the conductive film (104_1f) in other areas is exposed ((A) to (C) of FIG. 20). In this way, depending on the film thickness when forming the insulating film (192f), the insulating layer (192) may be formed without performing an etch-back treatment, thereby reducing the number of processes. However, when using this method, a gentle convex shape is likely to be formed on the upper surface of the insulating layer (192), as shown in FIG. 20 (B) and (C). Therefore, in order to further increase the flatness of the upper surface of the insulating layer (192), it may be more desirable to perform the aforementioned etch-back treatment.

[0376] Next, a conductive film (112a2f) is formed on the insulating layer (192) and on the conductive film (104_1f) ((A) to (C) of FIG. 21). The conductive film (112a2f) may be made of a material suitable for use in the conductive layer (112a2) described above. Additionally, for the formation of the conductive film (112a2f), a sputtering method may be used, for example.

[0377] Next, a conductive layer (112a2) and a conductive layer (104_1) are formed by removing a portion of the conductive film (112a2f) and the conductive film (104_1f) ((A) to (C) of FIG. 22). The conductive layer (112a2) and the conductive layer (104_1) are formed to include an area that overlaps with the opening (143). The end of the conductive layer (112a2) and the end of the conductive layer (104_1) are formed to substantially coincide when viewed in a planar view. Additionally, the upper surface of the insulating layer (106_1) is exposed in the area where the conductive film (112a2f) and the conductive film (104_1f) have been removed. It is preferable to use either or both of the wet etching method and the dry etching method for forming the conductive layer (112a2) and the conductive layer (104_1).

[0378] Thus, a transistor (10_1) is formed.

[0379] Next, an insulating film (193f) is formed on the conductive layer (112a2) and on the insulating layer (106_1). The insulating film (193f) is provided in contact with the upper and side surfaces of the conductive layer (112a2), the side surface of the conductive layer (104_1), and the upper surface of the insulating layer (106_1). The insulating film (193f) may be made of a material suitable for use in the insulating layer (193) described above. For example, the ALD method, PECVD method, sputtering method, etc., may be used to form the insulating film (193f).

[0380] Next, an insulating film (194f) is formed on the insulating film (193f) ((A) to (C) of FIG. 23). The insulating film (194f) may be appropriately made of a material that can be used for the insulating layer (194) described above. The insulating film (194f) is formed such that the height of the upper surface is higher than the height of the upper surface of any region of the insulating film (193f). For example, when an organic insulating material such as polyimide resin is used as the insulating film (194f), an insulating film (194f) with a substantially flat upper surface can be easily formed by methods such as spin coating.

[0381] Next, an etch-back process is performed on the insulating film (194f). The etch-back process is performed until the highest region (the region overlapping with the conductive layer (112a2)) is exposed when viewed from the substrate surface of the insulating film (193f). Through this process, an insulating layer (194) is formed with a flat upper surface and a height substantially matching the upper surface of the highest region when viewed from the substrate surface of the insulating film (193f) ((A) to (C) of FIG. 24).

[0382] Additionally, in FIGS. 23 (A) to FIGS. 24 (C), a method of performing an etch-back treatment to form an insulating layer (194) has been described, but is not limited thereto. In one embodiment of the present invention, an insulating layer (194) may be formed without performing an etch-back treatment.

[0383] For example, after forming the insulating film (193f) shown in (A) to (C) of FIG. 23, the insulating film (194f) described above is formed on the insulating film (193f). However, at this time, the thickness of the insulating film (194f) is formed to be thinner than in the case where the etch-back treatment described above is assumed to be performed.

[0384] Next, light (139) is irradiated onto the insulating film (194f) through the mask (138) to sensitize the area of ​​the insulating film (194f) that does not overlap with the mask (138) ((A) to (C) of FIG. 25).

[0385] Next, by performing a development to remove the exposed area from the insulating film (194f), the insulating layer (194) is formed only in the area that does not overlap with the opening (143), and the upper surface of the insulating film (193f) in other areas is exposed ((A) to (C) of FIG. 26). In this way, depending on the film thickness when forming the insulating film (194f), the insulating layer (194) may be formed without performing an etch-back treatment, thereby reducing the number of processes. However, when using this method, a gentle convex shape is likely to be formed on the upper surface of the insulating layer (194), as shown in FIG. 26 (B) and (C). Therefore, in order to further increase the flatness of the upper surface of the insulating layer (194), it may be more desirable to perform the aforementioned etch-back treatment.

[0386] Next, an insulating film (110a2f), an insulating film (110b2f), an insulating film (110c2f), and a conductive film (112b2f) are formed in this order on the insulating layer (194) and on the insulating film (193f) ((A) to (C) of FIG. 27). For materials and formation methods that can be used for the insulating film (110a2f), insulating film (110b2f), insulating film (110c2f), and conductive film (112b2f), reference can be made to the descriptions regarding the insulating film (110a1f), insulating film (110b1f), insulating film (110c1f), and conductive film (112b1f) described above, respectively.

[0387] Next, a conductive layer (112b2e) is formed by removing a portion of the conductive film (112b2f) (Fig. 28 (A) to (C)). For forming the conductive layer (112b2e), either or both of the wet etching method and the dry etching method may be used. The conductive layer (112b2e) is formed to include an area that overlaps with the conductive layer (112a2).

[0388] Next, a process is performed to remove a portion of each of the conductive layer (112b2e), insulating film (110c2f), insulating film (110b2f), insulating film (110a2f), and insulating film (193f) to form an opening (144) extending to the conductive layer (112a2). For example, a dry etching method may be suitably used for the above process. By the above process, the conductive layer (112b2), insulating layer (110c2), insulating layer (110b2), insulating layer (110a2), and insulating layer (193), each including an opening, are formed ((A) to (C) of FIG. 29).

[0389] Next, a semiconductor film is formed to become a semiconductor layer (108_2) by contacting the upper surface of the conductive layer (112a2) within the opening (144), the side of the insulating layer (193) within the opening (144), the side of the insulating layer (110_2) (insulating layer (110a2), insulating layer (110b2), and insulating layer (110c2)) within the opening (144), the side of the conductive layer (112b2) within the opening (144), and the upper surface of the conductive layer (112b2). After that, a portion of the semiconductor film is removed by etching to form the semiconductor layer (108_2) (Fig. 30 (A) to (C)). The semiconductor layer (108_2) is provided to include an area that overlaps with the opening (144). Additionally, the semiconductor layer (108_2) is provided to include an area where the end contacts the conductive layer (112b2).

[0390] For materials and formation methods that can be used for the semiconductor film that becomes the semiconductor layer (108_2), you can refer to the description regarding materials and formation methods that can be used for the semiconductor film that becomes the semiconductor layer (108_1) described above.

[0391] Next, a semiconductor layer (108_2), a conductive layer (112b2), and an insulating layer (110c2) are covered to form an insulating layer (106_2) ((A) to (C) of FIG. 31). The insulating layer (106_2) includes an area in contact with the upper and side surfaces of the semiconductor layer (108_2), the upper and side surfaces of the conductive layer (112b2), and the upper surface of the insulating layer (110c2). For materials and methods of formation that can be used for the insulating film (106_2), one may refer to the descriptions regarding materials and methods of formation that can be used for the insulating layer (106_1) described above.

[0392] Next, a conductive film is formed on the insulating layer (106_2) to form a conductive layer (104_2). For the materials and methods of forming that can be used for the conductive film, refer to the description of the materials and methods of forming that can be used for the conductive film (104_1f) described above.

[0393] Next, a portion of the conductive film that becomes the conductive layer (104_2) is removed to form the conductive layer (104_2). The conductive layer (104_2) is formed to include an area that overlaps with the opening (144). Additionally, in the area where the conductive film that becomes the conductive layer (104_2) is removed, the upper surface of the insulating layer (106_2) is exposed. For forming the conductive layer (104_2), it is preferable to use either or both of the wet etching method and the dry etching method.

[0394] Thus, a transistor (10_2) is formed.

[0395] A semiconductor device (100) can be manufactured through the above-described process ((A) of FIG. 1 to (B) of FIG. 2).

[0396] The present embodiment may be appropriately combined with other embodiments. In addition, where multiple configuration examples are described in one embodiment in this specification, the configuration examples may be appropriately combined.

[0397] (Embodiment 2)

[0398] A semiconductor device of one form of the present invention can be applied, for example, to a scan line driving circuit of a display device. In this embodiment, examples of the configuration of the circuit and parts to which the semiconductor device is applied in the circuit are described.

[0399] FIGS. 32 (A) to (C) illustrates examples of configurations of a driving circuit to which a semiconductor device of one form of the present invention can be applied. The driving circuit may function, for example, as a scan line driving circuit of a display device. FIG. 32 (A) is an example of a sequence circuit. FIG. 32 (B) is an example of a driving circuit configured with the sequence circuit shown in FIG. 32 (A). FIG. 32 (C) is an example of a timing chart of the driving circuit shown in FIG. 32 (B).

[0400] <Example of Driving Circuit Configuration>

[0401] Below, an example of a driving circuit configured by connecting multiple sequence circuits and functioning as a shift register is described. As described above, a semiconductor device of one form of the present invention described in the above embodiment can be applied to the driving circuit.

[0402] Figure 32 (A) is a diagram illustrating the input and output terminals of the sequence circuit (20). The sequence circuit (20) includes input terminals to which signals (LIN), (RIN), (RES), (CLK1), (CLK2), and (CLK3) are input, respectively, and output terminals to which output terminals (SROUT), output terminal (OUTA), and output terminal (OUTB) are output terminals.

[0403] Figure 32 (B) shows an example of the configuration of a driving circuit (30). The driving circuit (30) includes a plurality of sequence circuits (20). Figure 32 (B) shows sequence circuits (20_1) to sequence circuits (20_6). Hereinafter, the sequence circuit located at the nth position on the side close to the input of the driving circuit (30) is designated as sequence circuit (20_n) (where n is an integer greater than or equal to 1).

[0404] In the sequence circuit (20_n), any three of signals (CLK1) to (CLK4) are used as signals (CLK1), (CLK2), and (CLK3). The combination of signals (CLK1) to (CLK4) is the same for every 4 stages. That is, the same signals as signals (CLK1), (CLK2), and (CLK3) are input to the sequence circuit (20_n) and the sequence circuit (20_n+4). For example, in the case of the sequence circuits (20_1) to (20_6) constituting the driving circuit (30) shown in (B) of FIG. 32, the same signals (here, signals (CLK1), (CLK2), and (CLK3)) as signals (CLK1), (CLK2), and (CLK3) are input to the sequence circuit (20_1) and the sequence circuit (20_5). In addition, the same signal (here, signal (CLK2), signal (CLK3), and signal (CLK4)) is input to the sequence circuit (20_2) and the sequence circuit (20_6) as signal (CLK1), signal (CLK2), and signal (CLK3).

[0405] Here, a clock signal can be used as the signal (CLK). The clock signal may suitably be a signal with a duty cycle (the ratio of the period of high-level potential during one cycle of the signal) of 45% or more and 55% or less. More preferably, a signal with a duty cycle of 50% may be used as the clock signal. Furthermore, the duty cycle of the clock signal is not limited to the above and can be appropriately changed according to the driving method.

[0406] Furthermore, in this specification and others, a clock signal refers to a signal in which high and low potentials repeat, and the interval between a rise in potential and the next rise, or between a fall in potential and the next fall, is constant. Additionally, in this specification and others, a pulse signal refers to a signal in which the potential changes over time. Furthermore, a pulse signal includes signals in which the potential changes periodically. For example, a pulse signal includes signals in which the potential changes periodically, such as a square wave, a triangular wave, a sawtooth wave, or a sine wave. Therefore, a clock signal may be considered a form of a pulse signal.

[0407] In the sequence circuit (20_1), the signal (SP) is input as a signal (LIN). Also, in the sequence circuit (20_n) where n is 2 or more, the signal from the output terminal (SROUTn-1) of the sequence circuit (20_n-1) one stage ahead is input as a signal (LIN). Also, in the sequence circuit (20_n), the signal from the output terminal (SROUTn+2) of the sequence circuit (20_n+2) two stages later is input as a signal (RIN).

[0408] Specifically, the sequence circuit (20_1) receives signals (CLK1), (CLK2), (CLK3), (SP), and the signal from the output terminal (SROUT3) of the sequence circuit (20_3), and outputs output signals to the output terminal (SROUT1), output terminal (OUTA1), and output terminal (OUTB1), respectively. Additionally, the sequence circuit (20_2) receives signals (CLK2), (CLK3), (CLK4), the signal from the output terminal (SROUT1) of the sequence circuit (20_1), and the signal from the output terminal (SROUT4) of the sequence circuit (20_4), and outputs output signals to the output terminal (SROUT2), output terminal (OUTA2), and output terminal (OUTB2), respectively.

[0409] A timing chart according to the driving method of the driving circuit (30) is shown in (C) of FIG. 32. In FIG. 32 (C), the time change of potential is shown for each of the above signals (SP), signals (CLK1) to (CLK4), signals (RES), output terminals (OUTA1) to (OUTA6), output terminals (OUTB1) to (OUTB6), and output terminals (SROUT1) to (SROUT6).

[0410] First, at time T0, signals (SP), (CLK3), and (CLK4) become high potentials, and signals (CLK1) and (CLK2) become low potentials. At this time, low potentials are output to output terminals (OUTA2) through (OUTA6), high potentials are output to output terminals (OUTB2) through (OUTB6), and low potentials are output to output terminals (SROUT1) through (SROUT6). Additionally, as signal (SP) becomes high potential, high potential is output to output terminal (OUTA1), and low potential is output to output terminal (OUTB1).

[0411] Next, at time T1, the signal (CLK1) changes from a low potential to a high potential and the signal (CLK3) changes from a high potential to a low potential, thereby maintaining the high potential output for the output terminal (OUTA1) and the low potential output for the output terminal (OUTB1) from the sequence circuit (20_1), and the high potential is output to the output terminal (SROUT1). Additionally, the high potential is output to the output terminal (OUTA2) and the low potential is output to the output terminal (OUTB2).

[0412] Subsequently, by means of signals (CLK1) to (CLK4), a high potential is sequentially output to output terminals after output terminal (OUTA2), a low potential is sequentially output to output terminals after output terminal (OUTB2), and a high potential is sequentially output to output terminals after output terminal (SROUT2).

[0413] Signals (CLK1) to (CLK4) are clock signals offset by one-quarter of a period, respectively. Therefore, as shown in (C) of FIG. 32, signals offset by one-quarter of a period, such as signal (CLK1), are output to output terminals (OUTA1) to (OUTA6), output terminals (OUTB1) to (OUTB6), and output terminals (SROUT1) to (SROUT6), respectively.

[0414] In addition, the configuration of the driving circuit is not limited to this, and the signal, output terminal, etc. can be appropriately changed to match the configuration of the sequence circuit used.

[0415] This concludes the explanation of the configuration example of the driving circuit.

[0416] <Example of Sequential Circuit Configuration 1>

[0417] Figure 33 (A) shows an example of the configuration of a sequence circuit (20A) in one embodiment of the present invention. The sequence circuit (20A) includes a circuit (11) and a circuit (12). The circuit (11) includes a wiring (WA) connected to an output terminal (OUTA) and a wiring (WB) connected to an output terminal (OUTB). The circuit (11) and the circuit (12) are connected through the wiring (WA) and the wiring (WB).

[0418] The circuit (11) includes a transistor (Tr11), a transistor (Tr12), a transistor (Tr13), a transistor (Tr14), a transistor (Tr15), a transistor (Tr21), a transistor (Tr22), and a capacitance element (C21).

[0419] The circuit (12) includes a transistor (Tr16), a transistor (Tr20), a transistor (Tr23), and a capacitance element (C11).

[0420] In addition, a potential (VDD) is applied from a high potential power source and a potential (VSS) is applied from a low potential power source to circuits (11) and (12).

[0421] Signals (CLK2), (CLK3), (LIN), (RIN), and (RES) are input to the circuit (11). The circuit (11) has the function of outputting a first signal to the wiring (WA) according to the potentials of signals (CLK2), (CLK3), (LIN), and (RIN), and outputting a second signal, which is the inverted version of the first signal, to the wiring (WB). That is, the circuit (11) may also be called a control circuit. Additionally, a signal that controls the reset operation of the sequence circuit (20A) is supplied to the signal (RES).

[0422] A signal (CLK1), a first signal, and a second signal are input to the circuit (12). The circuit (12) has the function of outputting either the signal (CLK1) or the potential (VSS) to an output terminal (SROUT) based on the potentials of the signal (CLK1), the first signal, and the second signal. The circuit (12) outputs the signal (CLK1) when the first signal is at a high potential (the second signal is at a low potential), and outputs the potential (VSS) when the second signal is at a high potential (the first signal is at a low potential). The circuit (12) may be called an amplification circuit or a buffer circuit, etc.

[0423] The sequence circuit (20A) functions as a flip-flop circuit and can be used in part of a shift register circuit. For example, the sequence circuit (20A) can be used in part of a driving circuit of a display device. In particular, it can be suitably used in part of a scan line driving circuit of a display device.

[0424] When the sequence circuit (20A) is applied to the scan line driving circuit, a scan line (also called a gate line) connected to a plurality of pixels of the display device can be connected to at least one or both of the output terminal (OUTA) and the output terminal (OUTB). By configuring the scan line to be connected to each of the output terminal (OUTA) and the output terminal (OUTB), the pixel can be driven with two types of scan line signals, thereby enabling the realization of a pixel with more functions.

[0425] Detailed information regarding the configuration of the sequence circuit (20A) is explained.

[0426] In circuit (11), the gate of transistor (Tr11) is connected to a wire to which a signal (LIN) is supplied, one of the source and drain of transistor (Tr11) is connected to a wire (WA) and one of the source and drain of transistor (Tr21), and the other of the source and drain of transistor (Tr11) is connected to a wire to which a potential (VDD) is applied. The gate of transistor (Tr12) is connected to a wire to which a signal (CLK3) is supplied, one of the source and drain of transistor (Tr12) is connected to one of the source and drain of transistor (Tr13), and the other of the source and drain of transistor (Tr12) is connected to a wire to which a potential (VDD) is applied. The gate of transistor (Tr13) is connected to the wiring to which the signal (CLK2) is supplied, and the other of the source and drain of transistor (Tr13) is connected to the wiring (WB), one electrode of the capacitance element (C21), and the gate of transistor (Tr21), respectively. The gate of transistor (Tr14) is connected to the wiring to which the signal (RIN) is supplied, and one of the source and drain of transistor (Tr14) is connected to the wiring (WB), and the other of the source and drain of transistor (Tr14) is connected to the wiring to which the potential (VDD) is applied. The gate of transistor (Tr15) is connected to the wiring to which the signal (RES) is supplied, and one of the source and drain of transistor (Tr15) is connected to the wiring (WB), and the other of the source and drain of transistor (Tr15) is connected to the wiring to which the potential (VDD) is applied. The other end of the source and drain of transistor (Tr21) is connected to the wiring to which the potential (VSS) is applied. The gate of transistor (Tr22) is connected to the wiring to which the signal (LIN) is supplied, one end of the source and drain of transistor (Tr22) is connected to the wiring (WB), and the other end of the source and drain of transistor (Tr22) is connected to the wiring to which the potential (VSS) is applied. The other electrode of the capacitance element (C21) is connected to the wiring to which the potential (VSS) is applied.

[0427] In circuit (12), the gate of transistor (Tr16) is connected to a wire to which a potential (VDD) is applied, one of the source and drain of transistor (Tr16) is connected to a wire (WA), and the other of the source and drain is connected to one electrode of the capacitance element (C11) and the gate of transistor (Tr20). One of the source and drain of transistor (Tr20) is connected to the other electrode of the capacitance element (C11) and the output terminal (SROUT), and the other of the source and drain of transistor (Tr20) is connected to a wire to which a signal (CLK1) is supplied. The gate of transistor (Tr23) is connected to a wire (WB), one of the source and drain of transistor (Tr23) is connected to the output terminal (SROUT), and the other of the source and drain of transistor (Tr23) is connected to a wire to which a potential (VSS) is applied.

[0428] Transistors (Tr11) and (Tr22) are selected to conduct or not conduct depending on the potential of the signal (LIN). Transistor (Tr14) is selected to conduct or not conduct depending on the potential of the signal (RIN).

[0429] When signal (LIN) is at a high potential and signal (RIN) is at a low potential, transistors (Tr11) and (Tr22) are turned on, and transistor (Tr14) is turned off. Therefore, the wiring to which potential (VDD) is applied and wiring (WA) are connected through transistor (Tr11). Also, the wiring to which potential (VSS) is applied and wiring (WB) are connected through transistor (Tr22). At this time, as wiring (WA) becomes at a high potential, a high potential is applied to the gate of transistor (Tr20) through transistor (Tr16), so transistor (Tr20) is turned on. Therefore, signal (CLK1) is output to the output terminal (SROUT) through transistor (Tr20).

[0430] Meanwhile, when signal (LIN) is at a low potential and signal (RIN) is at a high potential, transistor (Tr14) is turned on, and transistors (Tr11) and (Tr22) are turned off. Therefore, the wiring to which potential (VDD) is applied and wiring (WB) are connected through transistor (Tr14). Also, as wiring (WB) becomes at a high potential, transistor (Tr21) is turned on. Therefore, the wiring to which potential (VSS) is applied and wiring (WA) are connected through transistor (Tr21). At this time, as wiring (WB) becomes at a high potential, a high potential is applied to the gate of transistor (Tr23), so transistor (Tr23) is turned on. Therefore, potential (VSS) is output to the output terminal (SROUT) through transistor (Tr23).

[0431] In addition, as described above, when a high potential is applied to the wiring (WA), the transistor (Tr20) turns on. At this time, when the high potential applied to the wiring (WA) is equal to the potential (VDD), a potential lower than the potential (VDD) by the threshold voltage of the transistor (Tr16) is applied to the gate of the transistor (Tr20). Since the output terminal (SROUT) and the gate of the transistor (Tr20) are connected through a capacitance element (C11), the potential of the gate of the transistor (Tr20) (the potential of the other side between the source and drain of the transistor (Tr16)) rises as the potential of the output terminal (SROUT) rises due to the bootstrap effect. Since the potential of the gate of the transistor (Tr20) rises to a potential close to twice the potential (VDD), for example, the potential (VDD) can be output to the output terminal (SROUT) without being affected by the threshold voltage of the transistor (Tr20). By doing so, a sequence circuit (20A) with high output performance can be realized without increasing the types of power potentials.

[0432] After that, when the potential of the other side between the source and drain of the transistor (Tr16) exceeds the potential (VDD), the transistor (Tr16) is turned off, so the gate of the transistor (Tr20) and the wiring (WA) are electrically separated, and the gate of the transistor (Tr23) becomes floating. In addition, since the transistor (Tr16) is turned off, the potential of the wiring (WA) does not rise above the output potential of the circuit (12), so it is possible to prevent a potential higher than the output potential from being applied to the transistor, etc. in the circuit (12) through the wiring (WA). Therefore, the reliability of the sequence circuit (20A) can be increased.

[0433] It is preferable to use an OS transistor as the transistor constituting the sequence circuit (20A). The leakage current flowing between the source and drain in the off state of an OS transistor is significantly lower than that of a Si transistor. By applying an OS transistor to circuits (11) and (12), the power consumption of each can be made very low.

[0434] FIG. 35 is a circuit diagram showing some transistors extracted from the sequential circuit (20A). FIG. 36 is a cross-sectional view corresponding to the circuit diagram of FIG. 35. Here, focusing on the transistors constituting the circuit (11), one of the source and drain of transistors (Tr11) and (Tr21) is connected to the wire (WA), and one of the source and drain of transistors (Tr14), (Tr12), and (Tr15) is connected to the wire (WB). Additionally, the gate of transistor (Tr21) is connected to one of the source and drain of transistor (Tr14). The gate of transistor (Tr21) is connected to one of the source and drain of transistor (Tr12). The gate of transistor (Tr21) is connected to one of the source and drain of transistor (Tr15).

[0435] For example, for each combination of transistor (Tr21) and transistor (Tr14), combination of transistor (Tr21) and transistor (Tr12), or combination of transistor (Tr21) and transistor (Tr15), the semiconductor device (100) and semiconductor device (100C) described in Embodiment 1 may be applied. In this case, transistor (Tr21) corresponds to transistor (10_1) included in the semiconductor device (100), etc., and transistor (Tr14), transistor (Tr12), or transistor (Tr15) corresponds to transistor (10_2) included in the semiconductor device (100), etc.

[0436] That is, some of the transistors in the circuit (11) can be provided by stacking. For example, as shown in FIGS. 35 and 36, transistors (Tr11), transistor (Tr21), etc., in which one of the source and drain is connected to the wiring (WA), are formed in the first layer, and transistors (Tr14), transistor (Tr12), transistor (Tr15), etc., in which one of the source and drain is connected to the wiring (WB), are formed in the second layer, thereby significantly reducing the area occupied by the circuit (11) compared to when they are formed on the same plane. In addition, since one form of the transistor of the present invention is a vertical transistor, the area occupied by the circuit (11) can be further reduced compared to when a planar transistor is applied.

[0437] <Example of Sequential Circuit Configuration 2>

[0438] An example of the configuration of a sequence circuit (20B) different from the sequence circuit (20A) shown in FIG. 33 (A) is shown in FIG. 33 (B). The configuration of the transistors in the sequence circuit (20B) is different from that of the sequence circuit (20A).

[0439] Specifically, in the sequence circuit (20B), a transistor including a back gate is applied as all transistors included in the circuit (11) and circuit (12).

[0440] Among them, the back gates of transistors (Tr21) and (Tr23) are connected to the wiring to which the potential (VSS) is applied. That is, the back gates of transistors (Tr21) and (Tr23) have a configuration in which they are electrically connected to the source.

[0441] Here, when the sequence circuit (20B) is used in the scan line driving circuit, the period during which the wiring (WB) is at a high potential becomes significantly longer than the period during which the wiring (WB) is at a low potential. Therefore, in transistors (Tr21) and (Tr23) whose gates are connected to the wiring (WB), the period during which they are in the ON state becomes significantly longer than the period during which they are in the OFF state. Consequently, transistors (Tr21) and (Tr23) are more prone to fluctuations in threshold voltage than other transistors. Specifically, the threshold voltage of the transistors is more prone to shifting in the positive direction.

[0442] Therefore, the transistor (Tr21) and the transistor (Tr23) are configured such that one of the pair of gates, which are superimposed with a semiconductor layer in between, is electrically connected to a wiring to which a low potential is applied (a wiring to which a potential (VSS) is applied). By configuring it in this way, the threshold voltage of the transistor (Tr21) and the transistor (Tr23) can be appropriately suppressed from shifting in the positive direction. Thus, the reliability of the sequence circuit (20B), or the semiconductor device, display device, electronic device, etc. using the sequence circuit (20B), can be increased.

[0443] In addition, by configuring the transistor (Tr21) and transistor (Tr23) such that one gate and source are connected, the threshold voltage can be appropriately prevented from becoming a negative value. That is, it becomes easier to make the transistor (Tr21) and transistor (Tr23) normally off. In addition, by configuring the transistor (Tr21) and transistor (Tr23) such that one gate and source are connected, there is also an effect of increasing saturation. Therefore, the design of circuit (11) and circuit (12) becomes easier, and a circuit capable of stable operation can be realized.

[0444] Meanwhile, transistors other than transistor (Tr21) and transistor (Tr23) are used as transistors with a pair of gates connected. By connecting a pair of gates that overlap with a semiconductor layer in between, the on-current of the transistor can be increased. This allows the driving capability of the sequence circuit (20B) to be improved.

[0445] Additionally, in the sequence circuit (20B), all transistors included in the circuit (11) and the circuit (12) are configured to include a back gate, but are not limited thereto, and any one (or multiple) of the transistors included in the circuit (11) and the circuit (12) may be configured to include a back gate.

[0446] For example, in a configuration where transistor (Tr21) among the transistors included in the circuit (11) includes a back gate, and transistors (Tr14), transistor (Tr12), and transistor (Tr15) do not include a back gate, the semiconductor device (100A) and semiconductor device (100B) described in Embodiment 1 may be applied to each of the combination of transistor (Tr21) and transistor (Tr14), the combination of transistor (Tr21) and transistor (Tr12), or the combination of transistor (Tr21) and transistor (Tr15). In this case, transistor (Tr21) corresponds to transistor (10_1) included in the semiconductor device (100A), etc., and transistor (Tr14), transistor (Tr12), or transistor (Tr15) corresponds to transistor (10_2) included in the semiconductor device (100A), etc.

[0447] In addition, for example, when transistors (Tr21), transistor (Tr14), transistor (Tr12), and transistor (Tr15) included in the circuit (11) are configured to include a back gate, the semiconductor device (100D) described in Embodiment 1 may be applied to each combination of transistor (Tr21) and transistor (Tr14), combination of transistor (Tr21) and transistor (Tr12), or combination of transistor (Tr21) and transistor (Tr15). In this case, transistor (Tr21) corresponds to transistor (10_1) included in the semiconductor device (100D), and transistor (Tr14), transistor (Tr12), or transistor (Tr15) corresponds to transistor (10_2) included in the semiconductor device (100D).

[0448] For details regarding the sequence circuit (20B) other than those mentioned above, refer to the description of the sequence circuit (20A) above.

[0449] <Sequential Circuit Configuration Example 3>

[0450] In FIG. 34 (A), an example of the configuration of a sequence circuit (20C) different from the sequence circuit (20A) shown in FIG. 33 (A) is shown. The configuration of the transistors included in the circuit (12) of the sequence circuit (20C) is different from that of the sequence circuit (20A).

[0451] Specifically, in the sequence circuit (20C), the transistor corresponding to the transistor (Tr20) in the sequence circuit (20A) is composed of two transistors named transistor (Tr20a) and transistor (Tr20b).

[0452] One of the source and drain of transistor (Tr20a) is connected to one of the source and drain of transistor (Tr20b). The other of the source and drain of transistor (Tr20a) is connected to the other of the source and drain of transistor (Tr20b). The gate of transistor (Tr20a) and the gate of transistor (Tr20b) are connected. In other words, transistor (Tr20a) and transistor (Tr20b) can be said to be connected in parallel with each other.

[0453] In this way, by configuring two transistors in parallel, if each transistor has an equivalent current generating capability, approximately twice the on-current can be obtained compared to a configuration containing only one transistor. Additionally, although the sequential circuit (20C) shows an example of a configuration in which two transistors, transistor (Tr20a) and transistor (Tr20b), are connected in parallel, it is not limited thereto and can be configured with three or more transistors connected in parallel. It is desirable because increasing the number of parallel connections of transistors can increase the overall output current.

[0454] As described above, the circuit (12) functions as an amplification circuit and serves to output the signal generated by the circuit (11) to the output terminal (SROUT). It is desirable for the circuit (12) to amplify the signal generated by the circuit (11) as much as possible and supply it to the output terminal (SROUT). Therefore, it is desirable to configure the transistor located immediately before the output terminal (SROUT), such as the circuit (12) included in the sequence circuit (20C), as a configuration in which multiple transistors are connected in parallel, so that a higher current can be supplied to the output terminal (SROUT) than when only one transistor is included.

[0455] In addition, when multiple transistors are connected in parallel, such as in the circuit (12) included in the sequence circuit (20C), the output current can be increased, but there is a concern that the total area occupied by the semiconductor device may increase due to the increased number of transistors. However, in one embodiment of the present invention, since transistors can be provided by stacking, the output current can be increased without increasing the area occupied by the semiconductor device. For example, regarding the combination of transistor (Tr20a) and transistor (Tr20b) included in the sequence circuit (20C), the semiconductor device (200) described in Embodiment 1 can be applied. Also, FIGS. 35 and 36 show an example in which two transistors (Tr20) connected in parallel in the circuit (12) are provided by stacking. FIGS. 35 and 36 illustrate an example in which a first transistor (Tr20) (one of the transistor (Tr20a) and transistor (Tr20b) included in the sequence circuit (20C)) is formed on the first layer in which the aforementioned transistor (Tr21) is formed, and a second transistor (Tr20) (the other of the transistor (Tr20a) and transistor (Tr20b) included in the sequence circuit (20C)) is formed on the second layer in which the aforementioned transistors (Tr14), transistor (Tr12), and transistor (Tr15) are formed.

[0456] In addition, the sequence circuit (20C) shows a configuration in which only transistors corresponding to the transistor (Tr20) in the sequence circuit (20A) are connected in parallel, but it is not limited to this and can also be configured in which transistors other than the transistor (Tr20) are connected in parallel.

[0457] For details regarding the sequence circuit (20C) other than those mentioned above, refer to the description of the sequence circuit (20A) above.

[0458] <Sequential Circuit Configuration Example 4>

[0459] In FIG. 34 (B), an example of the configuration of a sequence circuit (20D) different from the sequence circuit (20A) shown in FIG. 33 (A) is shown. The configuration of the transistors in the sequence circuit (20D) is different from that of the sequence circuit (20A).

[0460] Specifically, in the sequence circuit (20D), the transistor corresponding to the transistor (Tr14) in the sequence circuit (20A) is composed of two transistors, namely transistor (Tr14a) and transistor (Tr14b). Additionally, the transistor corresponding to the transistor (Tr15) in the sequence circuit (20A) is composed of two transistors, namely transistor (Tr15a) and transistor (Tr15b). Furthermore, the transistor corresponding to the transistor (Tr21) in the sequence circuit (20A) is composed of two transistors, namely transistor (Tr21a) and transistor (Tr21b). Additionally, the transistor corresponding to the transistor (Tr22) in the sequence circuit (20A) is composed of two transistors, namely transistor (Tr22a) and transistor (Tr22b). Furthermore, the transistor corresponding to the transistor (Tr23) in the sequence circuit (20A) is composed of two transistors, namely transistor (Tr23a) and transistor (Tr23b).

[0461] One of the source and drain of transistor (Tr14a) is connected to one of the source and drain of transistor (Tr14b). The gate of transistor (Tr14a) is connected to the gate of transistor (Tr14b). In other words, transistor (Tr14a) and transistor (Tr14b) can be said to be connected in series with each other. The same applies to transistor (Tr15a) and transistor (Tr15b), transistor (Tr21a) and transistor (Tr21b), transistor (Tr22a) and transistor (Tr22b), and transistor (Tr23a) and transistor (Tr23b), respectively.

[0462] By configuring two transistors in series in this way, if each transistor has an equivalent current generating capability, the off-current can be suppressed to approximately half compared to a configuration containing only one transistor. In addition, the voltage withstand capability between the source and drain can be increased.

[0463] In addition, when multiple transistors are connected in series, such as in the sequence circuit (20D), it is possible to reduce off-current and improve the voltage withstand capability between the source and drain, but there is a concern that the total area occupied by the semiconductor device may increase due to the increased number of transistors. However, in one embodiment of the present invention, since transistors can be provided in a stacked manner, it is possible to reduce off-current and improve the voltage withstand capability between the source and drain without increasing the area occupied by the semiconductor device. For example, the semiconductor device (300) described in Embodiment 1 can be applied to a combination of serial connections of two transistors included in the sequence circuit (20D).

[0464] In addition, in the sequential circuit (20D), an example has been shown in which two transistors are connected in series for transistors corresponding to transistors (Tr14), transistor (Tr15), transistor (Tr21), transistor (Tr22), and transistor (Tr23) in the sequential circuit (20A), but this is not limited thereto, and a configuration in which two transistors are connected in series can also be applied for transistors corresponding to transistors (Tr11), transistor (Tr12), transistor (Tr13), transistor (Tr16), and transistor (Tr20) in the sequential circuit (20A). Furthermore, the number of transistors connected in series is not limited to two, and a configuration in which three or more transistors are connected in series may be used. It is desirable to increase the number of transistors connected in series because it can lower the overall off-current. It is also desirable because it can increase the overall source-drain withstand voltage.

[0465] For details regarding the sequence circuit (20D) other than those mentioned above, refer to the description of the sequence circuit (20A) above.

[0466] As such, a semiconductor device of one embodiment of the present invention has a configuration in which two vertical transistors having various connection relationships (parallel connection, series connection, etc.) are stacked. Therefore, by using a semiconductor device of one embodiment of the present invention, for example, in a scan line driving circuit of a display device, the area occupied by the scan line driving circuit can be reduced compared to the case where each transistor is provided on the same plane, thereby allowing the bezel of the display device to be narrowed.

[0467] The configuration described in this embodiment may be used in appropriate combination with the configuration described in other embodiments.

[0468] (Embodiment 3)

[0469] In this embodiment, an electronic device of one form of the present invention is described using FIG. 37 (A) to FIG. 39 (G).

[0470] The electronic device of the present embodiment includes a display device of one form of the present invention in the display section. The display device of one form of the present invention can easily increase precision and resolution. Therefore, it can be used in the display section of various electronic devices.

[0471] Electronic devices include, for example, televisions, desktop or laptop personal computers, monitors for computers, digital signage, large game machines such as pachinko machines, and other electronic devices having relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound playback devices.

[0472] In particular, since one form of the present invention can increase the precision, it can be suitably used in electronic devices having a relatively small display area. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), VR devices such as head-mounted displays, glasses-type AR devices, MR devices, and wearable devices that can be mounted on the head.

[0473] A display device of one embodiment of the present invention preferably has a very high resolution, such as HD (pixels 1280×720), FHD (pixels 1920×1080), WQHD (pixels 2560×1440), WQXGA (pixels 2560×1600), 4K (pixels 3840×2160), 8K (pixels 7680×4320), etc. In particular, it is preferable to have a resolution of 4K, 8K, or higher than these. In addition, the pixel density (resolution) of a display device of one embodiment of the present invention is preferably 100 ppi or higher, more preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and more preferably 7000 ppi or higher. By using a display device having one or both of such high resolution and high resolution, the sense of realism and depth can be further enhanced. In addition, the aspect ratio (aspect ratio) of a display device of one embodiment of the present invention is not particularly limited. For example, the display device can support various aspect ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0474] The electronic device of the present embodiment may include a sensor (including a function to detect, sense, or measure force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared radiation).

[0475] The electronic device of the present embodiment may have various functions. For example, it may have a function of displaying various information (still images, video, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of executing various software (programs), a wireless communication function, and a function of reading programs or data stored on a recording medium.

[0476] Using FIG. 37 (A) to (D), an example of a wearable device that can be mounted on the head is described. These wearable devices have at least one of a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content. By having an electronic device that has a function to display at least one of AR, VR, SR, and MR content, the user's sense of immersion can be enhanced.

[0477] The electronic device (700A) shown in (A) of FIG. 37 and the electronic device (700B) shown in (B) of FIG. 37 each include a pair of display panels (751), a pair of housings (721), a communication unit (not shown), a pair of mounting units (723), a control unit (not shown), an imaging unit (not shown), a pair of optical members (753), a frame (757), and a pair of nose pads (758).

[0478] A display device of one form of the present invention can be applied to the display panel (751). Thus, it can be an electronic device capable of displaying with very high precision.

[0479] The electronic device (700A) and the electronic device (700B) can each project an image displayed on the display panel (751) onto the display area (756) of the optical member (753). Since the optical member (753) is transparent, the user can view the image displayed on the display area by overlaying it on the transmitted image seen through the optical member (753). Therefore, the electronic device (700A) and the electronic device (700B) are each electronic devices capable of AR display.

[0480] The electronic device (700A) and the electronic device (700B) may each be provided with a camera capable of capturing the forward direction as an imaging unit. Additionally, the electronic device (700A) and the electronic device (700B) may each include an accelerometer such as a gyroscope sensor to detect the direction of the user's head and display an image corresponding to that direction in the display area (756).

[0481] The communication unit includes a wireless communication device and can supply video signals, etc. via the wireless communication device. In addition, instead of or in addition to the wireless communication device, it may include a connector capable of connecting a cable to which a video signal and power potential are applied.

[0482] Since the electronic device (700A) and the electronic device (700B) are each provided with a battery (not shown), they can be charged wirelessly or wired, or both.

[0483] A touch sensor module may be provided in the housing (721). The touch sensor module has the function of detecting that the outer surface of the housing (721) is touched. Various processing can be performed by detecting user tap operations or slide operations through the touch sensor module. For example, processing such as pausing or resuming a video can be performed by tap operations, and processing such as fast-forwarding or fast-rewinding can be performed by slide operations. In addition, the range of operations can be expanded by providing a touch sensor module in each of the two housings (721).

[0484] Various touch sensors can be applied to the touch sensor module. For example, various methods such as capacitive, resistive, infrared, electromagnetic induction, surface acoustic wave, and optical methods can be adopted. In particular, it is desirable to apply capacitive or optical sensors to the touch sensor module.

[0485] When using an optical touch sensor, a photoelectric conversion element may be used as a light-receiving element. In the active layer of the photoelectric conversion element, one or both of an inorganic semiconductor and an organic semiconductor may be used.

[0486] The electronic device (800A) shown in (C) of FIG. 37 and the electronic device (800B) shown in (D) of FIG. 37 each include a pair of display units (820), a housing (821), a communication unit (822), a pair of mounting units (823), a control unit (824), a pair of imaging units (825), and a pair of lenses (832).

[0487] A display device of one form of the present invention can be applied to the display unit (820). Thus, it can be an electronic device capable of displaying very high precision. As a result, the user can feel a high sense of immersion.

[0488] The display unit (820) is provided at a position visible through the lens (832) inside the housing (821). Additionally, by displaying different images on a pair of display units (820), a three-dimensional display using parallax is also possible.

[0489] The electronic device (800A) and the electronic device (800B) can each be described as an electronic device for VR. A user wearing the electronic device (800A) or the electronic device (800B) can view an image displayed on the display unit (820) through the lens (832).

[0490] It is preferable that the electronic device (800A) and the electronic device (800B) each have a mechanism capable of adjusting the left and right positions of the lens (832) and the display unit (820) so that they are in an optimal position according to the user's eye position. It is also preferable that they have a mechanism for adjusting the focus by changing the distance between the lens (832) and the display unit (820).

[0491] The user can mount an electronic device (800A) or an electronic device (800B) on their head via the mounting portion (823). In addition, in Fig. 37 (C), etc., it is exemplified as having a shape similar to eyeglass temples (also called temples), but is not limited thereto. The mounting portion (823) may be a helmet type or a band type, for example, so as to be mountable by the user.

[0492] The imaging unit (825) has the function of acquiring external information. Data acquired by the imaging unit (825) can be output to the display unit (820). An image sensor may be used in the imaging unit (825). Additionally, multiple cameras may be provided to accommodate multiple angles of view, such as telephoto and wide-angle.

[0493] In addition, although an example including an imaging unit (825) is shown here, it is preferable to provide a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object. That is, the imaging unit (825) is a form of the detection unit. As the detection unit, for example, a distance image sensor such as an image sensor or a LIDAR (Light Detection And Ranging) can be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information is acquired, making it possible to perform gesture operations with higher precision.

[0494] The electronic device (800A) may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having the vibration mechanism may be applied to any one or more of the display unit (820), housing (821), and mounting unit (823). As a result, audio devices such as headphones, earphones, or speakers are not required separately, so video and audio can be enjoyed simply by mounting the electronic device (800A).

[0495] The electronic device (800A) and the electronic device (800B) may each include an input terminal. A cable supplying a video signal from a video output device, power for charging a battery provided within the electronic device, etc., can be connected to the input terminal.

[0496] An electronic device of one embodiment of the present invention may have a function of wirelessly communicating with an earphone (750). The earphone (750) includes a communication unit (not shown) and has a wireless communication function. The earphone (750) can receive information (e.g., voice data) from an electronic device through the wireless communication function. For example, the electronic device (700A) shown in (A) of FIG. 37 has a function of transmitting information to the earphone (750) through the wireless communication function. Also, for example, the electronic device (800A) shown in (C) of FIG. 37 has a function of transmitting information to the earphone (750) through the wireless communication function.

[0497] The electronic device may include an earphone section. The electronic device (700B) shown in (B) of FIG. 37 includes an earphone section (727). For example, the earphone section (727) and the control section may be configured to be connected to each other by a wire. A portion of the wiring connecting the earphone section (727) and the control section may be placed inside the housing (721) or the mounting section (723).

[0498] Likewise, the electronic device (800B) shown in (D) of FIG. 37 includes an earphone unit (827). For example, the earphone unit (827) and the control unit (824) may be configured to be connected to each other by a wire. A portion of the wiring connecting the earphone unit (827) and the control unit (824) may be placed inside the housing (821) or the mounting unit (823). Additionally, the earphone unit (827) and the mounting unit (823) may include magnets. This is desirable because the earphone unit (827) can be fixed to the mounting unit (823) by magnetic force, making storage easier.

[0499] In addition, the electronic device may include an audio output terminal to which earphones or headphones can be connected. Furthermore, the electronic device may include either or both of an audio input terminal and an audio input device. As the audio input device, a sound collecting device such as a microphone may be used, for example. By having an audio input device, the electronic device may be endowed with the function of a so-called headset.

[0500] As described above, as one form of the electronic device of the present invention, both glasses type (electronic device (700A), electronic device (700B), etc.) and goggle type (electronic device (800A), electronic device (800B), etc.) are suitable.

[0501] An electronic device of one form of the present invention can transmit information to an earphone via a wired or wireless connection.

[0502] The electronic device (6500) shown in (A) of FIG. 38 is a portable information terminal that can be used as a smartphone.

[0503] The electronic device (6500) includes a housing (6501), a display unit (6502), a power button (6503), a button (6504), a speaker (6505), a microphone (6506), a camera (6507), a light source (6508), etc. The display unit (6502) has a touch panel function.

[0504] A display device of one form of the present invention can be applied to the display unit (6502).

[0505] Figure 38 (B) is a schematic cross-sectional view including the end of the housing (6501) on the side of the microphone (6506).

[0506] A light-transmitting protective member (6510) is provided on the display side of the housing (6501), and a display panel (6511), an optical member (6512), a touch sensor panel (6513), a printed circuit board (6517), a battery (6518), etc. are arranged within the space enclosed by the housing (6501) and the protective member (6510).

[0507] A display panel (6511), an optical member (6512), and a touch sensor panel (6513) are fixed to the protective member (6510) by an adhesive layer (not shown).

[0508] A portion of the display panel (6511) is folded in an area outside the display portion (6502), and an FPC (6515) is connected to this folded portion. An IC (6516) is mounted on the FPC (6515). The FPC (6515) is connected to a terminal provided on the printed circuit board (6517).

[0509] A flexible display of one form of the present invention can be applied to the display panel (6511). Therefore, a very lightweight electronic device can be realized. Also, since the display panel (6511) is very thin, a large capacity battery (6518) can be installed without increasing the thickness of the electronic device. Additionally, by folding a part of the display panel (6511) and placing a connection part with the FPC (6515) on the back side of the display unit (6502), a slim bezel electronic device can be realized.

[0510] An example of a television device is shown in (C) of FIG. 38. In the television device (7100), a display unit (7000) is included in the housing (7101). Here, a configuration is shown in which the housing (7101) is supported by a stand (7103).

[0511] A display device of one form of the present invention can be applied to the display unit (7000).

[0512] The operation of the television device (7100) shown in (C) of FIG. 38 can be performed by an operation switch included in the housing (7101) and a separate remote controller (7111). Alternatively, a touch sensor may be included in the display unit (7000), or the television device (7100) may be operated by touching the display unit (7000) with a finger or the like. The remote controller (7111) may include a display unit that displays information output from the remote controller (7111). Channels and volume can be operated by an operation key or touch panel included in the remote controller (7111), and images displayed on the display unit (7000) can be operated.

[0513] Additionally, the television device (7100) is configured to include a receiver, a modem, etc. General television broadcasts can be received via the receiver. Furthermore, by connecting to a communication network via a wired or wireless connection through the modem, one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication can be performed.

[0514] An example of a notebook-type personal computer is shown in (D) of FIG. 38. The notebook-type personal computer (7200) includes a housing (7211), a keyboard (7212), a pointing device (7213), an external connection port (7214), etc. A display unit (7000) is included in the housing (7211).

[0515] A display device of one form of the present invention can be applied to the display unit (7000).

[0516] An example of digital signage is shown in (E) and (F) of Fig. 38.

[0517] The digital signage (7300) shown in (E) of FIG. 38 includes a housing (7301), a display unit (7000), and a speaker (7303), etc. It may also include an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, etc.

[0518] (F) of FIG. 38 shows a digital signage (7400) mounted on a cylindrical column (7401). The digital signage (7400) includes a display (7000) provided along the curved surface of the column (7401).

[0519] In (E) and (F) of FIG. 38, a display device of one form of the present invention can be applied to the display unit (7000).

[0520] The wider the display area (7000), the more information can be provided at once. Also, the wider the display area (7000), the easier it is to catch people's eyes, so, for example, the promotional effect of an advertisement can be increased.

[0521] It is desirable to apply a touch panel to the display unit (7000) so that not only can images or videos be displayed on the display unit (7000), but the user can also operate it intuitively. In addition, when used for the purpose of providing information such as route information or traffic information, usability can be enhanced through intuitive operation.

[0522] As shown in (E) and (F) of FIG. 38, it is preferable that the digital signage (7300) or digital signage (7400) be connected via wireless communication with an information terminal (7311) or information terminal (7411), such as a smartphone owned by the user. For example, information about an advertisement displayed on the display unit (7000) can be displayed on the screen of the information terminal (7311) or information terminal (7411). Additionally, the display of the display unit (7000) can be switched by operating the information terminal (7311) or information terminal (7411).

[0523] A game may be executed on digital signage (7300) or digital signage (7400) using the screen of an information terminal (7311) or an information terminal (7411) as a means of operation (controller). By doing so, an unspecified number of users can simultaneously participate in and enjoy the game.

[0524] The electronic device shown in (A) to (G) of FIG. 39 includes a housing (9000), a display unit (9001), a speaker (9003), an operation key (9005) (including a power switch or an operation switch), a connection terminal (9006), a sensor (9007) (having the function of detecting, detecting, or measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, longitude, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, smell, or infrared radiation), a microphone (9008), etc.

[0525] In (A) to (G) of FIG. 39, a display device of one form of the present invention can be applied to the display portion (9001).

[0526] The electronic device shown in (A) to (G) of FIG. 39 has various functions. For example, it may have a function of displaying various information (still images, video, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of controlling processing by various software (programs), a wireless communication function, and a function of reading and processing programs or data stored on a recording medium. Furthermore, the functions of the electronic device are not limited to these and may have various functions. The electronic device may include multiple display units. Additionally, the electronic device may be provided with a camera, etc., and may have a function of capturing still images or video and storing them on a recording medium (an external recording medium or a recording medium built into the camera), and a function of displaying the captured images on a display unit.

[0527] Detailed information regarding the electronic device shown in (A) to (G) of FIG. 39 will be explained below.

[0528] FIG. 39 (A) is a perspective view showing a portable information terminal (9101). The portable information terminal (9101) can be used, for example, as a smartphone. Additionally, the portable information terminal (9101) may be provided with a speaker (9003), a connection terminal (9006), a sensor (9007), etc. Additionally, the portable information terminal (9101) may display text and image information on its multiple surfaces. FIG. 39 (A) shows an example in which three icons (9050) are displayed. Additionally, information (9051) represented by a dashed rectangle may be displayed on another surface of the display unit (9001). Examples of information (9051) include notifications of incoming calls such as email, SNS, and phone calls, the subject of the email or SNS, the sender's name, date and time, time, remaining battery level, signal strength, etc. Alternatively, an icon (9050), etc., may be displayed at the location where the information (9051) is displayed.

[0529] FIG. 39 (B) is a perspective view showing a portable information terminal (9102). The portable information terminal (9102) has the function of displaying information on three or more sides of the display unit (9001). Here, an example is shown in which information (9052), information (9053), and information (9054) are displayed on different sides. For example, while the portable information terminal (9102) is stored in the chest pocket of clothing, the user may check the information (9053) displayed in a position visible from above the portable information terminal (9102). The user can check the display without taking the portable information terminal (9102) out of the pocket and, for example, decide whether to answer a call.

[0530] Figure 39 (C) is a perspective view showing a tablet terminal (9103). The tablet terminal (9103) can run various applications such as mobile phone, email, text viewing and writing, music playback, internet communication, and computer games, for example. The tablet terminal (9103) includes a display unit (9001), a camera (9002), a microphone (9008), and a speaker (9003) on the front of the housing (9000), an operation key (9005) as an operation button on the side of the housing (9000), and a connection terminal (9006) on the bottom surface.

[0531] FIG. 39 (D) is a perspective view showing a wristwatch-type portable information terminal (9200). The portable information terminal (9200) can be used, for example, as a smartwatch (registered trademark). Additionally, the display unit (9001) is provided with a curved display surface and can display along the curved display surface. Furthermore, the portable information terminal (9200) can make hands-free calls by communicating with, for example, a headset capable of wireless communication. Additionally, the portable information terminal (9200) can exchange data with other information terminals or charge via a connection terminal (9006). Additionally, the charging operation may be performed by wireless power supply.

[0532] FIGS. 39 (E) to (G) are perspective views showing a foldable portable information terminal (9201). FIGS. 39 (E) is a perspective view showing the portable information terminal (9201) in an unfolded state, FIGS. 39 (G) is a perspective view showing the portable information terminal (9201) in a folded state, and FIGS. 39 (F) is a perspective view showing the portable information terminal (9201) in a state in the middle of changing from one side to the other among the states shown in FIGS. 39 (E) and (G). The portable information terminal (9201) has excellent portability when folded, and when unfolded, it has excellent visibility of the display because it includes a wide display area without seams. The display part (9001) of the portable information terminal (9201) is supported by three housings (9000) connected by a hinge (9055). For example, the display part (9001) can be bent to a radius of curvature of 0.1 mm or more and 150 mm or less.

[0533] This embodiment can be appropriately combined with other embodiments. Explanation of the symbols

[0534] 10_1: Transistor, 10_2: Transistor, 11: Circuit, 12: Circuit, 20: Sequential Circuit, 20_1: Sequential Circuit, 20_2: Sequential Circuit, 20_3: Sequential Circuit, 20_4: Sequential Circuit, 20_5: Sequential Circuit, 20_6: Sequential Circuit, 20A: Sequential Circuit, 20B: Sequential Circuit, 20C: Sequential Circuit, 20D: Sequential Circuit, 30: Driving Circuit, 100: Semiconductor Device, 100A: Semiconductor Device, 100B: Semiconductor Device, 100C: Semiconductor Device, 100D: Semiconductor Device, 102: Substrate, 104_1: Conductive Layer, 104_1f: Conductive Film, 104_2: Conductive Layer, 106_1: Insulating Layer, 106_2: Insulating Layer, 108_1: Semiconductor Layer, 108_2: Semiconductor layer, 110_1: Insulating layer, 110_2: Insulating layer, 110a1: Insulating layer, 110a1f: Insulating film, 110a2: Insulating layer, 110a2f: Insulating film, 110b1: Insulating layer, 110b1f: Insulating film, 110b2: Insulating layer, 110b2f: Insulating film, 110c1: Insulating layer, 110c1f: Insulating film, 110c2: Insulating layer, 110c2f: Insulating film, 110d1: Insulating layer, 110d2: Insulating layer, 110e1: Insulating layer, 110e2: Insulating layer, 110f1: Insulating layer, 110f2: Insulating layer, 110g1: Insulating layer, 110g2: Insulating layer, 110h1: Insulating layer, 110h2: insulating layer, 110i1: insulating layer, 110i2: insulating layer, 110s1: insulating layer, 110s2: insulating layer, 112a1: conductive layer, 112a2: conductive layer, 112a2f: conductive film, 112b1: conductive layer, 112b1e: conductive layer, 112b1f: conductive film, 112b2: conductive layer, 112b2e: conductive layer, 112b2f: conductive film, 114_1: conductive layer, 114_2: conductive layer, 116: insulating layer, 136: mask, 138: mask, 139: light, 143: aperture, 144: aperture, 192e: insulating layer, 192f: insulating film, 192: insulating layer, 193f: insulating film, 193: Insulating layer, 194f: Insulating film, 194: Insulating layer, 200: Semiconductor device, 300: Semiconductor device,700A: Electronic device, 700B: Electronic device, 721: Housing, 723: Mounting part, 727: Earphone part, 750: Earphone, 751: Display panel, 753: Optical component, 756: Display area, 757: Frame, 758: Nose pad, 800A: Electronic device, 800B: Electronic device, 820: Display part, 821: Housing, 822: Communication part, 823: Mounting part, 824: Control part, 825: Imaging part, 827: Earphone part, 832: Lens, 6500: Electronic device, 6501: Housing, 6502: Display part, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6510: Protective member, 6511: Display panel, 6512: Optical member, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed board, 6518: Battery, 7000: Display unit, 7100: Television unit, 7101: Housing, 7103: Stand, 7111: Remote controller, 7200: Laptop-type personal computer, 7211: Housing, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7300: Digital signage, 7301: Housing, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7411: Information terminal, 9000: Housing, 9001: Display, 9002: Camera, 9003: Speaker, 9005: Operation Key, 9006: Connection Terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9101: Portable Information Terminal, 9102: Portable Information Terminal, 9103: Tablet Terminal, 9200: Portable Information Terminal, 9201: Portable Information Terminal,

Claims

Claim 1 As a semiconductor device, it functions as part of a sequential circuit, wherein the sequential circuit comprises a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer, wherein the first transistor comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a gate insulating layer, and a gate electrode, wherein the second transistor comprises a second semiconductor layer, a third conductive layer, and a fourth conductive layer, wherein the first insulating layer is provided on the first conductive layer, and the second conductive layer is provided on the first insulating layer, wherein the first insulating layer and the second conductive layer each comprise a first opening extending to the first conductive layer, wherein within the first opening, the first semiconductor layer is provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer, wherein the gate insulating layer is provided in contact with the upper surface of the first semiconductor layer, and the gate electrode is provided with the first opening and A semiconductor device comprising: a second insulating layer provided in contact with the upper surface of the gate insulating layer to include an overlapping region; a second insulating layer provided on the gate electrode to fill the first opening; a third conductive layer provided in contact with the second insulating layer and the gate electrode; a third insulating layer provided on the third conductive layer; a fourth conductive layer provided on the third insulating layer; the third insulating layer and the fourth conductive layer each include a second opening extending to the third conductive layer; within the second opening, the second semiconductor layer is provided in contact with the upper surface of the third conductive layer, the side of the third insulating layer, and the side of the fourth conductive layer; and the second insulating layer comprises an organic insulating material. Claim 2 A semiconductor device according to claim 1, wherein a fourth insulating layer is provided in a region on the gate insulating layer that does not overlap with the first opening, the third insulating layer is provided on the fourth insulating layer, and the fourth insulating layer comprises the same material as the second insulating layer. Claim 3 A semiconductor device according to claim 1 or 2, wherein the second insulating layer comprises one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins. Claim 4 A semiconductor device according to claim 1 or 2, wherein the first transistor comprises a back gate electrode, the back gate electrode is provided between the first conductive layer and the second conductive layer to include a region overlapping with each of the first conductive layer and the second conductive layer, and within the first opening, one side of the first semiconductor layer faces the gate electrode and the other side of the first semiconductor layer faces the back gate electrode. Claim 5 A semiconductor device according to claim 1, wherein at least one of the first semiconductor layer and the second semiconductor layer comprises a metal oxide, the metal oxide comprises two or three types selected from indium, element M, and zinc, the element M comprises one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium, and at least one of the first insulating layer and the third insulating layer comprises silicon oxide or silicon nitride. Claim 6 A semiconductor device according to claim 5, wherein the first insulating layer comprises a fifth insulating layer, a sixth insulating layer above the fifth insulating layer, and a seventh insulating layer above the sixth insulating layer, the third insulating layer comprises an eighth insulating layer, a ninth insulating layer above the eighth insulating layer, and a tenth insulating layer above the ninth insulating layer, wherein the fifth insulating layer, the seventh insulating layer, the eighth insulating layer, and the tenth insulating layer each comprise silicon nitride, silicon nitride oxide, hafnium oxide, or aluminum oxide, and the sixth insulating layer and the ninth insulating layer each comprise silicon oxide or silicon nitride oxide. Claim 7 A semiconductor device comprises a first transistor, a second transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer; the first transistor comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a first gate insulating layer, and a first gate electrode; the second transistor comprises a second semiconductor layer, a third conductive layer, a fourth conductive layer, a second gate insulating layer, and a second gate electrode; the first insulating layer is provided on the first conductive layer, and the second conductive layer is provided on the first insulating layer; the first insulating layer and the second conductive layer each comprise a first opening extending to the first conductive layer; within the first opening, the first semiconductor layer is provided in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer; and the first gate insulating layer is provided in contact with the first semiconductor layer A first gate electrode is provided in contact with the upper surface of the first gate insulating layer to include an area overlapping with the first opening, the second insulating layer is provided on the first gate electrode to fill the first opening, the third insulating layer is provided in contact with the upper surface of the second insulating layer, the side of the first gate electrode, and the upper surface of the first gate insulating layer, the third conductive layer is provided in contact with the upper surface of the third insulating layer, the fourth insulating layer is provided on the third conductive layer, the fourth conductive layer is provided on the fourth insulating layer, the fourth insulating layer and the fourth conductive layer each include a second opening extending to the third conductive layer, and within the second opening, the second semiconductor layer is provided in contact with the upper surface of the third conductive layer, the side of the fourth insulating layer, and the side of the fourth conductive layer, and the second gate insulating layer is provided in contact with the upper surface of the second semiconductor layer.A semiconductor device wherein the second gate electrode is provided in contact with the upper surface of the second gate insulating layer to include a region overlapping with the second opening, and the second insulating layer comprises an organic insulating material. Claim 8 A semiconductor device according to claim 7, wherein the first conductive layer and the third conductive layer are connected, the second conductive layer and the fourth conductive layer are connected, and the first gate electrode and the second gate electrode are connected. Claim 9 A semiconductor device according to claim 7, wherein the second conductive layer and the third conductive layer are connected, and the first gate electrode and the second gate electrode are connected. Claim 10 A semiconductor device according to claim 7, wherein a fifth insulating layer is provided in a region on the first gate insulating layer that does not overlap with the first opening, the fourth insulating layer is provided on the fifth insulating layer, and the fifth insulating layer comprises the same material as the second insulating layer. Claim 11 A semiconductor device according to claim 7 or 10, wherein the second insulating layer comprises one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins. Claim 12 A semiconductor device according to claim 7, wherein at least one of the first semiconductor layer and the second semiconductor layer comprises a metal oxide, the metal oxide comprises two or three types selected from indium, element M, and zinc, and the element M comprises one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium, and at least one of the first insulating layer and the fourth insulating layer comprises silicon oxide or silicon nitride. Claim 13 A semiconductor device according to claim 12, wherein the first insulating layer comprises a sixth insulating layer, a seventh insulating layer above the sixth insulating layer, and an eighth insulating layer above the seventh insulating layer, the fourth insulating layer comprises a ninth insulating layer, a tenth insulating layer above the ninth insulating layer, and an eleventh insulating layer above the tenth insulating layer, wherein the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each comprise silicon nitride, silicon nitride oxide, hafnium oxide, or aluminum oxide, and the seventh insulating layer and the tenth insulating layer each comprise silicon oxide or silicon nitride oxide.

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