Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. A semiconductor device according to one embodiment comprises a first transistor structure, a second transistor structure, and a connection structure. The first transistor structure comprises lower channel patterns, lower source / drain patterns located on both sides of the lower channel patterns, a lower gate electrode surrounding the lower channel patterns, a lower junction insulating layer located on the lower source / drain patterns and the lower gate electrode, and a lower contact structure located between the lower junction insulating layer and the lower source / drain patterns. The second transistor structure comprises an upper junction insulating layer located on the lower junction insulating layer, upper channel patterns located on the upper junction insulating layer, upper source / drain patterns located on both sides of the upper channel patterns and on the upper junction insulating layer, an upper gate electrode surrounding the upper channel patterns, and an upper contact structure located between the upper junction insulating layer and the upper source / drain patterns. The connection structure penetrates the lower junction insulating layer and the upper junction insulating layer to connect the lower contact structure and the upper contact structure. Connect electrically.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor device. Background Technology

[0002] A semiconductor is a material that falls within the intermediate range between conductors and insulators and conducts electricity under specific conditions. Various semiconductor devices can be manufactured using such materials, such as memory devices. These semiconductor devices can be used in a wide variety of electronic devices.

[0003] As the electronics industry develops to a high degree, demands regarding the characteristics of semiconductor devices are steadily increasing. For example, there is a growing demand for high reliability, high speed, and / or multifunctionality in semiconductor devices. To meet these required characteristics, the structures within semiconductor devices are becoming increasingly complex and integrated. The problem to be solved

[0004] The embodiments can improve the reliability of the semiconductor device. means of solving the problem

[0005] A semiconductor device according to one embodiment comprises a first transistor structure, a second transistor structure, and a connection structure, wherein the first transistor structure comprises lower channel patterns, lower source / drain patterns located on both sides of the lower channel patterns, a lower gate electrode surrounding the lower channel patterns, a lower junction insulating layer located on the lower source / drain patterns and the lower gate electrode, and a lower contact structure located between the lower junction insulating layer and the lower source / drain patterns, and the second transistor structure comprises an upper junction insulating layer located on the lower junction insulating layer, upper channel patterns located on the upper junction insulating layer, upper source / drain patterns located on both sides of the upper channel patterns and on the upper junction insulating layer, an upper gate electrode surrounding the upper channel patterns, and an upper contact structure located between the upper junction insulating layer and the upper source / drain patterns, and the connection structure penetrates the lower junction insulating layer and the upper junction insulating layer to electrically connect the lower contact structure and the upper contact structure.

[0006] A semiconductor device according to one embodiment comprises a first transistor structure, a second transistor structure, and a connection structure, wherein the first transistor structure comprises lower channel patterns, lower source / drain patterns located on both sides of the lower channel patterns, a lower gate electrode surrounding the lower channel patterns, a lower interlayer insulating layer located on the lower source / drain patterns, a lower junction insulating layer located on the lower interlayer insulating layer and the lower gate electrode, and a lower contact structure extending in a first direction and connected to the lower source / drain patterns through the lower interlayer insulating layer, and the second transistor structure comprises an upper junction insulating layer located on the lower junction insulating layer, upper channel patterns located on the upper junction insulating layer, an upper interlayer insulating layer located on the upper junction insulating layer, upper source / drain patterns located on both sides of the upper channel patterns and on the upper interlayer insulating layer, an upper gate electrode surrounding the upper channel patterns, and an upper contact extending in the first direction and connected to the upper source / drain patterns through the upper interlayer insulating layer. It includes a structure, wherein the connecting structure extends in a second direction intersecting the first direction to electrically connect the lower contact structure and the upper contact structure, and the connecting structure overlaps with the lower contact structure in the first direction and overlaps with the upper contact structure in the second direction.

[0007] A semiconductor device according to one embodiment comprises a first transistor structure, a second transistor structure, and a connection structure, wherein the first transistor structure comprises lower channel patterns, lower source / drain patterns located on both sides of the lower channel patterns, a lower gate electrode surrounding the lower channel patterns, a lower interlayer insulating layer located on the lower source / drain patterns, a lower junction insulating layer located on the lower interlayer insulating layer and the lower gate electrode, and a lower contact structure connected to the lower source / drain patterns by penetrating the lower interlayer insulating layer; the second transistor structure comprises an upper junction insulating layer located on the lower junction insulating layer, upper channel patterns located on the upper junction insulating layer, an upper interlayer insulating layer located on the upper junction insulating layer, upper source / drain patterns located on both sides of the upper channel patterns and on the upper interlayer insulating layer, an upper gate electrode surrounding the upper channel patterns, and an upper contact structure connected to the upper source / drain patterns by penetrating the upper interlayer insulating layer; and the connection structure comprises the lower contact The structure and the upper contact structure are electrically connected, and the length of the connection structure is less than or equal to the distance between the lower surface of the lower source / drain pattern and the upper surface of the upper source / drain pattern.

[0008] A method for manufacturing a semiconductor device according to one embodiment comprises the steps of: forming a second transistor structure comprising upper channel patterns, upper source / drain patterns located on both sides of the upper channel patterns, an upper gate electrode surrounding the upper channel patterns, an upper junction insulating layer located on the upper source / drain patterns and the upper gate electrode, and an upper contact structure located between the upper junction insulating layer and the upper source / drain patterns; forming a first transistor structure comprising a lower junction insulating layer located on the upper junction insulating layer, lower channel patterns located on the lower junction insulating layer, lower source / drain patterns located on both sides of the lower channel patterns and on the lower junction insulating layer, a lower gate electrode surrounding the lower channel patterns, and a lower contact structure located between the lower source / drain patterns and the lower junction insulating layer; forming a connection recess that penetrates the lower contact structure, the lower junction insulating layer, and the upper junction insulating layer to expose the upper contact structure; forming a connection structure material layer within the connection recess; and removing at least a portion of the connection structure material layer to form a connection structure It includes the step of forming, and the step of flipping the second transistor structure and the first transistor structure.

[0009] The above connection recess may not overlap with the above upper source / drain pattern.

[0010] The above connection recess can expose the side of the lower contact structure.

[0011] The step of forming the above-mentioned connection structure material layer may include the step of forming a second connection electrode material layer on the inner wall and bottom surface of the connection recess, and the step of forming a first connection electrode material layer on the second connection electrode material layer.

[0012] The second connecting electrode material layer may be located between the lower contact structure and the first connecting electrode material layer and between the upper contact structure and the first connecting electrode material layer.

[0013] The step of forming the above recess may include the step of removing at least a portion of the upper contact structure together.

[0014] The above connecting structure may overlap with the lower contact structure in a first direction and overlap with the upper contact structure in a second direction that intersects the first direction.

[0015] The lower contact structure and the upper contact structure are extended in the first direction, and the length of the lower contact structure along the first direction may be different from the length of the upper contact structure along the first direction.

[0016] The length of the above connection structure may be less than or equal to the distance between the lower surface of the lower source / drain pattern and the upper surface of the upper source / drain pattern.

[0017] The length of the above-mentioned connection structure may be greater than or equal to the distance between the lower contact structure and the upper contact structure. Effects of the invention

[0018] According to the embodiments, the reliability of the semiconductor device can be improved. Brief explanation of the drawing

[0019] FIG. 1 is a plan view showing a semiconductor device according to one embodiment. Figure 2 is a cross-sectional view taken along A-A' of Figure 1. Figure 3 is a cross-sectional view taken along B-B' of Figure 1. Figure 4 is a cross-sectional view taken along C-C' of Figure 1. FIG. 5 is a circuit diagram showing an application example of a semiconductor device according to one embodiment. FIGS. 6, FIGS. 7, FIGS. 8, FIGS. 9, FIGS. 10, and FIGS. 11 are cross-sectional views corresponding to B-B' of FIG. 1, showing semiconductor devices according to some embodiments. FIG. 12 is a cross-sectional view corresponding to A-A' of FIG. 1 showing a semiconductor device according to some embodiment. FIG. 13 is a cross-sectional view corresponding to A-A' in FIG. 1, showing an intermediate step of a method for manufacturing a semiconductor device according to one embodiment. FIG. 14 is a cross-sectional view corresponding to B-B' of FIG. 1, showing an intermediate step of a method for manufacturing a semiconductor device according to one embodiment. FIG. 15 is a cross-sectional view corresponding to A-A' of FIG. 1, showing an intermediate step of a method for manufacturing a semiconductor device according to one embodiment. FIGS. 16, 17, 18, 19, and 20 are cross-sectional views corresponding to B-B' of FIG. 1, showing an intermediate step of a method for manufacturing a semiconductor device according to one embodiment. FIG. 21 is a cross-sectional view corresponding to A-A' of FIG. 1, showing an intermediate step of a method for manufacturing a semiconductor device according to one embodiment. FIG. 22 is a cross-sectional view corresponding to B-B' of FIG. 1, showing an intermediate step of a method for manufacturing a semiconductor device according to one embodiment. Specific details for implementing the invention

[0020] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0021] To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are used for identical or similar components throughout the specification.

[0022] Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thicknesses have been enlarged in the drawings to clearly represent various layers and regions. Additionally, for convenience of explanation, the thickness of some layers and regions has been exaggerated in the drawings.

[0023] Furthermore, when it is said that a part, such as a layer, membrane, region, or plate, is "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when it is said that a part is "directly above" another part, it means that there is no other part in between. Also, saying that a part is "on" or "on" a reference part means that it is located above or below the reference part, and does not necessarily mean that it is located "on" or "on" in the direction opposite to gravity.

[0024] Additionally, throughout the specification, the terms “upper” or “lower” are relative concepts established from the observer’s perspective, and depending on the observer’s perspective, “upper” may mean “lower” and “lower” may mean “upper.”

[0025] Furthermore, throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0026] Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side.

[0027] In the drawing relating to a semiconductor device according to one embodiment, the device may, for example, be configured with a GAA (Gate All Around) or 3DSFET (3D Stack Field Effect Transistor) structure in which four sides of the channel are surrounded by gate electrodes. However, it is not limited thereto, and the transistor may be configured with a FinFET (Fin Field Effect Transistor) structure or an MBCFET TM It may also be composed of a Multi-Bridge Channel Field Effect Transistor (Multi-Bridge Channel Field Effect Transistor) structure, a Complementary Field Effect Transistor (CFET) structure, etc.

[0028] FIG. 1 is a plan view showing a semiconductor device according to one embodiment. FIG. 2 is a cross-sectional view taken along A-A' of FIG. 1. FIG. 3 is a cross-sectional view taken along B-B' of FIG. 1. FIG. 4 is a cross-sectional view taken along C-C' of FIG. 1.

[0029] Referring to FIGS. 1 to 4, a semiconductor device according to one embodiment may include a first transistor structure (TR1), a second transistor structure (TR2) located on the first transistor structure (TR1), and a connecting structure (300) connecting the first transistor structure (TR1) and the second transistor structure (TR2).

[0030] The first transistor structure (TR1) and the second transistor structure (TR2) can each function as a transistor. For example, the first transistor structure (TR1) and the second transistor structure (TR2) are each a GAA (Gate All Around) or MBCFET in which the four sides of the channel are surrounded by gate electrodes. TMIt may be composed of a Multi-Bridge Channel Field Effect Transistor structure, etc. However, it is not limited thereto, and each of the first transistor structure (TR1) and the second transistor structure (TR2) may be composed of a FinFET (Fin Field Effect Transistor) structure, a 3DSFET (3D Stack Field Effect Transistor) structure, etc. The first transistor structure (TR1) and the second transistor structure (TR2) may have different conductivity types. For example, the first transistor structure (TR1) may be a first conductivity type MOSFET, and the second transistor structure (TR2) may be a second conductivity type MOSFET. Here, the first conductivity type may be N-type and the second conductivity type may be P-type, but is not limited thereto.

[0031] The first transistor structure (TR1) and the second transistor structure (TR2) may be joined together. Each of the first transistor structure (TR1) and the second transistor structure (TR2) may be formed separately and have a structure joined together. For example, the first transistor structure (TR1) and the second transistor structure may be formed as a 3D-SFET (three-dimensional-stacked FET) structure stacked in a third direction (Z direction). The first transistor structure (TR1) and the second transistor structure (TR2) may have shapes that are symmetric to each other with respect to a reference axis extending in the first direction (X direction), but are not limited thereto. In a semiconductor device according to one embodiment, as the separately formed first transistor structure (TR1) and the second transistor structure (TR2) are joined together, the structure of the transistor can be designed in a relatively diverse manner, and the difficulty of the process can be reduced.

[0032] The first transistor structure (TR1) and the second transistor structure (TR2) can be electrically connected to each other. For example, a connection structure (300) can connect the first transistor structure (TR1) and the second transistor structure (TR2). The first transistor structure (TR1) and the second transistor structure (TR2) can be electrically connected to each other by the connection structure (300). In an exemplary embodiment, the first transistor structure (TR1) and the second transistor structure (TR2) are electrically connected to each other to perform functions such as a CMOS (Complementary MOSFET) or an inverter. A detailed description regarding this will be provided later in the description of the connection structure (300).

[0033] Below, the first transistor structure (TR1) will be described.

[0034] A first transistor structure (TR1) of a semiconductor device according to one embodiment may include lower channel patterns (140), a lower source / drain pattern (150) located above the lower channel patterns (140), a lower gate electrode (120) surrounding the lower channel patterns (140), a lower junction insulating layer (195) located above the lower source / drain pattern (150) and the lower gate electrode (120), and a lower contact structure (160) located between the lower junction insulating layer (195) and the lower source / drain pattern (150).

[0035] A first transistor structure (TR1) of a semiconductor device according to one embodiment may further include a lower pattern (110).

[0036] The lower pattern (110) may be formed as part of an insulating substrate. The lower pattern (110) may extend in a first direction (X direction). The lower pattern (110) may include various insulating materials. The lower pattern (110) may include oxides, nitrides, nitrates, or a combination thereof. For example, the lower pattern (110) may include silicon oxide (SiO2). The lower pattern (110) may be a pattern formed by removing the lower active pattern (111 in FIG. 13), which will be described later, and filling the removed space with insulating material.

[0037] A semiconductor device according to one embodiment may further include a first base insulating layer.

[0038] The first base insulating layer may be an insulating substrate. The first base insulating layer may include various insulating materials. The first base insulating layer may include an oxide, a nitride, a nitrate, or a combination thereof. For example, the first base insulating layer may include silicon oxide (SiO2). In one embodiment, the lower pattern (110) may be formed as part of the first base insulating layer. In one embodiment, a first transistor structure (TR1) may be provided on the first base insulating layer, but is not limited thereto. The upper and lower surfaces of the first base insulating layer (100) may be formed as planes parallel to a first direction (X direction) and a second direction (Y direction) that intersects the first direction (X direction). Here, the second direction (Y direction) may be a direction that intersects the first direction (X direction). In one embodiment, the second direction (Y direction) may be a direction that is orthogonal to the first direction (X direction).

[0039] Lower channel patterns (140) may be positioned above the lower pattern (110). Lower channel patterns (140) may be spaced apart from the lower pattern (110) in a third direction (Z direction). Each of the lower channel patterns (140) may be spaced apart in a third direction (Z direction). Here, the third direction (Z direction) may be a direction that intersects the first direction (X direction) and the second direction (Y direction). In one embodiment, the width of the lower channel patterns (140) along the first direction (X direction) may be substantially the same, but is not limited thereto. As another example, the width of the lower channel patterns (140) along the first direction (X direction) may be different.

[0040] The lower channel patterns (140) may include a semiconductor material. For example, the lower channel patterns (140) may include silicon (Si) or germanium (Ge), which are elemental semiconductor materials. The lower channel patterns (140) may be formed by etching a portion of the first substrate (101 in FIG. 13) or may include an epitaxial layer grown from the first substrate (101 in FIG. 13).

[0041] The lower channel patterns (140) may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. Here, the group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn). The group III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimonium (Sb). In one embodiment, the lower channel patterns (140) may include silicon (Si). As another example, the lower channel patterns (140) may include silicon germanium (SiGe).

[0042] In FIG. 2, two lower channel patterns (140) are shown stacked spaced apart in a third direction (Z direction), but this is not limited thereto. The number of lower channel patterns (140) can be varied.

[0043] As illustrated in FIGS. 3 and 4, a first transistor structure (TR1) of a semiconductor device according to one embodiment may further include a lower field insulating layer (105) located on both sides of a lower pattern (110).

[0044] The lower field insulating layer (105) may cover at least a portion of the side of the lower pattern (110). For example, as shown in FIGS. 3 and 4, the lower field insulating layer (105) may cover both sides of the lower pattern (110). The lower field insulating layer (105) may overlap the lower pattern (110) in a second direction (Y direction). Additionally, the lower field insulating layer (105) may not be located on the upper surface of the lower pattern (110). The lower field insulating layer (105) may include, for example, an oxide, a nitride, a nitrate, or a combination thereof. Although the lower field insulating layer (105) is depicted as a single film, this is for convenience of explanation only and is not limited thereto.

[0045] The lower source / drain pattern (150) may be positioned on the lower pattern (110). The lower source / drain pattern (150) may be positioned on at least one side of the lower channel patterns (140). For example, the lower source / drain pattern (150) may be positioned on both sides along the first direction (X direction) of the lower channel patterns (140). The lower source / drain pattern (150) may be in contact with the side of the lower channel patterns (140) and the upper surface of the lower pattern (110). The lower source / drain pattern (150) may be electrically connected to the lower channel patterns (140). The upper surface of the lower source / drain pattern (150) may be positioned at substantially the same level as the upper surface of the lower channel patterns (140), but is not limited thereto.

[0046] The lower source / drain pattern (150) may be epitaxial patterns formed by an optional epitaxial growth process using the lower channel patterns (140) and the lower active pattern (111 in FIG. 13) as seeds. The lower source / drain pattern (150) may include a semiconductor material. For example, the lower source / drain pattern (150) may include silicon (Si) or silicon germanium (SiGe). The lower source / drain pattern (150) may have a first conductivity type. The lower source / drain pattern (150) may be doped with a first conductivity type impurity. Here, the first conductivity type may be N-type, but is not limited thereto. For example, the lower source / drain pattern (150) may include P, Sb, As, or a combination thereof.

[0047] In FIGS. 2 to 4, the lower source / drain pattern (150) is described as being composed of a single layer, but is not limited thereto. As another example, the lower source / drain pattern (150) may be composed of a double layer containing a semiconductor material or may be composed of three or more layers.

[0048] The lower gate electrode (120) may be positioned over the lower pattern (110). The lower gate electrode (120) may extend in a second direction (Y direction). The lower gate electrode (120) may cross the lower pattern (110) in a plane. The lower gate electrode (120) may intersect the lower pattern (110) in a plane. For example, the lower gate electrode (120) may extend in a second direction (Y direction).

[0049] The lower gate electrode (120) can surround the lower channel patterns (140). For example, the lower gate electrode (120) can cover the side, bottom, and top surfaces along the second direction (Y direction) of each of the lower channel patterns (140). That is, the lower gate electrode (120) can completely surround the four sides of each of the lower channel patterns (140). Accordingly, the side, bottom, and top surfaces of the lower channel patterns (140) can each come into contact with the lower gate electrode (120). Lower source / drain patterns (150) can be located on both sides of the lower gate electrode (120). That is, the lower gate electrode (120) can be located between adjacent lower source / drain patterns (150) in the first direction (X direction).

[0050] A lower gate electrode (120) of a semiconductor device according to one embodiment may include a plurality of lower sub-gate electrodes (120S) and a lower main gate electrode (120M). The plurality of lower sub-gate electrodes (120S) may be located between lower channel patterns (140) adjacent in a third direction (Z direction) and between a lower pattern (110) and a lower channel pattern located at the bottom. The plurality of lower sub-gate electrodes (120S) may be adjacent to a lower source / drain pattern (150). The lower main gate electrode (120M) may be located on a lower channel pattern located at the top.

[0051] According to one embodiment, the number of a plurality of lower sub-gate electrodes (120S) may be proportional to the number of lower channel patterns (140) stacked in the third direction (Z direction). For example, the number of a plurality of lower sub-gate electrodes (120S) may be equal to the number of lower channel patterns (140) stacked in the third direction (Z direction). For example, as shown in FIG. 2, the number of a plurality of lower sub-gate electrodes (120S) may be two. However, this is not limited thereto, and the first transistor structure (TR1) may include three or more lower sub-gate electrodes (120S).

[0052] The lower gate electrode (120) may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal nitride. The lower gate electrode (120) is, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbide nitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbide nitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum It may include at least one of nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof, but is not limited thereto. Conductive metal oxides and conductive metal nitrides may include oxidized forms of the materials described above, but are not limited thereto.

[0053] A first transistor structure (TR1) of a semiconductor device according to one embodiment may further include a lower gate insulating layer surrounding a lower gate electrode (120).

[0054] The lower gate insulating layer may surround the lower sub-gate electrode (120S). The lower gate insulating layer may be located between the lower sub-gate electrode (120S) and the lower source / drain pattern (150), and between the lower sub-gate electrode (120S) and the lower channel patterns (140). Additionally, the lower gate insulating layer may be located between the lower main gate electrode (120M) and the lower channel pattern located at the top. The lower gate insulating layer may include various insulating materials. The lower gate insulating layer may be composed of a single layer or multiple layers. In this case, at least some layers of the lower gate insulating layer may include a high dielectric constant material. Here, the high dielectric constant material may be a material with a dielectric constant greater than that of silicon oxide (SiO2), such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO).

[0055] A semiconductor device according to one embodiment may further include a first gate spacer (142). The first gate spacer (142) may be located on the side of a lower gate electrode (120). For example, the first gate spacer (142) may be located between a lower main gate electrode (120M) and a lower interlayer insulating layer (190) to be described later. The first gate spacer (142) may not be located on the side of a plurality of lower sub-gate electrodes (120S).

[0056] The first gate spacer (142) may include various insulating materials. For example, the first gate spacer (142) may include silicon nitride (SiN). However, it is not limited thereto, and the first gate spacer (142) may include at least one of silicon nitride (SiN), silicon nitrate (SiON), silicon oxide (SiO2), silicon carbonate nitride (SiOCN), silicon boron nitride (SiBN), silicon oxalate nitride (SiOBN), silicon oxalate (SiOC), and combinations thereof. In FIG. 2, the first gate spacer (142) is shown as being composed of a single layer, but it is not limited thereto. For example, the first gate spacer (142) may be composed of multiple layers.

[0057] A semiconductor device according to one embodiment may further include a first capping layer (145) located on a lower gate electrode (120).

[0058] The first capping layer (145) may be positioned on the lower gate electrode (120). The first capping layer (145) may be positioned on the side of the first gate spacer (142), but is not limited thereto. In an exemplary embodiment, the first capping layer (145) may be positioned on the first gate spacer (142) and the lower gate electrode (120). The first capping layer (145) may include, for example, at least one of silicon nitride (SiN), silicon nitride oxide (SiON), silicon carbide nitride (SiCN), silicon carbonate nitride (SiOCN), and combinations thereof. The first capping layer (145) may include a material having an etch selectivity with respect to the lower interlayer insulating layer (190) described later.

[0059] A first transistor structure (TR1) of a semiconductor device according to one embodiment may further include a lower interlayer insulating layer (190) located over a lower source / drain pattern (150). The lower interlayer insulating layer (190) may not cover the upper surface of the lower gate electrode (120). The lower interlayer insulating layer (190) may be located over the side of the lower gate electrode (120). The lower interlayer insulating layer (190) may be located over the side of the first gate spacer (142). As illustrated in FIGS. 3 and 4, the lower interlayer insulating layer (190) may surround at least a portion of the lower source / drain pattern (150).

[0060] The lower interlayer insulating layer (190) may include, for example, at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon nitride (SiON), and a low dielectric constant material. Low-k materials include, for example, Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethyleyCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), and TriMethylSilyl Borate. (TMSB), DiAcetoxyDitertiaryButoSiloxane (DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polyimide nanofoams such as polypropylene oxide, CDO (Carbon Doped silicon Oxide), OSG (Organo Silicate) Glass), SiLK, Amorphous Fluorinated Carbon, silica aerogels, silica xerogels, It may include mesoporous silica or a combination thereof, but is not limited thereto.

[0061] A first transistor structure (TR1) of a semiconductor device according to one embodiment may further include a first etch stop layer (185) located between a lower interlayer insulating layer (190) and a lower source / drain pattern (150), and between a lower interlayer insulating layer (190) and a first gate spacer (142).

[0062] As illustrated in FIG. 2, the first etch stop layer (185) may be located on the side of the first gate spacer (142) and on the upper surface of the lower source / drain pattern (150). Additionally, as illustrated in FIG. 3 and FIG. 4, the first etch stop layer (185) may surround at least a portion of the lower source / drain pattern (150). The first etch stop layer (185) may be located on the lower field insulating layer (105). The first etch stop layer (185) may be located between the lower field insulating layer (105) and the lower interlayer insulating layer (190). The first etch stop layer (185) may comprise a material having an etch selectivity with respect to the lower interlayer insulating layer (190). Additionally, the first etch stop layer (185) may comprise a material having an etch selectivity with respect to the lower source / drain pattern (150). The first etching stop layer (185) may include, for example, at least one of silicon nitride (SiN), silicon nitrate (SiON), silicon carbonate nitride (SiOCN), silicon boron nitride (SiBN), silicon oxalo nitride (SiOBN), silicon oxalo nitride (SiOC), and combinations thereof.

[0063] The lower junction insulating layer (195) may be positioned over the lower source / drain pattern (150) and the lower gate electrode (120). The lower junction insulating layer (195) may be positioned over the lower interlayer insulating layer (190). Additionally, the lower junction insulating layer (195) may be positioned over the first gate spacer (142) and the first capping layer (145). The lower junction insulating layer (195) may be in contact with the upper surface of the lower interlayer insulating layer (190), the upper surface of the first gate spacer (142), and the upper surface of the first capping layer (145), but is not limited thereto.

[0064] The lower junction insulating layer (195) may include a first surface (195a) facing the second transistor structure (TR2) and a second surface opposite to the first surface (195a). The first surface (195a) of the lower junction insulating layer (195) may form a junction interface with the upper junction insulating layer (295) of the second transistor structure (TR2). The lower junction insulating layer (195) may be bonded to the upper junction insulating layer (295) of the second transistor structure (TR2).

[0065] The lower junction insulating layer (195) may include various insulating materials. For example, the lower junction insulating layer (195) may include silicon oxide (SiO2). However, it is not limited thereto, and as another example, the lower junction insulating layer (195) may include at least one of silicon nitride (SiN), silicon nitrate (SiON), silicon carbonate nitride (SiOCN), silicon boron nitride (SiBN), silicon oxalo nitride (SiOBN), silicon oxalo nitride (SiOC), and combinations thereof.

[0066] The lower contact structure (160) may be located between the lower bonding insulation layer (195) and the lower source / drain pattern (150). The lower contact structure (160) may be located on the lower source / drain pattern (150). The lower contact structure (160) may be connected to the lower source / drain pattern (150) by penetrating the lower interlayer insulation layer (190). At least a portion of the lower contact structure (160) may be located within the lower source / drain pattern (150). At least a portion of the lower contact structure (160) may be surrounded by the lower source / drain pattern (150), but is not limited thereto. At least a portion of the lower contact structure (160) may overlap with the lower channel patterns (140) in a first direction (X direction). The lower contact structure (160) may be electrically connected to the lower source / drain pattern (150). The lower contact structure (160) can be located between the lower source / drain pattern (150) and the upper source / drain pattern (250) to be described later.

[0067] As illustrated in FIG. 3, the lower contact structure (160) may be extended in a second direction (Y direction). The lower contact structure (160) may be extended parallel to the lower gate electrode (120). The lower contact structure (160) may overlap with the lower source / drain pattern (150) in a third direction (Z direction). The length of the lower contact structure (160) along the second direction (Y direction) may be greater than the length of the lower source / drain pattern (150) along the second direction (Y direction).

[0068] The lower contact structure (160) may include a first surface facing the lower junction insulating layer (195) and a second surface (160b) opposite to the first surface. The first surface of the lower contact structure (160) may be a surface facing the upper source / drain pattern (250) of the second transistor structure (TR2), and the second surface (160b) of the lower contact structure (160) may be a surface facing the lower source / drain pattern (150). The first surface of the lower contact structure (160) may refer to the upper surface of the lower contact structure (160), and the second surface (160b) of the lower contact structure (160) may refer to the lower surface of the lower contact structure (160), but is not limited thereto.

[0069] The second surface (160b) of the lower contact structure (160) may be in contact with the lower source / drain pattern (150). Additionally, at least a portion of the second surface (160b) of the lower contact structure (160) may be in contact with the lower interlayer insulation layer (190). The first surface of the lower contact structure (160) may be in contact with the lower bonding insulation layer (195).

[0070] The lower contact structure (160) may include a first lower contact electrode (161) and a second lower contact electrode (162) surrounding the first lower contact electrode (161). The first lower contact electrode (161) may be located between the lower interlayer insulating layer (190) and the lower bonding insulating layer (195). The upper surface of the first lower contact electrode (161) may be in contact with the lower bonding insulating layer (195). The second lower contact electrode (162) may cover the lower surface and side of the first lower contact electrode (161). The second lower contact electrode (162) may not be located on the upper surface of the first lower contact electrode (161).

[0071] The first lower contact electrode (161) and the second lower contact electrode (162) may include a conductive material. The first lower contact electrode (161) and the second lower contact electrode (162) may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. As an example, the first lower contact electrode (161) may include tungsten (W), molybdenum (Mo), or a combination thereof, and the second lower contact electrode (162) may include titanium nitride (TiN). As another example, the second lower contact electrode (162) may include at least one metal silicide film.

[0072] A first transistor structure (TR1) of a semiconductor device according to one embodiment may further include a lower penetration structure (180) that penetrates a lower pattern (110).

[0073] The lower penetration structure (180) may be positioned on the lower surface of the lower source / drain pattern (150). The lower penetration structure (180) may penetrate the lower pattern (110) and be connected to the lower source / drain pattern (150). The lower penetration structure (180) may extend in a second direction (Y direction). The lower penetration structure (180) may extend parallel to the lower contact structure (160). The lower penetration structure (180) may overlap with the lower source / drain pattern (150) in a third direction (Z direction). The length of the lower penetration structure (180) in the second direction (Y direction) may be greater than the length of the lower source / drain pattern (150) in the second direction (Y direction).

[0074] The lower through-hole structure (180) may include a first lower through-hole via (181) and a second lower through-hole via (182) surrounding the first lower through-hole via (181). The second lower through-hole via (182) may cover the upper surface and side surface of the first lower through-hole via (181).

[0075] The first lower through-via (181) and the second lower through-via (182) may include a conductive material. The first lower through-via (181) and the second lower through-via (182) may include the same material as the first lower contact electrode (161) and the second lower contact electrode (162). The first lower through-via (181) and the second lower through-via (182) may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material.

[0076] Below, we will describe the second transistor structure (TR2) located on the first transistor structure (TR1).

[0077] A second transistor structure (TR2) of a semiconductor device according to one embodiment may include an upper junction insulating layer (295) located on a lower junction insulating layer (195), upper channel patterns (240) located on the upper junction insulating layer (295), upper source / drain patterns (250) located on the upper junction insulating layer (295), an upper gate electrode (220) surrounding the upper channel patterns (240), and an upper contact structure (260) located between the upper junction insulating layer (295) and the upper source / drain patterns (250).

[0078] The upper junction insulating layer (295) may be positioned on the lower junction insulating layer (195). The upper junction insulating layer (295) may include a second surface (295b) facing the first transistor structure (TR1) and a first surface opposite to the second surface (295b). The second surface (295b) of the upper junction insulating layer (295) may form a junction interface with the first surface (195a) of the lower junction insulating layer (195). That is, the second surface (295b) of the upper junction insulating layer (295) may come into contact with the first surface (195a) of the lower junction insulating layer (195).

[0079] The upper junction insulating layer (295) may include various insulating materials. The upper junction insulating layer (295) may include the same material as the lower junction insulating layer (195). For example, the upper junction insulating layer (295) may include silicon oxide (SiO2). However, it is not limited thereto, and as another example, the upper junction insulating layer (295) may include at least one of silicon nitride (SiN), silicon nitrate (SiON), silicon carbonate nitride (SiOCN), silicon boron nitride (SiBN), silicon oxalo nitride (SiOBN), silicon oxalo nitride (SiOC), and combinations thereof.

[0080] The upper channel patterns (240) may be positioned on the upper bonding insulation layer (295). The upper channel patterns (240) may be spaced apart from the lower channel patterns (140) in a third direction (Z direction). Each of the upper channel patterns (240) may be spaced apart in a third direction (Z direction). In one embodiment, the width of the upper channel patterns (240) along the first direction (X direction) may be substantially the same, but is not limited thereto. As another example, the width of the upper channel patterns (240) along the first direction (X direction) may be different.

[0081] The upper channel patterns (240) may include a semiconductor material. The upper channel patterns (240) may include the same material as the lower channel patterns (140), but are not limited thereto. For example, the upper channel patterns (240) may include silicon (Si) or germanium (Ge), which are elemental semiconductor materials. The upper channel patterns (240) may be formed by etching a portion of the second substrate (201 in FIG. 13), or may include an epitaxial layer grown from the second substrate (201 in FIG. 13).

[0082] The upper channel patterns (240) may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. Here, the group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn). The group III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as a group III element with one of phosphorus (P), arsenic (As), and antimonium (Sb) as a group V element. In one embodiment, the upper channel patterns (240) may include silicon (Si). As another example, the upper channel patterns (240) may include silicon germanium (SiGe).

[0083] In FIG. 2, two upper channel patterns (240) are shown stacked spaced apart in a third direction (Z direction), but this is not limited thereto. The number of upper channel patterns (240) can be varied.

[0084] The upper source / drain pattern (250) may be located on the upper junction insulating layer (295). The upper source / drain pattern (250) may be located on at least one side of the upper channel patterns (240). For example, the upper source / drain pattern (250) may be located on both sides along the first direction (X direction) of the upper channel patterns (240). The upper source / drain pattern (250) may be in contact with the side of the upper channel patterns (240). The upper source / drain pattern (250) may be electrically connected to the upper channel patterns (240). The upper surface of the upper source / drain pattern (250) may be located at substantially the same level as the upper surface of the upper channel patterns (240), but is not limited thereto.

[0085] The upper source / drain pattern (250) may be positioned spaced apart from the lower source / drain pattern (150) in a third direction (Z direction). The upper source / drain pattern (250) may overlap with the lower source / drain pattern (150) in a third direction (Z direction). The side of the upper source / drain pattern (250) may be aligned with the side of the lower source / drain pattern (150), but is not limited thereto.

[0086] The upper source / drain pattern (250) may be epitaxial patterns formed by an optional epitaxial growth process using the upper channel patterns (240) and the upper active pattern (211 in FIG. 13) as seeds. The upper source / drain pattern (250) may include a semiconductor material. The upper source / drain pattern (250) may include the same material as the lower source / drain pattern (150). For example, the upper source / drain pattern (250) may include silicon (Si) or silicon germanium (SiGe). The upper source / drain pattern (250) may have a second conductivity type different from the first conductivity type. The upper source / drain pattern (250) may be doped with a second conductivity type impurity. Here, the second conductivity type may be P-type, but is not limited thereto. For example, the upper source / drain pattern (250) may include B, V, In, Ga, Al, or a combination thereof.

[0087] In FIGS. 2 to 4, the upper source / drain pattern (250) is described as being composed of a single layer, but is not limited thereto. As another example, the upper source / drain pattern (250) may be composed of a double layer containing a semiconductor material or may be composed of three or more layers.

[0088] The upper gate electrode (220) may be positioned on the upper junction insulating layer (295). The upper gate electrode (220) may extend in a second direction (Y direction). The upper gate electrode (220) may surround the upper channel patterns (240). For example, the upper gate electrode (220) may cover the side, top, and top surfaces along the second direction (Y direction) of each of the upper channel patterns (240). That is, the upper gate electrode (220) may completely surround each of the four sides of the upper channel patterns (240). Accordingly, the side, top, and top surfaces of the upper channel patterns (240) may each come into contact with the upper gate electrode (220). Upper source / drain patterns (250) may be positioned on both sides of the upper gate electrode (220). That is, the upper gate electrode (220) can be positioned between adjacent upper source / drain patterns (250) in the first direction (X direction).

[0089] According to one embodiment, the upper gate electrode (220) of a semiconductor device may include a plurality of upper sub-gate electrodes (220S) and an upper main gate electrode (220M). The plurality of upper sub-gate electrodes (220S) may be located between upper channel patterns (240) adjacent in a third direction (Z direction) and between the upper pattern (210) described later and the upper channel pattern located at the top. The plurality of upper sub-gate electrodes (220S) may be adjacent to an upper source / drain pattern (250). The upper main gate electrode (220M) may be located below the upper channel pattern located at the bottom.

[0090] According to one embodiment, the number of upper sub-gate electrodes (220S) may be proportional to the number of upper channel patterns (240) stacked in the third direction (Z direction). For example, as shown in FIG. 2, the number of upper sub-gate electrodes (220S) may be two. However, this is not limited thereto, and the second transistor structure (TR2) may include three or more upper sub-gate electrodes (220S).

[0091] The upper gate electrode (220) may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal nitride. The upper gate electrode (220) may include the same material as the lower gate electrode (120), but is not limited thereto.

[0092] A first transistor structure (TR1) of a semiconductor device according to one embodiment may further include an upper gate insulating layer surrounding an upper gate electrode (220).

[0093] The upper gate insulating layer may surround the upper sub-gate electrode (220S). The upper gate insulating layer may be located between the upper sub-gate electrode (220S) and the upper source / drain pattern (250), and between the upper sub-gate electrode (220S) and the upper channel patterns (240). Additionally, the upper gate insulating layer may be located between the upper main gate electrode (220M) and the upper channel pattern located at the bottom. The upper gate insulating layer may include various insulating materials. The upper gate insulating layer may be composed of a single layer or multiple layers. In this case, at least some layers of the upper gate insulating layer may include a high dielectric constant material. Here, the high dielectric constant material may be a material with a dielectric constant greater than that of silicon oxide (SiO2), such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO).

[0094] A semiconductor device according to one embodiment may further include a second gate spacer (242). The second gate spacer (242) may be located on the side of the upper gate electrode (220). For example, the second gate spacer (242) may be located between the upper main gate electrode (120M) and the upper interlayer insulating layer (290) to be described later. The second gate spacer (242) may not be located on the side of a plurality of upper sub-gate electrodes (120S).

[0095] The second gate spacer (242) may include various insulating materials. The second gate spacer (242) may include the same material as the first gate spacer (142), but is not limited thereto. For example, the second gate spacer (242) may include silicon nitride (SiN). However, it is not limited thereto, and the second gate spacer (242) may include at least one of silicon nitride (SiN), silicon nitrate (SiON), silicon oxide (SiO2), silicon carbonate nitride (SiOCN), silicon boron nitride (SiBN), silicon oxalo nitride (SiOBN), silicon oxalate (SiOC), and combinations thereof. In FIG. 2, the second gate spacer (242) is shown as being composed of a single layer, but is not limited thereto. For example, the second gate spacer (242) may be composed of multiple layers.

[0096] A semiconductor device according to one embodiment may further include a second capping layer (245) located between an upper gate electrode (220) and an upper junction insulating layer (295).

[0097] The second capping layer (245) may be located between the upper gate electrode (220) and the upper junction insulating layer (295). The second capping layer (245) may be located on the side of the second gate spacer (242), but is not limited thereto. The second capping layer (245) may include the same material as the first capping layer (145), but is not limited thereto. The second capping layer (245) may include, for example, at least one of silicon nitride (SiN), silicon nitrate (SiON), silicon carbide nitride (SiCN), silicon carbonate nitride (SiOCN), and combinations thereof. The second capping layer (245) may include a material having an etch selectivity with respect to the upper interlayer insulating layer (290) described later.

[0098] A second transistor structure (TR2) of a semiconductor device according to one embodiment may further include an upper interlayer insulating layer (290) located between an upper source / drain pattern (250) and an upper junction insulating layer (295).

[0099] The upper interlayer insulating layer (290) may be located between the upper source / drain pattern (250) and the upper junction insulating layer (295). The upper interlayer insulating layer (290) may not cover the lower surface of the upper gate electrode (220). The upper interlayer insulating layer (290) may be located on the side of the upper gate electrode (220). The upper interlayer insulating layer (290) may be located on the side of the second gate spacer (242). As illustrated in FIGS. 3 and 4, the upper interlayer insulating layer (290) may surround at least a portion of the upper source / drain pattern (250).

[0100] The upper interlayer insulating layer (290) may include the same material as the lower interlayer insulating layer (190). The upper interlayer insulating layer (290) may include, for example, at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon nitride (SiON), and a low dielectric constant material.

[0101] A second transistor structure (TR2) of a semiconductor device according to one embodiment may further include a second etch stop layer (285) located between an upper interlayer insulating layer (290) and an upper source / drain pattern (250), and between an upper interlayer insulating layer (290) and a second gate spacer (242).

[0102] As illustrated in FIG. 2, the second etch stop layer (285) may be located on the side of the second gate spacer (242) and on the lower surface of the upper source / drain pattern (250). Additionally, as illustrated in FIG. 3 and FIG. 4, the second etch stop layer (285) may surround at least a portion of the upper source / drain pattern (250). The second etch stop layer (285) may be located on the upper field insulating layer (205), which will be described later. The second etch stop layer (285) may be located between the upper field insulating layer (205) and the upper interlayer insulating layer (290). The second etch stop layer (285) may comprise the same material as the first etch stop layer (185), but is not limited thereto.

[0103] The upper contact structure (260) may be located between the upper bonding insulation layer (295) and the upper source / drain pattern (250). The upper contact structure (260) may be connected to the upper source / drain pattern (250) by penetrating the upper interlayer insulation layer (290). At least a portion of the upper contact structure (260) may be located within the upper source / drain pattern (250). At least a portion of the upper contact structure (260) may be surrounded by the upper source / drain pattern (250), but is not limited thereto. At least a portion of the upper contact structure (260) may overlap with the upper channel patterns (240) in a first direction (X direction). The upper contact structure (260) may be electrically connected to the upper source / drain pattern (250). The upper contact structure (260) may be located between the lower source / drain pattern (150) and the upper source / drain pattern (250). The upper contact structure (260) may be located between the lower contact structure (160) and the upper source / drain pattern (250).

[0104] As illustrated in FIG. 3, the upper contact structure (260) may be extended in a second direction (Y direction). The upper contact structure (260) may be extended parallel to the upper gate electrode (220). Additionally, the upper contact structure (260) may be extended parallel to the lower contact structure (160). The upper contact structure (260) may overlap with the upper source / drain pattern (250) in a third direction (Z direction). The length of the upper contact structure (260) in the second direction (Y direction) may be greater than the length of the upper source / drain pattern (250) in the second direction (Y direction).

[0105] The length of the upper contact structure (260) along the second direction (Y direction) may differ from the length of the lower contact structure (160) along the second direction (Y direction). For example, the length of the upper contact structure (260) along the second direction (Y direction) may be longer than the length of the lower contact structure (160) along the second direction (Y direction). This may be due to process characteristics in which, after forming the lower contact structure (160), at least a portion of the lower contact structure (160) is removed to form a connection recess (300R), and a connection structure (300) is formed within the connection recess (300R).

[0106] The upper contact structure (260) may include a first surface facing the upper source / drain pattern (250) and a second surface (260b) opposite to the first surface. The second surface (260b) of the upper contact structure (260) may be a surface facing the lower source / drain pattern (150). The first surface of the upper contact structure (260) may refer to the upper surface of the upper contact structure (260), and the second surface (260b) of the upper contact structure (260) may refer to the lower surface of the upper contact structure (260), but is not limited thereto.

[0107] A first surface of the upper contact structure (260) may be in contact with the upper source / drain pattern (250). Additionally, at least a portion of the first surface of the upper contact structure (260) may be in contact with the upper interlayer insulation layer (290). A second surface (260b) of the upper contact structure (260) may be in contact with the upper bonding insulation layer (295).

[0108] The upper contact structure (260) may include a first upper contact electrode (261) and a second upper contact electrode (262) surrounding the first upper contact electrode (261). The first upper contact electrode (261) may be located between the upper interlayer insulating layer (290) and the upper bonding insulating layer (295). The lower surface of the first upper contact electrode (261) may be in contact with the upper bonding insulating layer (295). The second upper contact electrode (262) may cover the upper surface and side of the first upper contact electrode (261). The second upper contact electrode (262) may not be located on the lower surface of the first upper contact electrode (261).

[0109] The first upper contact electrode (261) and the second upper contact electrode (262) may include a conductive material. The first upper contact electrode (261) and the second upper contact electrode (262) may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. As an example, the first upper contact electrode (261) may include tungsten (W), molybdenum (Mo), or a combination thereof, and the second upper contact electrode (262) may include titanium nitride (TiN). As another example, the second upper contact electrode (262) may include at least one metal silicide film.

[0110] A second transistor structure (TR2) of a semiconductor device according to one embodiment may further include an upper pattern (210) located on an upper source / drain pattern (250). The upper pattern (210) may be formed as part of an insulating substrate. The upper pattern (210) may extend in a first direction (X direction). The upper pattern (210) may include various insulating materials. The upper pattern (210) may include the same material as the lower pattern (110), but is not limited thereto. The upper pattern (210) may include an oxide, a nitride, a nitrate, or a combination thereof. For example, the upper pattern (210) may include silicon oxide (SiO2). The upper pattern (210) may be a pattern formed by removing the upper active pattern (211 in FIG. 13), which will be described later, and filling the removed space with an insulating material.

[0111] As illustrated in FIGS. 3 and 4, a second transistor structure (TR2) of a semiconductor device according to one embodiment may further include an upper field insulating layer (205) located on both sides of an upper pattern (210).

[0112] The upper field insulating layer (205) may cover at least a portion of the side of the upper pattern (210). For example, as shown in FIGS. 3 and 4, the upper field insulating layer (205) may cover both sides of the upper pattern (210). The upper field insulating layer (205) may overlap the upper pattern (210) in a second direction (Y direction). Additionally, the upper field insulating layer (205) may not be located on the lower surface of the upper pattern (210). The upper field insulating layer (205) may contain the same material as the lower field insulating layer (105), but is not limited thereto. The upper field insulating layer (205) may include, for example, an oxide, a nitride, a nitrate, or a combination thereof. Although the upper field insulating layer (205) is depicted as a single film, this is for convenience of explanation only and is not limited thereto.

[0113] A second transistor structure (TR2) of a semiconductor device according to one embodiment may further include an upper penetrating structure (280) penetrating an upper pattern (210).

[0114] The upper penetration structure (280) may be positioned on the upper surface of the upper source / drain pattern (250). The upper penetration structure (280) may penetrate the upper pattern (210) and be connected to the upper source / drain pattern (250). The upper penetration structure (280) may extend in a second direction (Y direction). The upper penetration structure (280) may extend parallel to the upper contact structure (260). The upper penetration structure (280) may overlap with the upper source / drain pattern (250) in a third direction (Z direction). The length of the upper penetration structure (280) in the second direction (Y direction) may be greater than the length of the upper source / drain pattern (250) in the second direction (Y direction).

[0115] The upper through-hole structure (280) may include a first upper through-hole via (281) and a second upper through-hole via (282) surrounding the first upper through-hole via (281). The second upper through-hole via (282) may cover the upper surface and side of the first upper through-hole via (281).

[0116] The first upper through-via (281) and the second upper through-via (282) may include a conductive material. The first upper through-via (281) may include the same material as the first lower through-via (181), and the second upper through-via (282) may include the same material as the second lower through-via (182). The first upper through-via (281) and the second upper through-via (282) may include the same material as the first upper contact electrode (261) and the second upper contact electrode (262). The first upper through-via (281) and the second upper through-via (282) may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material.

[0117] As illustrated in FIG. 3, a connection structure (300) of a semiconductor device according to one embodiment can connect between a first transistor structure (TR1) and a second transistor structure (TR2). For example, the connection structure (300) can connect between a lower contact structure (160) and an upper contact structure (260). Accordingly, through the connection structure (300), a lower source / drain pattern (150) connected to the lower contact structure (160) and an upper source / drain pattern (250) connected to the upper contact structure (260) can be electrically connected.

[0118] The connecting structure (300) may be positioned on the lower interlayer insulation layer (190). The connecting structure (300) may extend in a third direction (Z direction) through the upper bonding insulation layer (295) and the lower bonding insulation layer (195). The connecting structure (300) may be positioned within a connecting recess (300R) that penetrates the lower bonding insulation layer (195) and the upper bonding insulation layer (295) and recesses at least a portion of the lower interlayer insulation layer (190). The inner wall of the connecting recess (300R) may be defined by the upper bonding insulation layer (295), the lower bonding insulation layer (195), the lower contact structure (160), and the lower interlayer insulation layer (190). For example, one side wall along the second direction (Y direction) of the connection recess (300R) may be defined by an upper bonding insulation layer (295), a lower bonding insulation layer (195), and a lower contact structure (160), and the other side wall facing the one side wall of the connection recess (300R) may be defined by an upper bonding insulation layer (295), a lower bonding insulation layer (195), a lower contact structure (160), and a lower interlayer insulation layer (190). The bottom surface of the connection recess (300R) may be defined by an upper contact structure (260). The connection structure (300) may be in contact with the side of the lower contact structure (160) and the second surface (260b) of the upper contact structure (260).

[0119] The connection structure (300) may include a first surface (300a) facing the upper source / drain pattern (250) and a second surface (300b) opposite to the first surface (300a). The second surface (300b) of the connection structure (300) may be a surface facing the lower source / drain pattern (150). The first surface (300a) of the connection structure (300) may refer to the lower surface of the connection structure (300), and the second surface (300b) of the connection structure (300) may refer to the upper surface of the connection structure (300), but is not limited thereto.

[0120] The first surface (300a) of the connection structure (300) may be located at a lower level than the first surface of the upper contact structure (260). The first surface (300a) of the connection structure (300) may be located closer to the first surface (195a) of the lower bonding insulating layer (195) than to the first surface of the upper contact structure (260). The first surface (300a) of the connection structure (300) may be located at substantially the same level as the second surface (260b) of the upper contact structure (260), but is not limited thereto. An explanation regarding this will be provided later with reference to FIG. 6.

[0121] The second surface (300b) of the connection structure (300) may be located at a lower level than the first surface of the lower contact structure (160). The second surface (300b) of the connection structure (300) may be located further from the first surface (195a) of the lower bonding insulation layer (195) than the first surface of the lower contact structure (160). The second surface (300b) of the connection structure (300) may be located at substantially the same level as the second surface (160b) of the lower contact structure (160), but is not limited thereto. As another example, the second surface (300b) of the connection structure (300) may be located at a higher or lower level than the second surface (160b) of the lower contact structure (160). An explanation regarding this will be given later with reference to FIG. 10.

[0122] The length of the connecting structure (300) along the third direction (Z direction) may be greater than or equal to the distance along the third direction (Z direction) between the lower contact structure (160) and the upper contact structure (260). In other words, the length of the connecting structure (300) along the third direction (Z direction) may be greater than or equal to the distance along the third direction (Z direction) between the first surface of the lower contact structure (160) and the second surface (260b) of the upper contact structure (260). This may be due to process characteristics in which, after forming the lower contact structure (160) and the upper contact structure (260), at least a portion of the lower contact structure (160) is removed to form a connecting recess (300R), and the connecting structure (300) is formed within the connecting recess (300R). In this range, the length along the third direction (Z direction) of the connection structure (300) can be reduced, thereby preventing parasitic capacitance from occurring and improving the reliability of the semiconductor device.

[0123] In one embodiment, the connection structure (300) may be positioned spaced apart from the lower source / drain pattern (150) and the upper source / drain pattern (250). The connection structure (300) may not overlap with the lower source / drain pattern (150) and the upper source / drain pattern (250).

[0124] For example, the connecting structure (300) may be positioned spaced apart from the lower source / drain pattern (150) and the upper source / drain pattern (250) in a second direction (Y direction). Accordingly, the connecting structure (300) may not overlap with the lower source / drain pattern (150) and the upper source / drain pattern (250) in a third direction (Z direction), and may overlap with the lower interlayer insulation layer (190) and the upper interlayer insulation layer (290) in a third direction (Z direction). The connecting structure (300) may completely overlap with the lower interlayer insulation layer (190) and the upper interlayer insulation layer (290) in a third direction (Z direction), but is not limited thereto. This may be due to process characteristics in which, after forming the lower contact structure (160) and the upper contact structure (260), at least a portion of the lower contact structure (160) is removed to form a connection recess (300R), and a connection structure (300) is formed within the connection recess (300R). Accordingly, the lower source / drain pattern (150) and / or the upper source / drain pattern (250) can be prevented from deteriorating during the process of forming the connection structure (300).

[0125] Additionally, the connection structure (300) may be positioned spaced apart from the upper source / drain pattern (250) in a third direction (Z direction). Accordingly, the connection structure (300) may not overlap with the upper source / drain pattern (250) in a second direction (Y direction). The first surface (300a) of the connection structure (300) may be positioned at a lower level than the lower surface of the upper source / drain pattern (250). That is, the first surface (300a) of the connection structure (300) may be positioned closer to the first surface (195a) of the lower bonding insulation layer (195) than to the lower surface of the upper source / drain pattern (250).

[0126] The connection structure (300) may not overlap with the lower source / drain pattern (150) in a second direction (Y direction). The second surface (300b) of the connection structure (300) may be located at a higher level than the lower surface of the lower source / drain pattern (150). The second surface (300b) of the connection structure (300) may be located closer to the first surface (195a) of the lower bonding insulation layer (195) than to the lower surface of the lower source / drain pattern (150). The second surface (300b) of the connection structure (300) may be located at substantially the same level as the upper surface of the lower source / drain pattern (150). That is, the second surface (300b) of the connection structure (300) and the upper surface of the lower source / drain pattern (150) may be located at substantially the same distance from the first surface (195a) of the lower bonding insulation layer (195). However, this is not limited thereto, and as another example, the second surface (300b) of the connection structure (300) may be located closer to the first surface (195a) of the lower bonding insulation layer (195) than to the upper surface of the lower source / drain pattern (150). As yet another example, the second surface (300b) of the connection structure (300) may be located further from the first surface (195a) of the lower bonding insulation layer (195) than to the upper surface of the lower source / drain pattern (150). At least a portion of the connection structure (300) may overlap with the lower source / drain pattern (150) in the second direction (Y direction). An explanation regarding this will be provided later with reference to FIG. 10.

[0127] In summary, the connection structure (300) can be non-overlapping with the lower source / drain pattern (150) in the second direction (Y direction) and the third direction (Z direction), and can be non-overlapping with the upper source / drain pattern (250) in the second direction (Y direction) and the third direction (Z direction). Accordingly, the length of the connection structure (300) along the third direction (Z direction) may be less than or equal to the distance along the third direction (Z direction) between the lower surface of the lower source / drain pattern (150) and the upper surface of the upper source / drain pattern (250). Additionally, the length of the connection structure (300) along the third direction (Z direction) may be less than or equal to the distance along the third direction (Z direction) between the upper surface of the lower source / drain pattern (150) and the lower surface of the upper source / drain pattern (250). That is, the length along the third direction (Z direction) of the connection structure (300) may be less than or equal to the distance between the second surface (160b) of the lower contact structure (160) and the first surface of the upper contact structure (260). This may be due to process characteristics in which, after forming the lower contact structure (160) and the upper contact structure (260), at least a portion of the lower contact structure (160) is removed to form a connection recess (300R), and the connection structure (300) is formed within the connection recess (300R). Within this range, the length along the third direction (Z direction) of the connection structure (300) may be reduced, thereby preventing the occurrence of parasitic capacitance and improving the reliability of the semiconductor device.

[0128] The connection structure (300) may include a first connection electrode (310) and a second connection electrode (320) that surrounds at least a portion of the first connection electrode (310).

[0129] The second connecting electrode (320) may be located within the connecting recess (300R). The second connecting electrode (320) may be conformally positioned on the bottom surface and inner wall of the connecting recess (300R). The second connecting electrode (320) may be positioned on the upper surface and side surface of the first connecting electrode (310). The second connecting electrode (320) may cover the upper surface and side surface of the first connecting electrode (310).

[0130] The second connecting electrode (320) may be located between the first connecting electrode (310) and the lower contact structure (160), between the first connecting electrode (310) and the lower interlayer insulating layer (190), between the first connecting electrode (310) and the lower bonding insulating layer (195), between the first connecting electrode (310) and the upper bonding insulating layer (295), and between the first connecting electrode (310) and the upper contact structure (260).

[0131] The second connecting electrode (320) may come into contact with the side of the lower contact structure (160). For example, the second connecting electrode (320) may come into contact with the first lower contact electrode (161) and the second lower contact electrode (162) of the lower contact structure (160). Additionally, the second connecting electrode (320) may come into contact with the second surface (260b) of the upper contact structure (260). For example, the second connecting electrode (320) may come into contact with the first upper contact electrode (261) and the second upper contact electrode (262) of the upper contact structure (260).

[0132] The second connecting electrode (320) may include a conductive material. The second connecting electrode (320) may include the same material as the second upper contact electrode (262) and the second lower contact electrode (162). For example, the second connecting electrode (320) may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. As an example, the second connecting electrode (320) may include titanium nitride (TiN), but is not limited thereto. As another example, the second connecting electrode (320) may include at least one metal silicide film.

[0133] The first connecting electrode (310) can fill the remaining portion after the second connecting electrode (320) is formed within the connecting recess (300R). The first connecting electrode (310) can come into contact with the lower interlayer insulating layer (190). For example, the lower surface of the first connecting electrode (310) can come into contact with the lower interlayer insulating layer (190). This may be due to process characteristics in which, during the process of forming the connecting structure (300), after forming the first connecting electrode material layer (310P in FIG. 18) and the second connecting electrode material layer (320P in FIG. 18), at least a portion of the first connecting electrode material layer (310P in FIG. 18) and the second connecting electrode material layer (320P in FIG. 18) is removed to form the first connecting electrode (310) and the second connecting electrode (320).

[0134] The first connecting electrode (310) may include a conductive material. The first connecting electrode (310) may include the same material as the first upper contact electrode (261) and the first lower contact electrode (161). For example, the first connecting electrode (310) may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. As an example, the first connecting electrode (310) may include tungsten (W), molybdenum (Mo), or a combination thereof, but is not limited thereto.

[0135] In a semiconductor device according to one embodiment, a first transistor structure (TR1) and a second transistor structure (TR2) may be joined together. To connect the lower source / drain pattern (150) of the first transistor structure (TR1) and the upper source / drain pattern (250) of the second transistor structure (TR2), the semiconductor device may include a lower contact structure (160) located between the lower source / drain pattern (150) and the upper source / drain pattern (250), and a connection structure (300) connecting the upper contact structure (260) and the lower contact structure (160) and the upper contact structure (260). As the lower contact structure (160) and the upper contact structure (260) are positioned between the lower source / drain pattern (150) and the upper source / drain pattern (250), the distance along the third direction (Z direction) between the lower contact structure (160) and the upper contact structure (260) can be reduced, and the length along the third direction (Z direction) of the connection structure (300) can be reduced. Accordingly, the semiconductor device can prevent parasitic capacitance from occurring due to the connection structure (300) and can improve the reliability of the semiconductor device.

[0136] Additionally, the connection structure (300) may not overlap with the lower source / drain pattern (150) in the second direction (Y direction) and the third direction (Z direction), and may not overlap with the upper source / drain pattern (250) in the second direction (Y direction) and the third direction (Z direction). Accordingly, the deterioration of the lower source / drain pattern (150) and / or the upper source / drain pattern (250) can be prevented during the process of forming the connection structure (300).

[0137] Hereinafter, a semiconductor device according to one embodiment will be described with reference to FIG. 5.

[0138] FIG. 5 is a circuit diagram showing an application example of a semiconductor device according to one embodiment.

[0139] Referring to FIG. 5, a first transistor structure (TR1) and a second transistor structure (TR2) of a semiconductor device according to one embodiment can be connected to each other by a connection structure (300). The first transistor structure (TR1) may have a first conductivity type, and the second transistor structure (TR2) may have a second conductivity type.

[0140] The first transistor structure (TR1) may include a source electrode (S1), a drain electrode (D1), and a gate electrode (G1). The drain electrode (D2) of the second transistor structure (TR2) may be connected to the drain electrode (D2) of the second transistor structure (TR2). The gate electrode (G1) of the first transistor structure (TR1) may be connected to the gate electrode (G2) of the second transistor structure (TR2). Additionally, an input signal (Vin) may be applied to the gate electrode (G1) of the first transistor structure (TR1), and a first power supply voltage (VSS) may be applied to the source electrode (S1) of the first transistor structure (TR1). The first power supply voltage (VSS) may be, for example, a ground voltage.

[0141] The second transistor structure (TR2) may include a source electrode (S2), a drain electrode (D2), and a gate electrode (G2). The drain electrode (D2) of the second transistor structure (TR2) may be connected to the drain electrode (D2) of the second transistor structure (TR2). The gate electrode (G2) of the second transistor structure (TR2) may be connected to the gate electrode (G1) of the first transistor structure (TR1). Additionally, an input signal (Vin) may be applied to the gate electrode (G2) of the second transistor structure (TR2), and a second power supply voltage (VDD) may be applied to the source electrode (S2) of the second transistor structure (TR2). The second power supply voltage (VDD) may be greater than, for example, the first power supply voltage (VSS).

[0142] In the embodiment of FIG. 5, the source electrode (S1) and drain electrode (D1) of the first transistor structure (TR1) may correspond to the lower source / drain pattern (150) of the embodiment of FIG. 1 to 4, and the gate electrode (G1) of the first transistor structure (TR1) may correspond to the lower gate electrode (120) of the embodiment of FIG. 1 to 4. Additionally, the source electrode (S2) and drain electrode (D2) of the second transistor structure (TR2) may correspond to the upper source / drain pattern (250) of the embodiment of FIG. 1 to 4, and the gate electrode (G2) of the second transistor structure (TR2) may correspond to the upper gate electrode (220) of the embodiment of FIG. 1 to 4.

[0143] In a semiconductor device according to one embodiment, an input signal (Vin) can be applied to the gate electrode (G1) of a first transistor structure (TR1) and the gate electrode (G2) of a second transistor structure (TR2). At this time, since the drain electrode (D1) of the first transistor structure (TR1) and the drain electrode (D2) of the second transistor structure (TR2) are connected to each other by a connection structure (300), an output signal (Vout) can be output to the drain electrode (D1) of the first transistor structure (TR1) and the drain electrode (D2) of the second transistor structure (TR2), and accordingly, the semiconductor device can perform the function of a CMOS inverter.

[0144] Hereinafter, a stacked structure of a semiconductor device according to several embodiments will be described with reference to FIGS. 6 to 12.

[0145] FIGS. 6, 7, 8, 9, 10, and 11 are cross-sectional views corresponding to B-B' of FIG. 1 showing a semiconductor device according to some embodiment. FIG. 12 is a cross-sectional view corresponding to A-A' of FIG. 1 showing a semiconductor device according to some embodiment.

[0146] Since the embodiments illustrated in FIGS. 6 to 12 have substantial identical parts to the embodiments illustrated in FIGS. 1 to 4, the description thereof is omitted, and the differences are described in detail.

[0147] Referring to FIG. 6, a connection structure (300) of a semiconductor device according to some embodiments may be located within an upper contact structure (260). The connection structure (300) may include a portion that overlaps with the upper contact structure (260) in a second direction (Y direction). At least a portion of the connection structure (300) may be embedded within the upper contact structure (260). A first surface (300a) and a portion of the side of the connection structure (300) may be surrounded by the upper contact structure (260). Accordingly, the bonding area between the connection structure (300) and the upper contact structure (260) may be increased. At least a portion of the connection structure (300) may overlap with the upper contact structure (260) in a second direction (Y direction). The first surface (300a) of the connection structure (300) may be located at a higher level than the second surface (260b) of the upper contact structure (260). That is, the first surface (300a) of the connection structure (300) may be located further from the first surface (195a) of the lower bonding insulation layer (195) than the second surface (260b) of the upper contact structure (260).

[0148] Referring to FIGS. 7 and 8, a connection structure (300) of a semiconductor device according to some embodiments may include an extension (311) extending in a third direction (Z direction) and a protrusion (312) protruding in a second direction (Y direction) toward a lower contact structure (160).

[0149] The extension (311) may extend in a third direction (Z direction) through the upper bonding insulation layer (295) and the lower bonding insulation layer (195). The extension (311) may be connected to the upper contact structure (260). The upper surface of the extension (311) may be in contact with the upper contact structure (260).

[0150] The protrusion (312) may protrude in a second direction (Y direction) from one side of the extension (311). The protrusion (312) may be located within a recess (300E) located within the lower contact structure (160). The recess (300E) may be defined by the lower contact structure (160). The protrusion (312) may not overlap with the lower source / drain pattern (150) and the upper source / drain pattern (250) in a third direction (Z direction). The side of the protrusion (312) may have various shapes. For example, as shown in FIG. 7, the side of the protrusion (312) may extend in a third direction (Z direction). As another example, as shown in FIG. 8, the side of the protrusion (312) may have a convex curved shape toward the lower contact structure (160).

[0151] Referring to FIG. 9, a portion of the connection structure (300) of a semiconductor device according to some embodiments may not overlap with the upper contact structure (260) in a third direction (Z direction). For example, a portion of the connection structure (300) may overlap with the upper contact structure (260) in a third direction (Z direction), and the remaining portion may not overlap with the upper contact structure (260) in a third direction (Z direction). The remaining portion of the connection structure (300) may overlap with the upper interlayer insulating layer (290) in a third direction (Z direction). A portion of the connection structure (300) may be in contact with the upper contact structure (260), and the remaining portion may be in contact with the upper interlayer insulating layer (290).

[0152] Referring to FIG. 10, a connection structure (300) of a semiconductor device according to some embodiments may overlap with a lower source / drain pattern (150) in a second direction (Y direction). For example, the connection structure (300) may extend further toward the lower pattern (110) from the second surface (160b) of the lower contact structure (160). The second surface (300b) of the connection structure (300) may be located at a lower level than the second surface (160b) of the lower contact structure (160). That is, the second surface (300b) of the connection structure (300) may be located further from the first surface (195a) of the lower junction insulating layer (195) than the second surface (160b) of the lower contact structure (160). Accordingly, the second surface (300b) of the connection structure (300) may be located further from the first surface (195a) of the lower bonding insulation layer (195) than the upper surface of the lower source / drain pattern (150). However, even in this case, the second surface (300b) of the connection structure (300) may be located closer from the first surface (195a) of the lower bonding insulation layer (195) than the lower surface of the lower source / drain pattern (150).

[0153] Referring to FIG. 11, a semiconductor device according to some embodiments may further include an insulating pattern (350) located on a second surface (300b) of a connection structure (300).

[0154] The insulating pattern (350) may extend in a third direction (Z direction). The insulating pattern (350) may penetrate the lower interlayer insulating layer (190), the first etch stop layer (185), and the lower field insulating layer (105). The insulating pattern (350) may overlap with the connection structure (300) in the third direction (Z direction). The insulating pattern (350) may overlap with the lower source / drain pattern (150) and the lower pattern (110) in the second direction (Y direction). The insulating pattern (350) may be a pattern formed by forming a connection structure material layer (300P in FIG. 18) within a connection recess (300R) during the process of forming the connection structure (300), and then forming an insulating material layer within the removed space after removing at least a portion of the connection structure material layer (30 in FIG. 18).

[0155] The insulation pattern (350) may include various insulating materials. The insulation pattern (350) may include the same material as the lower interlayer insulation layer (190) and the lower field insulation layer (105), but is not limited thereto, and may include a material different from the lower interlayer insulation layer (190) and the lower field insulation layer (105). For example, the insulation pattern (350) may include at least one of silicon nitride (SiN), silicon nitrate (SiON), silicon oxide (SiO2), silicon carbonate nitride (SiOCN), silicon boron nitride (SiBN), silicon oxalo nitride (SiOBN), silicon oxalo nitride (SiOC), and combinations thereof.

[0156] Referring to FIG. 12, a semiconductor device according to some embodiments may include a plurality of lower through-hole structures (180_1, 180_2) and a plurality of upper through-hole structures (280_1, 280_2). For example, a semiconductor device according to some embodiments may include a first lower through-hole structure (180_1) connected to a lower source / drain pattern (150) that is not connected to a lower contact structure (160), and a second lower through-hole structure (180_2) connected to a lower source / drain pattern (150) connected to a lower contact structure (160). Additionally, a semiconductor device according to some embodiments may include a first upper through-hole structure (280_1) connected to an upper source / drain pattern (250) that is not connected to an upper contact structure (260), and a second upper through-hole structure (280_2) connected to an upper source / drain pattern (250) connected to an upper contact structure (260).

[0157] However, this is merely illustrative, and a plurality of lower penetration structures (180_1, 180_2) may be connected to at least one of a plurality of lower source / drain patterns (150), and a plurality of upper penetration structures (280_1, 280_2) may be connected to at least one of a plurality of upper source / drain patterns (250).

[0158] Hereinafter, a method for manufacturing a semiconductor device according to one embodiment will be described with reference to FIGS. 13 to 22.

[0159] FIG. 13 is a cross-sectional view corresponding to A-A' in FIG. 1, showing an intermediate step of a method for manufacturing a semiconductor device according to one embodiment. FIG. 14 is a cross-sectional view corresponding to B-B' in FIG. 1, showing an intermediate step of a method for manufacturing a semiconductor device according to one embodiment. FIG. 15 is a cross-sectional view corresponding to A-A' in FIG. 1, showing an intermediate step of a method for manufacturing a semiconductor device according to one embodiment. FIG. 16, FIG. 17, FIG. 18, FIG. 19, and FIG. 20 are cross-sectional views corresponding to B-B' in FIG. 1, showing an intermediate step of a method for manufacturing a semiconductor device according to one embodiment. FIG. 21 is a cross-sectional view corresponding to A-A' in FIG. 1, showing an intermediate step of a method for manufacturing a semiconductor device according to one embodiment. FIG. 22 is a cross-sectional view corresponding to B-B' in FIG. 1, showing an intermediate step of a method for manufacturing a semiconductor device according to one embodiment.

[0160] As shown in FIGS. 13 and 14, a second transistor structure (TR2) and a first transistor structure (TR1) can be formed, and the first transistor structure (TR1) can be joined on the second transistor structure (TR2).

[0161] The second transistor structure (TR2) may include a second substrate (201), upper channel patterns (240) located on the second substrate (201), upper source / drain patterns (250) located on both sides along a first direction (X direction) of the upper channel patterns (240), an upper gate electrode (220) surrounding the upper channel patterns (240), an upper junction insulating layer (295) located on the upper source / drain patterns (250), and an upper contact structure (260) located between the upper junction insulating layer (295) and the upper source / drain patterns (250).

[0162] The second substrate (201) may be silicon-on-insulator (SOI) or bulk silicon. Alternatively, the second substrate (201) may be a silicon substrate or may include other materials, such as silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto. The upper contact structure (260) may extend in a second direction (Y direction).

[0163] The second transistor structure (TR2) may further include an upper active pattern (211) located between the second substrate (201) and the upper channel patterns (240) and between the second substrate (201) and the upper source / drain pattern (250). The second transistor structure (TR2) may further include an upper field insulating layer (205) located on the second substrate (201). The upper field insulating layer (205) may be located on both sides along the second direction (Y direction) of the upper channel patterns (240).

[0164] The second transistor structure (TR2) may further include an upper dummy source / drain pattern (286) located on the lower surface of the upper source / drain pattern (250). The upper dummy source / drain pattern (286) may be located on the second substrate (201). The upper dummy source / drain pattern (286) may be in contact with the upper source / drain pattern (250). The second transistor structure (TR2) may further include an upper interlayer insulating layer (290) located between the upper source / drain pattern (250) and the upper junction insulating layer (295). The upper interlayer insulating layer (290) may be penetrated by the upper contact structure (260). The remaining description of each component of the second transistor structure (TR2) may correspond to the description of each component of the second transistor structure (TR2) of the embodiment of FIGS. 1 to 4.

[0165] The first transistor structure (TR1) may include a lower junction insulating layer (195) located on top of an upper junction insulating layer (295), lower channel patterns (140) located on top of the lower junction insulating layer (195), lower source / drain patterns (150) located on top of the lower junction insulating layer (195) and located on both sides along a first direction (X direction) of the lower channel patterns (140), a lower gate electrode (120) surrounding the lower channel patterns (140), and a lower contact structure (160) located between the lower source / drain patterns (150) and the lower junction insulating layer (195).

[0166] The lower contact structure (160) can be extended in a second direction (Y direction). The lower contact structure (160) can be extended parallel to the upper contact structure (260).

[0167] The first transistor structure (TR1) may further include a lower active pattern (111) located on the lower source / drain pattern (150) and the lower gate electrode (120). The lower active pattern (111) may include the same material as the upper active pattern (211), but is not limited thereto.

[0168] The first transistor structure (TR1) may further include a first substrate (101) positioned on the lower active pattern (111). The first substrate (101) may be silicon-on-insulator (SOI) or bulk silicon. Alternatively, the first substrate (101) may be a silicon substrate or may include other materials, such as silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto. The upper contact structure (260) may extend in a second direction (Y direction).

[0169] The first transistor structure (TR1) may further include a lower interlayer insulating layer (190) located between the lower source / drain pattern (150) and the lower junction insulating layer (195). The lower interlayer insulating layer (190) may be penetrated by the lower contact structure (160).

[0170] The first transistor structure (TR1) may further include a lower dummy source / drain pattern (186) located above the upper source / drain pattern (250). The lower dummy source / drain pattern (186) may be located between the lower source / drain pattern (150) and the first substrate (101). The lower dummy source / drain pattern (186) may be in contact with the lower source / drain pattern (150).

[0171] The first transistor structure (TR1) may further include a lower field insulating layer (105) located on the lower interlayer insulating layer (190). The lower field insulating layer (105) may be located between the lower interlayer insulating layer (190) and the first substrate (101). The lower field insulating layer (105) may be located on both sides along the second direction (Y direction) of the lower channel patterns (140). The remaining description of each component of the first transistor structure (TR1) may correspond to the description of each component of the first transistor structure (TR1) of the embodiment of FIGS. 1 to 4.

[0172] A first transistor structure (TR1) and a second transistor structure (TR2) can be joined. An upper junction insulating layer (295) of the second transistor structure (TR2) and a lower junction insulating layer (195) of the first transistor structure (TR1) can be joined. Accordingly, the second surface (295b) of the upper junction insulating layer (295) and the first surface (195a) of the lower junction insulating layer (195) can form a junction interface.

[0173] As illustrated in FIGS. 15 and 16, the first substrate (101) and the lower active pattern (111) can be removed, and the lower pattern (110) can be formed. After removing the lower dummy source / drain pattern (186), a lower through-structure (180) can be formed in the removed space.

[0174] First, the first substrate (101) and the lower active pattern (111) can be removed, and a lower pattern (110) can be formed. The process of removing the first substrate (101) and the lower active pattern (111) can be carried out using chemical mechanical flashing and wet etching methods, but is not limited thereto. The lower pattern (110) can be formed in the space where the lower active pattern (111) has been removed. The lower pattern (110) may include various insulating materials. For example, the lower pattern (110) may include silicon oxide (SiO2), but is not limited thereto. Accordingly, the upper surface of the lower dummy source / drain pattern (186) may be exposed.

[0175] Next, the exposed lower dummy source / drain pattern (186) can be removed. The process of removing the lower dummy source / drain pattern (186) may be performed using a wet etching method or a dry etching method, but is not limited thereto. Accordingly, the lower source / drain pattern (150) can be exposed.

[0176] Next, a lower through-hole structure (180) can be formed within the space from which the lower dummy source / drain pattern (186) has been removed. A lower through-hole structure (180) can be formed by sequentially forming a second lower through-hole via (182) and a first lower through-hole via (181) within the space from which the lower dummy source / drain pattern (186) has been removed. The first lower through-hole via (181) and the second lower through-hole via (182) may include a conductive material. The first lower through-hole via (181) and the second lower through-hole via (182) may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The lower through-hole structure (180) may come into contact with the lower source / drain pattern (150). The lower through-structure (180) can be connected to the lower source / drain pattern (150).

[0177] As shown in FIG. 17, a connection recess (300R) can be formed by patterning the lower field insulation layer (105), the lower interlayer insulation layer (190), the lower contact structure (160), the lower bonding insulation layer (195), and the upper bonding insulation layer (295).

[0178] Specifically, the lower contact structure (160) can be exposed by first patterning the lower field insulating layer (105), the second etch stop layer (285), and the lower interlayer insulating layer (190). The process of patterning the lower field insulating layer (105), the second etch stop layer (285), and the lower interlayer insulating layer (190) can be performed using a dry etching method, but is not limited thereto. Next, at least a portion of the exposed lower contact structure (160) can be etched to expose the lower bond insulating layer (195). At least a portion of the lower contact structure (160) can be etched using a material having an etch selectivity ratio for the lower field insulating layer (105), the second etch stop layer (285), and the lower interlayer insulating layer (190). Accordingly, during the process of etching at least a portion of the lower contact structure (160), the lower field insulating layer (105), the second etch stop layer (285), and the lower interlayer insulating layer (190) may not be etched. Finally, the exposed lower junction insulating layer (195) and the upper junction insulating layer (295) may be sequentially patterned to form a connection recess (300R). The connection recess (300R) may extend in a third direction (Z direction).

[0179] The inner wall of the connection recess (300R) may be defined by an upper bonding insulation layer (295), a lower bonding insulation layer (195), a lower contact structure (160), and a lower interlayer insulation layer (190). For example, one side wall along the second direction (Y direction) of the connection recess (300R) may be defined by an upper bonding insulation layer (295), a lower bonding insulation layer (195), and a lower contact structure (160), and the other side wall facing the one side wall of the connection recess (300R) may be defined by an upper bonding insulation layer (295), a lower bonding insulation layer (195), a lower contact structure (160), and a lower interlayer insulation layer (190). The bottom surface of the connection recess (300R) may be defined by an upper contact structure (260).

[0180] A second side (260b) of the upper contact structure (260) may be exposed by the connection recess (300R). A side of the lower contact structure (160) may be exposed by the connection recess (300R). The connection recess (300R) may not overlap with the upper source / drain pattern (250) in a second direction (Y direction). The connection recess (300R) may not overlap with the upper source / drain pattern (250) and the lower source / drain pattern (150) in a third direction (Z direction).

[0181] As the connection recess (300R) is formed, the length along the second direction (Y direction) of the lower contact structure (160) may differ from the length along the second direction (Y direction) of the upper contact structure (260). For example, the length along the second direction (Y direction) of the lower contact structure (160) may be shorter than the length along the second direction (Y direction) of the upper contact structure (260).

[0182] In some embodiments, at least a portion of the upper contact structure (260) may be removed together during the process of forming the connection recess (300R). That is, at least a portion of the connection recess (300R) may be surrounded by the upper contact structure (260). In this case, the connection recess (300R) may be formed within the upper contact structure (260).

[0183] As illustrated in FIG. 18, a connecting structure material layer (300P) can be formed within a connecting recess (300R). First, a second connecting electrode material layer (320P) can be formed on the inner wall and bottom surface of the connecting recess (300R). The second connecting electrode material layer (320P) can be formed conformally on the inner wall and bottom surface. The second connecting electrode material layer (320P) may include a conductive material. For example, the second connecting electrode material layer (320P) may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. As an example, the second connecting electrode material layer (320P) may include titanium nitride (TiN), but is not limited thereto. As another example, the second connecting electrode material layer (320P) may include at least one metal silicide film.

[0184] Next, a first connecting electrode material layer (310P) can be formed on a second connecting electrode material layer (320P) to fill the connecting recess (300R), thereby forming a connecting structure material layer (300P). Accordingly, the second connecting electrode material layer (320P) may be located between the lower contact structure (160) and the first connecting electrode material layer (310P), and between the upper contact structure (260) and the first connecting electrode material layer (310P). The first connecting electrode material layer (310P) may include a conductive material. For example, the first connecting electrode material layer (310P) may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. For example, the first connecting electrode material layer (310P) may include tungsten (W), molybdenum (Mo), or a combination thereof, but is not limited thereto.

[0185] The connecting structure material layer (300P) may extend in a third direction (Z direction). The connecting structure material layer (300P) may not overlap with the upper source / drain pattern (250) in a second direction (Y direction). The connecting structure material layer (300P) may not overlap with the upper source / drain pattern (250) and the lower source / drain pattern (150) in a third direction (Z direction).

[0186] As illustrated in FIG. 19, a connection structure (300) can be formed by removing at least a portion of the connection structure material layer (300P). A connection structure (300) can be formed by removing the portion of the connection structure material layer (300P) located on the upper side of the connection recess (300R).

[0187] The connecting structure (300) may be located between the lower interlayer insulation layer (190) and the upper contact structure (260). The connecting structure (300) may be located on the second surface (260b) of the upper contact structure (260). The connecting structure (300) may be located on the side of the lower contact structure (160). The connecting structure (300) may overlap with the lower contact structure (160) in a first direction (X direction). The connecting structure (300) may overlap with the lower contact structure (160) in a second direction (Y direction). The connecting structure (300) may not overlap with the lower contact structure (160) in a third direction (Z direction), but is not limited thereto. Additionally, the connecting structure (300) may overlap with the upper contact structure (260) in a third direction (Z direction). The connecting structure (300) may be non-overlapping with the upper contact structure (260) in the second direction (Y direction), but is not limited thereto.

[0188] The connection structure (300) may include a first surface (300a) facing the upper source / drain pattern (250) and a second surface (300b) opposite to the first surface (300a). The second surface (300b) of the connection structure (300) may be a surface facing the lower source / drain pattern (150). The first surface (300a) of the connection structure (300) may refer to the lower surface of the connection structure (300), and the second surface (300b) of the connection structure (300) may refer to the upper surface of the connection structure (300), but is not limited thereto.

[0189] The first surface (300a) of the connection structure (300) may be located closer to the first surface (195a) of the lower bonding insulation layer (195) than the first surface of the upper contact structure (260). The first surface (300a) of the connection structure (300) and the second surface (260b) of the upper contact structure (260) may be located at substantially the same distance from the first surface (195a) of the lower bonding insulation layer (195). The second surface (300b) of the connection structure (300) may be located further from the first surface (195a) of the lower bonding insulation layer (195) than the first surface of the lower contact structure (160). The second surface (300b) of the connection structure (300) and the second surface (160b) of the lower contact structure (160) may be located at substantially the same distance from the first surface (195a) of the lower bonding insulation layer (195), but are not limited thereto. For example, if the connection structure material layer (300P) is less removed, as in the embodiment of FIG. 10, the second surface (300b) of the connection structure (300) may be located further from the first surface (195a) of the lower bonding insulation layer (195) than the second surface (160b) of the lower contact structure (160).

[0190] The length of the connecting structure (300) along the third direction (Z direction) may be less than or equal to the distance between the second surface (160b) of the lower contact structure (160) and the first surface of the upper contact structure (260). The length of the connecting structure (300) along the third direction (Z direction) may be greater than or equal to the distance along the third direction (Z direction) between the lower contact structure (160) and the upper contact structure (260). In other words, the length of the connecting structure (300) along the third direction (Z direction) may be greater than or equal to the distance along the third direction (Z direction) between the first surface of the lower contact structure (160) and the second surface (260b) of the upper contact structure (260). In this range, the length along the third direction (Z direction) of the connection structure (300) can be reduced, thereby preventing parasitic capacitance from occurring and improving the reliability of the semiconductor device.

[0191] The connecting structure (300) may be positioned spaced apart from the upper source / drain pattern (250) in a third direction (Z direction). The connecting structure (300) may be positioned spaced apart from the lower source / drain pattern (150) and the upper source / drain pattern (250) in a second direction (Y direction). The connecting structure (300) may not overlap with the lower source / drain pattern (150) in the second direction (Y direction) and the third direction (Z direction), and may not overlap with the upper source / drain pattern (250) in the second direction (Y direction) and the third direction (Z direction). Accordingly, the length of the connecting structure (300) along the third direction (Z direction) may be smaller than the distance along the third direction (Z direction) between the upper surface of the lower source / drain pattern (150) and the lower surface of the upper source / drain pattern (250). For example, the length along the third direction (Z direction) of the connection structure (300) may be smaller than the distance along the third direction (Z direction) between the lower surface of the lower source / drain pattern (150) and the upper surface of the upper source / drain pattern (250). Within this range, the length along the third direction (Z direction) of the connection structure (300) may be reduced, thereby preventing the occurrence of parasitic capacitance and improving the reliability of the semiconductor device.

[0192] As illustrated in FIG. 20, an insulating material may be filled into the remaining connection recess (300R) after the connection structure (300) is formed. The insulating material may include the same material as the lower interlayer insulating layer (190) and the lower field insulating layer (105). Accordingly, the boundary between the insulating material and the lower interlayer insulating layer (190) and between the insulating material and the lower field insulating layer (105) may not be visible, but is not limited thereto. For example, as illustrated in FIG. 11, an insulating pattern (350 in FIG. 11) may be formed in the remaining connection recess (300R) after the connection structure (300) is formed. The insulating pattern (350 in FIG. 11) may include a material different from the lower interlayer insulating layer (190) and the lower field insulating layer (105).

[0193] As illustrated in FIGS. 21 and 22, the semiconductor device can be flipped over, the second substrate (201) and the upper active pattern (211) can be removed, the upper pattern (210) can be formed, and after removing the upper dummy source / drain pattern (286), an upper through-structure (280) can be formed in the removed space.

[0194] First, the second substrate (201) and the upper active pattern (211) can be removed, and an upper pattern (210) can be formed. The process of removing the second substrate (201) and the upper active pattern (211) can be carried out using chemical mechanical flashing and wet etching methods, but is not limited thereto. An upper pattern (210) can be formed in the space where the upper active pattern (211) has been removed. The upper pattern (210) may include various insulating materials. For example, the upper pattern (210) may include silicon oxide (SiO2), but is not limited thereto. Accordingly, the upper surface of the upper dummy source / drain pattern (286) may be exposed.

[0195] Next, the exposed upper dummy source / drain pattern (286) can be removed. The process of removing the upper dummy source / drain pattern (286) may be performed using a wet etching method or a dry etching method, but is not limited thereto. Accordingly, the upper source / drain pattern (250) can be exposed.

[0196] Next, an upper through-hole structure (280) can be formed within the space from which the upper dummy source / drain pattern (286) has been removed. An upper through-hole structure (280) can be formed by sequentially forming a second upper through-hole via (282) and a first upper through-hole via (281) within the space from which the upper dummy source / drain pattern (286) has been removed. The first upper through-hole via (281) and the second upper through-hole via (282) may include a conductive material. The first upper through-hole via (281) and the second upper through-hole via (282) may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The upper through-hole structure (280) may be in contact with the upper source / drain pattern (250). The upper through-structure (280) can be connected to the upper source / drain pattern (250).

[0197] Accordingly, a semiconductor device according to one embodiment can be formed.

[0198] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention. Explanation of the symbols

[0200] 110: Lower pattern 140: Sub-channel patterns 150: Bottom source / drain pattern 120: Lower gate electrode 160: Lower contact structure 180: Lower penetration structure 190: Lower interlayer insulation layer 195: Lower junction insulation layer 210: Upper pattern 240: Upper channel patterns 250: Top source / drain pattern 220: Upper gate electrode 260: Upper contact structure 280: Upper penetration structure 290: Upper interlayer insulation layer 295: Upper junction insulation layer 300: Link structure

Claims

Claim 1 A semiconductor device comprising a first transistor structure, a second transistor structure, and a connection structure, wherein the first transistor structure comprises lower channel patterns, lower source / drain patterns located on both sides of the lower channel patterns, a lower gate electrode surrounding the lower channel patterns, a lower junction insulating layer located on the lower source / drain patterns and the lower gate electrode, and a lower contact structure located between the lower junction insulating layer and the lower source / drain patterns; the second transistor structure comprises an upper junction insulating layer located on the lower junction insulating layer, upper channel patterns located on the upper junction insulating layer, upper source / drain patterns located on both sides of the upper channel patterns and on the upper junction insulating layer, an upper gate electrode surrounding the upper channel patterns, and an upper contact structure located between the upper junction insulating layer and the upper source / drain patterns; and the connection structure penetrates the lower junction insulating layer and the upper junction insulating layer to electrically connect the lower contact structure and the upper contact structure. Claim 2 In claim 1, the semiconductor device is positioned on the side of the lower contact structure and on the first surface of the upper contact structure. Claim 3 A semiconductor device according to claim 1, wherein the connection structure overlaps with the lower contact structure in a first direction and overlaps with the upper contact structure in a second direction intersecting the first direction. Claim 4 A semiconductor device according to claim 3, wherein the lower contact structure and the upper contact structure extend in the first direction, and the length of the lower contact structure along the first direction is different from the length of the upper contact structure along the first direction. Claim 5 In paragraph 3, the semiconductor device comprises a connection structure including an extension extending in the second direction and a protrusion protruding in the first direction toward the lower contact structure. Claim 6 A semiconductor device according to claim 1, wherein the connection structure comprises a first surface facing the upper source / drain pattern and a second surface facing the lower source / drain pattern, and the second surface of the connection structure is located closer to the upper surface of the lower junction insulating layer than to the lower surface of the lower source / drain pattern. Claim 7 In claim 1, the connection structure is a semiconductor device that does not overlap with the lower source / drain pattern and the upper source / drain pattern. Claim 8 In claim 1, the connection structure comprises a first connection electrode and a second connection electrode surrounding at least a portion of the first connection electrode, and the second connection electrode is a semiconductor device in contact with the side of the lower contact structure. Claim 9 A semiconductor device comprising a first transistor structure, a second transistor structure, and a connection structure, wherein the first transistor structure comprises lower channel patterns, lower source / drain patterns located on both sides of the lower channel patterns, a lower gate electrode surrounding the lower channel patterns, a lower interlayer insulating layer located on the lower source / drain patterns, a lower junction insulating layer located on the lower interlayer insulating layer and the lower gate electrode, and a lower contact structure extending in a first direction and connected to the lower source / drain patterns through the lower interlayer insulating layer, and the second transistor structure comprises an upper junction insulating layer located on the lower junction insulating layer, upper channel patterns located on the upper junction insulating layer, an upper interlayer insulating layer located on the upper junction insulating layer, upper source / drain patterns located on both sides of the upper channel patterns and on the upper interlayer insulating layer, an upper gate electrode surrounding the upper channel patterns, and an upper contact structure extending in a first direction and connected to the upper source / drain patterns through the upper interlayer insulating layer. A semiconductor device comprising, wherein the connecting structure extends in a second direction intersecting the first direction to electrically connect the lower contact structure and the upper contact structure, and the connecting structure overlaps with the lower contact structure in the first direction and overlaps with the upper contact structure in the second direction. Claim 10 A semiconductor device comprising a first transistor structure, a second transistor structure, and a connection structure, wherein the first transistor structure comprises lower channel patterns, lower source / drain patterns located on both sides of the lower channel patterns, a lower gate electrode surrounding the lower channel patterns, a lower interlayer insulating layer located on the lower source / drain patterns, a lower junction insulating layer located on the lower interlayer insulating layer and the lower gate electrode, and a lower contact structure connected to the lower source / drain patterns by penetrating the lower interlayer insulating layer; the second transistor structure comprises an upper junction insulating layer located on the lower junction insulating layer, upper channel patterns located on the upper junction insulating layer, an upper interlayer insulating layer located on the upper junction insulating layer, upper source / drain patterns located on both sides of the upper channel patterns and on the upper interlayer insulating layer, an upper gate electrode surrounding the upper channel patterns, and an upper contact structure connected to the upper source / drain patterns by penetrating the upper interlayer insulating layer; and the connection structure comprises the lower contact structure and the upper contact A semiconductor device that electrically connects structures, wherein the length of the connecting structure is less than or equal to the distance between the lower surface of the lower source / drain pattern and the upper surface of the upper source / drain pattern.

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