Semiconductor device

Abstract

The present disclosure may provide a semiconductor device with improved electrical characteristics and integration density. The semiconductor device comprises a substrate, a first stacked structure including a plurality of semiconductor patterns disposed on the substrate and stacked spaced apart from each other in a first direction, a first conductive pattern disposed on one side of the first stacked structure and extending in a first direction, and a plurality of data storage patterns disposed on the other side of the first stacked structure, spaced apart from each other in a first direction, and extending in a second direction intersecting the first direction, wherein the width in a third direction intersecting each of the first direction and the second direction of each of the plurality of semiconductor patterns may be greater than the width in a third direction of each of the plurality of data storage patterns.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor device. Background Technology

[0002] As the miniaturization, multifunctionality, and high performance of electronic products are required, high-capacity semiconductor devices are needed, and increased integration density is required to provide high-capacity semiconductor devices. Since the integration density of conventional semiconductor devices is mainly determined by the area occupied by a unit cell, the integration density of 2D semiconductor devices is increasing but remains limited. Accordingly, 3D semiconductor devices are being proposed to increase memory capacity by stacking multiple cells vertically on a substrate. The problem to be solved

[0003] The problem that the present disclosure aims to solve is to provide a semiconductor device with improved electrical characteristics and integration density. means of solving the problem

[0004] According to some embodiments of the present disclosure for solving the above technical problem, a semiconductor device comprises a substrate, a first stacked structure including a plurality of semiconductor patterns disposed on the substrate and stacked spaced apart from each other in a first direction, a first conductive pattern disposed on one side of the first stacked structure and extending in a first direction, and a plurality of data storage patterns disposed on the other side of the first stacked structure, spaced apart from each other in a first direction, and extending in a second direction intersecting the first direction, and the width in a third direction intersecting each of the first direction and the second direction of each of the plurality of semiconductor patterns may be greater than the width in a third direction of each of the plurality of data storage patterns.

[0005] According to some embodiments of the present disclosure for solving the above technical problem, a semiconductor device comprises a substrate, a first stacked structure comprising a plurality of semiconductor patterns disposed on the substrate and stacked spaced apart from each other in a first direction, a first conductive pattern disposed on one side of the first stacked structure and extending in a first direction, a plurality of data storage patterns disposed on the other side of the first stacked structure and spaced apart from each other in a first direction and extending in a second direction intersecting the first direction, a second stacked structure disposed on the substrate and spaced apart from the first stacked structure in a third direction intersecting each of the first direction and the second direction, and a support pattern disposed between the first stacked structure and the second stacked structure, wherein the support pattern comprises a first region and a second region extending from the first region in a second direction, and the depth of the first region in the first direction may be smaller than the depth of the second region in the first direction.

[0006] According to some embodiments of the present disclosure for solving the above technical problem, a semiconductor device comprises a substrate, a first stacked structure including a plurality of semiconductor patterns disposed on the substrate and stacked spaced apart from each other in a first direction, a first conductive pattern disposed on one side of the first stacked structure and extending in a first direction, a plurality of data storage patterns disposed on the other side of the first stacked structure opposite to one side of the first stacked structure, spaced apart from each other in a first direction, and extending in a second direction intersecting the first direction, a second stacked structure disposed on the substrate and spaced apart in a third direction intersecting the first stacked structure and the first direction and the second direction, respectively, and a support pattern disposed between the first stacked structure and the second stacked structure, wherein the width of each of the plurality of semiconductor patterns in the third direction is greater than the width of each of the plurality of data storage patterns in the third direction, and the width of each of the plurality of semiconductor patterns in the third direction decreases as it approaches the other side of the first stacked structure along the second direction, and the support pattern includes a first region and a second region extending from the first region in a second direction, and the depth of the first region in the first direction The depth of the second region in the first direction may be smaller than the depth of the second region.

[0007] According to some embodiments of the present disclosure for solving the above technical problem, a method for manufacturing a semiconductor device may include the steps of: stacking a plurality of sacrificial layers and a plurality of semiconductor layers alternately in a first direction on a substrate; forming a plurality of through holes that penetrate the plurality of sacrificial layers and the plurality of semiconductor layers to expose the substrate; forming a plurality of support patterns within the plurality of through holes; forming a plurality of trenches that penetrate the plurality of sacrificial layers and the plurality of semiconductor layers to expose the substrate; removing a plurality of sacrificial layers; partially removing each of the plurality of semiconductor layers in a first direction to form a plurality of semiconductor bars; forming a data storage pattern within a first trench among the plurality of trenches; and forming a first conductive pattern within a second trench among the plurality of trenches.

[0008] According to some embodiments of the present disclosure for solving the above technical problem, a plurality of through holes are included in a first region and a second region extending in a second direction intersecting a first direction from the first region, and the step of forming the plurality of through holes may include the step of forming the plurality of through holes such that the width in a third direction intersecting each of the first direction and the second direction of the first region is smaller than the width in a third direction of the second region.

[0009] According to some embodiments of the present disclosure for solving the above technical problem, a plurality of through holes are included in a first region and a second region extending in a second direction intersecting a first direction from the first region, and the step of forming the plurality of through holes may include the step of forming the plurality of through holes such that the depth of the first region in the first direction is smaller than the depth of the second region in the first direction.

[0010] According to some embodiments of the present disclosure for solving the above technical problem, the step of forming a plurality of through holes may include the step of forming a plurality of through holes such that the depth in the first direction of a first region increases as it approaches a second region.

[0011] According to some embodiments of the present disclosure for solving the above technical problem, prior to the step of forming a data storage pattern within a first trench among a plurality of trenches, the method may further include the step of partially removing each of a plurality of semiconductor bars in a second direction intersecting a first direction to form a data storage pattern. Effects of the invention

[0012] According to some embodiments of the present disclosure, the integration density of a semiconductor device can be improved by increasing the spacing between data storage patterns adjacent to each other in the horizontal direction.

[0013] According to some embodiments of the present disclosure, a semiconductor device with improved electrical characteristics and reliability can be provided by increasing the spacing between data storage patterns adjacent to each other in the horizontal direction.

[0014] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0015] FIG. 1 is an equivalent circuit diagram showing a cell array of a semiconductor device according to some embodiments of the present disclosure. FIG. 2 is a plan view showing a semiconductor device according to some embodiments of the present disclosure. Figure 3 is a cross-sectional view taken along the line B-B' of Figure 2. Figure 4 is a cross-sectional view taken along the line C-C' of Figure 2. FIGS. 5 to 17 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 18 is a plan view showing a semiconductor bar according to some embodiments of the present disclosure. FIG. 19 is a cross-sectional view taken along the line C-C' of FIG. 16. Specific details for implementing the invention

[0016] Semiconductor devices according to some embodiments of the present disclosure will be described in detail below with reference to the drawings. The embodiments disclosed herein are exemplary embodiments. Accordingly, the present invention is not limited thereto and may be embodied in various other forms. Each of the embodiments provided below is not excluded from being connected to another embodiment or one or more features of other embodiments that are consistent with the present invention but are not provided in or within the present specification. For example, even if a matter described in a particular exemplary embodiment is not described in another exemplary embodiment, such matter may be understood to be associated with another exemplary embodiment unless otherwise stated in the description. Furthermore, it should be understood that all descriptions of principles, aspects, and exemplary embodiments are intended to include their structural and functional equivalents. Furthermore, such equivalents should be understood to include not only currently well-known equivalents but also equivalents to be developed in the future, that is, all devices to be invented to perform the same function regardless of structure. For example, the material forming the contact or via may not be limited to the metals exemplified in the present specification, provided that the present invention can be applied to them.

[0017] When an element, component, layer, pattern, structure, region, etc. of a semiconductor device (hereinafter collectively referred to as "component") is described as being "over," "above," "on," "below," "under," "beneath," "connected to," or "coupled to" another component of the semiconductor device, it may be directly connected to, coupled to, or have an intermediate component present. In contrast, when one component of a semiconductor device is described as being "directly over," "directly above," "directly on," "directly below," "directly under," "directly beneath," "directly connected to," or "directly coupled to" another component of a semiconductor device, there are no intermediate components. Additionally, in this specification, the same reference numerals may refer to the same components.

[0018] In this specification, spatially relative terms such as "over," "above," "on," "upper," "below," "under," "beneath," "lower," "top," and "bottom" may be used for convenience of explanation to describe the relationship between one component and another as illustrated in the drawings. It will be understood that spatially relative terms are intended to include other directions of the semiconductor device in use or operation in addition to the directions illustrated in the drawings. For example, if the semiconductor device is inverted in the drawings, a component described as "below" or "beneath" another component may be facing "above" the other component, and the "top" or "upper" surface of a component may be the "bottom" or "lower" surface of the component. Accordingly, depending on the applicable circumstances, the term "below" may include both the up and down directions, and The term "top" may include both the top and the bottom. As such, the semiconductor device may be oriented (rotated 90 degrees or in other directions), and spatially relative descriptions used in the specification may be interpreted accordingly.

[0019] In this disclosure, although terms such as "first," "second," etc. are used to describe various elements or components, these elements or components are not limited by these terms. These terms should be understood as being used merely to distinguish one element or component from another. It is obvious that the first element or component mentioned below may be the second element or component within the technical scope of this disclosure.

[0020] A semiconductor device and a method for manufacturing the same according to some embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0021] FIG. 1 is an equivalent circuit diagram showing a cell array of a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1, the semiconductor device (100) may include a plurality of memory cells (MC) composed of cell transistors (TR) and cell capacitors (CAP) that are arranged along a first direction (D1) and a second direction (D2) and connected to each other. The plurality of memory cells (MC) may be arranged in rows spaced apart from each other along each of the first direction (D1) and the third direction (D3) to form a sub-cell array (SCA). Here, the second direction (D2) may be a direction that intersects (e.g., orthogonally) with the first direction (D1). The third direction (D3) may be a direction that intersects (e.g., orthogonally) with each of the first direction (D1) and the second direction (D2).

[0022] A semiconductor device (100) may have a plurality of sub-cell arrays (SCA) spaced apart from each other along a third direction (D3). A plurality of word lines (WL) may extend along the third direction (D3) and may be spaced apart from each other along a first direction (D1) and a second direction (D2). A plurality of bit lines (BL) may extend along the first direction (D1) and may be spaced apart from each other along the second direction (D2) and the third direction (D3), respectively.

[0023] Some of the multiple bit lines (BL) may be connected to each other by a bit line strapping line (BLS) that extends along the second direction (D2). For example, the bit line strapping line (BLS) may connect bit lines (BL) arranged along the second direction (D2) among the multiple bit lines (BL).

[0024] Multiple cell capacitors (CAP) can be commonly connected to an upper electrode (PLATE) extending in a first direction (D1) and a third direction (D3). For convenience of illustration, the upper electrode (PLATE) is illustrated as extending in the first direction (D1), but the upper electrode (PLATE) arranged along the third direction (D3 direction) can form a single unit.

[0025] The cell capacitor (CAP) and cell transistor (TR) arranged along the second direction (D2) can be arranged in a mirror-symmetric manner with respect to a plane extending in the first direction (D1) perpendicular to the third direction (D3) where the upper electrode (PLATE) is placed.

[0026] The cell transistor (TR) can be connected to the bit line (BL) through DC (DC) and to the cell capacitor (CAP) through BC (BC).

[0027] FIG. 2 is a plan view showing a semiconductor device according to some embodiments of the present disclosure. FIG. 3 is a cross-sectional view taken along line B-B' of FIG. 2. FIG. 4 is a cross-sectional view taken along line C-C' of FIG. 2. Referring to FIG. 2 to FIG. 4, a semiconductor device (100) according to some embodiments of the present disclosure may include a substrate (102), a plurality of cell array structures (CS1, CS2), a plurality of first conductive patterns (152), a plurality of support patterns (132), and an upper insulating layer (TIL), etc.

[0028] The substrate (102) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (102) may further include impurities. The substrate (102) may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0029] A first cell array structure (CS1) may be disposed on a substrate (102). For example, the first cell array structure (CS1) may be disposed on the substrate (102) along a direction perpendicular to the upper surface of the substrate (102). Here, the direction perpendicular to the upper surface of the substrate (102) may be referred to as the first direction (D1). In some embodiments, the first cell array structure (CS1) may refer to the sub-cell array (SCA) illustrated in FIG. 1.

[0030] The first cell array structure (CS1) may include a plurality of first stacked structures (SS1) and a plurality of data storage patterns (210). The plurality of first stacked structures (SS1) may be disposed on a lower pattern (BP) formed on a substrate (102). Each of the plurality of first stacked structures (SS1) may be disposed spaced apart from each other in a second direction (D2) that intersects a first direction (D1).

[0031] A plurality of data storage patterns (210) may be disposed on a lower pattern (BP) formed on a substrate (102). Each of the plurality of data storage patterns (210) may be disposed spaced apart from each other in a first direction (D1). The plurality of data storage patterns (210) may extend from a first stacked structure (SS1) in a second direction (D2). The plurality of data storage patterns (210) may be connected to the first stacked structure (SS1).

[0032] A plurality of data storage patterns (210) may be arranged between first stacked structures (SS1) that are adjacent to each other in the second direction (D2) among a plurality of first stacked structures (SS1). In some embodiments, each of the plurality of first stacked structures (SS1) may represent a cell transistor (TR) as illustrated in FIG. 1. In some embodiments, each of the plurality of data storage patterns (210) may represent a cell capacitor (CAP) as illustrated in FIG. 1.

[0033] The first stacked structure (SS1) may include a plurality of semiconductor patterns (SP), a plurality of gate insulating layers (GI), a plurality of interlayer insulating films (ILD), a plurality of second conductive patterns (154), a plurality of first spacers (S1), a plurality of second spacers (S2), and a plurality of first insulating liners (IL1).

[0034] A plurality of semiconductor patterns (SP) may be spaced apart from the substrate (102). Each of the plurality of semiconductor patterns (SP) may be spaced apart from each other in a first direction (D1). Here, each of the plurality of semiconductor patterns (SP) may overlap each other in the first direction (D1). Each of the plurality of semiconductor patterns (SP) may extend in a second direction (D2). Each of the plurality of semiconductor patterns (SP) may include a first edge portion (EA1), a second edge portion (EA2), and a channel portion (CH). In some embodiments, the thickness of the semiconductor pattern (SP) placed at the top among the plurality of semiconductor patterns (SP) in the first direction (D1) may be greater than the thickness of the remaining semiconductor patterns (SP) in the first direction (D1). The semiconductor pattern (SP) placed at the top among the plurality of semiconductor patterns (SP) may extend further in the second direction (D2) than the remaining semiconductor patterns (SP). For example, among the plurality of semiconductor patterns (SP), the semiconductor pattern (SP) placed at the top can overlap with the data storage pattern (210) in the first direction (D1).

[0035] The first edge portion (EA1) and the second edge portion (EA2) may be spaced apart from each other in the second direction (D2). The channel portion (CH) may be positioned between the first edge portion (EA1) and the second edge portion (EA2). The first edge portion (EA1) may be in contact with the first conductive pattern (152). The first edge portion (EA1) may be electrically connected to the first conductive pattern (152). Here, the first conductive pattern (152) may refer to the bit line (BL) illustrated in FIG. 1. The second edge portion (EA2) may be in contact with at least one of the plurality of data storage patterns (210). The second edge portion (EA2) may be electrically connected to the data storage pattern (210). That is, each of the plurality of semiconductor patterns (SP) may be connected to the corresponding data storage pattern (210) among the plurality of data storage patterns (210).

[0036] The semiconductor pattern (SP) may have a first side (F1) and a second side (F2) facing each other in a second direction (D2). The first side (F1) may be a side of the first edge portion (EA1), and the second side (F2) may be a side of the second edge portion (EA2). The first side (F1) of the semiconductor pattern (SP) may be in contact with the first conductive pattern (152), and the second side (F2) may be in contact with the data storage pattern (210).

[0037] The semiconductor pattern (SP) may include at least one of a single-crystal semiconductor, a polycrystalline semiconductor, an oxide semiconductor, and a two-dimensional material. For example, the single-crystal semiconductor may be single-crystal silicon. For example, the polycrystalline semiconductor may be polysilicon. For example, the oxide semiconductor may be IGZO (Indium Gallium Zinc Oxide). For example, the two-dimensional material may be MoS2, WS2, MoSe2, or WSe2.

[0038] In some embodiments, the first edge portion (EA1) and the second edge portion (EA2) of the semiconductor pattern (SP) may each include an impurity region doped with an impurity (e.g., n-type or p-type impurity). The impurity region may constitute a source / drain region of the semiconductor pattern (SP).

[0039] The second conductive pattern (154) is placed on the semiconductor pattern (SP) and can be extended in a third direction (D3). The second conductive pattern (154) can surround the channel portion (CH) of the semiconductor pattern (SP). That is, the channel portion (CH) can overlap with the second conductive pattern (154) in the first direction (D1). For example, the second conductive pattern (154) can have a structure that surrounds the channel portion (CH) of the semiconductor pattern (SP) (i.e., a gate-all-around structure). A single second conductive pattern (154) can surround the channel portion (CH) of each of the semiconductor patterns (SP) that are spaced apart from each other in the third direction (D3). Here, the third direction (D3) can be a direction that intersects the first direction (D1) and the second direction (D2), respectively.

[0040] Each of the plurality of second conductive patterns (154) surrounds the channel portion (CH) of a corresponding semiconductor pattern (SP) among the plurality of semiconductor patterns (SP) spaced apart from each other in the first direction (D1) and can be extended along the third direction (D3). The second conductive patterns (154) can be spaced apart from each other in the first direction (D1). The second conductive pattern (154) may represent the word line (WL) shown in FIG. 1. The second conductive pattern (154) may include any one of TiN, MoN, Mo, Ti, or Co.

[0041] A gate insulating layer (GI) may be disposed between the second conductive pattern (154) and the semiconductor pattern (SP). The gate insulating layer (GI) may surround at least a portion of the semiconductor pattern (SP). For example, the gate insulating layer (GI) may surround the first edge portion (EA1) and the channel portion (CH) of the semiconductor pattern (SP). Multiple gate insulating layers (GI) may be provided. Each of the multiple gate insulating layers (GI) may surround at least a portion of the corresponding semiconductor pattern (SP).

[0042] The gate insulating layer (GI) may comprise at least one of silicon oxide, silicon oxynitride, and a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material may comprise a metal oxide or a metal oxynitride. For example, a high dielectric constant material usable as the gate insulating layer (GI) may comprise at least one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, and Al2O3, but is not limited thereto. A high-k material may be defined as a material having a dielectric constant higher than that of silicon oxide.

[0043] An interlayer insulating film (ILD) may be disposed between second conductive patterns (154) that are adjacent to each other in a first direction (D1). The second conductive patterns (154) may be spaced apart from each other in the first direction (D1) by the interlayer insulating film (ILD). One side of the interlayer insulating film (ILD) may be in contact with the side of the first conductive pattern (152). Multiple interlayer insulating films (ILD) may be provided. The first laminated structure (SS1) may have a structure in which multiple second conductive patterns (154) and multiple interlayer insulating films (ILD) are alternately laminated in the first direction (D1). The interlayer insulating film (ILD) may include a single film or a composite film containing an insulating material.

[0044] The first spacer (S1) may be positioned between adjacent interlayer insulating films (ILDs) in a first direction (D1). The first spacer (S1) may surround at least a portion of the semiconductor pattern (SP). For example, the first spacer (S1) may surround the first edge portion (EA1) of the semiconductor pattern (SP). The first spacer (S1) may surround at least a portion of the gate insulating layer (GI). One side of the first spacer (S1) may be in contact with the side of the first conductive pattern (152). The first spacer (S1) may be provided in multiple numbers. The first spacer (S1) may include a single film or a composite film comprising an insulating material.

[0045] The second spacer (S2) may be disposed between interlayer insulating films (ILDs) that are adjacent to each other in the first direction (D1). The second spacer (S2) may surround at least a portion of the semiconductor pattern (SP). For example, the second spacer (S2) may surround the second edge portion (EA2) of the semiconductor pattern (SP). The second spacer (S2) may be provided in multiple numbers. The second spacer (S2) may include a single film or a composite film comprising an insulating material.

[0046] A first insulating liner (IL1) may be disposed between second spacers (S2) that are adjacent to each other in a first direction (D1). The first insulating liner (IL1) may surround at least a portion of the semiconductor pattern (SP). For example, the insulating liner (IL1) may surround the upper and lower surfaces of the second edge portion (EA2) of the semiconductor pattern (SP). The first insulating liner (IL1) may be disposed on one side of the second spacer (S2). The first insulating liner (IL1) may include silicon oxide, silicon nitride, or a metal oxide with a dielectric constant greater than that of silicon oxide. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof. The first insulating liner (IL1) may be a single layer or a multilayer.

[0047] A first conductive pattern (152) may be placed on a substrate (102). The first conductive pattern (152) may fill a second trench (STR2) formed on the substrate (102). The first conductive pattern (152) may be placed on one side of a first stacked structure (SS1). The first conductive pattern (152) may extend in a first direction (D1). For example, the first conductive pattern (152) may be provided on a first side (F1) of a semiconductor pattern (SP). The first conductive pattern (152) may extend along a first direction (D1) on a first side (F1) of a semiconductor pattern (SP). Accordingly, a single first conductive pattern (152) may come into contact with the first side (F1) of each of a plurality of semiconductor patterns (SP) that are spaced apart from each other in the first direction (D1), and may be electrically connected to the plurality of semiconductor patterns (SP).

[0048] The first conductive pattern (152) may include at least one of doped polysilicon, a metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), a conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, RuTiN), a conductive metal silicide, or a conductive metal oxide (e.g., PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo), but is not limited thereto. The first conductive pattern (152) may include a single layer or a multilayer of the materials described above. In some embodiments, the first conductive pattern (152) may include a two-dimensional material. For example, the two-dimensional material may include graphene, carbon nanotubes, or a combination thereof.

[0049] The data storage pattern (210) may include a first electrode (212), a capacitor dielectric film (214) disposed on the first electrode (212), and a second electrode (216) disposed on the capacitor dielectric film (214). In some embodiments, the semiconductor device (100) may be a Dynamic Random Access Memory (DRAM), and the data storage pattern (210) may be a capacitor. The first electrode (212) may be spaced apart from the second electrode (216) with the capacitor dielectric film (214) in between. In the illustrated embodiment, the data storage pattern (210) is disclosed as a so-called pillar-shaped structure, but is not limited thereto, and the data storage pattern (210) may be configured in any shape, such as a cylinder shape or a concave shape.

[0050] Each of the first electrode (212) and the second electrode (216) may include a conductive material. For example, each of the first electrode (212) and the second electrode (216) may comprise at least one of impurity-doped silicon (Si), impurity-doped silicon germanium (SiGe), a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.), a metal nitride (e.g., nitride of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc., titanium silicon nitride (e.g., TiSiN), titanium aluminum nitride (e.g., TiAlN) and tantalum aluminum nitride (e.g., TaAlN), etc.), a conductive oxide (e.g., PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo), and a metal silicide. Each of the first electrode (212) and the second electrode (216) may be a single membrane made of a single material or a composite membrane containing two or more materials.

[0051] For example, the capacitor dielectric film (214) may include at least one of a metal oxide such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3 and TiO2 and a dielectric material of a perovskite structure such as SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT (lead zirconate titanate), and PLZT (lead(plomb) lanthanum zirconate titanate).

[0052] In some embodiments, the data storage pattern (210) may be a variable resistance pattern that can be switched between two resistance states by an electrical pulse. In this case, the data storage pattern (DSP) may include a phase-change material, perovskite compounds, transition metal oxide, magnetic materials, ferromagnetic materials, or antiferromagnetic materials whose crystal state changes depending on the amount of current.

[0053] The upper insulating layer (TIL) may be disposed on the first stacked structure (SS1). The upper insulating layer (TIL) may be disposed on the uppermost semiconductor pattern (SP) among a plurality of semiconductor patterns (SP). One side of the upper insulating layer (TIL) may be in contact with the side of the first conductive pattern (152). The upper insulating layer (TIL) may overlap the first stacked structure (SS1) and the data storage pattern (210) in the first direction (D1). The upper insulating layer (TIL) may include a single film or a composite film containing an insulating material. For example, the upper insulating layer (TIL) may include silicon oxide, silicon oxynitride, or silicon nitride, etc.

[0054] The semiconductor device (100) may further include a first filling film (FL1). The first filling film (FL1) may be disposed on a substrate (102). The first filling film (FL1) may fill a first trench (STR1) formed on the substrate (102). A portion of the first filling film (FL1) may extend in a second direction (D2) and be disposed on a data storage pattern (210). For example, the first filling film (FL1) may be disposed between data storage patterns (210) that are adjacent to each other in a first direction (D1). That is, the first filling film (FL1) may overlap with the data storage pattern (210) in the first direction (D1). Alternatively, the first filling film (FL1) may overlap with the data storage pattern (210) in the second direction (D2). The first filling layer (FL1) may overlap with the upper insulating layer (TIL) in the second direction (D2). The first filling layer (FL1) may be in contact with the data storage pattern (210). The first filling layer (FL1) may include silicon germanium (SiGe). Meanwhile, although the semiconductor device (100) has been described as including the first filling layer (FL1), the second electrode (216) may be configured such that the first filling layer (FL1) is not formed and the second electrode (216) is a plate electrode, and is not limited thereto.

[0055] The second cell array structure (CS2) may be spaced apart from the first cell array structure (CS1) in a third direction (D3). The second cell array structure (CS2) may be disposed on the substrate (102) along a direction perpendicular to the upper surface of the substrate (102). The second cell array structure (CS2) may be disposed on a lower pattern (BP) formed on the substrate (102). In some embodiments, the second cell array structure (CS2) may refer to the sub-cell array (SCA) illustrated in FIG. 1. The second cell array structure (CS2) may include the same or similar configuration as the first cell array structure (CS1). Accordingly, the description of configurations that overlap with the first cell array structure (CS1) is omitted. The second cell array structure (CS2) may include a plurality of second stacked structures (SS2). A plurality of second stacked structures (SS1) may be spaced apart from a plurality of first stacked structures (SS1) of the first cell array structure (CS1) in a third direction (D3). The second stacked structures (SS2) may include a configuration identical or similar to that of the first stacked structures (SS1). Accordingly, the description of the configuration of the second stacked structures (SS2) that overlaps with the first stacked structures (SS1) is omitted.

[0056] A support pattern (132) may be disposed on a substrate (102). The support pattern (132) may be disposed between a first stacked structure (SS1) and a second stacked structure (SS2). The support pattern (132) may be composed of the same material as the upper insulating layer (TIL). For example, the support pattern (132) may include silicon oxide, silicon oxynitride, or silicon nitride.

[0057] In some embodiments, a data storage pattern (210) connected to a first stacked structure (SS1) and a data storage pattern (210) connected to a second stacked structure (SS2) may be spaced apart from each other in a third direction (D3). For example, a support pattern (132) may be placed between the data storage pattern (210) connected to the first stacked structure (SS1) and the data storage pattern (210) connected to the second stacked structure (SS2). The data storage pattern (210) connected to the first stacked structure (SS1) and the data storage pattern (210) connected to the second stacked structure (SS2) may be spaced apart by a predetermined distance in the third direction (D3).

[0058] In some embodiments, the width of each of the plurality of semiconductor patterns (SP) in the third direction (D3) may be greater than the width of each of the plurality of data storage patterns (210) in the third direction. Accordingly, the distance between the plurality of semiconductor patterns (SP) of the first stacked structure (SS1) and the plurality of semiconductor patterns (SP) of the second stacked structure (SS2) in the third direction (D3) may be smaller than the distance between the plurality of data storage patterns (210) of the first stacked structure (SS1) and the plurality of data storage patterns (SP) of the second stacked structure (SS2) in the third direction (D3). In some embodiments, the part of the first stacked structure (SS1) connected to the data storage pattern (210) may be defined as the other side of the first stacked structure (SS1). Here, the width of each of the plurality of semiconductor patterns (SP) of the first stacked structure (SS1) in the third direction (D3) may decrease as it approaches the other side of the first stacked structure (SS1) along the second direction (D2). However, there may be a section where the width of the semiconductor pattern (SP) in the third direction (D3) is constant.

[0059] FIGS. 5 through 17 are intermediate step drawings for illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. For convenience of explanation, detailed descriptions of components identical or similar to those described in detail in the embodiments disclosed in FIGS. 1 through 4 may be omitted.

[0060] Referring to FIGS. 5 and 6, according to a method for manufacturing a semiconductor device according to some embodiments of the present disclosure, a plurality of sacrificial layers (110) and a plurality of semiconductor layers (120) may be alternately stacked on a substrate (102) to form a pre-stacking structure (PS). For example, a plurality of sacrificial layers (110) and a plurality of semiconductor layers (120) may be alternately stacked in a first direction (D1) on a substrate (120). The sacrificial layer (110) may include silicon germanium (SiGe), and the semiconductor layer (120) may include silicon (Si). A semiconductor layer (120) may be placed at the top of the stacking structure. An upper insulating layer (TIL) may be further placed on the semiconductor layer (120) placed at the top to form a pre-stacking structure (PS).

[0061] In some embodiments, a plurality of sacrificial layers (110), a plurality of semiconductor layers (120), and an upper insulating layer (TIL) may be formed by a process such as Chemical Vapor Deposition (CVD), Plasma Enhanced CVD (PECVD), or Atomic Layer Deposition (ALD). In some embodiments, each of the plurality of sacrificial layers (110) and the plurality of semiconductor layers (120) may be formed in a single-crystal state using a layer in contact below as a seed layer, or formed in a single-crystal state through a heat treatment process. In some embodiments, each of the plurality of sacrificial layers (110) and the plurality of semiconductor layers (120) may be formed to have a generally uniform thickness.

[0062] Referring to FIGS. 7 and 8, after forming a first mask layer (130) on a pre-laminated structure (PS), a plurality of through holes (STH) can be formed that penetrate the pre-laminated structure (PS) and expose a substrate (102) by using the first mask layer (130) as an etching mask. The first mask layer (130) may have a plurality of openings corresponding to the plurality of through holes (STH). In some embodiments, the first mask layer (130) may be composed of silicon nitride.

[0063] In some embodiments, the stacked through holes (STH) may be arranged in mirror symmetry with respect to a virtual line extending in a third direction (D3) between two adjacent stacked through holes (STH) along a second direction (D2).

[0064] In some embodiments, each of the plurality of through holes (STH) may include a first region (R1) and a second region (R2) extending from the first region (R1) in a second direction (D2). The width of the first region (R1) in a third direction (D3) may be smaller than the width of the second region (R2) in a third direction (D3). Because the widths of the first region (R1) and the second region (R2) in a third direction (D3) are different, as a result of etching using the first mask layer (130), the depth of the first region (R1) in a first direction (D1) may be smaller than the depth of the second region (R2) in a first direction (D1). In some embodiments, the depth of the first region (R1) in a first direction (D1) may increase as it approaches the second region (R2).

[0065] Referring to FIGS. 9 and 10, a plurality of support patterns (132) may be formed within a plurality of through holes (STH). For example, a plurality of support patterns (132) may fill a plurality of through holes (STH). Accordingly, each of the plurality of support patterns (132) may include a first region (R1) and a second region (R2) extending from the first region (R1) in a second direction (D2). The width of the first region (R1) in the third direction (D3) may be smaller than the width of the second region (R2) in the third direction (D3). The depth of the first region (R1) in the first direction (D1) may be smaller than the depth of the second region (R2) in the first direction (D1). In some embodiments, the depth of the first region (R1) in the first direction (D1) may increase as it approaches the second region (R2). Multiple support patterns (132) can be formed by CVD, PECVD, or ALD, etc.

[0066] Referring to FIGS. 11 to 13, after forming a second mask layer (140) on a first mask layer (130), the second mask layer (140) can be used as an etching mask. By using the second mask layer (140) as an etching mask, a plurality of trenches (STR1, STR2) can be formed that penetrate the pre-stacked structure (PS) and expose the substrate (102). The second mask layer (140) may have a plurality of openings corresponding to the plurality of trenches (STR1, STR2). In some embodiments, the second mask layer (140) may be composed of silicon nitride. Here, the first trench (STR1) and the second trench (STR2) may be formed to penetrate at least a portion of the substrate. Accordingly, a lower pattern (BP) may be formed on the substrate (102). A pre-stacked structure (PS) may be disposed on the lower pattern (BP).

[0067] Referring to FIGS. 11 to 15 together, a plurality of sacrificial layers (110) can be removed through a first trench (STR1) and a second trench (STR2). For example, the plurality of sacrificial layers (110) can be removed through an isotropic etching process having an etching selectivity ratio with respect to a substrate (102), a plurality of semiconductor layers (120), a plurality of support patterns (132), and an upper insulating layer (TIL). Next, a plurality of semiconductor bars (120S) can be formed by removing a portion of the plurality of semiconductor layers (120) exposed through the first trench (STR1) and the second trench (STR2) (for example, a thinning process to thin the plurality of semiconductor layers (120)). For example, a plurality of semiconductor bars (120S) can be formed by removing a portion of each of the plurality of semiconductor layers (120) in a first direction (D1). Here, the semiconductor layer (120) placed at the top may not be removed. Accordingly, the width of each of the plurality of semiconductor bars (120S) in the first direction (D1) can be formed to have a value smaller than the width of the uppermost semiconductor layer (120) in the first direction (D1).

[0068] A plurality of semiconductor bars (120S) can be formed by removing a portion of a plurality of semiconductor layers (120) through an isotropic etching process having an etching selectivity ratio with respect to a plurality of support patterns (132) and an upper insulating layer (TIL). Accordingly, the plurality of semiconductor bars (120S) can be spaced apart from each other in a first direction (D1). The plurality of semiconductor bars (120S) can be supported by a plurality of support patterns (132).

[0069] Referring to FIGS. 16 and 17, a plurality of second conductive patterns (154), a plurality of first spacers (S1), and a plurality of second spacers (S2) may be formed to surround at least a portion of a semiconductor bar (120S). Additionally, a plurality of interlayer insulating films (ILD) may be formed between the second conductive patterns (154) that are adjacent to each other in a first direction (D1).

[0070] Additionally, a gate insulating layer (GI), a first insulating liner (IL1), and a second insulating liner (IL2) may be formed to surround at least a portion of a plurality of semiconductor bars (120S). The second insulating liner (IL2) may be disposed on the first insulating liner (IL1). The second insulating liner (IL2) may include silicon oxide, silicon nitride, or silicon oxynitride, etc. And, a second filling film (FL2) may fill the first through-hole (STR1). Additionally, a first conductive pattern (152) may fill the second through-hole (STR2).

[0071] In some embodiments, the second filling layer (FL2) may fill at least a portion of the first through-hole (STR1). For example, as illustrated, the second filling layer (FL2) may not fill the central portion of the first through-hole (STR1). The second filling layer (FL2) may fill at least a portion between a plurality of semiconductor bars (120S) spaced apart from each other in the first direction (D1). For example, the second filling layer (FL2) may overlap with the plurality of semiconductor bars (120S) in the first direction (D1). The second filling layer (FL2) may include silicon oxide, silicon nitride, or silicon oxynitride, etc. After that, a semiconductor device (100) can be formed by removing a part of the first insulating liner (IL1), the second insulating liner (IL2), the second filling film (FL2), and the second part of each of the plurality of semiconductor bars (120S), and then forming the first filling film (FL1) and the data storage pattern (210) shown in FIGS. 1 to 4. Here, in order to form the data storage pattern (210), each of the plurality of semiconductor bars (120S) may be partially removed in a second direction (D2) that intersects with a first direction (D1).

[0072] FIG. 18 is a plan view showing a semiconductor bar according to some embodiments of the present disclosure. FIG. 19 is a cross-sectional view taken along the line C-C' of FIG. 16. Referring to FIG. 18, the semiconductor bar (120S) may include a first portion (120S_1P) and a second portion (120S_2P). Here, the width of the first portion (120S_1P) in the third direction (D3) may be greater than the width of the second portion (120S_2P) in the third direction (D3). In some embodiments, the width of the first portion (120S_1P) in the third direction (D3) may decrease as it approaches the second portion (120S_2P). However, at least a portion of the first portion (120S_1P) may have a constant width in the third direction (D3) along the second direction (D2).

[0073] Referring to FIGS. 1 to 4 together, the first part (120S_1P) forms a semiconductor pattern (SP), and the second part (120S_2P) can be replaced with a data storage pattern (210). Accordingly, the width of the semiconductor pattern (SP) in the third direction (D3) may be greater than the width of the data storage pattern (210) in the third direction (D3). Accordingly, by increasing the distance between data storage patterns adjacent to each other in the third direction (D3), a semiconductor device with improved electrical characteristics and integration density can be provided.

[0074] Referring to FIGS. 18 and 19 together, two of the plurality of semiconductor bars (120S) may be spaced apart from each other in a third direction (D3). Here, a support pattern (132) may be placed between the semiconductor bars (120S). In some embodiments, the width of the second part (120S_2P) in the third direction (D3) may be smaller than the width of the first part (120S_2P) in the third direction (D3). Accordingly, the distance between the second parts (120S_2P) adjacent to each other in the third direction (D3) may be greater than the distance between the first parts (120S_2P). Accordingly, the first insulating liners (IL1) surrounding each of the second parts (120S_2P) adjacent to each other in the third direction (D3) may be spaced apart in the third direction (D3). Additionally, the second insulating liners (IL2) surrounding each of the second parts (120S_2P) adjacent to each other in the third direction (D3) may be spaced apart from each other in the third direction (D3). Accordingly, a semiconductor device with improved electrical characteristics and integration density may be provided.

[0075] Although the present invention has been described above by limited embodiments and drawings, the present invention is not limited thereto, and it is obvious that various modifications and variations are possible within the scope of the technical spirit of the present invention and the equivalent scope of the claims described below by those skilled in the art to which the present invention belongs. Explanation of the symbols

[0076] 100: Semiconductor device 102: Substrate BP: Lower pattern CS1: First cell array structure CS2: Second cell array structure SS1: First laminated structure SS2: Second laminated structure SP: Semiconductor pattern 210: Data storage patterns 152(BL): 1st Challenge Pattern

Claims

Claim 1 A semiconductor device comprising: a substrate; a first stacked structure including a plurality of semiconductor patterns disposed on the substrate and stacked spaced apart from each other in a first direction; a first conductive pattern disposed on one side of the first stacked structure and extending in the first direction; and a plurality of data storage patterns disposed on the other side of the first stacked structure, spaced apart from each other in the first direction, and extending in a second direction intersecting the first direction, wherein the width of each of the plurality of semiconductor patterns in a third direction intersecting the first direction and the second direction, respectively, is greater than the width of each of the plurality of data storage patterns in the third direction. Claim 2 A semiconductor device according to claim 1, wherein the width of each of the plurality of semiconductor patterns in the third direction decreases as it approaches the other side of the first stacked structure along the second direction. Claim 3 A semiconductor device according to claim 1, further comprising: a second stacked structure disposed on the substrate and spaced apart from the first stacked structure in the third direction; and a support pattern disposed between the first stacked structure and the second stacked structure. Claim 4 A semiconductor device according to claim 3, wherein the support pattern comprises a first region and a second region extending from the first region in the second direction, and the depth of the first region in the first direction is smaller than the depth of the second region in the first direction. Claim 5 A semiconductor device according to claim 4, wherein the depth in the first direction of the first region increases as it approaches the second region. Claim 6 A semiconductor device according to claim 4, wherein the first region overlaps with the plurality of semiconductor patterns in the third direction, and the second region overlaps with the plurality of data storage patterns in the third direction. Claim 7 A semiconductor device according to claim 1, wherein the thickness in the first direction of the semiconductor pattern positioned at the top of the plurality of semiconductor patterns is greater than the thickness in the first direction of the remaining semiconductor patterns among the plurality of semiconductor patterns. Claim 8 A semiconductor device comprising: a substrate; a first stacked structure including a plurality of semiconductor patterns disposed on the substrate and stacked spaced apart from each other in a first direction; a first conductive pattern disposed on one side of the first stacked structure and extending in the first direction; a plurality of data storage patterns disposed on the other side of the first stacked structure, spaced apart from each other in the first direction, and extending in a second direction intersecting the first direction; a second stacked structure disposed on the substrate and spaced apart from the first stacked structure in a third direction intersecting each of the first direction and the second direction; and a support pattern disposed between the first stacked structure and the second stacked structure, wherein the support pattern includes a first region and a second region extending from the first region in the second direction, and the depth of the first region in the first direction is smaller than the depth of the second region in the first direction. Claim 9 A semiconductor device according to claim 8, wherein the width of each of the plurality of semiconductor patterns in the third direction is greater than the width of each of the plurality of data storage patterns in the third direction. Claim 10 A substrate; a first stacked structure comprising a plurality of semiconductor patterns disposed on the substrate and stacked spaced apart from each other in a first direction; a first conductive pattern disposed on one side of the first stacked structure and extending in the first direction; a plurality of data storage patterns disposed on the other side of the first stacked structure, spaced apart from each other in the first direction, and extending in a second direction intersecting the first direction; a second stacked structure disposed on the substrate and spaced apart in a third direction intersecting the first stacked structure, the first direction, and the second direction, respectively. A semiconductor device comprising a first stacked structure and a second stacked structure and a support pattern disposed between the first stacked structure and the second stacked structure, wherein the width of each of the plurality of semiconductor patterns in the third direction is greater than the width of each of the plurality of data storage patterns in the third direction, and the width of each of the plurality of semiconductor patterns in the third direction decreases as it approaches the other side of the first stacked structure along the second direction, and the support pattern comprises a first region and a second region extending from the first region in the second direction, and the depth of the first region in the first direction is smaller than the depth of the second region in the first direction.

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