Semiconductor device

Abstract

A semiconductor device of the present invention comprises: an active region disposed on a substrate; a first gate line extending in a second direction on the active region; a second gate line disposed on the active region spaced apart from the first gate line in the first direction and extending in the second direction; a first source / drain contact pattern disposed on the active region on one side of the first gate line; a second source / drain contact pattern disposed on the active region on one side of the second gate line; and a dummy source / drain contact pattern disposed on the active region between the first gate line and the second gate line, wherein the dummy source / drain contact pattern has a smaller size compared to the first source / drain contact pattern and the second source / drain contact pattern.

Description

Technology Field

[0001] The technical concept of the present invention relates to a semiconductor device, and more specifically, to a semiconductor device with improved device performance. Background Technology

[0002] As semiconductor devices become smaller, the patterns contained within them are becoming increasingly finer. Consequently, the micro-patterning process required to form these fine patterns during semiconductor manufacturing is becoming increasingly difficult. Therefore, there is a need for measures that can overcome the challenges of the micro-patterning process while simultaneously improving the performance of miniaturized semiconductor devices. The problem to be solved

[0003] The problem that the technical concept of the present invention aims to solve is to provide a semiconductor device with improved device performance. means of solving the problem

[0004] To solve the above-mentioned problem, a semiconductor device according to one embodiment of the technical concept of the present invention comprises: an active region disposed on a substrate; a first gate line extending in a second direction on the active region; a second gate line disposed on the active region spaced apart from the first gate line in the first direction and extending in the second direction; a first source / drain contact pattern disposed on the active region on one side of the first gate line; a second source / drain contact pattern disposed on the active region on one side of the second gate line; and a dummy source / drain contact pattern disposed on the active region between the first gate line and the second gate line, wherein the dummy source / drain contact pattern has a smaller size compared to the first source / drain contact pattern and the second source / drain contact pattern.

[0005] A semiconductor device according to one embodiment of the technical concept of the present invention comprises: an active region disposed on a substrate having a first region width in a first direction and a first region length in a second direction perpendicular to the first direction; a first gate line extended in the second direction on the active region; a second gate line disposed on the active region spaced apart from the first gate line in the first direction and extended in the second direction; a first active contact region disposed on the active region on one side of the first gate line; a second active contact region disposed on the active region on one side of the second gate line; a dummy contact region disposed on the active region between the first gate line and the second gate line; a first source / drain contact pattern disposed on the first active contact region spaced apart from the first gate line in the first direction; and a second source / drain contact pattern disposed on the second active contact region spaced apart from the second gate line in the first direction.

[0006] A semiconductor device according to one embodiment of the technical concept of the present invention comprises: an active region formed on a substrate; a plurality of gate lines spaced apart in a first direction and extended in a second direction perpendicular to the first direction on the active region, wherein the gate lines include a first gate line located to the left in the first direction and a second gate line located to the right; a first active contact region disposed on one side of the first gate line in the active region; a second active contact region disposed on one side of the second gate line in the active region; a plurality of dummy contact regions disposed on the active region between the gate lines; a first source / drain contact pattern disposed on the first active contact region; a second source / drain contact pattern disposed on the second active contact region; and a plurality of dummy source / drain contact patterns disposed on at least one of the plurality of dummy contact regions, wherein the dummy source / drain contact patterns have a smaller size compared to the first source / drain contact pattern and the second source / drain contact pattern. Effects of the invention

[0007] A semiconductor device according to one embodiment of the present invention configures the size of a dummy source / drain contact pattern to be smaller than that of a first source / drain contact pattern and a second source / drain contact pattern. A semiconductor device according to one embodiment of the present invention does not place a dummy source / drain contact pattern on a dummy source / drain region.

[0008] Accordingly, damage to the dummy source / drain region located below the dummy source / drain contact pattern is suppressed when manufacturing a semiconductor device. As a result, the semiconductor device of the present invention can improve device performance by reducing the device resistance between the first source / drain contact pattern and the second source / drain contact pattern. Brief explanation of the drawing

[0009] FIGS. 1 and FIGS. 2 are plan views of a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 3 is a cross-sectional view of a semiconductor device according to one embodiment of the technical concept of the present invention. Figure 4 is a diagram showing the device resistance of the semiconductor device of Figure 3. FIG. 5 is a cross-sectional view of a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 7 is a cross-sectional view of a semiconductor device according to one embodiment of the technical concept of the present invention. FIGS. 8 and 9 are plan views of a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 10 is a plan view of a semiconductor device according to one embodiment of the technical concept of the present invention. Figure 11 is a diagram showing the device resistance of the semiconductor device of Figure 10. FIG. 12 is a plan view of a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 13 is a plan view of a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 14 is a cross-sectional view of a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 15 is a cross-sectional view of an active contact structure used in a semiconductor device according to the technical concept of the present invention. FIG. 16 is a cross-sectional view illustrating an embodiment of a dummy contact structure used in a semiconductor device according to the technical concept of the present invention. FIG. 17 is a cross-sectional view illustrating an embodiment of a dummy contact structure used in a semiconductor device according to the technical concept of the present invention. FIG. 18 is a schematic diagram showing an electronic system including a semiconductor device according to one embodiment of the technical concept of the present invention. Specific details for implementing the invention

[0010] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. The following embodiments of the present invention may be implemented as only one, and may also be implemented by combining one or more of the following embodiments. Accordingly, the technical concept of the present invention is not to be interpreted as being limited to a single embodiment.

[0011] FIGS. 1 and FIGS. 2 are plan views of a semiconductor device according to one embodiment of the technical concept of the present invention.

[0012] Specifically, the semiconductor device (EX1) may include an active area (12, active area (or active region)) disposed on a substrate (sb in FIG. 3), a first gate line (14a), a second gate line (14b), a first source / drain contact pattern (24), a second source / drain contact pattern (26), and a dummy source / drain contact pattern (28). In this specification, source / drain may mean source and drain.

[0013] The semiconductor device (EX1) may be an integrated circuit device. The semiconductor device (EX1) may be a Metal Oxide Silicon (MOS) transistor. The semiconductor device (EX1) may be a PMOS transistor or an NMOS transistor. The semiconductor device (EX1) may be a field effect transistor (FET).

[0014] The active region (12) may be a region where an active device is formed. The active region (12) may have a first region width (ta) in a first direction (X direction) and a first region length (tb) in a second direction (Y direction) perpendicular to the first direction (X direction). The portion excluding the active region (12) may be non-active regions (8, 10 in FIG. 3). The non-active regions (8, 10 in FIG. 3) may be named device isolation regions or field regions.

[0015] A first gate line (14a) is extended in a second direction (Y direction) on the active area (12). A first gate contact pattern (30) may be disposed on the first gate line (14a). A second gate line (14b) is disposed on the active area (12) spaced apart from the first gate line (14a) in a first direction (X direction).

[0016] A second gate contact pattern (32) may be disposed on the second gate line (14b). The second gate line (14b) extends in the second direction (Y direction). The first gate line (14a) and the second gate line (14b) are disposed outside the active area (12), i.e., in the non-active area.

[0017] Depending on the arrangement of the first gate line (14a) and the second gate line (14b), the active area (12) can be classified into a first active contact area (18), a second active contact area (20), and a dummy contact area (22). The first active contact area (18) can be placed in the active area (12) on one side of the first gate line (14a). The second active contact area (20) can be placed in the active area (12) on one side of the second gate line (14b). The dummy contact area (22) can be placed in the active area (12) between the first gate line (14a) and the second gate line (14b).

[0018] The first active contact area (18) may be the first source / drain area. The second active contact area (20) may be the second source / drain area. The dummy contact area (22) may be the dummy source / drain area.

[0019] A first source / drain contact pattern (24) is disposed on an active region (12) on one side of a first gate line (14a). The first source / drain contact pattern (24) may be disposed on a first active contact region (18). The first source / drain contact pattern (24) is spaced apart from the first gate line (14a) in a first direction (X direction). The first source / drain contact pattern (24) is spaced apart from one side edge (12c) of the active region (12) in a first direction (X direction).

[0020] A second source / drain contact pattern (26) is disposed on an active region (12) on one side of the second gate line (14b). The second source / drain contact pattern (26) may be disposed on a second active contact region (20). The second source / drain contact pattern (26) is spaced apart from the second gate line (14b) in a first direction (X direction). The second source / drain contact pattern (26) is spaced apart from one side edge (12d) of the active region (12) in a first direction (-X direction).

[0021] A dummy source / drain contact pattern (28) is disposed on the active region (12) between the first gate line (14a) and the second gate line (14b). The semiconductor device (EX1) may have a symmetrical structure in the first direction (X direction) with respect to the dummy source / drain contact pattern (28). The dummy source / drain contact pattern (28) may be disposed on the dummy contact region (22).

[0022] The dummy source / drain contact pattern (28) is spaced apart from one edge (12a) of the active area (12) by a first separation distance (g) in the second direction (-Y direction). The dummy source / drain contact pattern (28) is spaced apart from the other edge (12b) of the active area (12) by a second separation distance (h) in the second direction (Y direction).

[0023] The dummy source / drain contact pattern (28) may have a smaller size compared to the first source / drain contact pattern (24) and the second source / drain contact pattern (26). In this specification, size may refer to the width, length, or area of ​​the pattern. Here, the sizes of the first source / drain contact pattern (24), the second source / drain contact pattern (26), and the dummy source / drain contact pattern (28) are described in detail.

[0024] The dummy source / drain contact pattern (28) may have a first pattern width (a) in the first direction (X direction) and a first pattern length (b) in the second direction (Y direction). The first source / drain contact pattern (24) may have a second pattern width (c) in the first direction (X direction) and a second pattern length (d) in the second direction (Y direction). The second source / drain contact pattern (26) may have a third pattern width (e) in the first direction (X direction) and a third pattern length (f) in the second direction (Y direction). The second pattern length (d) of the first source / drain contact pattern (24) and the third pattern length (f) of the second source / drain contact pattern (26) may be equal to the first region length (tb) of the active region (12).

[0025] In some embodiments, the first pattern width (a), the first pattern length (b), the second pattern width (c), the second pattern length (d), the third pattern width (e), and the third pattern length (f) may have a size of several nanometers (nm) to tens of nanometers (nm).

[0026] The first pattern width (a) of the dummy source / drain contact pattern (28) may be the same as the second pattern width (c) in the first direction (X direction) of the first source / drain contact pattern (24), and the second source / drain contact pattern (26) may be the same as the third pattern width (e) in the first direction (X direction).

[0027] The first pattern length (b) of the dummy source / drain contact pattern (28) may be smaller than the second pattern length (d) in the second direction (Y direction) of the first source / drain contact pattern (24) and the third pattern length (f) in the second direction (Y direction) of the second source / drain contact pattern (26). The first pattern length (b) of the dummy source / drain contact pattern (28) may be smaller than the first region length (tb) of the active region (12).

[0028] As described above, the semiconductor device (EX1) is configured such that the first pattern length (b) of the dummy source / drain contact pattern (28) is smaller than the second pattern length (d) of the first source / drain contact pattern (24) and the third pattern length (f) of the second source / drain contact pattern (26).

[0029] Accordingly, damage to the active region (12), such as the dummy source / drain region, located below the dummy source / drain contact pattern (28) of the semiconductor device (EX1) can be suppressed. As a result, the device resistance between the first source / drain contact pattern (24) and the second source / drain contact pattern (26) of the semiconductor device (EX1) is reduced during device operation, thereby improving device performance.

[0030] FIG. 3 is a cross-sectional view of a semiconductor device according to one embodiment of the technical concept of the present invention, and FIG. 4 is a diagram showing the device resistance of the semiconductor device of FIG. 3.

[0031] Specifically, the semiconductor device (EX1) may be a cross-sectional view along X-X' of FIG. 1. In FIG. 3 and FIG. 4, reference numerals identical to those in FIG. 1 and FIG. 2 indicate identical components. In FIG. 3 and FIG. 4, details identical to those in FIG. 1 and FIG. 2 are briefly described or omitted.

[0032] The semiconductor device (EX1) is a planar transistor and can be manufactured by a gate-first process. Accordingly, the semiconductor device (EX1) may have a first gate insulating layer (13) and a second gate insulating layer (15) formed on the lower portions of the first gate line (14a) and the second gate line (14b), respectively.

[0033] To explain in more detail, the semiconductor device (EX1) may include an active region (12) and a non-active region (8, 10) formed on a substrate (sb). The non-active region (8, 10) may include a first non-active region (8) and a second non-active region (10). The substrate (sb) may be made of one or more semiconductor materials selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. The active region (12) may be composed of the same material as the substrate. The active region (12) may be defined by forming the first and second non-active regions (8, 10) on the substrate (sb). The first and second non-active regions (8, 10) may be insulating regions. The first and second non-active regions (8, 10) may be trench insulating regions.

[0034] A first gate line (14a) and a second gate line (14b) may be formed on the active region (12) of the substrate (sb). The first gate line (14a) and the second gate line (14b) may be referred to as planar gate lines formed on the substrate (Sb). The first gate line (14a) and the second gate line (14b) may include a metal, such as W or TiN. The second gate line (14b) is spaced apart from the first gate line (14a) in a first direction (X direction). A first gate insulating layer (13) may be formed below the first gate line (14a). A second gate insulating layer (15) may be formed below the second gate line (14b).

[0035] A first active contact region (18) may be formed in the active region (14) of the substrate (sb) on one side of the first gate line (14a). The first active contact region (18) may be a first source / drain region. The first source / drain region may be an impurity-doped region in which impurities are doped into the substrate (sb).

[0036] A second active contact region (20) may be formed in the active region (14) of the substrate (sb) on one side of the second gate line (14b). The second active contact region (20) may be a second source / drain region. The second source / drain region may be an impurity-doped region in which impurities are doped into the substrate (sb).

[0037] A dummy contact region (22) may be formed in the active region (14) of the substrate (sb) between the first gate line (14a) and the second gate line (14b). The dummy contact region (22) may be a dummy source / drain region. The dummy source / drain region may be an impurity-doped region in which impurities are doped into the substrate (sb).

[0038] A first source / drain contact pattern (24) may be formed on the first active contact region (18). In other words, the first source / drain contact pattern (24) may be formed on the first active contact region (18) spaced apart from the first gate line (14a).

[0039] A second source / drain contact pattern (26) may be formed on the second active contact area (20). In other words, the second source / drain contact pattern (26) may be formed on the second active contact area (20) spaced apart from the second gate line (14b). A dummy source / drain contact pattern (28) may be formed on the dummy contact area (22).

[0040] When forming a dummy source / drain contact pattern (28) for manufacturing a semiconductor device (EX1), the dummy contact region (22) may be damaged to form a dummy source / drain loss region (34). The dummy source / drain loss region (34) may have a depth (de1) from the surface (6a) of the substrate (sb) as shown in FIG. 4.

[0041] As previously explained, the dummy source / drain contact pattern (28) of the semiconductor device (EX1) of the present invention may have a smaller size compared to the first source / drain contact pattern (24) and the second source / drain contact pattern (26). Accordingly, as shown in FIG. 4, the semiconductor device (EX1) of the present invention can minimize the size of the dummy source / drain loss region (34) to reduce the resistance (Rsd) of the dummy contact region (22). The resistance (Rsd) of the dummy contact region (22) may be connected to the channel resistance (Rch).

[0042] Consequently, the semiconductor device (EX1) of the present invention can reduce the device resistance between the first active contact region (18, or the first source / drain region) and the second active contact region (20, or the second source / drain region) during device operation.

[0043] FIG. 5 is a cross-sectional view of a semiconductor device according to one embodiment of the technical concept of the present invention.

[0044] Specifically, the semiconductor device (EX2) may be identical to the semiconductor device (EX1) of FIG. 3 except that the structure of the first gate line (14a-1) and the second gate line (14b-1) is different. The semiconductor device (EX2) of FIG. 5 may be a cross-sectional view along X-X' of FIG. 1. In FIG. 5, reference numerals identical to those in FIG. 3 indicate identical components. In FIG. 5, the details described in FIG. 3 are briefly explained or omitted.

[0045] The semiconductor device (EX2) of FIG. 5 is a planar transistor and can be manufactured by a gate last process. The semiconductor device (EX2) may have a symmetrical structure in the first direction (X direction) with respect to a dummy source / drain contact pattern (28). The first gate line (14a-1) and the second gate line (14b-1) of the semiconductor device (EX2) can be manufactured in the same process. The first gate line (14a-1) and the second gate line (14b-1) can be named as trench-type gate lines formed in a gate trench on the substrate (Sb).

[0046] Specifically, the semiconductor device (EX2) may have a first gate insulating layer (13-1) formed within a first gate trench (TE1) on a substrate (Sb). A first gate line (14a-1) may be formed on the first gate insulating layer (13-1) within the first gate trench (TE1). The first gate line (14a-1) may include a first metal layer (mg1) and a second metal layer (mg2). Although the first gate line (14a-1) is composed of two metal layers, it may also be composed of three or more metal layers.

[0047] A semiconductor device (EX2) may have a second gate insulating layer (15-1) formed within a second gate trench (TE2) on a substrate (Sb). A second gate line (14b-1) may be formed on the second gate insulating layer (15-1) within the second gate trench (TE2). The second gate line (14b-1) may include a third metal layer (mg3) and a fourth metal layer (mg4).

[0048] The second gate line (14b-1) is composed of two metal layers, but it may also be composed of three or more metal layers. The first metal layer (mg1) and the third metal layer (mg3) may include at least one of TiN, TaN, TiC, and TaC. The second metal layer (mg2) and the fourth metal layer (mg4) may include W or Al.

[0049] FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the technical concept of the present invention.

[0050] Specifically, the semiconductor device (EX3) may be identical to the semiconductor device (EX1) of FIG. 3 except that it includes a fin-type active region (12-1). The semiconductor device (EX3) may be a cross-sectional view along X-X' of FIG. 1. In FIG. 6, the same reference numerals as in FIG. 3 indicate the same components. In FIG. 6, the descriptions in FIG. 3 are briefly explained or omitted.

[0051] The semiconductor device (EX3) is a fin-type field-effect transistor (FinFET) and can be manufactured by a gate-first process. The semiconductor device (EX3) may have a symmetrical structure in the first direction (X direction) with respect to a dummy source / drain contact pattern (28). The semiconductor device (EX3) may include a fin-type active region (12-1) protruding from the surface of the first and second non-active regions (8, 10).

[0052] The surface (8a) of the first non-active region (8) may be lower than the surface (6) of the substrate (sb). The surface (10a) of the second non-active region (10) may be lower than the surface (6) of the substrate (sb). The first active contact region (18) may protrude above the surface (8a) of the first non-active region (8). The second active contact region (20) may protrude above the surface (10a) of the second non-active region (10).

[0053] FIG. 7 is a cross-sectional view of a semiconductor device according to one embodiment of the technical concept of the present invention.

[0054] Specifically, the semiconductor device (EX4) may be identical to the semiconductor device (EX2) of FIG. 5 except that it includes a fin-type active region (12-1). The semiconductor device (EX4) may be a cross-sectional view along X-X' of FIG. 1. In FIG. 7, the same reference numerals as in FIG. 5 indicate the same components. In FIG. 7, the descriptions in FIG. 5 are briefly explained or omitted.

[0055] The semiconductor device (EX4) is a fin-type field-effect transistor (FinFET) and can be manufactured by a gate last process. The semiconductor device (EX4) may have a symmetric structure in the first direction (X direction) with respect to a dummy source / drain contact pattern (28). The semiconductor device (EX4) may include a first gate line (14a-1) and a second gate line (14b-1).

[0056] The semiconductor device (EX4) may include a fin-type active region (12-1) protruding from the surfaces of the first and second non-active regions (8, 10). The first active contact region (18) may protrude beyond the surface (8a) of the first non-active region (8). The second active contact region (20) may protrude beyond the surface (10a) of the second non-active region (10).

[0057] FIGS. 8 and 9 are plan views of a semiconductor device according to one embodiment of the technical concept of the present invention.

[0058] Specifically, the semiconductor device (EX5) may be identical to the semiconductor device (EX1) of FIGS. 1 and 2, except that the arrangement of the dummy source / drain contact pattern (28-1) is different. In FIGS. 8 and 9, the same reference numerals as in FIGS. 1 and 2 indicate the same components. In FIGS. 8 and 9, the descriptions in FIGS. 1 and 2 are briefly described or omitted.

[0059] The semiconductor device (EX5) may include an active region (12), a first gate line (14a), a second gate line (14b), a first source / drain contact pattern (24), a second source / drain contact pattern (26), and a dummy source / drain contact pattern (28-1). The semiconductor device (EX5) may have a symmetrical structure in a first direction (X direction) with respect to the dummy source / drain contact pattern (28-1).

[0060] The active region (12) may have a first region width (ta) in the first direction (X direction) and a first region length (tb) in the second direction (Y direction) perpendicular to the first direction (X direction). Depending on the arrangement of the first gate line (14a) and the second gate line (14b), the active region (12) may be classified into a first active contact region (18), a second active contact region (20), and a dummy contact region (22).

[0061] The dummy source / drain contact pattern (28-1) is in contact with one edge (12a) and the other edge (12b) of the active region (12) in the second direction (Y direction) without being separated. The dummy source / drain contact pattern (28-1) may have a smaller size compared to the first source / drain contact pattern (24) and the second source / drain contact pattern (26).

[0062] The dummy source / drain contact pattern (28-1) may have a first pattern width (a-1) in the first direction (X direction) and a first pattern length (b-1) in the second direction (Y direction). The first pattern width (a-1) in the first direction (X direction) of the dummy source / drain contact pattern (28-1) may be smaller than the second pattern width (c) in the first direction (X direction) of the first source / drain contact pattern (24) and the third pattern width (e) in the first direction (X direction) of the second source / drain contact pattern (26).

[0063] The first pattern length (b-1) in the second direction (Y direction) of the dummy source / drain contact pattern (28-1) may be the same as the second pattern length (d) in the second direction (Y direction) of the first source / drain contact pattern (24) and the third pattern length (f) in the third direction (Y direction) of the second source / drain contact pattern (26). The second pattern length (d) of the first source / drain contact pattern (24) and the third pattern length (f) of the second source / drain contact pattern (26) may be the same as the first region length (tb) of the active region (12).

[0064] In some embodiments, the first pattern width (a-1), the first pattern length (b-1), the second pattern width (c), the second pattern length (d), the third pattern width (e), and the third pattern length (f) may have a size of several nanometers (nm) to tens of nanometers (nm).

[0065] As described above, the semiconductor device (EX5) is configured such that the first pattern width (a-1) of the dummy source / drain contact pattern (28-1) is smaller than the second pattern width (c) of the first source / drain contact pattern (24) and the third pattern width (e) of the second source / drain contact pattern (26).

[0066] Accordingly, damage to the active region (12), such as the dummy source / drain region, located below the dummy source / drain contact pattern (28-1) of the semiconductor device (EX5) can be suppressed. As a result, the semiconductor device (EX5) can improve device performance by reducing the device resistance between the first source / drain contact pattern (24) and the second source / drain contact pattern (26) during device operation.

[0067] FIG. 10 is a plan view of a semiconductor device according to one embodiment of the technical concept of the present invention, and FIG. 11 is a drawing showing the device resistance of the semiconductor device of FIG. 10.

[0068] Specifically, the semiconductor device (EX6) may be identical to the semiconductor device (EX1) of FIGS. 1 and 2, except that a dummy source / drain contact pattern is not placed in the dummy contact region (22). In FIGS. 10 and 11, the same reference numerals as in FIGS. 1 and 2 indicate the same components. In FIGS. 10 and 11, the descriptions in FIGS. 1 and 2 are briefly described or omitted.

[0069] A semiconductor device (EX6) may include an active region (12), a first gate line (14a), a second gate line (14b), a first source / drain contact pattern (24), and a second source / drain contact pattern (26). Depending on the arrangement of the first gate line (14a) and the second gate line (14b), the active region (12) may be classified into a first active contact region (18), a second active contact region (20), and a dummy contact region (22). A dummy source / drain contact pattern is not arranged in the dummy contact region (22).

[0070] As described above, the semiconductor device (EX6) does not have a dummy source / drain contact pattern placed in the dummy contact region (22). Accordingly, the semiconductor device (EX6) has no damage to the dummy contact region (22), i.e., the dummy source / drain region, so the resistance (Rsd) of the dummy contact region (22) can be reduced. The resistance (Rsd) of the dummy contact region (22) can be connected to the channel resistance (Rch).

[0071] Consequently, the semiconductor device (EX6) of the present invention can reduce the device resistance between the first active contact region (18, or the first source / drain region) and the second active contact region (20, or the second source / drain region) during device operation.

[0072] FIG. 12 is a plan view of a semiconductor device according to one embodiment of the technical concept of the present invention.

[0073] Specifically, the semiconductor device (EX7) may be identical to the semiconductor device (EX1) of FIGS. 1 and 2 except that it has a plurality of gate lines (14c-14f) and a different arrangement of dummy source / drain contact patterns (28-2). In FIG. 12, reference numerals identical to those in FIG. 1 and 2 indicate identical components. In FIG. 12, the descriptions in FIG. 1 and 2 are briefly explained or omitted.

[0074] The semiconductor device (EX7) may include an active region (12) disposed on a substrate (sb in FIG. 3), a plurality of gate lines (14c-14f), a first source / drain contact pattern (24), a second source / drain contact pattern (26), and a dummy source / drain contact pattern (28-2).

[0075] The gate lines (14c-14f) are spaced apart in a first direction (X direction) on the active region (12) and extend in a second direction (Y direction) perpendicular to the first direction (X direction). The gate lines (14c-14f) may include a first gate line (14c) located to the left in the first direction (X direction) and a second gate line (14f) located to the right.

[0076] Depending on the arrangement of the gate lines (14c-14f), the active area (12) can be classified into a first active contact area (18), a second active contact area (20), and a dummy contact area (22-1). The first active contact area (18) can be placed in the active area (20) on one side of the first gate line (14c). The second active contact area (20) can be placed in the active area (20) on one side of the second gate line (14f).

[0077] A dummy contact area (22-1) may be placed in the active area (20) between the gate lines (14c-14f). The dummy contact area (22-1) may include first to third dummy contact areas (22a-22c). A dummy source / drain contact pattern (28-2) may be placed in the dummy contact area (22-1).

[0078] The dummy source / drain contact pattern (28-2) may include first to third dummy source / drain contact patterns (28a-28c). The first to third dummy source / drain contact patterns (28a-28c) may be disposed in each of the first to third dummy contact regions (22a-22c).

[0079] The first dummy source / drain contact pattern (28a) is spaced apart from one edge (12a) of the active area (12) by a first separation distance (g1) in the second direction (-Y direction). The first dummy source / drain contact pattern (28a) may be the same as the dummy source / drain contact pattern (28) of FIGS. 1 and FIGS. 2. The first dummy source / drain contact pattern (28a) is spaced apart from the other edge (12b) of the active area (12) by a second separation distance (h1) in the second direction (Y direction).

[0080] The second dummy source / drain contact pattern (28b) is in contact with one edge (12a) of the active area (12) in the second direction (-Y direction). The second dummy source / drain contact pattern (28b) may be the same size as the first dummy source / drain contact pattern (28a). The second dummy source / drain contact pattern (28b) is spaced apart from the other edge (12b) of the active area (12) by a third separation distance (h2) in the second direction (Y direction).

[0081] The third dummy source / drain contact pattern (28c) is in contact with the other edge (12b) of the active area (12) in the second direction (Y direction). The third dummy source / drain contact pattern (28c) is spaced apart from the one edge (12a) of the active area (12) by a fourth separation distance (g2) in the second direction (-Y direction). The third dummy source / drain contact pattern (28c) may be the same size as the first dummy source / drain contact pattern (28a).

[0082] As described above, the dummy source / drain contact pattern (28-2) of the semiconductor device (EX7) may have a smaller size compared to the first source / drain contact pattern (24) and the second source / drain contact pattern (26). Accordingly, the semiconductor device (EX7) of the present invention can minimize the size of the dummy source / drain loss region located below the dummy source / drain contact pattern (28-2) to reduce the resistance of the dummy contact region (22-1).

[0083] Consequently, the semiconductor device (EX7) of the present invention can reduce the device resistance between the first active contact region (18, or the first source / drain region) and the second active contact region (20, or the second source / drain region) during device operation.

[0084] FIG. 13 is a plan view of a semiconductor device according to one embodiment of the technical concept of the present invention.

[0085] Specifically, the semiconductor device (EX8) may be identical to the semiconductor device (EX7) of FIG. 12 except that the arrangement or shape of the dummy source / drain contact pattern (28-3) is different. In FIG. 13, the same reference numerals as in FIG. 12 indicate the same components. In FIG. 13, the descriptions in FIG. 12 are briefly explained or omitted.

[0086] The semiconductor device (EX8) may include an active region (12) disposed on a substrate (sb in FIG. 3), a plurality of gate lines (14g-14k), a first source / drain contact pattern (24), a second source / drain contact pattern (26), and a dummy source / drain contact pattern (28-3).

[0087] The gate lines (14g-14k) are spaced apart in a first direction (X direction) on the active region (12) and extend in a second direction (Y direction) perpendicular to the first direction (X direction). The gate lines (14g-14k) may include a first gate line (14g) located to the left in the first direction (X direction) and a second gate line (14k) located to the right.

[0088] Depending on the arrangement of the gate lines (14g-14k), the active area (12) can be classified into a first active contact area (18), a second active contact area (20), and a dummy contact area (22-2). The first active contact area (18) can be placed in the active area (20) on one side of the first gate line (14c). The second active contact area (20) can be placed in the active area (20) on one side of the second gate line (14g).

[0089] A dummy contact area (22-2) may be placed in the active area (20) between the gate lines (14g-14k). The dummy contact area (22-2) may include first to fourth dummy contact areas (22d-22f). A dummy source / drain contact pattern (28-3) may be placed in the dummy contact area (22-2).

[0090] The dummy source / drain contact pattern (28-3) may include first to third dummy source / drain contact patterns (28e-28g). The first to third dummy source / drain contact patterns (28e-28g) may be disposed in each of the first to third dummy contact regions (22d-22f). A dummy source / drain contact pattern may not be formed in the fourth dummy contact region (22g).

[0091] The first dummy source / drain contact pattern (28e) is in contact with one edge (12a) and the other edge (12b) of the active region (12) in the second direction (Y direction). The first dummy source / drain contact pattern (28e) may be the same as the first dummy source / drain contact pattern (28-1) of FIGS. 8 and FIGS. 9. The first dummy source / drain contact pattern (28f) is in contact with one edge (12a) and the other edge (12b) of the active region (12) in the second direction (Y direction).

[0092] The second dummy source / drain contact pattern (28f) may include a plurality of sub-dummy source / drain contact patterns (28f1, 28f2). Although FIG. 13 includes two sub-dummy source / drain contact patterns (28f1, 28f2), it may include a larger number of sub-dummy source / drain contact patterns.

[0093] The third dummy source / drain contact pattern (28g) is spaced apart from one edge (12a) of the active area (12) by a fifth distance (h3) in the second direction (-Y direction). The third dummy source / drain contact pattern (28g) is spaced apart from the other edge (12b) of the active area (12) by a sixth distance (g3) in the second direction (Y direction). The third dummy source / drain contact pattern (28g) may have the same pattern width as the first dummy source / drain contact pattern (28e) in the first direction (X direction). The third dummy source / drain contact pattern (28g) may have a shorter length than the first dummy source / drain contact pattern (28e) in the second direction (Y direction).

[0094] As described above, the dummy source / drain contact pattern (28-3) of the semiconductor device (EX8) may have a smaller size compared to the first source / drain contact pattern (24) and the second source / drain contact pattern (26). Accordingly, the semiconductor device (EX8) of the present invention can minimize the size of the dummy source / drain loss region located below the dummy source / drain contact pattern (28-3) to reduce the resistance of the dummy contact region (22-2).

[0095] Consequently, the semiconductor device (EX8) of the present invention can reduce the device resistance between the first active contact region (18, or the first source / drain region) and the second active contact region (20, or the second source / drain region) during device operation.

[0096] FIG. 14 is a cross-sectional view of a semiconductor device according to one embodiment of the technical concept of the present invention.

[0097] Specifically, the semiconductor device (EX9) may be identical to the semiconductor device (EX1) of FIGS. 1 to 3, except that the structure of the dummy source / drain contact pattern (28-4) and the dummy contact region (22-3) is different. In FIG. 14, reference numerals identical to those in FIGS. 1 to 3 indicate identical components. In FIG. 14, the descriptions in FIGS. 1 to 3 are briefly explained or omitted.

[0098] The semiconductor device (EX9) may include an active region (12) disposed on a substrate (sb), first and second gate lines (14a, 14b), a first source / drain contact pattern (24), a second source / drain contact pattern (26), a dummy contact region (22-3), and a dummy source / drain contact pattern (28-3).

[0099] A first gate line (14a) is formed in the Y direction on the active region (12) of the substrate (sb). A first gate contact pattern (30) may be formed on the first gate line (14a). A second gate line (14b) is formed on the active region (12) of the substrate (sb) spaced apart from the first gate line (14a) in the first direction (X direction).

[0100] A first source / drain contact pattern (24) is disposed on an active region (12) on one side of a first gate line (14a). The first source / drain contact pattern (24) may be disposed on a first active contact region (18). When forming the first source / drain contact pattern (24), a source / drain loss region (19) may occur in the first active contact region (18). The first source / drain contact pattern (24) may have a second pattern width (c) in a first direction (X direction).

[0101] A second source / drain contact pattern (26) is disposed on an active region (12) on one side of the second gate line (14b). The second source / drain contact pattern (26) may be disposed on a second active contact region (20). When forming the second source / drain contact pattern (26), a source / drain loss region (21) may occur in the second active contact region (20). The second source / drain contact pattern (26) may have a third pattern width (e) in a first direction (X direction).

[0102] A dummy contact area (22-3) may be formed between the first gate line (14a) and the second gate line (14b). The dummy contact area (22-3) may include first to third dummy contact areas (22h-22i) spaced apart in the first direction (X direction).

[0103] A dummy source / drain contact pattern (28-4) is placed on the active region (12) between the first gate line (14a) and the second gate line (14b). The dummy source / drain contact pattern (28-4) may be placed on the dummy contact region (22-3).

[0104] The dummy source / drain contact pattern (28-4) may include first and second dummy source / drain contact patterns (28i, 28j). The first dummy source / drain contact pattern (28i) may be formed on the first dummy contact area (22h). When forming the first dummy source / drain contact pattern (28i), the first dummy contact area (22h) may have a dummy source / drain loss area (34-1).

[0105] The first dummy source / drain contact pattern (28i) may have a first sub-pattern width (a') in the first direction (X direction). The first sub-pattern width (a') may be smaller than the third pattern width (c).

[0106] A second dummy source / drain contact pattern (28j) may be formed on top of the second dummy contact area (22i). The second dummy source / drain contact pattern (28j) may not be in contact with the second dummy contact area (22i). The first dummy source / drain contact pattern (28i) may have a second sub-pattern width (a") in the first direction (X direction). The second sub-pattern width (a") may be smaller than the first sub-pattern width (a') and the third pattern width (c). A dummy source / drain contact pattern may not be formed on the second dummy contact area (22j).

[0107] As described above, the dummy source / drain contact pattern (28-4) of the semiconductor device (EX8) may have a smaller width compared to the first source / drain contact pattern (24) and the second source / drain contact pattern (26). Accordingly, the semiconductor device (EX8) of the present invention can minimize the size of the dummy source / drain loss region (34-1) located below the dummy source / drain contact pattern (28-4) to reduce the resistance of the dummy contact region (22-3).

[0108] Consequently, the semiconductor device (EX8) of the present invention can reduce the device resistance between the first active contact region (18, or the first source / drain region) and the second active contact region (20, or the second source / drain region) during device operation.

[0109] FIG. 15 is a cross-sectional view of an active contact structure used in a semiconductor device according to the technical concept of the present invention.

[0110] Specifically, an active contact structure (ACA) may be used in the semiconductor device of the technical concept of the present invention (previous EX1-EX9). The active contact structure (ACA) may include a first active contact structure (ACA-1), a second active contact structure (ACA-2), and a third active contact structure (ACA-3). At least one of the first active contact structure (ACA-1), the second active contact structure (ACA-2), and the third active contact structure (ACA-3) may be used in the semiconductor device of the technical concept of the present invention (previous EX1-EX9).

[0111] The first active contact structure (ACA-1) may include a source / drain contact pattern (24-1), a first via (40a), a first wiring layer (42a), a third via (44a), and a second wiring layer (46a). The first active contact structure (ACA-1) includes a source / drain contact pattern (24-1) formed on a source / drain region (e.g., 18 in FIG. 3) formed on a substrate (sb). The source / drain contact pattern (24-1) may be connected to the second wiring layer (46a) through the first via (40a), the first wiring layer (42a), and the third via (44a).

[0112] The second active contact structure (ACA-2) may include a source / drain contact pattern (24-2), a first via (40b), a first wiring layer (42b), a second via (40c), and a gate line (14-2). The first active contact structure (ACA-2) includes a source / drain contact pattern (24-2) formed on a source / drain region (e.g., 18 in FIG. 3) formed on a substrate (sb). The source / drain contact pattern (24-2) may be connected to the gate line (14-2) through the first via (40b), the first wiring layer (42b), and the second via (40c).

[0113] The third active contact structure (ACA-3) may include a first source / drain contact pattern (24-3), a first via (40d), a first wiring layer (42c), a second via (40e), a gate line (14-3), and a second source / drain contact pattern (26-1). The third active contact structure (ACA-2) includes a first source / drain contact pattern (24-3) formed on a source / drain region (e.g., 18 in FIG. 3) formed on a substrate (sb) and a second source / drain contact pattern (26-1) formed on a source / drain region (e.g., 20 in FIG. 3) formed on a substrate (sb). The first source / drain contact pattern (24-2) can be connected to the second source / drain contact pattern (26-1) through the first via (40d), the first wiring layer (42c), and the second via (40e).

[0114] FIG. 16 is a cross-sectional view illustrating an embodiment of a dummy contact structure used in a semiconductor device according to the technical concept of the present invention.

[0115] Specifically, a dummy contact structure (DCA1) may be used in the semiconductor device of the technical concept of the present invention (previous EX1-EX9). The dummy contact structure (DCA1) may include a first dummy contact structure (DCA-1) and a second dummy contact structure (DCA-2). At least one of the first dummy contact structure (DCA-1) and the second dummy contact structure (DCA-2) may be used in the semiconductor device of the technical concept of the present invention (previous EX1-EX9).

[0116] The first dummy contact structure (DCA-1) may include a dummy source / drain contact pattern (28-5a), a first via (48a), a second via (48b), and a first wiring layer (50a). The first dummy contact structure (DCA-1) includes a dummy source / drain contact pattern (28-5a) formed on a dummy source / drain region (e.g., 22 in FIG. 3) formed on a substrate (sb). In the first portion (PO1) of the first dummy contact structure (DCA-1), the dummy source / drain contact pattern (28-5a) is not connected to the first via (40a), and the first via (40a) may be connected to the first wiring layer (50a).

[0117] In the second part (PO2) of the first dummy contact structure (DCA-1), the dummy source / drain contact pattern (28-5a) is connected to the second via (40b), and the second via (40b) may not be connected to the first wiring layer (50a). In the third part (PO3) of the first dummy contact structure (DCA-1), the dummy source / drain contact pattern (28-5a) may not include a via and may not be connected to the first wiring layer (50a).

[0118] The second dummy contact structure (DCA-2) may include a dummy source / drain contact pattern (28-5b), a first via (48c), a first wiring layer (50b), a second via (52a), a third via (52b), and a second wiring layer (54). The second dummy contact structure (DCA-2) includes a dummy source / drain contact pattern (28-5b) formed on a dummy source / drain region (e.g., 22 in FIG. 3) formed on a substrate (sb). In the fourth portion (PO4) of the second dummy contact structure (DCA-1), the dummy source / drain contact pattern (28-5b) is connected to the first wiring layer (50b) through the first via (48c), and the first wiring layer (50b) may not be connected to the second via (52a).

[0119] In the fifth part (PO5) of the second dummy contact structure (DCA-1), the dummy source / drain contact pattern (28-5b) is connected to the first wiring layer (50b) through the first via (48c), and the first wiring layer (50b) can be connected to the third via (52b).

[0120] In the sixth part (PO6) of the second dummy contact structure (DCA-1), the dummy source / drain contact pattern (28-5b) is connected to the first wiring layer (50b) through the first via (48c), and the first wiring layer (50b) may not be connected to the second wiring layer (54).

[0121] FIG. 17 is a cross-sectional view illustrating an embodiment of a dummy contact structure used in a semiconductor device according to the technical concept of the present invention.

[0122] Specifically, a dummy contact structure (DCA2) may be used in the semiconductor device of the technical concept of the present invention (previous EX1-EX9). The dummy contact structure (DCA2) may include a third dummy contact structure (DCA-3) and a fourth dummy contact structure (DCA-4). At least one of the third dummy contact structure (DCA-3) and the fourth dummy contact structure (DCA-4) may be used in the semiconductor device of the technical concept of the present invention (previous EX1-EX9).

[0123] The third dummy contact structure (DCA-3) may include a dummy source / drain contact pattern (28-6a), a first via (56a), a second via (56b), a third via (56c), a first wiring layer (58a), and a gate line (14-4). The third dummy contact structure (DCA-3) includes a dummy source / drain contact pattern (28-6a) formed on a dummy source / drain region (e.g., 22 in FIG. 3) formed on a substrate (sb).

[0124] In the seventh part (PO7) of the third dummy contact structure (DCA-3), the dummy source / drain contact pattern (28-6a) is connected to the first wiring layer (58a) through the first via (56a), and the second via (56b) located below the first wiring layer (58a) may not be connected to the gate line (14-4).

[0125] In the eighth part (PO8) of the third dummy contact structure (DCA-3), the dummy source / drain contact pattern (28-6a) is connected to the first wiring layer (58a) through the first via (56a), and the first wiring layer (58a) may not be connected to the third via (56c) on the gate line (14-4).

[0126] In the ninth part (PO9) of the third dummy contact structure (DCA-3), the dummy source / drain contact pattern (28-6a) is connected to the first wiring layer (58a) through the first via (56a), and the first wiring layer (58a) may not be connected to the gate line (14-4).

[0127] The fourth dummy contact structure (DCA-4) may include a first dummy source / drain contact pattern (28-6b), a first via (56d), a second via (56e), a third via (56f), a first wiring layer (58b), and a second dummy source / drain contact pattern (28-6c). The fourth dummy contact structure (DCA-4) includes a first dummy source / drain contact pattern (28-6b) formed on a dummy source / drain region (e.g., 22 in FIG. 3) formed on a substrate (sb).

[0128] In the 10th portion (P1O) of the 4th dummy contact structure (DCA-4), the 1st dummy source / drain contact pattern (28-6a) is connected to the 1st wiring layer (58b) through the 1st via (56d), and the 2nd via (56e) located below the 1st wiring layer (58b) may not be connected to the 2nd dummy source / drain contact pattern (28-6c).

[0129] In the 11th portion (P11) of the 4th dummy contact structure (DCA-4), the 1st dummy source / drain contact pattern (28-6a) is connected to the 1st wiring layer (58b) through the 1st via (56d), and the 1st wiring layer (58b) may not be connected to the 3rd via (58f) on the 2nd dummy source / drain contact pattern (28-6c).

[0130] In the 12th part (P12) of the 4th dummy contact structure (DCA-4), the 1st dummy source / drain contact pattern (28-6a) is connected to the 1st wiring layer (58b) through the 1st via (56d), and the 1st wiring layer (58b) may not be connected to the 2nd dummy source / drain contact pattern (28-6c).

[0131] FIG. 18 is a schematic diagram showing an electronic system including a semiconductor device according to one embodiment of the technical concept of the present invention.

[0132] Specifically, the electronic system (100) may include a controller (110), an input / output device (120), a memory (130), and an interface (140). The electronic system (100) may be a mobile system or a system that transmits or receives information. The mobile system may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card.

[0133] The controller (110) can execute a program and control the system (100). The controller (110) may include a semiconductor device according to an embodiment of the present invention. The controller (110) may be, for example, a microprocessor, a digital signal processor, a microcontroller, or a similar device.

[0134] The input / output device (120) can be used to input or output data of the electronic system (100). The electronic system (100) can be connected to an external device, such as a personal computer or a network, using the input / output device (120) to exchange data with the external device. The input / output device (120) may be, for example, a keypad, a keyboard, or a display.

[0135] The memory (130) may store code and / or data for the operation of the controller (110), and / or data processed by the controller (110). The memory (130) may include semiconductor devices (EX1-EX9) according to an embodiment of the present invention. The interface (140) may be a data transmission channel between the electronic system (100) and another external device. The controller (110), the input / output device (120), the memory (130), and the interface (140) may communicate with each other via a bus (150).

[0136] For example, such electronic systems (100) can be used in mobile phones, MP3 players, navigation, portable multimedia players (PMP), solid state disks (SSDs), or household appliances.

[0137] Although embodiments of the present invention have been schematically described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the essential features of its technical concept.

[0138] Furthermore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0139] 12: Active area, 14a: First gate line, 14b: Second gate line, 24: First source / drain contact pattern, 26: Second source / drain contact pattern, 28: Dummy source / drain contact pattern

Claims

Claim 1 A semiconductor device comprising: an active region disposed on a substrate; a first gate line extending in a second direction on the active region; a second gate line extending in the second direction and disposed spaced apart from the first gate line and the second direction on the active region; a first source / drain contact pattern disposed on the active region on one side of the first gate line; a second source / drain contact pattern disposed on the active region on one side of the second gate line; and a dummy source / drain contact pattern disposed on the active region between the first gate line and the second gate line, wherein the dummy source / drain contact pattern has a smaller size compared to the first source / drain contact pattern and the second source / drain contact pattern. Claim 2 A semiconductor device according to claim 1, wherein the dummy source / drain contact pattern is spaced apart from at least one of one edge and the other edge of the active region in the second direction. Claim 3 A semiconductor device according to claim 1, wherein the dummy source / drain contact pattern comprises a plurality of dummy source / drain contact patterns, and the plurality of dummy source / drain contact patterns have a smaller size than the first and second source / drain contact patterns. Claim 4 A semiconductor device according to claim 1, wherein the dummy source / drain contact pattern has a first pattern width in the first direction and a first pattern length in the second direction, the first source / drain contact pattern has a second pattern width in the first direction and a second pattern length in the second direction, the second source / drain contact pattern has a third pattern width in the first direction and a third pattern length in the second direction, the first pattern width is equal to the second pattern width and the third pattern width, and the first pattern length is smaller than the second pattern length and the third pattern length. Claim 5 A semiconductor device according to claim 1, wherein the dummy source / drain contact pattern has a first pattern width in the first direction and a first pattern length in the second direction, the first source / drain contact pattern has a second pattern width in the first direction and a second pattern length in the second direction, the second source / drain contact pattern has a third pattern width in the first direction and a third pattern length in the second direction, the first pattern length is equal to the second pattern length and the third pattern length, and the first pattern width is smaller than the second pattern width and the third pattern width. Claim 6 A semiconductor device according to claim 1, wherein the dummy source / drain contact pattern comprises a plurality of sub-dummy source / drain contact patterns located apart from each other. Claim 7 A semiconductor device characterized by comprising: an active region disposed on a substrate having a first region width in a first direction and a first region length in a second direction perpendicular to the first direction; a first gate line extending in the second direction on the active region; a second gate line extending in the second direction and disposed on the active region spaced apart from the first gate line in the first direction; a first active contact region disposed on the active region on one side of the first gate line; a second active contact region disposed on the active region on one side of the second gate line; a dummy contact region disposed on the active region between the first gate line and the second gate line; a first source / drain contact pattern disposed on the first active contact region spaced apart from the first gate line in the first direction; and a second source / drain contact pattern disposed on the second active contact region spaced apart from the second gate line in the first direction. Claim 8 A semiconductor device according to claim 7, wherein the first source / drain contact pattern has a second pattern width in the first direction and a second pattern length in the second direction, and the second source / drain contact pattern has a third pattern width in the first direction and a third pattern length in the second direction, wherein the first region length is equal to the second pattern length and the third pattern length, and the first region width is greater than the second pattern width and the third pattern width. Claim 9 A semiconductor device comprising: an active region formed on a substrate; a plurality of gate lines spaced apart in a first direction and extended in a second direction perpendicular to the first direction on the active region, wherein the gate lines include a first gate line located to the left in the first direction and a second gate line located to the right; a first active contact region disposed on one side of the first gate line in the active region; a second active contact region disposed on one side of the second gate line in the active region; a plurality of dummy contact regions disposed on the active region between the gate lines; a first source / drain contact pattern disposed on the first active contact region; a second source / drain contact pattern disposed on the second active contact region; and a plurality of dummy source / drain contact patterns disposed on at least one of the plurality of dummy contact regions, wherein the dummy source / drain contact patterns have a smaller size compared to the first source / drain contact pattern and the second source / drain contact pattern. Claim 10 A semiconductor device according to claim 9, wherein the dummy source / drain contact patterns have different pattern widths in the first direction.

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