Semiconductor chip and semiconductor package comprising the same

Abstract

A semiconductor chip according to an exemplary embodiment of the present disclosure comprises: a semiconductor substrate having a first surface and a second surface opposite to the first surface, and having an active layer in a portion adjacent to the first surface; a through electrode extending vertically within the semiconductor substrate and having a lower surface connected to the active layer and an upper surface opposite to the lower surface and at a lower level than the second surface of the semiconductor substrate; a passivation layer on the second surface of the semiconductor substrate; and a bonding pad disposed on a portion of the passivation layer and the upper surface of the through electrode, having a vertical cross-section in the shape of a "T" to be connected to the through electrode.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to a semiconductor chip and a semiconductor package including the same. Background Technology

[0002] As the storage capacity of a semiconductor package increases, the semiconductor package may include multiple stacked semiconductor chips. Specifically, a lower semiconductor chip may have bonding pads, and an upper semiconductor chip mounted on the lower semiconductor chip may have chip connection terminals connected to the bonding pads of the lower semiconductor chip. Recently, research aimed at improving the reliability of the connection structure of multiple semiconductor chips has been active. The problem to be solved

[0003] One of the problems that the technical concept of the present disclosure aims to solve is to provide a semiconductor chip with improved structural reliability and a semiconductor package including the same. means of solving the problem

[0004] To achieve the above objective, an exemplary embodiment of the present disclosure provides a semiconductor substrate having a first surface and a second surface opposite to the first surface, and having an active layer in a portion adjacent to the first surface; a through electrode extending vertically within the semiconductor substrate and having a lower surface connected to the active layer and an upper surface opposite to the lower surface and at a lower level than the second surface of the semiconductor substrate; a passivation layer on the second surface of the semiconductor substrate; and a bonding pad disposed on a portion of the passivation layer and the upper surface of the through electrode and having a vertical cross-section in the shape of a "T" to be connected to the through electrode.

[0005] An exemplary embodiment of the present disclosure provides a semiconductor substrate having a first surface and a second surface opposite to the first surface, and having an active layer in a portion adjacent to the first surface; a through electrode extending vertically within the semiconductor substrate and having a lower surface connected to the active layer and an upper surface opposite to the lower surface and at a lower level than the second surface of the semiconductor substrate; a chip pad located on the first surface of the semiconductor substrate and connected to the active layer; a passivation layer on the second surface of the semiconductor substrate; a bonding pad disposed on a portion of the passivation layer and the upper surface of the through electrode and having a vertical cross-section in the shape of a "T" to be connected to the through electrode; and a pad seed layer disposed below the bonding pad and conformally formed along the lower surface of the bonding pad.

[0006] An exemplary embodiment of the present disclosure comprises: a package substrate; a lower semiconductor chip mounted on the package substrate, the lower semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a lower active layer in a portion adjacent to the first surface; a lower through-electrode having a lower surface extending vertically within the lower semiconductor substrate and connected to the active layer, and an upper surface opposite to the lower surface and at a level lower than the second surface of the lower semiconductor substrate; a lower passivation layer on the second surface of the lower semiconductor substrate; a lower bonding pad disposed on a portion of the lower passivation layer and on the upper surface of the lower through-electrode, and having a vertical cross-section in the shape of a "T" to be connected to the lower through-electrode; and a lower pad seed layer disposed below the lower bonding pad and conformally formed along the lower surface of the lower bonding pad; the lower semiconductor chip comprising: A semiconductor package is provided comprising: an upper semiconductor chip mounted on the lower semiconductor chip, the upper semiconductor substrate having a third surface facing the lower semiconductor chip and a fourth surface opposite to the third surface, and having an upper active layer in a portion adjacent to the third surface; an upper chip pad disposed on the third surface of the upper semiconductor substrate and connected to the upper active layer; and an upper chip connection terminal interposed between the upper chip pad and the lower bonding pad; and a molding layer surrounding the lower semiconductor chip and the upper semiconductor chip on the package substrate. Effects of the invention

[0007] A semiconductor chip according to the technical concept of the present disclosure may include a bonding pad having a vertical cross-section in the shape of the English letter "T" and a pad seed layer conformally formed along the lower surface of the bonding pad.

[0008] Due to the aforementioned structure of the bonding pad of the semiconductor chip, the contact area between the bonding pad and the pad seed layer can be increased. Accordingly, in the step of mounting a separate semiconductor chip on the semiconductor chip, the delamination phenomenon between the bonding pad and the pad seed layer can be reduced. In other words, the structural reliability of the semiconductor chip and the semiconductor package including it can be improved. Brief explanation of the drawing

[0009] FIG. 1 is a cross-sectional view of a semiconductor chip according to an exemplary embodiment of the present disclosure. Figures 2 and 3 are enlarged views of the area marked "A" in Figure 1. FIG. 4 is a cross-sectional view of a semiconductor chip according to an exemplary embodiment of the present disclosure. FIG. 5 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure. Figure 6 is an enlarged view of the area marked "B" in Figure 5. Figure 7 is an enlarged view of a part of a semiconductor package according to a comparative example. FIG. 8 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure. FIG. 9 is a flowchart showing some steps of a method for manufacturing a semiconductor chip according to an exemplary embodiment of the present disclosure. Additionally, FIGS. 10 to 19 are drawings showing each step of a method for manufacturing a semiconductor chip according to an exemplary embodiment of the present disclosure. Specific details for implementing the invention

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0011] FIG. 1 is a cross-sectional view of a semiconductor chip (10) according to an exemplary embodiment of the present disclosure. FIG. 2 and FIG. 3 are enlarged views of the area marked "A" in FIG. 1.

[0012] Referring together to FIGS. 1 to 3, a semiconductor chip (10) according to an exemplary embodiment of the present disclosure may include a semiconductor substrate (110), a chip pad (120), a through electrode (130), a bonding pad (140), a pad seed layer (150), a first passivation layer (160), a second passivation layer (170), and a chip connection terminal (180), etc.

[0013] A semiconductor chip (10) according to an exemplary embodiment of the present disclosure can function as a lower semiconductor chip (30) in a semiconductor package comprising a lower semiconductor chip (Fig. 5, 30) and an upper semiconductor chip (Fig. 5, 40) mounted on the lower semiconductor chip (30).

[0014] In an exemplary embodiment, the semiconductor chip (10) may include a logic semiconductor chip. The logic semiconductor chip may include, for example, a logic semiconductor chip such as a CPU (Central Processor Unit), MPU (Micro Processor Unit), GPU (Graphic Processor Unit), or AP (Application Processor).

[0015] Additionally, the semiconductor chip (10) may include a memory semiconductor chip. The memory semiconductor chip may include, for example, a volatile memory semiconductor chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), and may also include a non-volatile memory semiconductor chip such as PRAM (Phase-change Random Access Memory), MRAM (Magneto-resistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory).

[0016] The semiconductor substrate (110) of the semiconductor chip (10) may have a first surface (110a) and a second surface (110b) opposite to the first surface (110a). In an exemplary embodiment, the first surface (110a) of the semiconductor substrate (110) may be the lower surface of the semiconductor substrate (110) on which the chip pad (120) is mounted, and the second surface (110b) of the semiconductor substrate (110) may be the upper surface of the semiconductor substrate (110) on which the bonding pad (140) is mounted.

[0017] The semiconductor substrate (110) may have an active layer (AL) in a portion adjacent to the first surface (110a). In an exemplary embodiment, the active layer (AL) may include a plurality of individual devices of various types. For example, the plurality of individual devices may include various microelectronic devices, such as a complementary metal-oxide semiconductor transistor (CMOS transistor), a metal-oxide-semiconductor field effect transistor (MOSFET), a large-scale integration (LSI) system, an image sensor such as a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), active devices, and passive devices.

[0018] In an exemplary embodiment, the semiconductor substrate (110) may include silicon (Si). Additionally, the semiconductor substrate (110) may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). However, the material of the semiconductor substrate (110) is not limited to those described above.

[0019] A chip pad (120) of a semiconductor chip (10) may be a pad disposed on a first surface (110a) of a semiconductor substrate (110) and electrically connected to a plurality of individual elements within an active layer (AL). For example, a plurality of chip pads (120) may be provided.

[0020] In an exemplary embodiment, the material of the chip pad (120) may include aluminum (Al). However, not limited to the foregoing, the material of the chip pad (120) may include metals such as nickel (Ni), copper (Cu), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or combinations thereof.

[0021] The through electrode (130) of the semiconductor chip (10) may be positioned to extend vertically within the semiconductor substrate (110). The vertical direction may be defined as a direction perpendicular to the direction in which the first surface (110a) and the second surface (110b) of the semiconductor substrate (110) extend, and the horizontal direction may be defined as a direction parallel to the direction in which the first surface (110a) and the second surface (110b) of the semiconductor substrate (110) extend.

[0022] In an exemplary embodiment, the through electrode (130) may be in the shape of a column. For example, the through electrode (130) may be in the shape of a cylinder, or may be in the shape of a polygonal column such as a triangular column or a square column. Additionally, the through electrode (130) may have a lower surface (130a) connected to the active layer (AL) of the semiconductor substrate (110), and an upper surface (130b) opposite to the lower surface (130a) and connected to the bonding pad (140).

[0023] In FIG. 1, the through electrode (130) is depicted as passing through only a part of the semiconductor substrate (110) and being connected to the active layer (AL), but is not limited thereto, and the through electrode (130) may pass completely through the semiconductor substrate (110) and be in contact with the chip pad (120).

[0024] In an exemplary embodiment, the level of the upper surface (130b) of the through electrode (130) may be lower than the level of the second surface (110b) of the semiconductor substrate (110). Hereinafter, the level of the first configuration may be defined as the height formed by the first configuration in a vertical direction from the first surface (110a) of the semiconductor substrate (110). For example, the level of the upper surface (130b) of the through electrode (130) may be defined as the height formed by the upper surface (130b) of the through electrode (130) in a vertical direction from the first surface (110a) of the semiconductor substrate (110). Additionally, the level of the second surface (110b) of the semiconductor substrate (110) may be defined as the height formed by the second surface (110b) of the semiconductor substrate (110) in a vertical direction from the first surface (110a).

[0025] In an exemplary embodiment, the level of the upper surface (130b) of the through electrode (130) may be lower than the level of the second surface (110b) of the semiconductor substrate (110), so that a substrate groove (Fig. 15, 110H) defined by the inner surface of the semiconductor substrate (110) and the upper surface (130b) of the through electrode (130) may be provided on the upper surface of the through electrode (130). The substrate groove (110H) may be filled by a bonding pad (140) and a pad seed layer (150) to be described later.

[0026] In an exemplary embodiment, the through electrode (130) may include a barrier film (not shown) formed on the surface of the through electrode (130) and a layer of embedded conductive material (not shown) filling the inside of the barrier film.

[0027] The first passivation layer (160) of the semiconductor chip (10) may be a layer of insulating material disposed on the second surface (110b) of the semiconductor substrate (110). For example, the first passivation layer (160) may be disposed on the first surface (110b) of the semiconductor substrate (110) and may surround a portion of the pad seed layer (150). Additionally, the first passivation layer (160) may not cover the upper surface (130b) of the through electrode (130).

[0028] In an exemplary embodiment, the material of the first passivation layer (160) may include silicon nitride (SiN). However, it is not limited thereto, and the material of the first passivation layer (160) may include silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon carbonitride (SiCN), or a combination thereof.

[0029] A bonding pad (140) of a semiconductor chip (10) may be a pad disposed on a part of a first passivation layer (160) and a through electrode (130), and electrically connected to said through electrode (130). Additionally, the bonding pad (140) may be a pad that contacts a chip connection terminal (Fig. 5, 440) included in a separate semiconductor chip (Fig. 5, 40) mounted on the semiconductor chip (10).

[0030] In an exemplary embodiment, referring to FIG. 1, the vertical cross-section of the bonding pad (140) may be in the shape of the letter "T". Additionally, the horizontal cross-section of the bonding pad (140) may be in the shape of a circle.

[0031] In an exemplary embodiment, the bonding pad (140) may include a first pad portion (143) and a second pad portion (145). The first pad portion (143) may be a part of the bonding pad (140) surrounded by the semiconductor substrate (110) and the first passivation layer (160). Additionally, the first pad portion (143) may be a part of the bonding pad (140) in contact with the first seed portion (153) and the second seed portion (155) of the pad seed layer (150) to be described later.

[0032] In an exemplary embodiment, the second pad portion (145) may be a part of the bonding pad (140) disposed on a part of the first passivation layer (160) and the first pad portion (143), having a horizontal length (145d) greater than the horizontal length (143d) of the first pad portion (143). Additionally, the second pad portion (145) may be a part of the bonding pad (140) supported by a third seed portion (157) of the pad seed layer (150) to be described later.

[0033] In an exemplary embodiment, the first pad portion (143) and the second pad portion (145) of the bonding pad (140) may be integrated. Additionally, the first pad portion (143) and the second pad portion (145) of the bonding pad (140) may comprise substantially the same material.

[0034] In an exemplary embodiment, the vertical cross-section of the first pad portion (143) of the bonding pad (140) may be rectangular. Additionally, the vertical cross-section of the second pad portion (145) of the bonding pad (140) may be rectangular, having a horizontal length (145d) greater than the horizontal length (143d) of the first pad portion (143).

[0035] In an exemplary embodiment, the horizontal length (143d) of the first pad portion (143) of the bonding pad (140) may be about 2 micrometers to about 6 micrometers. For example, the horizontal length (143d) of the first pad portion (143) may be about 4 micrometers.

[0036] Referring to FIG. 2, the sum of the horizontal length (143d) of the first pad portion (143) of the bonding pad (140) and the thickness of the pad seed layer (150) may be substantially the same as the horizontal length (130d) of the through electrode (130).

[0037] However, not limited thereto, with reference to FIG. 3, the horizontal length (143d) of the first pad portion (143) of the bonding pad (140) may be greater than the horizontal length (130d) of the through electrode (130).

[0038] The horizontal length (143d) of the first pad portion (143) of the bonding pad (140) may be greater than the horizontal length (130d) of the through electrode (130), so that the structural reliability of the bonding pad (140) can be improved. For example, in the step of mounting a separate semiconductor chip (Fig. 5, 40) on a semiconductor chip (10) according to an exemplary embodiment of the present disclosure, the delamination phenomenon between the bonding pad (140) and the pad seed layer (150) can be reduced.

[0039] In an exemplary embodiment, the horizontal length (145d) of the second pad portion (145) of the bonding pad (140) may be about 15 micrometers to about 20 micrometers. For example, the horizontal length of the second pad portion (145) may be about 17 micrometers.

[0040] Additionally, the vertical length (145h) of the second pad portion (145) of the bonding pad (140) may be about 2 micrometers to about 3 micrometers. For example, the vertical length (145h) of the second pad portion (145) may be 2.5 micrometers.

[0041] Additionally, the thickness of the pad seed layer (150) may be much smaller than the vertical length (145h) of the second pad portion (145), so the vertical length of the second pad portion (145) may be defined as a length including the thickness of the pad seed layer (150).

[0042] In an exemplary embodiment, the material of the bonding pad (140) may include a metal or a combination thereof, such as nickel (Ni), aluminum (Al), copper (Cu), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc. For example, the material of the bonding pad (140) may have a structure in which gold (Au) is laminated on nickel (Ni).

[0043] The pad seed layer (150) of the semiconductor chip (10) may be a layer formed conformally along a portion of the first passivation layer (160), the inner surface of the semiconductor substrate (110), and the upper surface (130b) of the through electrode (130), which is disposed below the bonding pad (140). In other words, the pad seed layer (150) may be a layer formed conformally along the lower surface of the bonding pad (140).

[0044] In an exemplary embodiment, the thickness of the pad seed layer (150) may be about 200 nanometers to about 300 nanometers. For example, the thickness of the pad seed layer (150) may be about 250 nanometers.

[0045] In an exemplary embodiment, the pad seed layer (150) may be formed by performing physical vapor deposition, and the bonding pad (140) may be formed by performing a plating process utilizing the pad seed layer (150). For example, when copper (Cu) is used as the material for the bonding pad (140), at least a portion of the pad seed layer (150) may act as a diffusion barrier layer.

[0046] In an exemplary embodiment, the material of the pad seed layer (150) may be titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), aluminum (Al), or a combination thereof. For example, the structure of the pad seed layer (150) may be Cu / Ti, in which copper is deposited on titanium, or Cu / TiW, in which copper is deposited on titanium tungsten. However, the material of the pad seed layer (150) is not limited to the aforementioned materials.

[0047] In an exemplary embodiment, the pad seed layer (150) may include a first seed portion (153), a second seed portion (155), and a third seed portion (157). The first seed portion (153) may be a part of the pad seed layer (150) interposed between the upper surface (130b) of the through electrode (130) and the lower surface of the first pad portion (143) of the bonding pad (140). Additionally, the first seed portion (153) may be a part of the pad seed layer (150) that overlaps in a vertical direction with the first pad portion (143) of the bonding pad (140).

[0048] In an exemplary embodiment, the second seed portion (155) may be a part of a pad seed layer (150) that extends vertically from the first seed portion (153) and is interposed between the inner surface of the semiconductor substrate (110) and the first passivation layer (160) and the side of the first pad portion (143) of the bonding pad (140). Additionally, the second seed portion (155) may surround the side of the first pad portion (143). Additionally, the second seed portion (155) may be a part of the pad seed layer (150) that overlaps horizontally with the first pad portion (143) of the bonding pad (140).

[0049] In an exemplary embodiment, the third seed portion (157) may extend horizontally from the second seed portion (155) and be interposed between the first passivation layer (160) and the second pad portion (145) of the bonding pad (140). Additionally, the third seed portion (157) may be a part of the pad seed layer (150) that supports the edge of the second pad portion (145). Additionally, the third seed portion (157) may be a part of the pad seed layer (150) that does not overlap vertically with the first pad portion (143) of the bonding pad (140) but overlaps vertically with the second pad portion (145).

[0050] In an exemplary embodiment, the second passivation layer (170) may be a layer of insulating material disposed on the first surface (110a) of the semiconductor substrate (110) and surrounding the side of the chip pad (120). Additionally, the second passivation layer (170) may not cover the bonding surface of the chip pad (120).

[0051] In an exemplary embodiment, the material of the second passivation layer (170) may include silicon nitride (SiN). However, it is not limited thereto, and the material of the first passivation layer (170) may include silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon carbonitride (SiCN), or a combination thereof.

[0052] The chip connection terminal (180) of the semiconductor chip (10) may be a connection terminal for electrically connecting the semiconductor chip (10) to a package substrate (Fig. 5, 710). However, it is not limited to the above, and the chip connection terminal (180) may be a connection terminal for electrically connecting semiconductor chips.

[0053] In an exemplary embodiment, the chip connection terminal (180) may be attached to the bonding surface of the chip pad (120). The chip connection terminal (180) may be a solder ball of a metal material comprising at least one of tin (Sn), silver (Ag), copper (Cu), and aluminum (Al).

[0054] In the case of a semiconductor chip according to a comparative example, the bonding pad and pad seed layer included in the semiconductor chip may be in the shape of a plate, in which the upper and lower surfaces are parallel and the shape and area of ​​the upper and lower surfaces are the same.

[0055] A semiconductor chip (10) according to an exemplary embodiment of the present disclosure may include a bonding pad (140) having a vertical cross-section in the shape of a “T”, and a pad seed layer (150) conformally formed along the lower surface of the bonding pad (140).

[0056] The contact area of ​​the bonding pad (140) and the pad seed layer (150) of the semiconductor chip (10) according to an exemplary embodiment of the present disclosure may be larger than the contact area of ​​the bonding pad and the pad seed layer of the semiconductor chip according to a comparative example.

[0057] Accordingly, the structural reliability of the bonding pad (140) of the semiconductor chip (10) according to an exemplary embodiment of the present disclosure can be improved. For example, in the step of mounting a separate semiconductor chip (Fig. 5, 40) on the semiconductor chip (10), the delamination phenomenon between the bonding pad (140) and the pad seed layer (150) can be reduced.

[0058] FIG. 4 is a cross-sectional view of a semiconductor chip (20) according to an exemplary embodiment of the present disclosure.

[0059] Referring to FIG. 4, a semiconductor chip (20) according to an exemplary embodiment of the present disclosure may include a semiconductor substrate (110), a chip pad (120), a through electrode (130), a bonding pad (140), a pad seed layer (150), a first passivation layer (160), a second passivation layer (170), a redistribution structure (210), an under bump metal (UBM, 220), and a chip connection terminal (230), etc.

[0060] In the following, the overlapping details of the semiconductor chip (10) of FIG. 1 and the semiconductor chip (20) of FIG. 4 will be omitted, and the differences will be explained in detail.

[0061] The redistribution structure (210) of the semiconductor chip (20) may be a structure disposed on a first surface (110a) of the semiconductor substrate (110). In an exemplary embodiment, the redistribution structure (210) may include a redistribution insulating layer (213), a redistribution line pattern (215) extending horizontally within the redistribution insulating layer (213), and a redistribution via pattern (217) extending vertically within the redistribution insulating layer (213).

[0062] The redistribution insulating layer (213) may be a layer of insulating material that covers the redistribution line pattern (215) and the redistribution via pattern (217). In an exemplary embodiment, the redistribution insulating layer (213) may include an oxide or a nitride. For example, the redistribution insulating layer (213) may include silicon oxide or silicon nitride.

[0063] In an exemplary embodiment, the redistribution insulating layer (213) may comprise an insulating material of a photo-imageable dielectric (PID) material capable of photolithography processing. For example, the redistribution insulating layer (213) may comprise photosensitive polyimide (PSPI).

[0064] Unlike as illustrated in FIG. 4, the redistribution line pattern (215) may have multiple layers within the redistribution insulation layer (213), and the redistribution line pattern (215) may be electrically connected through the redistribution via pattern (217).

[0065] In an exemplary embodiment, a portion of the rewiring via pattern (217) may electrically connect the chip pad (120) and the rewiring line pattern (215). Additionally, a portion of the rewiring via pattern (217) may electrically connect the rewiring line pattern (215) and the under-bump metal (220).

[0066] In an exemplary embodiment, the material of the redistribution line pattern (215) and the redistribution via pattern (217) may include copper (Cu). However, it is not limited thereto, and the material of the redistribution line pattern (215) and the redistribution via pattern (217) may be a metal or an alloy thereof such as nickel (Ni), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc.

[0067] The under-bump metal (220) of the semiconductor chip (20) may be a pad attached to one side of the redistribution structure (210) and connected to the redistribution via pattern (233). One side of the under-bump metal (220) may be in contact with the redistribution via pattern (217), and the other side opposite to the one side may be in contact with the chip connection terminal (230).

[0068] The material of the under-bump metal (220) may include metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc., or alloys thereof, but is not limited to these.

[0069] The chip connection terminal (230) of the semiconductor chip (20) is attached to the under bump metal (220) and can be electrically connected to the active layer (AL) of the semiconductor substrate (110) through the redistribution line pattern (215) and the redistribution via pattern (217).

[0070] In an exemplary embodiment, the chip connection terminal (230) may be a solder ball of a metal material comprising at least one of tin (Sn), silver (Ag), copper (Cu), and aluminum (Al).

[0071] FIG. 5 is a cross-sectional view of a semiconductor package (1) according to an exemplary embodiment of the present disclosure. FIG. 6 is an enlarged view of the area marked "B" in FIG. 5.

[0072] Referring to FIG. 5 and FIG. 6 together, a semiconductor package (1) according to an exemplary embodiment of the present disclosure may be a semiconductor package comprising a plurality of semiconductor chips (30, 40). Specifically, the semiconductor package (1) may be a semiconductor package comprising a lower semiconductor chip (30) and an upper semiconductor chip (40) mounted on the lower semiconductor chip (30).

[0073] A semiconductor package (1) according to an exemplary embodiment of the present disclosure may include a lower semiconductor chip (30), an upper semiconductor chip (40), a package substrate (710), a package connection terminal (720), an adhesive layer (730), an underfill member (760), a molding layer (770), etc.

[0074] The lower semiconductor chip (30) and the upper semiconductor chip (40) included in the semiconductor package (1) may be different types of semiconductor chips. For example, the semiconductor package (1) may be a system-in-package (SIP) in which different types of semiconductor chips (30, 40) are electrically connected to each other and operate as a single system.

[0075] For example, if the lower semiconductor chip (30) is a memory semiconductor chip, the upper semiconductor chip (40) may be a logic semiconductor chip. Also, if the lower semiconductor chip (30) is a logic semiconductor chip, the upper semiconductor chip (40) may be a memory semiconductor chip.

[0076] The lower semiconductor chip (30) may be a semiconductor chip mounted on a package substrate (710). The lower semiconductor chip (30) may include a lower semiconductor substrate (310) having a lower active layer (AL_1), a lower chip pad (320), a lower through-electrode (330), a lower bonding pad (340), a lower pad seed layer (350), a first lower passivation layer (360), a second lower passivation layer (370), and a lower chip connection terminal (380), etc.

[0077] The technical concept regarding the lower semiconductor chip (30) overlaps with the content of the semiconductor chip (10) described with reference to FIGS. 1 and FIGS. 2, so the details are omitted. The lower semiconductor chip (30) can be connected to the package substrate (710) through the lower chip connection terminal (380).

[0078] The lower bonding pad (340) of the lower semiconductor chip (30) may include a first lower pad portion (343) and a second lower pad portion (345). The first lower pad portion (343) may be a part of the lower bonding pad (140) surrounded by the lower semiconductor substrate (310) and the first lower passivation layer (360).

[0079] In an exemplary embodiment, the second lower pad portion (345) may be a portion of the lower bonding pad (340) disposed on a portion of the first lower passivation layer (360) and the first lower pad portion (343), having a horizontal length (345d) greater than the horizontal length (343d) of the first lower pad portion (343).

[0080] In an exemplary embodiment, the horizontal length (343d) of the first lower pad portion (343) of the lower bonding pad (340) may be about 2 micrometers to about 6 micrometers. For example, the horizontal length (343d) of the first lower pad portion (343) may be about 4 micrometers.

[0081] In an exemplary embodiment, the horizontal length (345d) of the second lower pad portion (345) of the lower bonding pad (340) may be about 15 micrometers to about 20 micrometers. For example, the horizontal length of the second lower pad portion (345) may be about 17 micrometers.

[0082] In an exemplary embodiment, the sum of the horizontal length (343d) of the first lower pad portion (343) of the lower bonding pad (340) and the thickness of the lower pad seed layer (350) may be substantially the same as the horizontal length (330d) of the lower through electrode (330).

[0083] However, it is not limited thereto, and the horizontal length (343d) of the first lower pad portion (343) of the lower bonding pad (340) may be greater than the horizontal length (330d) of the lower penetrating electrode (330). Since the horizontal length (343d) of the first lower pad portion (343) of the lower bonding pad (340) may be greater than the horizontal length (330d) of the lower penetrating electrode (330), the structural reliability of the lower bonding pad (340) may be improved.

[0084] Additionally, the vertical length (345h) of the second lower pad portion (345) of the lower bonding pad (340) may be about 2 micrometers to about 3 micrometers. For example, the vertical length (345h) of the second lower pad portion (345) may be 2.5 micrometers.

[0085] In an exemplary embodiment, the lower pad seed layer (350) of the lower semiconductor chip (30) may include a first lower seed portion (353), a second lower seed portion (355), and a third lower seed portion (357). The first lower seed portion (353) may be a part of the lower pad seed layer (350) interposed between the upper surface of the through electrode (330) and the lower surface of the first lower pad portion (343) of the lower bonding pad (340). Additionally, the first lower seed portion (353) may be a part of the lower pad seed layer (350) that overlaps vertically with the first lower pad portion (343) of the lower bonding pad (340).

[0086] In an exemplary embodiment, the second lower seed portion (355) may be a part of a lower pad seed layer (350) that surrounds the side of the first lower pad portion (343) of the lower bonding pad (340), interposed between the inner surface of the lower semiconductor substrate (310) and the first lower passivation layer (360). Additionally, the second lower seed portion (355) may be a part of a lower pad seed layer (350) that overlaps horizontally with the first lower pad portion (343) of the lower bonding pad (340).

[0087] In an exemplary embodiment, the third lower seed portion (357) may be a part of the lower pad seed layer (350) that is interposed between the first lower passivation layer (360) and the second lower pad portion (345) of the lower bonding pad (340) and supports the edge of the second lower pad portion (345). Additionally, the third lower seed portion (357) may be a part of the lower pad seed layer (350) that does not overlap vertically with the first lower pad portion (343) of the lower bonding pad (340) but overlaps vertically with the second lower pad portion (345).

[0088] The upper semiconductor chip (40) may be a semiconductor chip mounted on the lower semiconductor chip (30) and electrically connected to the lower semiconductor chip (30).

[0089] The upper semiconductor chip (40) may include an upper semiconductor substrate (410) having an upper active layer (AL_2), an upper chip pad (420), an upper passivation layer (430), an upper chip connection terminal (440), etc. Below, overlapping details of the lower semiconductor chip (40) and the upper semiconductor chip (40) will be omitted, and the differences will be explained mainly.

[0090] The upper semiconductor substrate (410) of the upper semiconductor chip (40) may have a third surface (410a) facing the lower semiconductor chip (30) and a fourth surface (410b) opposite to the third surface (410a). Additionally, the upper semiconductor chip (40) may have an upper active layer (AL_2) in a portion adjacent to the third surface (410a).

[0091] The upper chip pad (420) of the upper semiconductor chip (40) may be a pad that is placed on the third surface (410a) of the upper semiconductor substrate (410) and connected to the upper active layer (AL_2).

[0092] The upper passivation layer (430) of the upper semiconductor chip (40) may be a layer of insulating material disposed on the third surface (410a) of the upper semiconductor substrate (410) and surrounding the side of the upper chip pad (420).

[0093] The upper chip connection terminal (440) of the upper semiconductor chip (40) may be a connection terminal for connecting the lower semiconductor chip (30) and the upper semiconductor chip (40). Specifically, the upper chip connection terminal (440) may be interposed between the lower bonding pad (340) of the lower semiconductor chip (30) and the upper chip pad (420) of the upper semiconductor chip (40) to electrically connect the lower semiconductor chip (30) and the upper semiconductor chip (40).

[0094] The package substrate (710) may be a substrate on which a plurality of semiconductor chips (30, 40) are mounted and which is used to connect the plurality of semiconductor chips (30, 40) to an external device. In an exemplary embodiment, the package substrate (710) may be a double-sided printed circuit board (PCB) comprising a first package substrate pad (713) and a second package substrate pad (715). However, not limited to the above, the package substrate (710) may be a single-sided printed circuit board comprising the first package substrate pad (313) on only one side.

[0095] In an exemplary embodiment, the package substrate (710) is not limited to the structure and material of a printed circuit board and may include various types of substrates such as a ceramic substrate.

[0096] The package connection terminal (720) is attached to the second package substrate pad (715) of the package substrate (710) and may be a connection terminal for connecting the semiconductor package (1) to an external device. For example, the package connection terminal (720) may be a solder ball of a metal material comprising at least one of tin (Sn), silver (Ag), copper (Cu), and aluminum (Al).

[0097] The adhesive layer (730) may be a layer that is placed between the lower semiconductor chip (30) and the upper semiconductor chip (40) and covers the lower bonding pad (340) of the lower semiconductor chip (30) and the upper chip connection terminal (440) of the upper semiconductor chip (40).

[0098] Additionally, the adhesive layer (730) may include an adhesive material for fixing the upper semiconductor chip (40) onto the lower semiconductor chip (30). For example, the adhesive layer (730) may be a Die Attach Film (DAF). However, the type of the adhesive layer (730) is not limited to that described above.

[0099] In an exemplary embodiment, the side of the adhesive layer (730) may be coplanar with at least one of the side of the lower semiconductor chip (30) and the side of the upper semiconductor chip (40). For example, as shown in FIG. 5, the side of the adhesive layer (730) may be coplanar with the side of the lower semiconductor chip (30) and the side of the upper semiconductor chip (40).

[0100] The underfill member (760) may be a layer that fills the space between the lower semiconductor chip (30) and the package substrate (710) and surrounds the lower chip connection terminal (380) of the lower semiconductor chip (30). The underfill member (760) may be a layer configured to fix the lower semiconductor chip (30) on the package substrate (710).

[0101] In an exemplary embodiment, the underfill member (760) may comprise at least one of an insulating polymer and an epoxy resin. For example, the underfill member (760) may comprise an epoxy molding compound (EMC).

[0102] The molding layer (770) may be a layer surrounding a plurality of semiconductor chips (30, 40) on a package substrate (710). Additionally, the molding layer (770) may be a layer that fixes a plurality of semiconductor chips (30, 40) on the package substrate (710).

[0103] In an exemplary embodiment, the molding layer (770) can form the exterior of the semiconductor package (1) together with the package substrate (710). For example, the side of the molding layer (770) and the side of the package substrate (710) can form the side of the semiconductor package (1). Additionally, the upper surface of the molding layer (770) can form the upper surface of the semiconductor package (1), and the lower surface of the package substrate (710) can form the lower surface of the semiconductor package (1). Furthermore, the side of the molding layer (770) may be coplanar with the side of the package substrate (710).

[0104] In an exemplary embodiment, the molding layer (770) may cover the fourth surface (410_b) of the upper semiconductor substrate (410) of the upper semiconductor chip (40). However, it is not limited thereto, and one surface of the molding layer (770) may be on the same plane as the fourth surface (410_b) of the upper semiconductor substrate (410). When the fourth surface (410_b) of the upper semiconductor substrate (410) is exposed to the outside by the molding layer (770), the semiconductor package (1) may be thin and light, and the heat dissipation performance of the semiconductor package (1) may be improved.

[0105] In an exemplary embodiment, the molding layer (770) may include a material of an epoxy molding compound. However, the material of the molding layer (770) is not limited to the aforementioned epoxy molding compound and may include various materials, such as epoxy-based materials, thermosetting materials, thermoplastic materials, UV-treated materials, etc.

[0106] Figure 7 is an enlarged view of a part of a semiconductor package according to a comparative example.

[0107] Hereinafter, with reference to FIGS. 6 and FIGS. 7 together, a semiconductor package (1) according to an exemplary embodiment of the present disclosure and a semiconductor package (1') according to a comparative example will be described in comparison.

[0108] Referring to FIG. 7, a semiconductor package (1') according to a comparative example may include a lower semiconductor chip (30'), an upper semiconductor chip (40') mounted on the lower semiconductor chip (30'), and an adhesive layer (730') interposed between the lower semiconductor chip (30') and the upper semiconductor chip (40').

[0109] The lower semiconductor chip (30') may include a lower semiconductor substrate (310'), a lower passivation layer (360'), a lower through-electrode (330'), a lower bonding pad (340'), and a lower pad seed layer (350').

[0110] Additionally, the upper semiconductor chip (40') may include an upper semiconductor substrate (410'), an upper chip pad (420'), an upper passivation layer (430'), and an upper chip connection terminal (440').

[0111] The level of the upper surface (330b') of the lower through-electrode (330') of the lower semiconductor chip (30') may be higher than the level of the second surface (310b') of the lower semiconductor substrate (310'). For example, the upper surface (330b') of the lower through-electrode (330') may be coplanar with one surface of the lower passivation layer (360') disposed on the lower semiconductor substrate (310').

[0112] Additionally, the horizontal cross-sectional area along the vertical direction of the lower pad seed layer (350') and the lower bonding pad (340') of the lower semiconductor chip (30') may be uniform. Accordingly, the vertical cross-sectional area of ​​the lower pad seed layer (350') and the lower bonding pad (340') of the lower pad seed layer (350') may be rectangular.

[0113] Referring again to FIG. 6, the level of the upper surface (330b) of the lower penetrating electrode (330) of the lower semiconductor chip (30) according to an exemplary embodiment of the present disclosure may be lower than the level of the second surface (310b) of the lower semiconductor substrate (310).

[0114] Accordingly, a substrate groove (Fig. 15, 110H) defined by the inner surface of the lower semiconductor substrate (310) and the upper surface (330b) of the lower through electrode (330) may be provided on the upper part of the lower through electrode (330). The lower bonding pad (340) and the lower pad seed layer (350) of the lower semiconductor chip (30) may fill the substrate groove (110H) of the lower semiconductor substrate (310).

[0115] According to an exemplary embodiment of the present disclosure, the vertical cross-section of the lower bonding pad (340) may be in the shape of the letter "T". For example, the vertical cross-section of the first lower pad portion (343) of the lower bonding pad (340) may be rectangular. Additionally, the vertical cross-section of the second lower pad portion (345) of the lower bonding pad (340) may be rectangular, having a horizontal length (345d) greater than the horizontal length (343d) of the first lower pad portion (343).

[0116] Additionally, the lower pad seed layer (350) may be conformally formed along the lower surface of the lower bonding pad (340). For example, the first lower seed portion (353) of the lower pad seed layer (350) may be a part of the lower pad seed layer (350) that overlaps vertically with the first lower pad portion (343), the second lower seed portion (355) may be a part of the lower pad seed layer (350) that surrounds the side of the first lower pad portion (343), and the third lower seed portion (357) may be a part of the lower pad seed layer (350) that does not overlap vertically with the first lower pad portion (343) of the lower bonding pad (340) but overlaps vertically with the second lower pad portion (345).

[0117] The contact area of ​​the lower bonding pad (340) and the lower pad seed layer (350) of the lower semiconductor chip (30) of the semiconductor package (1) according to an exemplary embodiment of the present disclosure may be larger than the contact area of ​​the lower bonding pad (340') and the lower pad seed layer (350') of the lower semiconductor chip (30') of the semiconductor package (1') according to a comparative example.

[0118] Specifically, the contact area of ​​the lower bonding pad (340) and the lower pad seed layer (350) of the lower semiconductor chip (30) of the semiconductor package (1) according to an exemplary embodiment of the present disclosure may be larger than the contact area of ​​the lower bonding pad (340') and the lower pad seed layer (350') of the lower semiconductor chip (30') of the semiconductor package (1') according to a comparative example by the area of ​​the side of the first lower pad portion (343) of the lower bonding pad (340).

[0119] According to an exemplary embodiment of the present disclosure, the level of the lower through-electrode (330) of the lower semiconductor chip (30) of the semiconductor package (1) on the upper surface (330b) is lower than the level of the second surface (310b) of the lower semiconductor substrate (310), and the vertical cross-section of the lower bonding pad (340) connected to the lower through-electrode (330) may be in the shape of the letter "T", so that the contact area of ​​the lower bonding pad (340) of the lower semiconductor chip (30) and the lower pad seed layer (350) may be increased.

[0120] Accordingly, in the step of mounting the upper semiconductor chip (40) on the lower semiconductor chip (30) (i.e., in the step of contacting the lower bonding pad (340) of the lower semiconductor chip (30) and the upper chip connection terminal (440) of the upper semiconductor chip (40), the delamination phenomenon between the lower bonding pad (340) and the lower pad seed layer (350) can be reduced.

[0121] That is, the structural reliability of the semiconductor package (1) according to the exemplary embodiment of the present disclosure can be improved.

[0122] FIG. 8 is a cross-sectional view of a semiconductor package (2) according to an exemplary embodiment of the present disclosure.

[0123] Referring to FIG. 8, a semiconductor package (2) according to an exemplary embodiment of the present disclosure may include a package substrate (710), a package connection terminal (720), a lower semiconductor chip (50), an intermediate semiconductor chip (80), and an upper semiconductor chip (90), a first adhesive layer (730a), a second adhesive layer (730b), an underfill member (760), a molding layer (770), and a heat sink (790), etc.

[0124] In the following, the overlapping details of the semiconductor package (1) of FIG. 7 and the semiconductor package (2) of FIG. 8 will be omitted, and the differences will be explained in detail.

[0125] In an exemplary embodiment, the semiconductor package (2) of FIG. 7 is shown to include three semiconductor chips (50, 80, 90), but the number of semiconductor chips included in the semiconductor package (2) is not limited to what was described above.

[0126] A semiconductor package (2) according to an exemplary embodiment of the present disclosure may further include an intermediate semiconductor chip (80) interposed between a lower semiconductor chip (50) and an upper semiconductor chip (90).

[0127] The lower semiconductor chip (50) may include a lower semiconductor substrate (510) having a lower active layer (AL_1), a lower chip pad (520), a lower through-electrode (530), a lower bonding pad (540), a lower pad seed layer (550), a first lower passivation layer (560), a second lower passivation layer (570), and a lower chip connection terminal (580), etc.

[0128] Additionally, the upper semiconductor chip (90) may include an upper semiconductor substrate (910) having an upper active layer (AL_2), an upper chip pad (920), an upper passivation layer (930), an upper chip connection terminal (940), etc.

[0129] The technical concept regarding the lower semiconductor chip (50) and the upper semiconductor chip (90) of the semiconductor package (2) overlaps with the content explained with reference to FIG. 7, so the details are omitted.

[0130] The intermediate semiconductor chip (80) may include an intermediate semiconductor substrate (810) having an intermediate active layer (AL_3), an intermediate chip pad (820), an intermediate through-electrode (830), an intermediate bonding pad (840), an intermediate pad seed layer (850), a first intermediate passivation layer (860), a second intermediate passivation layer (870), and an intermediate chip connection terminal (880), etc.

[0131] Since the structure of the intermediate bonding pad (840) and intermediate pad seed layer (850) of the intermediate semiconductor chip (80) may be substantially the same as the structure of the lower bonding pad (540) and lower pad seed layer (550) of the lower semiconductor chip (50), a detailed description of the intermediate bonding pad (840) and intermediate pad seed layer (850) of the intermediate semiconductor chip (80) is omitted.

[0132] In an exemplary embodiment, the intermediate chip connection terminal (880) of the intermediate semiconductor chip (80) is interposed between the lower bonding pad (540) of the lower semiconductor chip (50) and the intermediate chip pad (820) of the intermediate semiconductor chip (80) to electrically connect the lower semiconductor chip (50) and the intermediate semiconductor chip (80).

[0133] In an exemplary embodiment, the intermediate bonding pad (840) of the intermediate semiconductor chip (80) may come into contact with the upper chip connection terminal (940) of the upper semiconductor chip (90). In other words, the upper chip connection terminal (940) of the upper semiconductor chip (90) may be interposed between the intermediate bonding pad (840) of the intermediate semiconductor chip (80) and the upper chip pad (920) of the upper semiconductor chip (90) to electrically connect the intermediate semiconductor chip (80) and the upper semiconductor chip (90).

[0134] The first adhesive layer (730a) of the semiconductor package (2) may be a layer that is placed between the intermediate semiconductor chip (80) and the upper semiconductor chip (90) and covers the intermediate bonding pad (840) of the intermediate semiconductor chip (80) and the upper chip connection terminal (940) of the upper semiconductor chip (90).

[0135] The second adhesive layer (730b) of the semiconductor package (2) may be a layer that is placed between the lower semiconductor chip (50) and the intermediate semiconductor chip (80) and covers the lower bonding pad (540) of the lower semiconductor chip (50) and the intermediate chip connection terminal (880) of the intermediate semiconductor chip (80).

[0136] The underfill member (760) of the semiconductor package (2) may be a layer that fills the space between the lower semiconductor chip (50) and the package substrate (710) and surrounds the lower chip connection terminal (580) of the lower semiconductor chip (50).

[0137] The molding layer (770) may be a layer surrounding a plurality of semiconductor chips (50, 80, 90) on a package substrate (710). Additionally, the molding layer (770) may be a layer that fixes a plurality of semiconductor chips (50, 80, 90) on the package substrate (710).

[0138] In an exemplary embodiment, the upper surface of the molding layer (770) may be on the same plane as the upper surface of the upper semiconductor chip (90). However, not limited to the above, the molding layer (770) may cover the upper surface of the upper semiconductor chip (90).

[0139] Additionally, the heat sink (790) may be attached to the molding layer (770) and configured to release heat generated from the semiconductor chips (50, 80, 90) to the outside.

[0140] In an exemplary embodiment, the heat sink (790) may include a metal-based material with excellent thermal conductivity. However, not limited to the foregoing, the heat sink (790) may include a ceramic-based material, a carbon-based material, a polymer-based material, etc.

[0141] In addition, to improve the heat dissipation performance of the semiconductor package (2), the structure of the heat sink (790) may be provided with an uneven structure in which concave and convex shapes are repeated.

[0142] In an exemplary embodiment, the heat sink (790) may be fixed onto the molding layer (770) by an adhesive film (795). For example, the adhesive film (795) may have adhesive properties of its own and may also be provided bonded to a separate thermally conductive adhesive tape. For example, the adhesive tape may be a double-sided adhesive tape.

[0143] FIG. 9 is a flowchart showing some steps of a method (S100) for manufacturing a semiconductor chip (10) according to an exemplary embodiment of the present disclosure. Also, FIGS. 10 to 19 are drawings showing each step of a method (S100) for manufacturing a semiconductor chip (10) according to an exemplary embodiment of the present disclosure.

[0144] Referring to FIG. 9, a method for manufacturing a semiconductor chip (10) according to an exemplary embodiment of the present disclosure (S100) may include the steps of removing a portion of a semiconductor substrate (110) to expose a through electrode (130) (S1100), forming a passivation layer (160) on the semiconductor substrate (110) (S1200), etching a portion of the through electrode (130) (S1300), forming a pad seed layer (150) on the semiconductor substrate (110) (S1400), and forming a bonding pad (140) on the semiconductor substrate (110) (S1500).

[0145] Referring together to FIGS. 9 to 12, step S1100 may include a step of grinding a part of the semiconductor substrate (110) (S1150) and a step of selectively removing a part of the semiconductor substrate (110) (S1170).

[0146] Referring to FIG. 10, a semiconductor substrate (110) having a first surface (110a) and a second surface (110b) and an active layer (AL) adjacent to the first surface (110a), and a through electrode (130) embedded inside the semiconductor substrate (110) and connected to the active layer (AL) may be provided.

[0147] In an exemplary embodiment, the vertical length of the semiconductor substrate (110) may be provided to be 700 micrometers or more. For example, the vertical length of the semiconductor substrate (110) may be about 770 micrometers. Additionally, the vertical length of the through electrode (130) embedded inside the semiconductor substrate (110) may be about 50 micrometers.

[0148] Referring to FIG. 11, step S1150 may be a step of removing a portion of the semiconductor substrate (110) by grinding the second surface (110b) of the semiconductor substrate (110). In an exemplary embodiment, in step S1100, a portion of the semiconductor substrate (110) may be physically removed until the level of the second surface (110b) of the semiconductor substrate (110) is relatively somewhat higher than the level of the upper surface of the through electrode (130).

[0149] Referring to FIG. 12, step S1170 may be a step of selectively removing a portion of the semiconductor substrate (110) to expose the through electrode (130) from the semiconductor substrate (110). In an exemplary embodiment, in step S1170, a portion of the semiconductor substrate (110) may be removed until the level of the second surface (110b) of the semiconductor substrate (110) is lower than the level of the upper surface of the through electrode (130).

[0150] In an exemplary embodiment, if the semiconductor substrate (110) comprises a silicon material, a portion of the semiconductor substrate (110) may be removed through a chemical solution. The chemical solution may be a solution that selectively removes only the semiconductor substrate (110) through a chemical reaction. In step S1170, the through electrode (130) may not be removed as it does not react chemically with the chemical solution.

[0151] Referring together to FIG. 9, FIG. 13, and FIG. 14, step S1200 may include a step (S1230) of applying a passivation layer (160) on a second surface (110b) of a semiconductor substrate (110) and a step (S1250) of etching a portion of the passivation layer (160) and a portion of the through electrode (130).

[0152] In an exemplary embodiment, referring to FIG. 13, in step S1230, the first passivation layer (160) may be applied on the second surface (110b) of the semiconductor substrate (110) to cover the through electrode exposed from the semiconductor substrate (110).

[0153] In an exemplary embodiment, referring to FIG. 14, in step S1250, a portion of the passivation layer (160) and the through electrode (130) may be ground until one side of the through electrode (130) is exposed.

[0154] In an exemplary embodiment, when step S1250 is performed, one side of the passivation layer (160) and one side of the through electrode (130) may be on the same plane. In other words, the passivation layer (160) may surround the side of the through electrode (130) on the second side (110b) of the semiconductor substrate (110) and expose the upper surface of the through electrode (130) to the outside.

[0155] Referring to FIG. 9 and FIG. 15 together, step S1300 may be a step of selectively etching only a part of the through electrode (130) without etching the semiconductor substrate (110).

[0156] In an exemplary embodiment, step S1300 may be a wet etching process that etches a portion of the through electrode (130) using a chemical agent that selectively dissolves only the through electrode (130).

[0157] However, not limited to the above, step S1300 may be a dry etching process that etches a portion of the penetrating electrode (130) through a chemical reaction by gas plasma or activated gas.

[0158] Additionally, through the execution of step S1300, the level of the upper surface (130b) of the through electrode (130) may be lower than the level of the second surface (110b) of the semiconductor substrate (110). Accordingly, a substrate groove (110H) defined by the inner surface of the semiconductor substrate (110) and the upper surface (130b) of the through electrode (130) may be provided on the upper surface of the through electrode (130).

[0159] In an exemplary embodiment, the vertical length of the substrate groove (110H) of the semiconductor substrate (110) may be about 2 micrometers to about 6 micrometers. For example, the vertical length of the through electrode (130) removed may be about 4 micrometers.

[0160] In an exemplary embodiment, the vertical length of the substrate groove (110H) of the semiconductor substrate (110) can be controlled by controlling the execution time of the etching process.

[0161] In an exemplary embodiment, the horizontal length (110H_d) of the substrate groove (110H) of the semiconductor substrate (110) may be greater than the horizontal length (130d) of the through electrode (130). However, it is not limited thereto, and the horizontal length (110H_d) of the substrate groove (110H) of the semiconductor substrate (110) may be substantially the same as the horizontal length (130d) of the through electrode (130).

[0162] Referring to FIG. 9 and FIG. 16 together, step S1400 may be a step of conformally forming a pad seed layer (150) on a semiconductor substrate (110).

[0163] In an exemplary embodiment, the pad seed layer (150) may be formed on the second surface (110b) of the semiconductor substrate (110) through a physical vapor deposition process. For example, the pad seed layer (150) may be formed on the second surface (110b) of the semiconductor substrate (110) with a thickness of about 200 nanometers to about 300 nanometers.

[0164] Referring together to FIG. 9 and FIG. 17 to 19, step S1500 may include a step of forming a photoresist material layer (PR) (S1530), a step of forming a bonding pad (140) (S1550), and a step of removing a portion of the photoresist material layer (PR) and the pad seed layer (150) (S1570).

[0165] Referring to FIG. 17, in step S1530, a photoresist material layer (PR) may be formed on the pad seed layer (150). The photoresist material layer (PR) may have pattern holes (PR_H) that expose through electrodes (130) through an exposure process and a development process.

[0166] Referring to FIG. 18, step S1550 may be a step of forming a bonding pad (140) through a plating process using a pad seed layer (150) exposed by a photoresist material layer (PR). In an exemplary embodiment, the bonding pad (140) may fill the pattern holes (PR_H) of the photoresist material layer (PR).

[0167] Referring to FIG. 19, step S1570 may be a step of removing a pad seed layer (150) that is not perpendicular to the photoresist material layer (PR) and the bonding pad (140).

[0168] In an exemplary embodiment, at step S1570, the passivation layer (160) may act as a stopper layer. In other words, the pad seed layer (150) that is not vertically overlapped with the bonding pad (140) may be removed so that the passivation layer (160) can be exposed to the outside.

[0169] The technical concept of the present disclosure described above is not limited to the aforementioned embodiments and the attached drawings. Furthermore, it will be obvious to those skilled in the art to which the present disclosure pertains that various substitutions, modifications, and changes are possible within the scope of the technical concept of the present disclosure.

Claims

Claim 1 A semiconductor substrate having a first surface and a second surface opposite to the first surface, and having an active layer in a portion adjacent to the first surface; a through electrode extending vertically within the semiconductor substrate and having a lower surface connected to the active layer and an upper surface opposite to the lower surface and at a lower level than the second surface of the semiconductor substrate; a passivation layer on the second surface of the semiconductor substrate; a bonding pad disposed on a portion of the passivation layer and the upper surface of the through electrode and having a vertical cross-section in the shape of a "T" to be connected to the through electrode; wherein the bonding pad comprises: a first pad portion surrounded by the semiconductor substrate and the passivation layer; and a second pad portion located on the first pad portion and having a horizontal length greater than the horizontal length of the first pad portion; wherein the horizontal length of the first pad portion of the bonding pad is greater than the horizontal length of the through electrode. Claim 2 delete Claim 3 delete Claim 4 A semiconductor chip according to claim 1, further comprising: a pad seed layer disposed below the bonding pad and conformally formed along the upper surface of the passivation layer and the upper surface of the through electrode. Claim 5 A semiconductor chip according to claim 4, wherein the pad seed layer comprises: a first seed portion interposed between the through electrode and the first pad portion; a second seed portion extending vertically from the first seed portion and surrounding the side of the first pad portion; and a third seed portion extending horizontally from the second seed portion and interposed between the passivation layer and the edge of the second pad portion. Claim 6 A semiconductor substrate having a first surface and a second surface opposite to the first surface, and having an active layer in a portion adjacent to the first surface; a through electrode extending vertically within the semiconductor substrate and having a lower surface connected to the active layer and an upper surface opposite to the lower surface and at a lower level than the second surface of the semiconductor substrate; a chip pad located on the first surface of the semiconductor substrate and connected to the active layer; a passivation layer on the second surface of the semiconductor substrate; a bonding pad disposed on a portion of the passivation layer and the upper surface of the through electrode and having a vertical cross-section in the shape of a "T" to be connected to the through electrode; and a pad seed layer disposed below the bonding pad and conformally formed along the lower surface of the bonding pad; comprising a semiconductor chip. Claim 7 A semiconductor chip according to claim 6, wherein the bonding pad comprises: a first pad portion surrounded by the semiconductor substrate and the passivation layer; and a second pad portion located on the passivation layer and the first pad portion and having a horizontal length greater than the horizontal length of the first pad portion, wherein the horizontal length of the first pad portion is greater than the horizontal length of the through electrode. Claim 8 A semiconductor chip according to claim 7, wherein the thickness of the pad seed layer is 200 nanometers to 300 nanometers, and the pad seed layer comprises: a first seed portion that overlaps in a vertical direction with the first pad portion of the bonding pad; a second seed portion that overlaps in a horizontal direction with the first pad portion of the bonding pad; and a third seed portion that does not overlap in a vertical direction with the first pad portion of the bonding pad but overlaps in a vertical direction with the second pad portion. Claim 9 A semiconductor chip according to claim 7, characterized in that the horizontal length of the first pad portion of the bonding pad is 2 micrometers to 6 micrometers, the horizontal length of the second pad portion of the bonding pad is 15 micrometers to 20 micrometers, and the vertical length of the second pad portion of the bonding pad is 2 micrometers to 3 micrometers. Claim 10 A package substrate; a lower semiconductor chip mounted on the package substrate, the lower semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a lower active layer in a portion adjacent to the first surface; a lower through-electrode having a lower surface extending vertically within the lower semiconductor substrate and connected to the active layer, and an upper surface opposite to the lower surface and at a level lower than the second surface of the lower semiconductor substrate; a lower passivation layer on the second surface of the lower semiconductor substrate; a lower bonding pad disposed on a portion of the lower passivation layer and the upper surface of the lower through-electrode, and having a vertical cross-section in the shape of a "T" to be connected to the lower through-electrode; and a lower pad seed layer disposed below the lower bonding pad and conformally formed along the lower surface of the lower bonding pad; the lower semiconductor chip comprising; and an upper semiconductor chip mounted on the lower semiconductor chip, the upper semiconductor substrate having a third surface facing the lower semiconductor chip and a fourth surface opposite to the third surface, and having an upper active layer in a portion adjacent to the third surface; A semiconductor package comprising: an upper semiconductor chip comprising: an upper chip pad disposed on the third surface of the upper semiconductor substrate and connected to the upper active layer; and an upper chip connection terminal interposed between the upper chip pad and the lower bonding pad; and a molding layer surrounding the lower semiconductor chip and the upper semiconductor chip on the package substrate.

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