Memory device and operating method thereof

Abstract

The present invention relates to an electronic device, and the memory device according to the present invention comprises a plurality of memory cells connected to a plurality of word lines, a peripheral circuit that performs a program operation for storing data in the plurality of memory cells, a vulnerable word line information storage unit that stores information regarding a vulnerable word line among the plurality of word lines, and a program operation control unit that controls the peripheral circuit to perform the program operation in a first program mode or a second program mode according to the result of comparing whether a selected word line corresponding to an address provided by a memory controller is a vulnerable word line based on the information regarding the vulnerable word line, and the information regarding the vulnerable word line includes information determined by a first pre-program operation that applies a precharge voltage to a source line commonly connected to the plurality of memory cells and raises the threshold voltage of the plurality of memory cells, and a second pre-program operation that applies a ground voltage to the source line and raises the threshold voltage of the plurality of memory cells.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to a memory device and a method of operating the same. Background Technology

[0002] A memory system is a device that stores data under the control of a host device, such as a computer or smartphone. A memory system may include a memory device where data is stored and a memory controller that controls the memory device. Memory devices are classified into volatile memory devices and non-volatile memory devices.

[0003] Non-volatile memory devices are memory devices in which data is not lost even when the power is cut off, and include ROM (Read Only Memory; ROM), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), and Flash Memory.

[0004] A non-volatile memory device includes memory cells that store data. Data stored in memory cells can be distinguished based on the degree to which the threshold voltage of the memory cells rises. In a three-dimensional memory cell structure, characteristics may differ depending on the location of the memory cells. If the characteristics of the memory cells differ, the degree to which the threshold voltage rises may differ even when the same voltage is applied to the memory cells. Accordingly, in a program operation for storing data in memory cells, the magnitude or duration of the applied voltages can be set differently according to the characteristics of the memory cells. Prior art literature

[65535] Republic of Korea Published Patent Application No. 10-2015-0091665 The problem to be solved

[0005] An embodiment of the present invention provides a memory device capable of improving the threshold voltage distribution of memory cells during program operation and a method of operating the same. means of solving the problem

[0006] A memory device according to an embodiment of the present invention includes a plurality of memory cells connected to a plurality of word lines, a peripheral circuit that performs a word line inspection operation to determine a vulnerable word line among the plurality of word lines, and a vulnerable word line determination unit that controls the peripheral circuit to store in one of the memory blocks a result of comparing a first number of off cells identified by a first pre-program operation in which a pre-charge voltage is applied to a source line commonly connected to the plurality of memory cells during the word line inspection operation, and a pre-program voltage is applied to a word line selected among the plurality of word lines, with a second number of off cells identified by a second pre-program operation in which a ground voltage is applied to the source line, and the pre-program voltage is applied to the selected word line.

[0007] A memory device according to an embodiment of the present invention comprises a plurality of memory cells connected to a plurality of word lines, a peripheral circuit that performs a program operation for storing data in the plurality of memory cells, a vulnerable word line information storage unit that stores information regarding a vulnerable word line among the plurality of word lines, and a program operation control unit that controls the peripheral circuit to perform the program operation in a first program mode or a second program mode according to the result of comparing whether a selected word line corresponding to an address provided by a memory controller is a vulnerable word line based on the information regarding the vulnerable word line, wherein the information regarding the vulnerable word line includes information determined by a first pre-program operation that applies a precharge voltage to a source line commonly connected to the plurality of memory cells and raises the threshold voltage of the plurality of memory cells, and a second pre-program operation that applies a ground voltage to the source line and raises the threshold voltage of the plurality of memory cells.

[0008] A method of operating a memory device comprising a plurality of memory cells connected to a plurality of word lines according to an embodiment of the present invention comprises: a step of comparing whether a selected word line corresponding to an address provided by a memory controller is a vulnerable word line based on information regarding a vulnerable word line; a step of determining one of a first program mode or a second program mode based on the result of the comparison; and a step of performing a program operation to store data in selected memory cells connected to the selected word line based on one of the modes. The information regarding the vulnerable word line includes information determined by a first pre-program operation of applying a precharge voltage to a source line commonly connected to the plurality of memory cells and raising the threshold voltage of the plurality of memory cells, and a second pre-program operation of applying a ground voltage to the source line and raising the threshold voltage of the plurality of memory cells. Effects of the invention

[0009] According to the present invention, a memory device capable of improving the threshold voltage distribution of memory cells during program operation and a method of operating the same are provided. Brief explanation of the drawing

[0010] FIG. 1 is a drawing for explaining a memory system including a memory device according to an embodiment of the present invention. Figure 2 is a diagram illustrating the structure of the memory device of Figure 1. FIG. 3 is a diagram for explaining the structure of one of the multiple memory blocks (BLK1~BKLz) of FIG. 2. Figure 4 is a diagram illustrating the threshold voltage distribution of memory cells according to the program operation of a memory device. Figure 5 is a diagram illustrating the program operation of a memory device. FIG. 6 is a diagram illustrating the operation of a vulnerable wordline determination unit according to an embodiment of the present invention. FIG. 7 is a diagram illustrating the operation of determining a vulnerable wordline according to an embodiment of the present invention. Figure 8 is a diagram illustrating information regarding vulnerable wordlines. FIG. 9 is a drawing for explaining a first embodiment of a program operation performed in a first program mode or a second program mode. FIG. 10 is a drawing for explaining a second embodiment of a program operation performed in a first program mode. FIG. 11 is a drawing for explaining a second embodiment of a program operation performed in a second program mode. FIG. 12 is a drawing for explaining a third embodiment of a program operation performed in a first program mode. FIG. 13 is a drawing for explaining a third embodiment of a program operation performed in a second program mode. FIG. 14 is a drawing for explaining a fourth embodiment of a program operation performed in a first program mode or a second program mode. FIG. 15 is a drawing for explaining a fifth embodiment of a program operation performed in a first program mode or a second program mode. FIG. 16 is a flowchart illustrating a wordline inspection operation for determining a vulnerable wordline according to an embodiment of the present invention. FIG. 17 is a flowchart for explaining the program operation of a memory device according to an embodiment of the present invention. FIG. 18 is a block diagram showing a memory card system to which a memory system according to one embodiment of the present invention is applied. FIG. 19 is a block diagram showing a user system to which a memory system according to one embodiment of the present invention is applied. Specific details for implementing the invention

[0011] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0013] FIG. 1 is a drawing for explaining a memory system including a memory device according to an embodiment of the present invention.

[0014] Referring to FIG. 1, the memory system (50) may include a memory device (100) and a memory controller (200). The memory system (50) may be a device that stores data under the control of a host (300), such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0015] The memory system (50) can be manufactured as any one of various types of storage devices according to the host interface, which is the method of communication with the host (300). For example, the memory system (50) can be configured as any one of various types of storage devices such as an SSD, MMC, eMMC, RS-MMC, micro-MMC type multimedia card, SD, mini-SD, micro-SD type secure digital card, USB (universal serial bus) storage device, UFS (universal flash storage) device, PCMCIA (personal computer memory card international association) card type storage device, PCI (peripheral component interconnection) card type storage device, PCI-E (PCI express) card type storage device, CF (compact flash) card, smart media card, memory stick, etc.

[0016] The memory system (50) can be manufactured in any one of various types of package forms. For example, the memory system (50) can be manufactured in any one of various types of package forms such as POP (package on package), SIP (system in package), SOC (system on chip), MCP (multi-chip package), COB (chip on board), WFP (wafer-level fabricated package), WSP (wafer-level stack package), etc.

[0017] The memory device (100) can store data. The memory device (100) operates in response to the control of the memory controller (200). The memory device (100) may include a memory cell array (not shown) comprising a plurality of memory cells that store data.

[0018] Memory cells can be configured as Single Level Cells (SLC) that store one bit of data, Multi Level Cells (MLC) that store two bits of data, Triple Level Cells (TLC) that store three bits of data, or Quad Level Cells (QLC) that can store four bits of data.

[0019] A memory cell array (not shown) may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. A single memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in a memory device (100) or reading data stored in a memory device (100). A memory block may be a unit for erasing data.

[0020] In the embodiment, the memory device (100) may be DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc. For convenience of explanation, the present specification assumes that the memory device (100) is a NAND flash memory.

[0021] A memory device (100) receives a command and an address from a memory controller (200) and is configured to access an area selected by the address among memory cell arrays. The memory device (100) can perform operations instructed by the command on the area selected by the address. For example, the memory device (100) can perform a write operation (program operation), a read operation, and an erase operation. During a write operation, the memory device (100) will program data in the area selected by the address. During a read operation, the memory device (100) will read data from the area selected by the address. During an erase operation, the memory device (100) will erase data stored in the area selected by the address.

[0022] In an embodiment, the memory device (100) may include a vulnerable wordline determination unit (140) and a program operation control unit (150).

[0023] The vulnerable wordline determination unit (140) can determine the characteristics of wordlines connected to memory cells. Memory cells may have different characteristics depending on the production and manufacturing processes. Additionally, in a memory cell structure configured in three dimensions, the characteristics may differ depending on the location of the memory cells. Depending on the characteristics, the memory cells may differ in the degree to which they are affected by voltages applied to the wordlines. Specifically, the degree to which the threshold voltage of the memory cells fluctuates due to voltages applied to the wordlines may differ. In an embodiment, the vulnerable wordline determination unit (140) can determine the wordlines connected to memory cells where the degree of fluctuation in the threshold voltage is large among the memory cells as vulnerable wordlines. For example, during program operation, memory cells connected to vulnerable wordlines may have a greater degree of threshold voltage increase than memory cells connected to other wordlines. The vulnerable wordline determination unit (140) can store information regarding vulnerable wordlines, which is information that has determined vulnerable wordlines among a plurality of wordlines. The specific operation of the vulnerable wordline determination unit (140) will be described later through FIGS. 6 and 7.

[0024] The program operation control unit (150) can control the program operation for memory cells. The program operation may be an operation of storing data in memory cells. Specifically, the program operation may be an operation of raising the threshold voltage of memory cells according to the data to be stored in the memory cells. When the program operation is performed, the memory cells may have a threshold voltage corresponding to any one of a plurality of program states. The plurality of program states may be determined according to the number of data bits stored in a single memory cell. For example, if a single memory cell is programmed as a Triple Level Cell (TLC) that stores three bits of data, the plurality of program states may mean an erase state and first to seventh program states. The threshold voltage of the memory cells after the program operation is performed may be determined according to the data to be stored in the memory cells. Each memory cell may have one of the plurality of program states as a target program state according to the data to be stored.

[0025] In an embodiment, the program operation may include a plurality of program loops. Each program loop may include a program voltage application operation and a verification operation. The program voltage application operation may be an operation of raising the threshold voltage of memory cells using a program voltage. The verification operation may be an operation of identifying whether the threshold voltage of memory cells has reached a threshold voltage corresponding to a target program state using a verification voltage.

[0026] In an embodiment, the program operation control unit (150) may perform a program operation in either a first program mode or a second program mode based on information regarding a vulnerable word line. The first program mode and the second program mode may have different magnitudes of voltages applied during the program operation. For example, the program operation control unit (150) may perform a program operation in the first program mode if the word line corresponding to the address input from the memory controller (200) is a vulnerable word line. As another example, the program operation control unit (150) may perform a program operation in the second program mode if the word line corresponding to the address input from the memory controller (200) is a normal word line.

[0027] The memory controller (200) can control the overall operation of the memory system (50).

[0028] When power is applied to the memory system (50), the memory controller (200) can execute firmware (FW). If the memory device (100) is a flash memory device, the firmware (FW) may include a Host Interface Layer (HIL) that controls communication with the host (300), a Flash Translation Layer (FTL) that controls communication between the host (300) and the memory device (100), and a Flash Interface Layer (FIL) that controls communication with the memory device (100).

[0029] In an embodiment, the memory controller (200) receives data and a logical block address (LBA) from the host (300) and can convert the logical block address into a physical block address (PBA) representing the addresses of memory cells to which data included in the memory device (100) will be stored. In this specification, the logical block address (LBA) and “logical address” or “logical address” may be used interchangeably. In this specification, the physical block address (PBA) and “physical address” or “physical address” may be used interchangeably.

[0030] The memory controller (200) can control the memory device (100) to perform write operations, read operations, or erase operations, etc., according to a request from the host (300). When performing a write operation, the memory controller (200) can provide a write command, a physical block address, and data to the memory device (100). When performing a read operation, the memory controller (200) can provide a read command and a physical block address to the memory device (100). When performing an erase operation, the memory controller (200) can provide an erase command and a physical block address to the memory device (100).

[0031] In an embodiment, the memory controller (200) can independently generate commands, addresses, and data and transmit them to the memory device (100) regardless of a request from the host (300). For example, the memory controller (200) can provide commands, addresses, and data to the memory device (100) for performing read and write operations associated with performing wear leveling, read reclaim, garbage collection, etc.

[0032] In an embodiment, the memory controller (200) can control at least two memory devices (100). In this case, the memory controller (200) can control the memory devices (100) according to an interleaving method to improve operational performance. The interleaving method may be a method of controlling the operation of at least two memory devices (100) so that it overlaps.

[0033] The host (300) can communicate with the memory system (50) using at least one of various communication methods such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), LRDIMM (Load Reduced DIMM).

[0034] In an embodiment, the memory system (50) may include a buffer memory (not shown). For example, the buffer memory may temporarily store data received from the host (300) or data received from the memory device (100), or temporarily store metadata of the memory device (100) (e.g., a mapping table). The buffer memory may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, etc., or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc.

[0035] Figure 2 is a diagram illustrating the structure of the memory device of Figure 1.

[0036] Referring to FIG. 2, the memory device (100) may include a memory cell array (110), peripheral circuits (120), and control logic (130).

[0037] A memory cell array (110) includes a plurality of memory blocks (BLK1 to BLKz). The plurality of memory blocks (BLK1 to BLKz) are connected to an address decoder (121) via row lines (RL). The plurality of memory blocks (BLK1 to BLKz) are connected to a page buffer group (123) via bit lines (BL1 to BLm). Each of the plurality of memory blocks (BLK1 to BLKz) includes a plurality of memory cells. In an embodiment, the plurality of memory cells are non-volatile memory cells. The plurality of memory cells are defined as a single page if the memory cells connected to the same word line. That is, the memory cell array (110) is composed of a plurality of pages. According to an embodiment of the present invention, each of the plurality of memory blocks (BLK1 to BLKz) included in the memory cell array (110) may include a plurality of dummy cells. At least one dummy cell may be connected in series between the drain select transistor and the memory cells and between the source select transistor and the memory cells.

[0038] The memory cells of the memory device (100) may each be configured as a single-level cell (SLC) that stores one bit of data, a multi-level cell (MLC) that stores two bits of data, a triple-level cell (TLC) that stores three bits of data, or a quad-level cell (QLC) that can store four bits of data.

[0039] The peripheral circuit (120) drives the memory cell array (110). For example, the peripheral circuit (120) can drive the memory cell array (110) to perform program operations, read operations, and erase operations under the control of the control logic (130). As another example, the peripheral circuit (120) can apply various operating voltages to row lines (RL) and bit lines (BL1~BLm) or discharge the applied voltages under the control of the control logic (130).

[0040] The peripheral circuit (120) may include an address decoder (121), a voltage generator (122), a page buffer group (123), a data input / output circuit (124), and a sensing circuit (125).

[0041] The address decoder (121) is connected to the memory cell array (110) through row lines (RL). The row lines (RL) may include drain select lines, word lines, source select lines, and a common source line. According to an embodiment of the present invention, the word lines may include normal word lines and dummy word lines. According to an embodiment of the present invention, the row lines (RL) may further include a pipe select line.

[0042] The address decoder (121) is configured to operate in response to the control of the control logic (130). The address decoder (121) receives an address (ADDR) from the control logic (130).

[0043] The address decoder (121) is configured to decode a block address among the received addresses (ADDR). The address decoder (121) selects at least one memory block among the memory blocks (BLK1~BLKz) according to the decoded block address. The address decoder (121) is configured to decode a row address (RADD) among the received addresses (ADDR). The address decoder (121) can select at least one word line of the selected memory block by applying voltages provided by the voltage generation unit (122) to at least one word line (WL) according to the decoded row address (RADD).

[0044] During program operation, the address decoder (121) will apply a program voltage to the selected word lines and a pass voltage of a level lower than the program voltage to the unselected word lines. During program verification operation, the address decoder (121) will apply a verification voltage to the selected word lines and a verification pass voltage of a level higher than the verification voltage to the unselected word lines.

[0045] During a read operation, the address decoder (121) will apply a read voltage to the selected word lines and apply a read pass voltage of a higher level than the read voltage to the unselected word lines.

[0046] The erase operation of the memory device (100) is performed in units of memory blocks. The address (ADDR) input to the memory device (100) during the erase operation includes a block address. The address decoder (121) decodes the block address and can select one memory block according to the decoded block address. During the erase operation, the address decoder (121) can apply a ground voltage to the word lines input to the selected memory block.

[0047] The address decoder (121) may be configured to decode the column address among the transmitted addresses (ADDR). The decoded column address may be transmitted to the page buffer group (123). For example, the address decoder (121) may include components such as a row decoder, a column decoder, an address buffer, etc.

[0048] The voltage generation unit (122) is configured to generate a plurality of operating voltages (Vop) using an external power supply voltage supplied to the memory device (100). The voltage generation unit (122) operates in response to the control of the control logic (130).

[0049] As an example, the voltage generating unit (122) can generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generating unit (122) is used as the operating voltage of the memory device (100).

[0050] As an example, the voltage generator (122) can generate various operating voltages (Vop) used for program, read, and erase operations in response to an operation signal (OPSIG). The voltage generator (122) can generate multiple operating voltages (Vop) using an external power supply voltage or an internal power supply voltage. The voltage generator (122) can be configured to generate various voltages required by the memory device (100). For example, the voltage generator (122) can generate multiple erase voltages, multiple program voltages, multiple pass voltages, multiple select read voltages, and multiple non-select read voltages.

[0051] The voltage generation unit (122) includes a plurality of pumping capacitors that receive an internal power supply voltage to generate a plurality of operating voltages (Vop) having various voltage levels, and will selectively activate the plurality of pumping capacitors in response to the control of the control logic (130) to generate a plurality of operating voltages (Vop).

[0052] The generated multiple operating voltages (Vop) can be supplied to the memory cell array (110) by the address decoder (121).

[0053] The page buffer group (123) includes first to m page buffers (PB1 to PBm). The first to m page buffers (PB1 to PBm) are each connected to a memory cell array (110) through first to m bit lines (BL1 to BLm). The first to m page buffers (PB1 to PBm) operate in response to the control of the control logic (130).

[0054] The first to m-th page buffers (PB1 to PBm) communicate data (DATA) with the data input / output circuit (124). During programming, the first to m-th page buffers (PB1 to PBm) receive data (DATA) to be stored through the data input / output circuit (124) and data lines (DL).

[0055] During a program operation, the first to m-page buffers (PB1 to PBm) will transmit data (DATA) to be stored through the data input / output circuit (124) to the selected memory cells through the bit lines (BL1 to BLm) when a program pulse is applied to a selected word line. The memory cells of the selected page are programmed according to the transmitted data (DATA). A memory cell connected to a bit line to which a program allow voltage (e.g., ground voltage) is applied will have an elevated threshold voltage. A memory cell connected to a bit line to which a program prohibit voltage (e.g., power supply voltage) is applied will maintain its threshold voltage. During a program verification operation, the first to m-page buffers (PB1 to PBm) read data (DATA) stored in the memory cells from the selected memory cells through the bit lines (BL1 to BLm).

[0056] When a read operation is performed, the page buffer group (123) can read data (DATA) from the memory cells of the selected page through bit lines (BL1~BLm) and store the read data (DATA) in the first to mth page buffers (PB1~PBm).

[0057] During an erase operation, the page buffer group (123) can float bit lines (BL1 to BLm). As an example, the page buffer group (123) may include a column selection circuit.

[0058] In an embodiment, while data stored in some of the page buffers among the plurality of page buffers included in the page buffer group (123) is programmed into the memory cell array (110), other page buffers can receive and store new data from the memory controller (200).

[0059] The data input / output circuit (124) is connected to the first to m-page buffers (PB1 to PBm) through data lines (DL). The data input / output circuit (124) operates in response to the control of the control logic (130).

[0060] The data input / output circuit (124) may include a plurality of input / output buffers (not shown) that receive input data (DATA). During program operation, the data input / output circuit (124) receives data (DATA) to be stored from an external controller (not shown). During a read operation, the data input / output circuit (124) outputs data (DATA) transmitted from the first to m-th page buffers (PB1~PBm) included in the page buffer group (123) to the external controller.

[0061] The sensing circuit (125) can generate a reference current in response to an allow bit (VRYBIT) signal generated by the control logic (130) during a read operation or a verification operation, and output a pass signal or a fail signal to the control logic (130) by comparing the sensing voltage (VPB) received from the page buffer group (123) with the reference voltage generated by the reference current. For example, the sensing circuit (125) can output a pass signal to the control logic (130) if the magnitude of the sensing voltage (VPB) is smaller than the reference voltage. As another example, the sensing circuit (125) can output a fail signal to the control logic (130) if the magnitude of the sensing voltage (VPB) is smaller than the reference voltage.

[0062] The control logic (130) may be connected to an address decoder (121), a voltage generator (122), a page buffer group (123), a data input / output circuit (124), and a sensing circuit (125). The control logic (130) may be configured to control the general operation of the memory device (100). The control logic (130) may operate in response to a command (CMD) transmitted from an external device.

[0063] The control logic (130) can control the peripheral circuit (120) by generating various signals in response to the command (CMD) and address (ADDR). For example, the control logic (130) can generate an operation signal (OPSIG), a row address (RADD), a page buffer control signal (PBSIGNALS), and an allow bit (VRYBIT) in response to the command (CMD) and address (ADDR). The control logic (130) can output the operation signal (OPSIG) to the voltage generation unit (122), output the row address (RADD) to the address decoder (121), output the page buffer control signal to the page buffer group (123), and output the allow bit (VRYBIT) to the sensing circuit (125). Additionally, the control logic (130) can determine whether the verification operation has passed or failed in response to a pass or fail signal (PASS / FAIL) output by the sensing circuit (125).

[0064] The vulnerable wordline determination unit (140) and program operation control unit (150) shown in FIG. 1 may be included in the control logic (130) shown in FIG. 2.

[0065] The vulnerable word line determination unit (140) can control the peripheral circuit (120) to perform a word line inspection operation to determine a vulnerable word line among a plurality of word lines. The word line inspection operation may include a first pre-program operation and a second pre-program operation. The first pre-program operation may be an operation to increase the threshold voltage of memory cells by applying a pre-charge voltage to a common source line connected to memory cells and applying a pre-program voltage to a word line connected to memory cells. The second pre-program operation may be an operation to increase the threshold voltage of memory cells by applying a ground voltage to a common source line connected to memory cells and applying a pre-program voltage to a word line connected to memory cells.

[0066] The vulnerable word line determination unit (140) can determine a word line connected to memory cells as a vulnerable word line based on the result of comparing the degree to which the threshold voltage of memory cells is raised by the first pre-program operation and the degree to which the threshold voltage of memory cells is raised by the second pre-program operation. The vulnerable word line determination unit (140) can store information regarding the vulnerable word line, which is information that determines the vulnerable word line among a plurality of word lines.

[0067] The program operation control unit (150) can control the peripheral circuit (120) to perform a program operation on the memory cells. The program operation control unit (150) can control the peripheral circuit (120) to apply operating voltages (Vop) to be used for the program operation to the row lines (RL) and bit lines (BL1~BLm).

[0068] FIG. 3 is a diagram for explaining the structure of one of the multiple memory blocks (BLK1~BKLz) of FIG. 2.

[0069] Referring to FIG. 3, a plurality of word lines arranged in parallel with each other may be connected between a first selection line and a second selection line. Here, the first selection line may be a source selection line (SSL), and the second selection line may be a drain selection line (DSL). More specifically, a memory block (BLKi) may include a plurality of strings (ST) connected between bit lines (BL1~BLm) and a common source line (CSL). Bit lines (BL1~BLm) may each be connected to strings (ST), and the common source line (CSL) may be connected to strings (ST) in common. Since strings (ST) may be configured identically, a string (ST) connected to the first bit line (BL1) will be described specifically as an example.

[0070] A string (ST) may include a source select transistor (SST), a plurality of memory cells (MCl+1 to MCm), a plurality of dummy memory cells (D_MC1 to D_MCl, D_MCm+1 to D_MCn), and a drain select transistor (DST) connected in series between a common source line (CSL) and a first bit line (BL1). A single string (ST) may include at least one source select transistor (SST) and one drain select transistor (DST).

[0071] The source of the source select transistor (SST) can be connected to the common source line (CSL), and the drain of the drain select transistor (DST) can be connected to the first bit line (BL1). Memory cells (MCl+1 to MCm) can be connected in series between the source select transistor (SST) and adjacent dummy memory cells (D_MC1 to D_MCl) and the drain select transistor (DST) and adjacent dummy memory cells (D_MCm+1 to D_MCn). The dummy memory cells (D_MC1 to D_MCl) adjacent to the source select transistor (SST) can be connected in series between the memory cells (MCl+1 to MCm) and the source select transistor (SST). The dummy memory cells (D_MCm+1 to D_MCn) adjacent to the drain select transistor (DST) can be connected in series between the memory cells (MCl+1 to MCm) and the drain select transistor (DST). The gates of source select transistors (SST) included in different strings (ST) can be connected to a source select line (SSL), the gates of drain select transistors (DST) can be connected to a drain select line (DSL), and the gates of memory cells (MCl+1 to MCm) can be connected to multiple word lines (WLl+1 to WLm). The gates of multiple dummy memory cells (D_MC1 to D_MCl, D_MCm+1 to D_MCn) can be connected to multiple dummy word lines (D_WL1 to D_WLl, D_WLm+1 to D_WLn). A group of memory cells connected to the same word line among the memory cells included in different strings (ST) can be called a physical page (PPG). Therefore, a memory block (BLKi) may contain as many physical pages (PPG) as there are word lines (WLl+1 to WLm).

[0072] A single memory cell can store one bit of data. This is commonly referred to as a single-level cell (SLC). In this case, a single physical page (PPG) can store one logical page (LPG) of data. One logical page (LPG) of data can contain as many data bits as the number of cells contained within a single physical page (PPG).

[0073] A single memory cell can store two or more bits of data. In this case, a single physical page (PPG) can store two or more logical pages (LPG) of data.

[0074] Figure 4 is a diagram illustrating the threshold voltage distribution of memory cells according to the program operation of a memory device.

[0075] In Figure 4, the horizontal axis of the graph represents the threshold voltage (Vth) of the memory cells, and the vertical axis of the graph represents the number of memory cells (# of cells).

[0076] Referring to Fig. 4, the threshold voltage distribution of memory cells can change from an initial state to a final program state depending on the program operation.

[0077] Figure 4 explains the case assuming that one memory cell is programmed as TLC to store three bits of data.

[0078] The initial state is a state where no program operation is performed, and the threshold voltage distribution of the memory cells may be in an erased state (E).

[0079] The final program state may be the threshold voltage distribution of the memory cells that performed the program operation. The threshold voltage of the memory cells that performed the program operation may have a threshold voltage corresponding to any one of the multiple program states. For example, if a single memory cell is programmed as a TLC storing three bits of data, the multiple program states may refer to an erase state (E) and first to seventh program states (PV1~PV7). In the embodiment, the threshold voltage of the memory cells that performed the program operation may have a threshold voltage corresponding to any one of the erase state (E) and first to seventh program states (PV1~PV7). The threshold voltage of the memory cells in the initial state may be raised through the program operation to a threshold voltage corresponding to any one of the erase state (E) and first to seventh program states (PV1~PV7).

[0080] Each memory cell may have an erase state (E) and one of the first to seventh program states (PV1~PV7) as a target program state. The target program state may be determined based on the data to be stored in the memory cell. Each memory cell may have a threshold voltage corresponding to the target program state among the final program states through a program operation.

[0081] Figure 5 is a diagram illustrating the program operation of a memory device.

[0082] In FIG. 5, the horizontal axis of the graph represents time, and the vertical axis of the graph represents the voltage (V) applied to the word line. The voltage (V) applied to the word line may include a program voltage (Vpgm) and a verification voltage (V_vfy).

[0083] Figure 5 describes the case where a single memory cell is programmed as a TLC to store three bits of data. However, the scope of the present invention is not limited thereto, and a single memory cell may be programmed to store two bits or less of data or four bits or more of data.

[0084] Referring to FIG. 5, the program operation of the memory device (100) may include a plurality of program loops (PL1 to PLn). The memory device (100) may perform a program operation by executing a plurality of program loops (PL1 to PLn) so that selected memory cells connected to selected word lines have a threshold voltage corresponding to any one of a plurality of program states. For example, when a memory cell is programmed as TLC, the memory device (100) may perform a program operation by executing a plurality of program loops (PL1 to PLn) so that it has a threshold voltage corresponding to an erase state (E) or any one of the first to seventh program states (PV1 to PV7).

[0085] Each of the multiple program loops (PL1 to PLn) may include a program voltage application operation (PGM Step) and a verification operation (Verify Step).

[0086] The program voltage application operation (PGM Step) may be an operation of applying a program voltage to a selected word line connected to selected memory cells. For example, the memory device (100) may apply a first program voltage (Vpgm1) to a selected word line connected to selected memory cells in a first program loop (PL1). After the first program voltage (Vpgm1) is applied to the selected word line, the threshold voltage of each of the selected memory cells may have a threshold voltage corresponding to a target program state among a plurality of program states.

[0087] The Verify Step may be an operation of applying a verification voltage to a selected word line connected to selected memory cells. The Verify Step may be an operation of determining whether the threshold voltage of each of the selected memory cells has a threshold voltage corresponding to a target program state among a plurality of program states. The Verify Step may be an operation of applying a verification voltage corresponding to a target program state of each of the selected memory cells.

[0088] In an embodiment, the memory device (100) may apply a first program voltage (Vpgm1) to a selected word line connected to selected memory cells in a first program loop (PL1), and then apply first to seventh verification voltages (V_vfy1 to V_vfy7). At this time, memory cells whose target program state is the first program state may perform a verification operation (Verify Step) using the first verification voltage (V_vfy1). Memory cells whose target program state is the second program state may perform a verification operation (Verify Step) using the second verification voltage (V_vfy2). Memory cells whose target program state is the third program state may perform a verification operation (Verify Step) using the third verification voltage (V_vfy3). Memory cells whose target program state is the fourth program state may perform a verification operation (Verify Step) using the fourth verification voltage (V_vfy4). Memory cells whose target program state is the 5th program state can perform a verification operation (Verify Step) using the 5th verification voltage (V_vfy5). Memory cells whose target program state is the 6th program state can perform a verification operation (Verify Step) using the 6th verification voltage (V_vfy6). Memory cells whose target program state is the 7th program state can perform a verification operation (Verify Step) using the 7th verification voltage (V_vfy7). As the verification voltage progresses from the 1st verification voltage (V_vfy1) to the 7th verification voltage (V_vfy7), the magnitudes of the verification voltages (V_vfy1~V_vfy7) may increase. Specifically, the magnitudes of the verification voltages (V_vfy1~V_vfy7) may be smallest at the 1st verification voltage (V_vfy1) and largest at the 7th verification voltage (V_vfy7). The number of verification voltages is not limited to this embodiment.

[0089] The threshold voltage of memory cells that have passed the Verify Step by each of the Verify voltages (V_vfy1~V_vfy7) can be determined to have a threshold voltage corresponding to the target program state. Memory cells that have passed the Verify Step can be programmed inhibited in the second program loop (PL2). A program inhibit voltage can be applied to the bit lines connected to the programmed memory cells.

[0090] The threshold voltage of memory cells for which the Verify Step failed by each of the verification voltages (V_vfy1~V_vfy7) can be determined to not have a threshold voltage corresponding to the target program state. Memory cells for which the Verify Step failed can perform the second program loop (PL2).

[0091] In the second program loop (PL2), the memory device (100) can apply a second program voltage (Vpgm2) that is higher than the first program voltage (Vpgm1) by a unit voltage (△Vpgm) to a selected word line connected to the selected memory cells. Afterward, the memory device (100) can perform the verification step of the second program loop (PL2) in the same way as the verification step of the first program loop (PL1).

[0092] Afterwards, the memory device (100) can perform the next program loop in the same way as the second program loop (PL2) a preset number of times.

[0093] In an embodiment, if the program operation is not completed within a preset number of program loops, the program operation may fail. If the program operation is completed within a preset number of program loops, the program operation may pass. Whether the program operation is completed may be determined by whether all verification steps for the selected memory cells have passed. If the verification steps for all selected memory cells have passed, the next program loop may not be executed.

[0094] In the embodiment, the program voltage can be determined according to the Incremental Step Pulse Programming (ISPP) method. The level of the program voltage can be increased or decreased stepwise as the program loops (PL1 to PLn) are repeated. The number of times the program voltages used in each program loop are applied, the voltage level, and the voltage application time can be determined in various forms according to the control of the memory controller (200).

[0095] FIG. 6 is a diagram illustrating the operation of a vulnerable wordline determination unit according to an embodiment of the present invention.

[0096] Referring to FIG. 6, the vulnerable wordline determination unit (140) can control the peripheral circuit (120) to perform a wordline inspection operation for a plurality of memory cells. During the wordline inspection operation, a first pre-program operation (Pre-PGM1, Pre-Verify1), an erase operation (Erase), a second pre-program operation (Pre-PGM2, Pre-Verify2), a vulnerable wordline determination operation (Comparing), and an erase operation (Erase) can be performed sequentially.

[0097] The first pre-program operation (Pre-PGM1, Pre-Verify1) may include a first pre-program voltage application operation (Pre-PGM1) and a first pre-verification operation (Pre-Verify1). The first pre-program voltage application operation (Pre-PGM1) may include a precharge interval (Precharge), a program pulse interval (Pgm Pulse), and a discharge interval (Discharge).

[0098] The second pre-program operation (Pre-PGM2, Pre-Verify2) may include a second pre-program voltage application operation (Pre-PGM2) and a second pre-verification operation (Pre-Verify2). The second pre-program voltage application operation (Pre-PGM2) may include a precharge interval (Precharge), a program pulse interval (Pgm Pulse), and a discharge interval (Discharge).

[0099] In FIG. 6, the first pre-program voltage application operation (Pre-PGM1) and the second pre-program voltage application operation (Pre-PGM2) are described, and the first pre-verification operation (Pre-Verify1), the second pre-verification operation (Pre-Verify2), and the vulnerable wordline determination operation (Comparing) will be described later through FIG. 7.

[0100] The interval t1 to t4 may be a interval for performing a first pre-program voltage application operation (Pre-PGM1). Specifically, the interval t1 to t2 may be a precharge interval. The precharge interval may be a interval for precharging the channel region of a plurality of memory cells. In the interval t1 to t2, the vulnerable word line determination unit (140) may apply a precharge voltage (Vpre) to the common source line (CSL). In the interval t1 to t2, the vulnerable word line determination unit (140) may apply a turn-on voltage (Von) to the source select line (SSL). The turn-on voltage (Von) may be a voltage higher than the threshold voltage of the source select transistor connected to the source select line. The vulnerable word line determination unit (140) may increase the channel potential of a plurality of memory cells by applying a precharge voltage (Vpre) to the common source line (CSL).

[0101] The interval t2 to t3 may be a program pulse interval (Pgm Pulse). The program pulse interval (Pgm Pulse) may be an interval that raises the threshold voltage of multiple memory cells. In the interval t2 to t3, the vulnerable word line determination unit (140) may apply a pre-program voltage (pre_Vp) to the selected word line (Sel_WL). In the interval t2 to t3, the vulnerable word line determination unit (140) may apply a pass voltage (Vpass) to the unselected word lines (Unsel_WL). In the interval t2 to t3, the vulnerable word line determination unit (140) may apply a ground voltage (Gnd) to the common source line (CSL). In the interval t2 to t3, the vulnerable word line determination unit (140) may apply a ground voltage (Gnd) to the source select line (SSL).

[0102] The t3~t4 interval may be a discharge interval. In the t3~t4 interval, the vulnerable word line determination unit (140) may apply a ground voltage (Gnd) to the selected word line (Sel_WL). In the t3~t4 interval, the vulnerable word line determination unit (140) may apply a ground voltage (Gnd) to the unselected word lines (Unsel_WL).

[0103] In the t4~t5 interval, the vulnerable wordline determination unit (140) can perform a first pre-verification operation (Pre-Verify1) and an erase operation (Erase).

[0104] The interval t5 to t8 may be a interval for performing a second pre-program voltage application operation (Pre-PGM2). Specifically, the interval t5 to t6 may be a precharge interval (Precharge). In the interval t5 to t6, the vulnerable word line determination unit (140) may apply a ground voltage (Gnd) to the common source line (CSL). In the interval t5 to t6, the vulnerable word line determination unit (140) may apply a ground voltage (Gnd) to the source select line (SSL).

[0105] The t6~t7 interval may be a program pulse interval (Pgm Pulse). In the t6~t7 interval, the vulnerable word line determination unit (140) may apply a pre-program voltage (pre_Vp) to the selected word line (Sel_WL). In the t6~t7 interval, the vulnerable word line determination unit (140) may apply a pass voltage (Vpass) to the unselected word lines (Unsel_WL).

[0106] The t7~t8 interval may be a discharge interval. In the t7~t8 interval, the vulnerable word line determination unit (140) may apply a ground voltage (Gnd) to the selected word line (Sel_WL). In the t7~t8 interval, the vulnerable word line determination unit (140) may apply a ground voltage (Gnd) to the unselected word lines (Unsel_WL).

[0107] After t8 hours, the vulnerable wordline determination unit (140) can perform a second pre-verification operation (Pre-Verify2), a vulnerable wordline determination operation (Comparing), and an erasure operation (Erase).

[0108] FIG. 7 is a diagram illustrating the operation of determining a vulnerable wordline according to an embodiment of the present invention.

[0109] In Figure 7, the horizontal axis of the graph represents the threshold voltage (Vth) of the memory cells, and the vertical axis of the graph represents the number of memory cells (# of cells).

[0110] The graph at the top of FIG. 7 may be the threshold voltage distribution of memory cells that have undergone a first pre-program voltage application operation. The graph in the middle of FIG. 7 may be the threshold voltage distribution of memory cells that are in an erased state (E). The graph at the bottom of FIG. 7 may be the threshold voltage distribution of memory cells that have undergone a second pre-program voltage application operation. The degree to which the threshold voltage of memory cells has risen due to the first pre-program voltage application operation may be greater than the degree to which the threshold voltage of memory cells has risen due to the second pre-program voltage application operation.

[0111] Referring to the graph at the top of FIG. 7, the vulnerable wordline determination unit (140) can perform a first pre-verification operation after performing a first pre-program voltage application operation. The vulnerable wordline determination unit (140) can perform a first pre-verification operation to identify the threshold voltage of memory cells raised by the first pre-program voltage application operation. The vulnerable wordline determination unit (140) can identify the threshold voltage of memory cells using the pre-verification voltage (pre_vfy) during the first pre-verification operation. The vulnerable wordline determination unit (140) can count the number of first off cells (Num pb1) having a threshold voltage higher than the pre-verification voltage (pre_vfy) during the first pre-verification operation. In an embodiment, the vulnerable wordline determination unit (140) can store the number of first off cells (Num pb1) identified by the first pre-verification operation in a page buffer. In the embodiment, the vulnerable wordline determination unit (140) can perform an erasure operation after performing a first pre-program operation.

[0112] Referring to the graph at the bottom of FIG. 7, the vulnerable wordline determination unit (140) can perform a second pre-verification operation after performing a second pre-program voltage application operation. The vulnerable wordline determination unit (140) can perform a second pre-verification operation to identify the threshold voltage of memory cells raised by the second pre-program voltage application operation. The vulnerable wordline determination unit (140) can identify the threshold voltage of memory cells using the pre-verification voltage (pre_vfy) during the second pre-verification operation. The vulnerable wordline determination unit (140) can count the number of second off cells (Num pb2) having a threshold voltage higher than the pre-verification voltage (pre_vfy) during the second pre-verification operation. In an embodiment, the vulnerable wordline determination unit (140) can store the number of second off cells (Num pb2) identified by the second pre-verification operation in a page buffer.

[0113] Subsequently, the vulnerable wordline determination unit (140) can perform a vulnerable wordline determination operation to determine whether a wordline connected to memory cells is a vulnerable wordline based on the number of first off cells (Num pb1) and the number of second off cells (Num pb2). Specifically, the vulnerable wordline determination unit (140) can determine a wordline connected to memory cells where the difference between the number of first off cells (Num pb1) and the number of second off cells (Num pb2) exceeds a reference number of off cells (Ref pb) as a vulnerable wordline. Alternatively, the vulnerable wordline determination unit (140) can determine a wordline connected to memory cells where the difference between the number of first off cells (Num pb1) and the number of second off cells (Num pb2) is less than or equal to the reference number of off cells (Ref pb) as a normal wordline. In the embodiment, the vulnerable wordline determination unit (140) can perform a deletion operation after performing a vulnerable wordline determination operation.

[0114] The vulnerable wordline determination unit (140) can determine whether each of the plurality of wordlines is a vulnerable wordline by performing a first pre-program operation and a second pre-program operation. In an embodiment, the vulnerable wordline determination unit (140) can store information regarding the vulnerable wordlines, for which the plurality of wordlines have been determined to be vulnerable words, in any one of the plurality of memory blocks (BLK1~BLKz) shown in FIG. 2. Any one of the memory blocks may be a CAM block (Content Addressable Memory Block). For example, the CAM block may store program voltage information and the address of a defective memory block, etc., necessary for performing a program operation of the memory device (100). In another embodiment, the vulnerable wordline determination unit (140) may include a vulnerable wordline information storage unit that stores information regarding vulnerable wordlines. The vulnerable wordline determination unit (140) may provide information regarding vulnerable wordlines to the program operation control unit (150).

[0115] Figure 8 is a diagram illustrating information regarding vulnerable wordlines.

[0116] Referring to FIG. 8, the memory cell array may have a structure in which a plurality of memory cells are stacked along a first channel region (CH1) and a second channel region (CH2). The first channel region (CH1) may include first memory cells. The second channel region (CH2) may include second memory cells. Each of the plurality of word lines (WL1~WLn) may have memory cells connected to it. The word lines located at the bottom of the first channel region (CH1) and the word lines located at the bottom of the second channel region (CH2) may be vulnerable word lines (Wk_WL). For example, the first to second word lines (WL1~WL2) and the i+2 to i+3 word lines (WLi+2~WLi+3) may be vulnerable word lines (Wk_WL). Word lines connected to memory cells located at the bottom of the first channel area (CH1) and the second channel area (CH2) may be vulnerable word lines (Wk_WL). The vulnerable word line determination unit (140) may store information regarding word lines located at the bottom of the first channel area (CH1) and the second channel area (CH2), respectively, as information regarding vulnerable word lines. In an embodiment, although not shown in FIG. 8, dummy word lines may be included between the drain selection line (DSL) and the nth word line (WLn). In another embodiment, dummy word lines may be included between the source selection line (SSL) and the first word line (WL1). In yet another embodiment, dummy word lines may be included between the i+1th word line (WLi+1) and the i+2th word line (WLi+2).

[0117] FIG. 9 is a drawing for explaining a first embodiment of a program operation performed in a first program mode or a second program mode.

[0118] In Fig. 9, the horizontal axis of the graph represents time, and the vertical axis of the graph represents the precharge voltage (Vpre) applied to the common source line.

[0119] The program operation control unit (150) can receive program commands, addresses, and data from the memory controller and perform program operations. The program operation control unit (150) can perform program operations on selected memory cells connected to selected word lines corresponding to the addresses received from the memory controller.

[0120] The program operation control unit (150) can determine the mode of program operation as a first program mode (Pgm mode1) or a second program mode (Pgm mode2) based on information regarding vulnerable word lines provided by the vulnerable word line determination unit (140). In an embodiment, the program operation control unit (150) can perform program operation in the first program mode if the word line selected based on the information regarding vulnerable word lines is a vulnerable word line. In another embodiment, the program operation control unit (150) can perform program operation in the second program mode if the word line selected based on the information regarding vulnerable word lines is a normal word line.

[0121] Referring to FIG. 9, the program operation may include a plurality of program loops (PL1 to PLn). The program operation control unit (150) may apply a precharge voltage (Vpre) to a common source line and then apply a program voltage to a selected word line in the program voltage application operation (PGM step).

[0122] In the first program mode (Pgm mode 1), the program operation control unit (150) can apply a precharge voltage (Vpre) to the common source line from any one of the multiple program loops (PL1 to PLn). Any one of the program loops may be a predetermined program loop. For example, in the first program mode (Pgm mode 1), the program operation control unit (150) can apply a precharge voltage (Vpre) to the common source line from the i+2nd program loop (PLi+2) among the multiple program loops (PL1 to PLn).

[0123] In the second program mode (Pgm mode 2), the program operation control unit (150) can apply a precharge voltage (Vpre) to the common source line from the previous program loop of any one program loop. For example, in the second program mode (Pgm mode 2), the program operation control unit (150) can apply a precharge voltage (Vpre) to the common source line from the i-th program loop (PLi) among a plurality of program loops (PL1 to PLn). That is, the number of program loops that apply a precharge voltage (Vpre) to the common source line in the first program mode (Pgm mode 1) may be less than the number of loops that apply a precharge voltage (Vpre) to the common source line in the second program mode (Pgm mode 2). In the program operation for memory cells connected to a vulnerable word line, the number of program loops that apply a precharge voltage (Vpre) to the common source line may be less than the number of program loops that apply a precharge voltage (Vpre) to the common source line in the program operation for memory cells connected to a normal word line.

[0124] FIG. 10 is a drawing for explaining a second embodiment of a program operation performed in a first program mode.

[0125] FIG. 11 is a drawing for explaining a second embodiment of a program operation performed in a second program mode.

[0126] Referring to FIGS. 10 and 11, each of the plurality of program loops (PL1 to PLn) may include a program voltage application operation (PGM Step) and a verification operation (Verify Step). The program voltage application operation (PGM Step) may include a precharge section (Precharge), a program pulse section (Pgm Pulse), and a discharge section (Discharge).

[0127] Referring to FIG. 10, the program operation control unit (150) can perform a program operation in a first program mode (Pgm mode1). The t1 to t2 interval may be a precharge interval. In the t1 to t2 interval, the program operation control unit (150) can apply a turn-on voltage (Von) to the selected word line (Sel_WL) for a first time (pre_t1) and then apply a ground voltage (Gnd). In the t1 to t2 interval, the program operation control unit (150) can apply a turn-on voltage (Von) to the unselected word lines (Unsel_WL) for a first time (pre_t1) and then apply a ground voltage (Gnd). In the interval t1 to t2, the program operation control unit (150) may apply a precharge voltage (Vpre) to the common source line (CSL) for a first time (pre_t1) and then apply a ground voltage (Gnd). In the interval t1 to t2, the program operation control unit (150) may apply a turn-on voltage (Von) to the source select line (SSL) for a first time (pre_t1) and then apply a ground voltage (Gnd).

[0128] Referring to FIG. 11, the program operation control unit (150) can perform a program operation in a second program mode (Pgm mode2). In the interval t1 to t2, the program operation control unit (150) can apply a turn-on voltage (Von) to the selected word line (Sel_WL) for a second time (pre_t2) and then apply a ground voltage (Gnd). In the interval t1 to t2, the program operation control unit (150) can apply a turn-on voltage (Von) to the unselected word lines (Unsel_WL) for a second time (pre_t2) and then apply a ground voltage (Gnd). In the interval t1 to t2, the program operation control unit (150) can apply a precharge voltage (Vpre) to the common source line (CSL) for a second time (pre_t2) and then apply a ground voltage (Gnd). In the t1~t2 interval, the program operation control unit (150) can apply a turn-on voltage (Von) to the source selection line (SSL) for a second time (pre_t2) and then apply a ground voltage (Gnd).

[0129] The first time (pre_t1) may be shorter than the second time (pre_t2). The time for applying a precharge voltage (Vpre) to the common source line (CSL) in the first program mode (Pgm mode1) may be shorter than the time for applying a precharge voltage (Vpre) to the common source line (CSL) in the second program mode (Pgm mode2). That is, the time for precharging the channel area of ​​memory cells in the first program mode (Pgm mode1) may be shorter than the time for precharging the channel area of ​​memory cells in the second program mode (Pgm mode2). The time for applying a precharge voltage (Vpre) to the common source line (CSL) in a program operation for memory cells connected to a weak word line may be shorter than the time for applying a precharge voltage (Vpre) to the common source line (CSL) in a program operation for memory cells connected to a normal word line.

[0130] Referring to FIGS. 10 and 11, the interval t2 to t3 may be a program pulse interval (Pgm Pulse). In the interval t2 to t3, the program operation control unit (150) may apply a pass voltage (Vpass) to the selected word line (Sel_WL) and then apply a program voltage (Vpgm). In the interval t2 to t3, the program operation control unit (150) may apply a pass voltage (Vpass) to the unselected word lines (Unsel_WL).

[0131] Referring to FIGS. 10 and 11, the t3 to t4 interval may be a discharge interval. In the t3 to t4 interval, the program operation control unit (150) may apply a ground voltage (Gnd) to the selected word line (Sel_WL). In the t3 to t4 interval, the program operation control unit (150) may apply a ground voltage (Gnd) to the unselected word lines (Unsel_WL).

[0132] FIG. 12 is a drawing for explaining a third embodiment of a program operation performed in a first program mode.

[0133] FIG. 13 is a drawing for explaining a third embodiment of a program operation performed in a second program mode.

[0134] In FIGS. 12 and 13, content that overlaps with FIGS. 10 and 11 will be omitted.

[0135] Referring to FIGS. 12 and 13, the program voltage application operation (PGM Step) may include a precharge section, a program pulse section (Pgm Pulse), and a discharge section.

[0136] Referring to FIG. 12, the program operation control unit (150) can perform a program operation in a first program mode (Pgm mode1). The t1 to t2 interval may be a precharge interval. In the t1 to t2 interval, the program operation control unit (150) can apply a turn-on voltage (Von) to a selected word line (Sel_WL) and then apply a ground voltage (Gnd). In the t1 to t2 interval, the program operation control unit (150) can apply a turn-on voltage (Von) to adjacent word lines (adj_WL) of the selected word line and then apply a ground voltage (Gnd). In the t1 to t2 interval, the program operation control unit (150) can apply a turn-on voltage (Von) to a first unselected word line group (Unsel_WL1) and then apply a ground voltage (Gnd). In an embodiment, during the interval t1 to t2, the program operation control unit (150) may apply a turn-on voltage (Von) to the first and second unselected wordline groups (Unsel_WL1, Unsel_WL2) and then apply a ground voltage (Gnd). In another embodiment, during the interval t1 to t2, the program operation control unit (150) may apply a ground voltage (Gnd) to the first and second unselected wordline groups (Unsel_WL1, Unsel_WL2). The first unselected wordline group (Unsel_WL1) may be wordlines adjacent to the source selection line (SSL). The third unselected wordline group (Unsel_WL3) may be wordlines adjacent to the drain selection line. In the t1 to t2 interval, the program operation control unit (150) can apply a precharge voltage (Vpre) to the common source line (CSL) and then apply a ground voltage (Gnd). In the t1 to t2 interval, the program operation control unit (150) can apply a turn-on voltage (Von) to the source select line (SSL) and then apply a ground voltage (Gnd).

[0137] Referring to FIG. 13, the program operation control unit (150) can perform a program operation in a second program mode (Pgm mode2). In the interval t1 to t2, the program operation control unit (150) can apply a turn-on voltage (Von) to the selected word line (Sel_WL) and then apply a ground voltage (Gnd). In the interval t1 to t2, the program operation control unit (150) can apply a turn-on voltage (Von) to the word lines adjacent to the selected word line (adj_WL) and then apply a ground voltage (Gnd). In the interval t1 to t2, the program operation control unit (150) can apply a ground voltage (Gnd) to the remaining word lines (r_WL) excluding the selected word line and adjacent word lines among the plurality of word lines. In the t1 to t2 interval, the program operation control unit (150) can apply a precharge voltage (Vpre) to the common source line (CSL) and then apply a ground voltage (Gnd). In the t1 to t2 interval, the program operation control unit (150) can apply a turn-on voltage (Von) to the source select line (SSL) and then apply a ground voltage (Gnd).

[0138] In the first program mode (Pgm mode1), a turn-on voltage (Von) may be applied to the remaining word lines, excluding the adjacent word lines of the selected word line, during the precharge period. In the second program mode (Pgm mode2), a ground voltage (Gnd) may be applied to the remaining word lines, excluding the adjacent word lines of the selected word line, during the precharge period. During a program operation for memory cells connected to a vulnerable word line, a turn-on voltage (Von) may be applied to the remaining word lines while a precharge voltage (Vpre) is applied to the common source line (CSL). During a program operation for memory cells connected to a normal word line, a ground voltage (Gnd) may be applied to the remaining word lines while a precharge voltage (Vpre) is applied to the common source line (CSL).

[0139] FIG. 14 is a drawing for explaining a fourth embodiment of a program operation performed in a first program mode or a second program mode.

[0140] In FIG. 14, only the program pulse interval (Pgm Pulse) included in the program voltage application operation (PGM Step), which is the difference between the first program mode or the second program mode, will be explained.

[0141] Referring to FIG. 14, in the first program mode (Pgm mode1), the program operation control unit (150) can apply a program voltage (Vpgm) after applying a first pass voltage (Vpass1) to a selected word line (Sel_WL). In the first program mode (Pgm mode1), the program operation control unit (150) can apply a first pass voltage (Vpass1) to unselected word lines (Unsel_WL). In the first program mode (Pgm mode1), the program operation control unit (150) can apply a first pass voltage (Vpass1) to dummy word lines (D_WL). In an embodiment, in a first program mode (Pgm mode1), the program operation control unit (150) may apply a second pass voltage (Vpass2) greater than the first pass voltage (Vpass1) to the word lines adjacent to the selected word line among the unselected word lines and to the dummy word lines (D_WL), and may apply the first pass voltage (Vpass1) to the remaining word lines excluding the adjacent word lines among the unselected word lines. For example, the dummy word lines (D_WL) may be the dummy word lines (D_WL1~D_WLI, D_WLm+1~D_WLn) shown in FIG. 3. As another example, the dummy word lines (D_WL) may be the word lines located between the i+1 word line (WLi+1) and the i+2 word line (WLi+2) shown in FIG. 8.

[0142] In the second program mode (Pgm mode2), the program operation control unit (150) can apply a second pass voltage (Vpass2) to the selected word line (Sel_WL) and then apply a program voltage (Vpgm). In the second program mode (Pgm mode2), the program operation control unit (150) can apply a second pass voltage (Vpass2) to the unselected word lines (Unsel_WL). In the second program mode (Pgm mode2), the program operation control unit (150) can apply a second pass voltage (Vpass2) to the dummy word lines (D_WL).

[0143] The magnitude of the second pass voltage (Vpass2) may be greater than the first pass voltage (Vpass1). In the first program mode (Pgm mode1), the program operation control unit (150) may apply the first pass voltage (Vpass1) to unselected word lines (Unsel_WL) and dummy word lines (D_WL) while applying the program voltage (Vpgm) to the selected word line (Sel_WL). In the second program mode (Pgm mode2), the program operation control unit (150) may apply a second pass voltage (Vpass2) greater than the first pass voltage (Vpass1) to the unselected word lines (Unsel_WL) and dummy word lines (D_WL) while applying the program voltage (Vpgm) to the selected word line (Sel_WL).

[0144] FIG. 15 is a drawing for explaining a fifth embodiment of a program operation performed in a first program mode or a second program mode.

[0145] In FIG. 15, only the program pulse interval (Pgm Pulse) included in the program voltage application operation (PGM Step), which is the difference between the first program mode or the second program mode, will be explained.

[0146] Referring to FIG. 15, in the first program mode (Pgm mode1), the program operation control unit (150) can apply a first pass voltage (Vpass1) to a selected word line (Sel_WL) and then apply a program voltage (Vpgm). In the first program mode (Pgm mode1), the program operation control unit (150) can apply a first pass voltage (Vpass1) to adjacent word lines (adj_WL) of the selected word line. In the first program mode (Pgm mode1), the program operation control unit (150) can apply a first pass voltage (Vpass1) to the remaining word lines (r_WL) among the unselected word lines, excluding the adjacent word lines of the selected word line.

[0147] In the second program mode (Pgm mode 2), the program operation control unit (150) may apply a first pass voltage (Vpass1) to a selected word line (Sel_WL) and then apply a program voltage (Vpgm). In the second program mode (Pgm mode 2), the program operation control unit (150) may apply a first pass voltage (Vpass1) to adjacent word lines (adj_WL) of the selected word line and then apply a second pass voltage (Vpass2) that is greater than the first pass voltage (Vpass1). In the second program mode (Pgm mode 2), the program operation control unit (150) may apply a first pass voltage (Vpass1) to the remaining word lines (r_WL).

[0148] In the first program mode (Pgm mode 1), the program operation control unit (150) may apply a first pass voltage (Vpass1) to adjacent word lines (adj_WL) of the selected word line while applying a program voltage (Vpgm) to the selected word line (Sel_WL). In the second program mode (Pgm mode 2), the program operation control unit (150) may apply a second pass voltage (Vpass2) greater than the first pass voltage (Vpass1) to adjacent word lines (adj_WL) of the selected word line while applying a program voltage (Vpgm) to the selected word line (Sel_WL).

[0149] FIG. 16 is a flowchart illustrating a wordline inspection operation for determining a vulnerable wordline according to an embodiment of the present invention.

[0150] Referring to FIG. 16, in step S1601, the memory device (100) can count the number of first off cells identified by a first pre-program operation among a plurality of memory cells. The memory device (100) can store the number of first off cells in a page buffer. In an embodiment, after performing step S1601, the memory device (100) can perform an erase operation on the plurality of memory cells.

[0151] In step S1603, the memory device (100) can count the number of second off cells identified by the second pre-program operation among the plurality of memory cells. The memory device (100) can store the number of second off cells in a page buffer. In an embodiment, the memory device (100) can perform an erase operation on the plurality of memory cells after performing step S1603.

[0152] In step S1605, the memory device (100) can determine whether the difference between the number of first off cells and the number of second off cells exceeds the reference number of off cells. If the difference between the number of first off cells and the number of second off cells exceeds the reference number of off cells, step S1607 may be performed. If the difference between the number of first off cells and the number of second off cells is less than or equal to the reference number of off cells, step S1609 may be performed.

[0153] In step S1607, the memory device (100) can determine a word line connected to a plurality of memory cells as a vulnerable word line if the difference between the number of first off cells and the number of second off cells exceeds the reference number of off cells.

[0154] In step S1609, the memory device (100) can determine a word line connected to a plurality of memory cells as a normal word line if the difference between the number of first off cells and the number of second off cells is less than or equal to the number of reference off cells.

[0155] FIG. 17 is a flowchart for explaining the program operation of a memory device according to an embodiment of the present invention.

[0156] Referring to FIG. 17, in step S1701, the memory device (100) may receive a command, an address, and data from the memory controller. The command received from the memory controller may be a program command.

[0157] In step S1703, the memory device (100) may compare whether the word line corresponding to the address received from the memory controller is a vulnerable word line. The word line corresponding to the address may be a selected word line. If the word line corresponding to the address received from the memory controller is a vulnerable word line, step S1705 may be performed. The word line corresponding to the address may be a selected word line. If the word line corresponding to the address received from the memory controller is not a vulnerable word line, step S1707 may be performed.

[0158] In step S1705, the memory device (100) can perform a program operation in a first program mode.

[0159] In step S1707, the memory device (100) can perform a program operation in a second program mode.

[0160] FIG. 18 is a block diagram showing a memory card system to which a memory system according to one embodiment of the present invention is applied.

[0161] Referring to FIG. 18, the memory card system (2000) includes a memory controller (2100), a memory device (2200), and a connector (2300).

[0162] The memory controller (2100) is connected to the memory device (2200). The memory controller (2100) is configured to access the memory device (2200). For example, the memory controller (2100) may be configured to control the read, write, erase, and background operations of the memory device (2200). The memory controller (2100) is configured to provide an interface between the memory device (2200) and a host. The memory controller (2100) is configured to run firmware for controlling the memory device (2200). The memory controller (2100) may be implemented in the same way as the memory controller (200) described with reference to FIG. 1. The memory device (2200) may be implemented in the same way as the memory device (100) described with reference to FIG. 1.

[0163] For example, the memory controller (2100) may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0164] The memory controller (2100) can communicate with an external device through a connector (2300). The memory controller (2100) can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller (2100) is configured to communicate with an external device through at least one of various communication standards such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. For example, the connector (2300) may be defined by at least one of the various communication standards described above.

[0165] For example, the memory device (2200) may be composed of various non-volatile memory devices such as EEPROM (Electrically Erasable and Programmable ROM), NAND flash memory, NOR flash memory, PRAM (Phase-change RAM), ReRAM (Resistive RAM), FRAM (Ferroelectric RAM), STT-MRAM (Spin Transfer Torque-Magnetic RAM), etc.

[0166] The memory controller (2100) and the memory device (2200) can be integrated into a single semiconductor device to form a memory card. For example, the memory controller (2100) and the memory device (2200) can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash card (CF), Smart Media card (SM, SMC), Memory Stick, Multimedia card (MMC, RS-MMC, MMCmicro, eMMC), SD card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc.

[0167] FIG. 19 is a block diagram showing a user system to which a memory system according to one embodiment of the present invention is applied.

[0168] Referring to FIG. 19, the user system (4000) includes an application processor (4100), a memory module (4200), a network module (4300), a storage module (4400), and a user interface (4500).

[0169] The application processor (4100) can run components included in the user system (4000), an operating system (OS), or user programs, etc. For example, the application processor (4100) may include controllers, interfaces, graphics engines, etc. that control components included in the user system (4000). The application processor (4100) may be provided as a system-on-chip (SoC).

[0170] The memory module (4200) can operate as the main memory, operational memory, buffer memory, or cache memory of the user system (4000). The memory module (4200) may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, etc. or non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM, etc. For example, the application processor (4100) and the memory module (4200) may be packaged based on POP (Package on Package) and provided as a single semiconductor package.

[0171] The network module (4300) can communicate with external devices. For example, the network module (4300) can support wireless communication such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile communication), WCDMA (wideband CDMA), CDMA-2000, TDMA (Time Division Multiple Access), LTE (Long Term Evolution), WiMAX, WLAN, UWB, Bluetooth, Wi-Fi, etc. For example, the network module (4300) can be included in the application processor (4100).

[0172] The storage module (4400) can store data. For example, the storage module (4400) can store data received from the application processor (4100). Alternatively, the storage module (4400) can transfer data stored in the storage module (4400) to the application processor (4100). For example, the storage module (4400) can be implemented as a non-volatile semiconductor memory device such as PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), NAND flash, NOR flash, or a three-dimensional NAND flash. For example, the storage module (4400) can be provided as a removable storage medium such as a memory card or an external drive of the user system (4000).

[0173] For example, the storage module (4400) may include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices may operate in the same manner as the memory device (100) described with reference to FIG. 1. The storage module (4400) may operate in the same manner as the memory system (50) described with reference to FIG. 1.

[0174] The user interface (4500) may include interfaces for inputting data or commands to the application processor (4100) or outputting data to an external device. For example, the user interface (4500) may include user input interfaces such as a keyboard, keypad, button, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric element, etc. The user interface (4500) may include user output interfaces such as an LCD (Liquid Crystal Display), OLED (Organic Light Emitting Diode) display, AMOLED (Active Matrix OLED) display, LED, speaker, monitor, etc. Explanation of the symbols

[0175] 50: Memory System 100: Memory device 140: Vulnerable Wordline Identifier 150: Program operation control unit 200: Memory controller 300: Host

Claims

Claim 1 A memory device comprising: a plurality of memory cells connected to a plurality of word lines; a peripheral circuit that performs a word line inspection operation to determine a vulnerable word line among the plurality of word lines; and a vulnerable word line determination unit that controls the peripheral circuit to store in one memory block the result of comparing a first number of off cells identified by a first pre-program operation in which a pre-charge voltage is applied to a source line commonly connected to the plurality of memory cells during the word line inspection operation, and a second number of off cells identified by a second pre-program operation in which a ground voltage is applied to the source line, and the pre-program voltage is applied to the selected word line. Claim 2 In claim 1, the vulnerable wordline determination unit is a memory device that controls the peripheral circuit to store result information indicating that the selected wordline is the vulnerable wordline in any one of the memory blocks when the difference between the first number of off-cells and the second number of off-cells exceeds a preset reference number of off-cells. Claim 3 In claim 2, the vulnerable wordline determination unit is a memory device that controls the peripheral circuit to store result information indicating that the selected wordline is a normal wordline in any one of the memory blocks if the difference between the first number of off-cells and the second number of off-cells is less than or equal to the reference number of off-cells. Claim 4 In claim 3, the first and second pre-program operations include a pre-verification operation that identifies the threshold voltage of selected memory cells connected to the selected word line using a pre-verification voltage, and the first and second off-cell count is the number of memory cells among the selected memory cells that have a threshold voltage greater than the pre-verification voltage. Claim 5 A memory device comprising: a plurality of memory cells connected to a plurality of word lines; a peripheral circuit that performs a program operation for storing data in the plurality of memory cells; a vulnerable word line information storage unit that stores information regarding a vulnerable word line among the plurality of word lines; and a program operation control unit that controls the peripheral circuit to perform the program operation in a first program mode or a second program mode according to the result of comparing whether a selected word line corresponding to an address provided by a memory controller is a vulnerable word line based on the information regarding the vulnerable word line; wherein the information regarding the vulnerable word line includes information determined by comparing a first pre-program operation that applies a precharge voltage to a source line commonly connected to the plurality of memory cells and raises the threshold voltage of the plurality of memory cells, and a second pre-program operation that applies a ground voltage to the source line and raises the threshold voltage of the plurality of memory cells. Claim 6 In claim 5, the information regarding the vulnerable wordline comprises information determined based on the result of comparing the first number of off-cells identified by the first pre-program operation and the second number of off-cells identified by the second pre-program operation. Claim 7 In claim 6, the information regarding the vulnerable wordline comprises a memory device including information regarding a wordline connected to memory cells in which the difference between the first number of off-cells and the second number of off-cells exceeds a preset reference number of off-cells. Claim 8 A memory device according to claim 5, wherein the plurality of memory cells include first memory cells included in a first channel region and second memory cells included in a second channel region located above the first channel region, and the information regarding the vulnerable word line includes information regarding word lines connected to memory cells located at the bottom of the first channel region and the second channel region, respectively. Claim 9 In claim 5, the program operation control unit controls the peripheral circuit to perform the program operation in the first program mode if the selected word line is a vulnerable word line, and to perform the program operation in the second program mode if the selected word line is a normal word line. Claim 10 A memory device according to claim 9, wherein the program operation comprises a plurality of program loops, and the program operation control unit controls the peripheral circuit to apply the precharge voltage to the source line from any one of the plurality of program loops that is preset in the first program mode, and to apply the precharge voltage to the source line from the program loop preceding any one of the program loops in the second program mode. Claim 11 In claim 9, the program operation control unit controls the peripheral circuit to apply the precharge voltage to the source line during a first interval in the first program mode and then apply the program voltage to the selected word line, and in the second program mode, apply the precharge voltage to the source line during a second interval shorter than the first interval and then apply the program voltage to the selected word line. Claim 12 In claim 9, the program operation control unit controls the peripheral circuit to apply a turn-on voltage to unselected word lines among the plurality of word lines while applying the precharge voltage to the source line in the first program mode, and to apply a ground voltage to the unselected word lines while applying the precharge voltage to the source line in the second program mode. Claim 13 In claim 9, the program operation control unit controls the peripheral circuit to apply a first pass voltage to non-selected word lines among the plurality of word lines while applying a program voltage to the selected word line in the first program mode, and to apply a second pass voltage greater than the first pass voltage to the non-selected word lines while applying the program voltage to the selected word line in the second program mode. Claim 14 In claim 9, the program operation control unit controls the peripheral circuit to apply a first pass voltage to non-selected word lines among the plurality of word lines while applying a program voltage to the selected word line in the first program mode, apply a second pass voltage greater than the first pass voltage to word lines adjacent to the selected word line while applying the program voltage to the selected word line in the second program mode, and apply the first pass voltage to the remaining word lines among the plurality of word lines excluding the selected word line and the adjacent word lines. Claim 15 A method of operation of a memory device comprising a plurality of memory cells connected to a plurality of word lines, comprising: a step of comparing whether a selected word line corresponding to an address provided by a memory controller is a vulnerable word line based on information regarding a vulnerable word line; a step of determining one of a first program mode or a second program mode based on the result of the comparison; and a step of performing a program operation to store data in selected memory cells connected to the selected word line based on the one of the program modes; wherein the information regarding the vulnerable word line comprises information determined by comparing a first pre-program operation of applying a precharge voltage to a source line commonly connected to the plurality of memory cells and raising the threshold voltage of the plurality of memory cells, and a second pre-program operation of applying a ground voltage to the source line and raising the threshold voltage of the plurality of memory cells. Claim 16 A method of operation of a memory device according to claim 15, wherein the information regarding the vulnerable word line comprises information regarding a word line connected to memory cells in which the difference between the number of first off cells identified by the first pre-program operation and the number of second off cells identified by the second pre-program operation exceeds a preset reference number of off cells. Claim 17 A method of operation of a memory device according to claim 15, wherein the step of determining any one of the program modes is to determine any one of the program modes as the first program mode if the selected word line is a vulnerable word line, and to determine any one of the program modes as the second program mode if the selected word line is a normal word line. Claim 18 A method of operation of a memory device according to claim 17, wherein the program operation comprises a plurality of program loops, and the number of program loops that apply the precharge voltage to the source line in the first program mode is less than the number of program loops that apply the precharge voltage to the source line in the second program mode. Claim 19 A method of operation of a memory device according to claim 17, wherein the time for pre-charging the channel region of the plurality of memory cells in the first program mode is shorter than the time for pre-charging the channel region of the plurality of memory cells in the second program mode. Claim 20 A method of operation of a memory device according to claim 17, wherein the first program mode applies a turn-on voltage to unselected word lines among the plurality of word lines while applying the precharge voltage to the source line, and the second program mode applies a ground voltage to the remaining word lines excluding the selected word line and the word lines adjacent to the selected word line among the plurality of word lines while applying the precharge voltage to the source line.

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