Semiconductor device for detecting defective buffer circuit

Abstract

A semiconductor device includes a buffer circuit that receives an external setting signal, a sampling code generation circuit that generates a sampling code by performing a counting operation during a sampling interval controlled based on the output signal of the buffer circuit, and a code comparator that generates a comparison flag by comparing the sampling code with a reference code.

Description

Technology Field

[0001] The present invention relates to a semiconductor device capable of detecting a defect in a buffer circuit. Background Technology

[0002] A semiconductor device can receive commands and addresses and perform various internal operations including active operations, write operations, read operations, and precharge operations. The semiconductor device includes multiple buffers to receive commands, addresses, and chip select signals, etc. If a defect occurs in at least one of the buffers, an error may occur in the internal operations performed based on the commands, addresses, and chip select signals, etc. The problem to be solved

[0003] The present invention provides a semiconductor device capable of detecting a defect in a buffer circuit. means of solving the problem

[0004] To this end, the present invention provides a semiconductor device comprising: a sampling code generation circuit that includes a buffer circuit for receiving an external setting signal and generates a sampling code by performing a counting operation during a sampling interval controlled based on the output signal of the buffer circuit; and a code comparator that generates a comparison flag by comparing the sampling code with a reference code.

[0005] In addition, the present invention provides a semiconductor device comprising: a sampling code generation circuit that generates a sampling oscillation signal by sampling an oscillation signal during a sampling interval adjusted according to whether a failure occurs in a buffer circuit, and generates a sampling code by counting the sampling oscillation signal; and a code comparator that generates a comparison flag by comparing the sampling code with a reference code.

[0006] In addition, the present invention provides a semiconductor device comprising: a buffer circuit that receives a command address and a chip selection signal and generates an internal command address and an internal chip selection signal; a defect detection signal generation circuit that generates a defect detection signal based on the internal command address and the internal chip selection signal; a driving signal output circuit that drives an initialized driving signal during an initialization operation so that the logic level transitions based on the defect detection signal; a sampling code output circuit that generates a sampling code based on an initialization pulse and the driving signal; and a code comparator that generates a comparison flag by comparing the sampling code with a reference code. Effects of the invention

[0007] According to the present invention, the sampling interval is adjusted based on whether a defect has occurred in the buffer circuit receiving the command address and chip selection signal, and a comparison flag containing information regarding the defect of the buffer circuit is generated by comparing a sampling code generated through a counting operation during the sampling interval with a reference code, thereby enabling easy detection of the defect of the buffer circuit receiving the command address and chip selection signal. Brief explanation of the drawing

[0008] FIG. 1 is a block diagram illustrating the configuration of a semiconductor device according to an example of the present disclosure. FIG. 2 is a block diagram illustrating the configuration according to an example of a sampling code generation circuit included in the semiconductor device shown in FIG. 1. FIG. 3 is a circuit diagram according to an example of an initial pulse generation circuit included in the sampling code generation circuit shown in FIG. 2. FIG. 4 is a diagram according to an example of a driving signal generation circuit included in the sampling code generation circuit shown in FIG. 2. FIG. 5 is a circuit diagram according to an example of a first command address buffer included in the driving signal generation circuit shown in FIG. 4. FIG. 6 and FIG. 7 are timing diagrams for explaining the operation of the first command address buffer shown in FIG. 5. FIG. 8 is a diagram according to an example of a sampling code output circuit included in the sampling code generation circuit shown in FIG. 2. FIG. 9 to 15 are diagrams for explaining the test operation of the semiconductor device shown in FIG. 1 to 8. Specific details for implementing the invention

[0009] In the description of the following embodiments, the term "pre-set" means that the numerical value of a parameter is predetermined when the parameter is used in a process or algorithm. Depending on the embodiment, the numerical value of the parameter may be set when the process or algorithm starts or during the period in which the process or algorithm is executed.

[0010] Terms such as "first" and "second," used to distinguish various components, are not limited by the components. For example, the first component may be named the second component, and conversely, the second component may be named the first component.

[0011] When it is stated that one component is "connected" or "connected" to another component, it should be understood that they are connected directly or through an intermediate component. On the other hand, the descriptions "directly connected" and "directly connected" should be understood as meaning that one component is directly connected to another component without any intermediary component.

[0012] "Logic high level" and "logic low level" are used to describe the logic levels of signals. A signal having a "logic high level" is distinguished from a signal having a "logic low level." For example, when a signal having a first voltage corresponds to a signal having a "logic high level," a signal having a second voltage may correspond to a signal having a "logic low level." According to one embodiment, the "logic high level" may be set to a voltage greater than the "logic low level." Meanwhile, the logic levels of the signals may be set to different logic levels or opposite logic levels according to an embodiment. For example, a signal having a logic high level may be set to have a logic low level according to an embodiment, and a signal having a logic low level may be set to have a logic high level according to an embodiment.

[0013] The present invention will be described in more detail below through examples. These examples are merely for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

[0014] As illustrated in FIG. 1, a semiconductor device (100) according to one embodiment of the present disclosure may include a sampling code generation circuit (101, SAP_C GEN), a reference code storage circuit (103, REF_C STORAGE CIRCUIT), and a code comparator (105, CODE COMPARATOR).

[0015] The sampling code generation circuit (101) can receive a test signal (TEN), a command address (CA), and a chip select signal (CS) from an external device (not shown) of the semiconductor device (100). The external device of the semiconductor device (100) may include a host (not shown), a controller (not shown), and a test device (not shown). According to an embodiment, the test signal (TEN) may be implemented to be generated by decoding the command address (CA) internally within the semiconductor device (100). Whether or not to perform a test may be determined based on the logic level of the test signal (TEN). For example, if the test signal (TEN) is set to a first logic level, no test operation can be performed, and if the test signal (TEN) is set to a second logic level, a test operation can be performed. In this embodiment, the first logic level may be set to a logic low level and the second logic level may be set to a logic high level, but this is merely an embodiment and is not limited thereto. The sampling code generation circuit (101) can generate a sampling code (SAP_C) based on a test signal (TEN) and an external setting signal. In this embodiment, the external setting signal may include a command address (CA) and a chip selection signal (CS). The sampling code generation circuit (101) may include a buffer circuit (131 in FIG. 4) that receives the command address (CA) and the chip selection signal (CS). The command address (CA) and the chip selection signal (CS) may be input to the buffer circuit (131 in FIG. 4) with the slope of the logic level change adjusted according to the test signal (TEN). The sampling code generation circuit (101) can adjust the sampling interval based on whether a defect has occurred in the buffer circuit (131 in FIG. 4) that receives the command address (CA) and chip selection signal (CS), and can generate a sampling code (SAP_C) through a counting operation performed during the sampling interval. The setting value of the sampling code (SAP_C) can be set to increase by '1' each time a counting operation is performed during the sampling interval.For example, assuming that the sampling code (SAP_C) contains 5 bits and that 12 counting operations are performed during the sampling interval, the setting value of the sampling code (SAP_C) can be set to the binary stream '01100' (decimal '12'), and assuming that 21 counting operations are performed during the sampling interval, the setting value of the sampling code (SAP_C) can be set to the binary stream '10101' (decimal '21'). The sampling code (SAP_C) can be generated by a counting operation performed during a sampling interval that is set to be larger than when no defect occurs when a defect occurs in the buffer circuit (131 in FIG. 4). In this embodiment, the sampling code generation circuit (101) can significantly adjust the sampling interval when a defect occurs in the buffer circuit (131 in FIG. 4) compared to when no defect occurs, but this is merely an example and is not limited to such an adjustment method.

[0016] The reference code storage circuit (103) can receive a test signal (TEN) from an external device (not shown) of the semiconductor device (100). The reference code storage circuit (103) can store a reference code (REF_C) before the test is performed. The reference code storage circuit (103) may include a storage medium for storing the reference code (REF_C). The storage medium included in the reference code storage circuit (103) may be implemented with a fuse (not shown) and a latch (not shown), etc. The reference code storage circuit (103) stores the reference code (REF_C) based on the test signal (TEN). It can output. The reference code storage circuit (103) can output the reference code (REF_C) when the test is performed. It can be output. The reference code (REF_C) may include multiple bits. The setting value of the reference code (REF_C) can be set to serve as a criterion for determining whether a defect has occurred in the buffer circuit (131 in FIG. 4). For example, when the setting value of the reference code (REF_C) is set to the binary stream '01111' (decimal '15'), the criterion for when a defect has occurred in the buffer circuit (131 in FIG. 4) is set to the case where a counting operation exceeding 15 times is performed during the sampling interval.

[0017] The code comparator (105) can receive a sampling code (SAP_C) from the sampling code generation circuit (101) and a reference code (REF_C) from the reference code storage circuit (103). The code comparator (105) can generate a comparison flag (COM_FLAG) based on the sampling code (SAP_C) and the reference code (REF_C). The code comparator (105) can set the logic level of the comparison flag (COM_FLAG) by comparing the sampling code (SAP_C) and the reference code (REF_C). For example, the code comparator (105) can generate a comparison flag (COM_FLAG) of the first logic level when the setting value of the sampling code (SAP_C) is less than or equal to the setting value of the reference code (REF_C), and can generate a comparison flag (COM_FLAG) of the second logic level when the setting value of the sampling code (SAP_C) is greater than the setting value of the reference code (REF_C). For example, when the reference code (REF_C) is set to the binary stream '01111' (decimal '15') and no defect occurs in the buffer circuit (131 in FIG. 4), the code comparator (105) can generate a comparison flag (COM_FLAG) of the first logic level when the setting value of the sampling code (SAP_C) is set to the binary stream '01100' (decimal '12'). Likewise, when the reference code (REF_C) is set to the binary stream '01111' (decimal '15') and a defect occurs in the buffer circuit (131 in FIG. 4) and the setting value of the sampling code (SAP_C) is set to the binary stream '10101' (decimal '21'), the code comparator (105) can generate a comparison flag (COM_FLAG) of the second logic level. As described above, since the comparison flag (COM_FLAG) contains information regarding whether the buffer circuit (131 in FIG. 4) is defective, the defect of the buffer circuit (131 in FIG. 4) can be easily confirmed through the logic level of the comparison flag (COM_FLAG).

[0018] As illustrated in FIG. 2, the sampling code generation circuit (101) may include an initialization pulse generation circuit (111), a driving signal generation circuit (113), and a sampling code output circuit (115).

[0019] The initialization pulse generation circuit (111) can generate an initialization pulse (INTP) based on an initialization signal (INT). Depending on the embodiment, the initialization pulse generation circuit (111) receives an initialization signal (INT) from outside the semiconductor device (100) or the semiconductor device (100) An initialization signal (INT) generated internally can be received. The initialization signal (INT) may be set to have a preset logic level during the initialization operation period of the semiconductor device (100). The initialization operation period of the semiconductor device (100) may be set as a period from the point when power begins to be supplied to the semiconductor device (100) until the point when power is supplied stably, but the initialization operation period may be set in various ways depending on the embodiment. In this embodiment, the initialization signal (INT) may be set to a second logic level during the initialization operation period and may be set to transition from the second logic level to the first logic level at the time when the initialization operation period ends, but this is merely an embodiment and is not limited thereto. The initialization pulse generation circuit (111) may generate an initialization pulse (INTP) at the time when the logic level of the initialization signal (INT) transitions. The initialization pulse generation circuit (111) may generate an initialization pulse (INTP) in synchronization with the time when the initialization operation period ends. In this embodiment, the initialization pulse (INTP) is generated as a logic low-level pulse, but this is merely an example and is not limited thereto.

[0020] The driving signal generation circuit (113) can generate a driving signal (PDS) based on an initialization signal (INT), a test signal (TEN), a reference voltage (VREF), a command address (CA), and a chip selection signal (CS). The driving signal generation circuit (113) can initialize the driving signal (PDS) to a first logic level by the initialization signal (INT) of a second logic level during the period in which the initialization operation is performed. The driving signal generation circuit (113) can drive the driving signal (PDS) so that the level of the driving signal (PDS) rises from the first logic level to the second logic level by the command address (CA) and the chip selection signal (CS) received based on the reference voltage (VREF) when the test is performed after the initialization operation is finished and the initialization signal (INT) has transitioned from the second logic level to the first logic level. The required interval for the level of the driving signal (PDS) to rise from the first logic level to the second logic level can be set to be longer as the interval for the command address (CA) and chip select signal (CS) to be input at a level higher than the reference voltage (VREF) becomes shorter. If a defect occurs in the buffer circuit (131 in FIG. 4), the command address (CA) and chip select signal (CS) input at a level higher than the reference voltage (VREF) cannot be properly received, so the required interval for the level of the activated driving signal (PDS) to rise from the first logic level to the second logic level can be set to be longer compared to the case where no defect occurs in the buffer circuit (131 in FIG. 4).

[0021] The sampling code output circuit (115) can receive an initialization pulse (INTP) from the initialization pulse generation circuit (111) and a driving signal (PDS) from the driving signal generation circuit (113). The sampling code output circuit (115) can generate a sampling code (SAP_C) based on the initialization pulse (INTP) and the driving signal (PDS). The sampling code output circuit (115) can generate a sampling oscillation signal (OSC in FIG. 8) by sampling the oscillation signal (OSC in FIG. 8) when the initialization operation is terminated and the initialization pulse (INTP) is generated and the driving signal (PDS) rises to the second logic level, and generate a sampling oscillation signal (S_OSC in FIG. 8) by performing a counting operation to count the sampling oscillation signal (S_OSC in FIG. 8) to generate the sampling code (SAP_C). The sampling code output circuit (115) can generate a sampling code (SAP_C) in which the setting value is set larger than in the case where no defect occurs in the buffer circuit (131 in FIG. 4) because the number of times the sampling oscillation signal (S_OSC in FIG. 8) is counted increases when the interval required for the level of the driving signal (PDS) to rise from the first logic level to the second logic level increases when a defect occurs in the buffer circuit (131 in FIG. 4).

[0022] As illustrated in FIG. 3, the initialization pulse generation circuit (111) may include an inversion delay circuit (121) and a pulse output circuit (123). The inversion delay circuit (121) may be implemented as an inverter chain. The inversion delay circuit (121) may receive an initialization signal (INT), delay it by a delay interval, and invert it to output it. The pulse output circuit (123) may receive the initialization signal (INT) and the output signal of the inversion delay circuit (121), perform a logical OR operation, and generate an initialization pulse (INTP). The initialization pulse generation circuit (111) may receive an initialization signal (INT) that transitions from a logic high level to a logic low level when the initialization operation ends, and generate an initialization pulse (INTP) in synchronization with the time when the initialization operation ends. The initialization pulse (INTP) can be set to be generated at a logic high level for a delay period set by the inversion delay circuit (121) at the time when the initialization operation ends.

[0023] As illustrated in FIG. 4, the driving signal generation circuit (113) may include a buffer circuit (131), a defect detection signal generation circuit (133), and a driving signal output circuit (135).

[0024] The buffer circuit (131) may include a first buffer (131_1), a second buffer (131_2), a third buffer (131_3), a fourth buffer (131_4), a fifth buffer (131_5), a sixth buffer (131_6), a seventh buffer (131_7), and an eighth buffer (131_8). The first buffer (131_1) is a first command address buffer, and based on a test signal (TEN) and a reference voltage (VREF), the first bit (CA) of the command address <1> From ) the first bit of the internal command address (ICA <1> ) can be generated. When a test is performed and a test signal (TEN) of the second logic level is input, the first buffer (131_1) generates the first bit (CA) of the command address based on the reference voltage (VREF). <1> Buffering ) to the first bit of the internal command address (ICA <1> ) can be generated. The second to seventh buffers (131_2 to 131_7) are each second to seventh command address buffers, and can generate the second to seventh bits (ICA<2:7>) of the internal command address from the second to seventh bits (CA<2:7>) of the command address based on the test signal (TEN) and the reference voltage (VREF). The second to seventh buffers (131_2 to 131_7) can generate the second to seventh bits (ICA<2:7>) of the internal command address by buffering the second to seventh bits (CA<2:7>) of the command address based on the reference voltage (VREF) when a test is performed and the test signal (TEN) of the second logic level is input. The eighth buffer (131_8) is a chip select buffer and can generate an internal chip select signal (ICS) from a chip select signal (CS) based on a test signal (TEN) and a reference voltage (VREF). The eighth buffer (131_8) can generate an internal chip select signal (ICS) by buffering the chip select signal (CS) based on the reference voltage (VREF) when a test is performed and a test signal (TEN) of the second logic level is input.It is preferable that when a test is performed, the first to seventh bits (CA<1:7>) of the command address and the chip select signal (CS) each input to the buffer circuit (131) are set to have a logic high level equal to the test pulse width. When a failure occurs in at least one of the first to eighth buffers (131_1~131_8) included in the buffer circuit (131), the pulse width at which at least one of the first to seventh bits (ICA<1:7>) of the internal command address and the internal chip select signal (ICS) is set to a logic high level may be set to be smaller than the test pulse width. For example, when a failure occurs in the third buffer (131_3) included in the buffer circuit (131), the third bit (ICA) of the internal command address <3> The pulse width at which ) is set to a logic high level is set smaller than the test pulse width.

[0025] The defect detection signal generation circuit (133) may include AND gates (133_1 to 133_6) and a NAND gate (133_7). The AND gate (133_1) is the first bit (ICA) of the internal command address. <1> ) and the second bit of the internal command address (ICA <2> It can perform a logical AND operation by receiving ). The AND gate (133_2) can receive the third bit (ICA) of the internal command address. <3> ) and the 4th bit of the internal command address (ICA <4> It can perform a logical AND operation by receiving ). The AND gate (133_3) can receive the 5th bit (ICA) of the internal command address. <5> ) and the 6th bit of the internal command address (ICA <6> It can perform a logical AND operation by receiving ). The AND gate (133_4) can receive the 7th bit (ICA) of the internal command address. <7> It can perform a logical AND operation by receiving the internal chip select signal (ICS) and the AND gate (133_5). The AND gate (133_5) can perform a logical AND operation by receiving the output signal of the AND gate (133_1) and the output signal of the AND gate (133_2). The AND gate (133_6) can perform a logical AND operation by receiving the output signal of the AND gate (133_3) and the output signal of the AND gate (133_4). The NAND gate (133_7) can generate a defect detection signal (FDET) by receiving the output signal of the AND gate (133_5) and the output signal of the AND gate (133_6) and performing a negative logical AND operation. The defect detection signal generation circuit (133) can generate a defect detection signal (FDET) based on the first to seventh bits (ICA<1:7>) of the internal command address and the internal chip select signal (ICS). The fault detection signal generation circuit (133) can generate a fault detection signal (FDET) that is set to a logic low level during the period when the first to seventh bits (ICA<1:7>) of the internal command address and the internal chip selection signal (ICS) are both at a logic high level. The period during which the fault detection signal (FDET) is set to a logic low level is formed to be longer when no fault occurs in the buffer circuit (131) than when a fault occurs in the buffer circuit (131).

[0026] The driving signal output circuit (135) may include a PMOS transistor (135_1), a resistor (135_3), an NMOS transistor (135_5), a capacitor (135_7), and inverters (135_8, 135_9). The PMOS transistor (135_1) and the resistor (135_3) are connected in series between the power supply voltage (VDD) and the node (nd131) to drive the node (nd131) to the power supply voltage (VDD) during the period in which the fault detection signal (FDET) is set to a logic low level. The voltage of the node (nd131) can be driven to a logic high level more quickly as the period in which the fault detection signal (FDET) is set to a logic low level becomes longer. The NMOS transistor (135_5) is connected between the node (nd131) and the ground voltage (VSS), so that when an initialization signal (INT) having a logic high level is input to the gate of the NMOS transistor (135_5) during the period in which the initialization operation is performed, the node (nd131) can be driven to the ground voltage (VSS) and initialized to a logic low level. The capacitor (135_7) is connected between the node (nd131) and the ground voltage (VSS) so that the voltage of the node (nd131) can be stably maintained. Inverters (135_8, 135_9) are connected in series to the node (nd131) and can buffer the signal of the node (nd131) and output it as a driving signal (PDS).

[0027] As illustrated in FIG. 5, the first buffer (131_1) may include a selection input circuit (137) and a differential amplifier circuit (139).

[0028] The selection input circuit (137) may include an inverter (137_1) and transmission gates (137_3, 137_5). The inverter (137_1) may output an inverted buffer of a test signal (TEN). The transmission gate (137_3) is turned on when the test signal (TEN) is at a logic low level because no test is performed, and the first bit (CA) of the command address <1> ) select the first bit of the command address (SCA <1> It can be transmitted to ). The transmission gate (137_5) is turned on when the test is performed and the test signal (TEN) is at a logic high level, and the first bit (CA) of the command address <1> ) select the first bit of the command address (SCA <1> It can be transmitted via ). In this embodiment, the resistance value of the transmission gate (137_5) can be set to be greater than the resistance value of the transmission gate (137_3). Accordingly, the first bit (SCA of the selection command address) <1> The slope of the transition from the logic low level to the logic high level can be set to be gentler when the test is performed compared to when the test is not performed. The resistance values ​​of the transmission gate (137_5) and the transmission gate (137_3) can be set in various ways depending on the embodiment.

[0029] The differential amplifier circuit (139) receives the first bit (SCA) of the selection command address from the selection input circuit (137). <1> ) can be received. The differential amplifier circuit (139) can receive the first bit (SCA) of the select command address. <1> Differentially amplifying ) based on the reference voltage (VREF) to the first bit of the internal command address (ICA <1> ) can be generated. For example, the differential amplifier circuit (139) can generate the first bit (SCA) of the select command address. <1> When ) is at a level below the reference voltage (VREF), the first bit (ICA) of the logic low-level internal command address <1> It can generate ) and the first bit of the select command address (SCA <1> When ) is at a level greater than the reference voltage (VREF), the first bit (ICA) of the logic-high level internal command address <1> Can generate ).

[0030] Referring to FIGS. 6 and 7, the first bit (SCA) of the select command address, which adjusts the slope of the logic level transition depending on whether a test is performed. <1> The waveform of ) and the first bit of the internal command address (ICA <1> The pulse width of ) can be checked.

[0031] As shown in FIG. 6, when the test signal (TEN) is at a logic low level ("L") because no test is performed, the first bit (CA) of the command address is transmitted through the transmission gate (137_3), which is set to have a resistance value smaller than that of the transmission gate (137_5). <1> Since ) is input, the first bit of the select command address (SCA <1> ) transitions from a logic low level to a logic high level with the first slope (Slope1), and the first bit (ICA) of the internal command address <1> ) is generated at a logic high level during the first pulse width (PW1) interval.

[0032] As illustrated in FIG. 7, when a test is performed and the test signal (TEN) is at a logic high level ("H"), the first bit (CA) of the command address is transmitted through a transmission gate (137_5) with a resistance value set larger than that of the transmission gate (137_3). <1> Since ) is input, the first bit of the select command address (SCA <1> ) transitions from a logic low level to a logic high level with a second slope (Slope2) that is smaller (gentler) than the first slope (Slope1), and the first bit (ICA) of the internal command address <1> ) is generated at a logic high level during the second pulse width (PW2) interval. Since the second slope (Slope2) is set to be gentler than the first slope (Slope1), the second pulse width (PW2) is set to be smaller than the first pulse width (PW1).

[0033] As illustrated in FIG. 8, the sampling code output circuit (115) may include a sampling interval signal generation circuit (141), an oscillation signal generation circuit (143), an oscillation signal sampling circuit (145), and a counter (147).

[0034] The sampling interval signal generation circuit (141) may include a PMOS transistor (141_1) and NMOS transistors (141_3, 141_5). The PMOS transistor (141_1) may be connected between the power supply voltage (VDD) and the node (nd141) and turned on in response to an initialization pulse (INTP). The NMOS transistors (141_3, 141_5) may be connected in series between the node (nd141) and the ground voltage (VSS). The NMOS transistor (141_3) may be turned on in response to the initialization pulse (INTP), and the NMOS transistor (141_5) may be turned on in response to a driving signal (PDS). The sampling interval signal generation circuit (141) may generate a sampling interval signal (SAP_EN) based on the initialization pulse (INTP) and the driving signal (PDS). The sampling interval signal generation circuit (141) can set the sampling interval signal (SAP_EN) to a logic high level by driving the node (nd141) to a power supply voltage (VDD) by means of a PMOS transistor (141_1) that turns on when the initialization pulse (INTP) is generated at a logic low level in synchronization with the time when the initialization operation ends. The sampling interval signal generation circuit (141) can set the sampling interval signal (SAP_EN) to a logic low level by driving the node (nd141) to a ground voltage (VSS) by means of NMOS transistors (141_3, 141_5) that turn on when the driving signal (PDS) transitions from a logic low level to a logic high level while the initialization pulse (INTP) is maintained at a logic high level after the initialization pulse (INTP) is generated at a logic low level.

[0035] The oscillation signal generation circuit (143) can generate an oscillation signal (OSC). The oscillation signal (OSC) can be set as a periodic signal having a constant period. The oscillation signal generation circuit (143) can be implemented as a general oscillator.

[0036] The oscillation signal sampling circuit (145) can receive a sampling interval signal (SAP_EN) from the sampling interval signal generation circuit (141) and can receive an oscillation signal (OSC) from the oscillation signal generation circuit (143). The oscillation signal sampling circuit (145) can generate a sampling oscillation signal (S_OSC) by sampling the oscillation signal (OSC) during the interval in which the sampling interval signal (SAP_EN) is set to a logic high level. The oscillation signal sampling circuit (145) can output the oscillation signal (OSC) generated during the interval from the point in time when the initialization pulse (INTP) is generated at a logic low level to the point in time when the driving signal (PDS) transitions from a logic low level to a logic high level, synchronized with the time when the initialization operation ends, as the sampling oscillation signal (S_OSC).

[0037] The counter (147) can receive a sampling oscillation signal (S_OSC) from the oscillation signal sampling circuit (145). The counter (147) can generate a sampling code (SAP_C) by counting the sampling oscillation signal (S_OSC). The setting value of the sampling code (SAP_C) can be set to change whenever the counter (147) performs a counting operation during the sampling interval. For example, when the sampling code (SAP_C) is 5 bits and initialized to '00000', the counter (147) can generate a sampling code (SAP_C) set to a binary stream '00001' (decimal '1') by counting the first pulse of the sampling oscillation signal (S_OSC), and generate a sampling code (SAP_C) set to a binary stream '00010' (decimal '2') by counting the second pulse of the sampling oscillation signal (S_OSC). Likewise, the counter (147) can generate a sampling code (SAP_C) set to a binary stream '11110' (decimal '30') by counting the 30th pulse of the sampling oscillation signal (S_OSC), and can generate a sampling code (SAP_C) set to a binary stream '11111' (decimal '31') by counting the 31st pulse of the sampling oscillation signal (S_OSC). In this embodiment, the sampling code (SAP_C) is 5 bits and the counter (147) counts up to the 31st pulse of the sampling oscillation signal (S_OSC) has been described as an example, but this is merely an example and is not limited thereto.

[0038] Referring to Fig. 9, the test operation of the semiconductor device (100) is as follows.

[0039] As illustrated in FIG. 9, when the initialization operation (S101) is performed, the initialization signal (INT) is set to a logic high level and the driving signal (PDS) is initialized to a logic low level. When the test operation is initiated after the initialization operation is completed, a command and an address are input to the buffer circuit (131). (S103) The sampling interval is adjusted according to whether the buffer circuit (131) is defective, and the sampling oscillation signal (S_OSC) is counted during the sampling interval to generate a sampling code (SAP_C). (S105) The sampling code (SAP_C) is compared with a reference code (REF_C) which is set to serve as a criterion for determining whether a defect has occurred in the buffer circuit (131 in FIG. 4). (S107) A comparison flag (COM_FLAG) is generated according to the comparison result between the sampling code (SAP_C) and the reference code (REF_C). (S109) Since the comparison flag (COM_FLAG) generated when the test operation of the semiconductor device (100) is performed contains information regarding whether the buffer circuit (131) is defective, through the logic level of the comparison flag (COM_FLAG) The defect status of the buffer circuit (131) can be easily checked.

[0040] Referring to FIGS. 10 to 14, the test operation of the semiconductor device (100) performed in a state where no defect occurs in the buffer circuit (131) is as follows.

[0041] As illustrated in FIGS. 10 and 11, during the period in which an initialization operation is performed by an initialization signal (INT) set to a logic high level, the NMOS transistor (135_5) included in the driving signal output circuit (135) is turned on so that the node (nd131) is driven by the ground voltage (VSS), and the driving signal (PDS) output through the inverters (135_8, 135_9) is initialized to a logic low level.

[0042] As illustrated in FIGS. 10 and 12, when the initialization operation is terminated and the initialization pulse (INTP) is generated at a logic low level, the PMOS transistor (141_1) included in the sampling interval signal generation circuit (141) is turned on, the node (nd141) is driven by the power supply voltage (VDD), and the sampling interval signal (SAP_EN) output from the node (nd141) is set to a logic high level ("H").

[0043] As illustrated in FIGS. 10 and 13, when a test is performed and the first to seventh bits (CA<1:7>) of the command address and the chip select signal (CS) are each set to have a logic high level equal to the test pulse width and input to the buffer circuit (131), the first to seventh bits (ICA<1:7>) of the internal command address and the internal chip select signal (ICS) output from the buffer circuit (131) are all generated as signals having the same internal test pulse width (td1). The fault detection signal generation circuit (133) sequentially receives the first to seventh bits (ICA<1:7>) and the internal chip select signal (ICS) having the same internal test pulse width (td1) and generates a fault detection signal (FDET). Therefore, the fault detection signal (FDET) is set to include a plurality of pulses having a logic low level equal to the internal test pulse width (td1) in sequence. The driving signal output circuit (135) can increase the voltage of the driving signal (PDS) by a preset voltage difference (△V) so that the driving signal (PDS) transitions from a logic low level to a logic high level by the fault detection signal (FDET).

[0044] As illustrated in FIGS. 10 and 14, when the driving signal (PDS) transitions to a logic high level ("H") while the initialization pulse (INTP) maintains a logic high level ("H") after the initialization operation is finished, the NMOS transistors (141_3, 141_5) included in the sampling interval signal generation circuit (141) are turned on, the node (nd141) is driven by the ground voltage (VSS), and the sampling interval signal (SAP_EN) output from the node (nd141) is set to a logic low level ("L").

[0045] As illustrated in FIG. 10, the period from the point in time when the sampling interval signal (SAP_EN) transitions from a logic low level to a logic high level by the initialization pulse (INTP) to the point in time when it transitions from a logic high level to a logic low level by the driving signal (PDS) is set as the sampling interval (spd1). As illustrated in FIG. 10 and FIG. 12, the oscillation signal sampling circuit (145) samples the oscillation signal (OSC) generated by the oscillation signal generation circuit (143) during the sampling interval (spd1) to generate a sampling oscillation signal (S_OSC), and the counter (147) counts the sampling oscillation signal (S_OSC) to generate a sampling code (SAP_C). Since the counting operation is performed 12 times during the sampling interval (spd1), the setting value of the sampling code (SAP_C) is set to the binary stream '01100' (decimal '12'). At this time, since the setting value of the reference code (REF_C) is set to a binary stream '01111' (decimal '15') which is larger than the setting value of the sampling code (SAP_C), the comparison flag (COM_FLAG) is generated at a logic low level. Through the logic low level comparison flag (COM_FLAG), information that no defect has occurred in the buffer circuit (131) can be confirmed.

[0046] Referring to FIG. 15, the test operation of the semiconductor device (100) performed when a defect occurs in the 7th buffer (131_7) among the 1st to 8th buffers (131_1~131_8) included in the buffer circuit (131) is as follows.

[0047] First, during the period in which the initialization operation is performed, if the initialization signal (INT) is set to a logic high level, the driving signal (PDS) is initialized to a logic low level.

[0048] Next, when the initialization operation is completed and the initialization pulse (INTP) is generated at a logic low level, the sampling interval signal (SAP_EN) is set to a logic high level.

[0049] Next, a test is performed and the first to seventh bits (CA<1:7>) of the command address and the chip select signal (CS) are each set to have a logic high level equal to the test pulse width, and when the first to seventh bits (CA<1:7>) of the command address and the chip select signal (CS) are each input to the first to eighth buffers (131_1~131_8), the first to sixth bits (ICA<1:6>) of the internal command address and the internal chip select signal (ICS) output from the first to sixth buffers (131_1~131_6) and the eighth buffer (131_8) are all generated as signals having the first internal test pulse width (td2), and the seventh bit (CA) of the internal command address output from the seventh buffer (131_7) <7> ) is generated as a signal having a second internal test pulse width (td3). The fault detection signal (FDET) is the 7th bit (CA) of the internal command address output from the 7th buffer (131_7) where the fault occurred. <7> The logic low level is sequentially set by the second internal test pulse width (td3). The driving signal (PDS) is raised by the voltage difference (△V) by the fault detection signal (FDET), and the logic level of the driving signal (PDS) transitions from the logic low level to the logic high level.

[0050] Next, when the driving signal (PDS) transitions to a logic high level while the initialization pulse (INTP) maintains a logic high level after the initialization operation is completed, the sampling interval signal (SAP_EN) is set to a logic low level. The interval from the point where the sampling interval signal (SAP_EN) transitions from a logic low level to a logic high level by the initialization pulse (INTP) to the point where it transitions from a logic high level to a logic low level by the driving signal (PDS) is set as the sampling interval (spd2). Since the sampling code (SAP_C) is set to a binary stream '10101' (decimal '21') because a counting operation is performed 21 times during the sampling interval (spd2), the setting value of the reference code (REF_C) is set to a binary stream '01111' (decimal '15'), which is smaller than the setting value of the sampling code (SAP_C), so the comparison flag (COM_FLAG) is generated at a logic high level. Information that a defect has occurred in the buffer circuit (131) can be confirmed through the logic high-level comparison flag (COM_FLAG).

[0051] The present invention has been described above with reference to embodiments. Those skilled in the art will understand that the present invention may be embodied in modified forms without departing from the essential characteristics of the invention. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the invention is defined by the claims, not by the foregoing description, and all variations within the scope of equivalents should be interpreted as being included in the invention. Explanation of the symbols

[0053] 100: Semiconductor device 101: Sampling code generation circuit 103: Reference code storage circuit 105: Code comparator 101: Sampling code generation circuit 111: Initialization pulse generation circuit 113: Driving signal generation circuit 115: Sampling code output circuit

Claims

Claim 1 A semiconductor device comprising: a sampling code generation circuit that includes a buffer circuit receiving an external setting signal and generates a sampling code by performing a counting operation during a sampling interval controlled based on the output signal of the buffer circuit; a code comparator that generates a comparison flag by comparing the sampling code with a reference code; and a reference code storage circuit that outputs the reference code, which provides a reference value for determining whether the buffer circuit is defective. Claim 2 In claim 1, the external setting signal is a semiconductor device including a command address and a chip selection signal. Claim 3 A semiconductor device according to claim 1, wherein the sampling code generation circuit sets the sampling interval larger when a defect occurs in the buffer circuit compared to when no defect occurs in the buffer circuit. Claim 4 A semiconductor device according to claim 1, wherein the sampling code generation circuit samples an oscillation signal during the sampling interval and generates the sampling code by counting the sampled oscillation signal. Claim 5 In claim 4, the semiconductor device comprises: a sampling code generation circuit that generates a driving signal based on the output signal of the buffer circuit; and a sampling code output circuit that generates the sampling code based on an initialization pulse and the driving signal. Claim 6 In claim 5, the semiconductor device further comprises an initialization pulse generating circuit that generates the initialization pulse at the time when the initialization operation ends. Claim 7 A semiconductor device according to claim 5, wherein the logic level transition interval of the driving signal generated by the driving signal generating circuit is set longer when a defect occurs in the buffer circuit compared to when no defect occurs in the buffer circuit. Claim 8 A semiconductor device according to claim 5, wherein the driving signal generating circuit comprises: a defect detection signal generating circuit that generates a defect detection signal based on the output signal of the buffer circuit; and a driving signal output circuit that drives the driving signal, which is set to a first logic level during an initialization operation, to a second logic level based on the defect detection signal. Claim 9 In claim 5, the sampling code output circuit comprises: an oscillation signal sampling circuit that samples an oscillation signal during the sampling interval to generate a sampling oscillation signal; and a counter that counts the sampling oscillation signal to change the set value of the sampling code. Claim 10 A semiconductor device according to claim 5, wherein the sampling interval is set as the interval from the point in time when the initialization pulse is generated to the point in time when the logic level of the driving signal transitions. Claim 11 delete Claim 12 In claim 1, the buffer circuit is a semiconductor device that receives the external setting signal and generates a selection setting signal in which the slope of the logic level changing according to the test signal is adjusted. Claim 13 A semiconductor device comprising: a sampling code generation circuit that generates a sampling oscillation signal by sampling an oscillation signal during a sampling interval controlled according to whether a defect occurs in the buffer circuit, and generates a sampling code by counting the sampling oscillation signal; a code comparator that generates a comparison flag by comparing the sampling code with a reference code; and a reference code storage circuit that outputs the reference code, which provides a reference value for determining whether the buffer circuit is defective. Claim 14 In claim 13, the buffer circuit is a semiconductor device that receives a command address and a chip select signal. Claim 15 In claim 13, the semiconductor device comprises: a sampling code generation circuit that generates a driving signal based on the output signal of the buffer circuit; and a sampling code output circuit that generates the sampling code based on an initialization pulse and the driving signal. Claim 16 A semiconductor device according to claim 15, wherein the logic level transition interval of the driving signal generated by the driving signal generating circuit is set longer when a defect occurs in the buffer circuit compared to when no defect occurs in the buffer circuit. Claim 17 A semiconductor device according to claim 15, wherein the driving signal generating circuit comprises: a defect detection signal generating circuit that generates a defect detection signal based on the output signal of the buffer circuit; and a driving signal output circuit that drives the driving signal, which is set to a first logic level during an initialization operation, to a second logic level based on the defect detection signal. Claim 18 In claim 15, the sampling code output circuit comprises: an oscillation signal sampling circuit that samples the oscillation signal during the sampling interval to generate the sampling oscillation signal; and a counter that counts the sampling oscillation signal to change the set value of the sampling code. Claim 19 A semiconductor device according to claim 15, wherein the sampling interval is set as the interval from the point in time when the initialization pulse is generated to the point in time when the logic level of the driving signal transitions. Claim 20 A semiconductor device comprising: a buffer circuit that receives a command address and a chip select signal and generates an internal command address and an internal chip select signal; a fault detection signal generating circuit that generates a fault detection signal based on the internal command address and the internal chip select signal; a driving signal output circuit that drives an initialized driving signal during an initialization operation so that the logic level transitions based on the fault detection signal; a sampling code output circuit that generates a sampling code based on an initialization pulse and the driving signal; and a code comparator that generates a comparison flag by comparing the sampling code with a reference code. Claim 21 In claim 20, the semiconductor device comprises: an oscillation signal sampling circuit that generates a sampling oscillation signal by sampling an oscillation signal during a sampling interval; and a counter that changes a set value of the sampling code by counting the sampling oscillation signal. Claim 22 A semiconductor device according to claim 21, wherein the sampling interval is set as the interval from the point in time when the initialization pulse is generated to the point in time when the logic level of the driving signal transitions. Claim 23 A semiconductor device according to claim 20, further comprising a reference code storage circuit that outputs a reference code providing a reference value for determining whether the buffer circuit is defective.

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